Memory device and method of forming a memory device

Abstract

The present disclosure relates to a memory device and a method for forming the memory device. A memory device may be provided, comprising: a base layer; an insulating layer arranged on the base layer, wherein the insulating layer may include a recess having opposite sidewalls; a first electrode arranged along the opposite sidewalls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a covering layer arranged on the recess, wherein the covering layer may at least partially overlap the first electrode, the switching element, and the second electrode.

Description

Technical Field

[0001] The present invention generally relates to memory devices and methods of forming memory devices. Background Art

[0002] Non-volatile memory devices are often used in consumer electronics such as smart phones and tablets. One type of non-volatile memory device is a resistive random access memory (RRAM) device. RRAM devices typically use a switching element such as a dielectric element sandwiched between two electrodes. The switching element is usually insulated. However, when a sufficiently high potential difference (set voltage / switching voltage) is applied between the electrodes, a conductive filament may be formed within the switching element. Therefore, the switching element becomes conductive via the conductive filament. The switching element may be insulated again by applying a sufficiently low voltage difference (reset voltage) to the electrodes to disconnect the conductive filament. A typical RRAM can switch between states based on the resistance of the switching element. When the switching element is insulated, the switching element has a high resistance, and the RRAM may be referred to as being in a high resistance state (HRS). When the switching element is turned on, the switching element has a low resistance, and the RRAM may be referred to as being in a low resistance state (LRS). In order to arrange the RRAM, the RRAM switches from the HRS to the LRS. In order to reset the RRAM, the RRAM switches from the LRS to the HRS.

[0003] The manufacture of memory devices such as RRAM devices typically involves several processes that may damage electrodes and portions of switching elements. This may adversely affect the formation of the conductive filaments, which in turn affects the performance of the memory device. For example, the resistance of an RRAM device may vary greatly over different switching cycles due to damage caused during the manufacturing process. Therefore, it is desirable to provide an improved memory device having reduced damage from the manufacturing process. Summary of the invention

[0004] According to various non-limiting embodiments, a memory device may be provided, comprising: a base layer; an insulating layer arranged above the base layer, wherein the insulating layer comprises a recess having opposite sidewalls; a first electrode arranged along the opposite sidewalls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a covering layer arranged above the recess, wherein the covering layer at least partially overlaps the first electrode, the switching element, and the second electrode.

[0005] According to various non-limiting embodiments, a method of forming a memory device may be provided. The method includes: providing a base layer; forming an insulating layer over the base layer, wherein the insulating layer includes a recess having opposite sidewalls; forming a first electrode along the opposite sidewalls of the recess; forming a switching element along the first electrode; forming a second electrode along the switching element; and forming a capping layer over the recess, wherein the capping layer at least partially overlaps the first electrode, the switching element, and the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, the same reference numerals generally refer to the same parts throughout the different views. In addition, the drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. Non-limiting embodiments of the present invention will now be described with reference only to the following drawings, in which:

[0007] Figure 1 shows simplified cross-sectional views of memory devices according to various non-limiting embodiments; and

[0008] Figures 2A to 2M A method for manufacturing a Figure 1 A simplified cross-sectional view of a method of a memory device. DETAILED DESCRIPTION

[0009] The present embodiments generally relate to semiconductor devices. More specifically, some embodiments relate to memory devices, for example, non-volatile memory devices such as RRAM devices in non-limiting examples. The memory devices can be used in several applications, such as but not limited to neuromorphic computing applications and multi-bit applications.

[0010] The various aspects of the present invention and its features, advantages and details are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of known materials, manufacturing tools, processing techniques, etc. are omitted so as not to unnecessarily obscure the details of the present invention. However, it should be understood that while indicating aspects of the present invention, the detailed description and specific examples are given only for the purpose of illustration and not for limitation. Through this disclosure, various substitutions, modifications, additions and / or arrangements within the spirit and / or scope of the following inventive concepts will be apparent to those skilled in the art.

[0011] As used throughout the specification and claims herein, approximate language may be applied to modify any quantitative representation, which may be permissibly changed without causing a change in the basic function associated therewith. Therefore, the value modified by a term or multiple terms such as "approximately", "about" is not limited to the specified exact value. In some cases, the approximate language may correspond to the accuracy of the instrument used to measure the value. In addition, a direction is modified by one or more terms, such as "substantially" meaning that the direction will be applied within the normal tolerance of the semiconductor industry. For example, "substantially parallel" means extending to a great extent in the same direction within the normal tolerance of the semiconductor industry, and "substantially vertical" means being at an angle of 90 degrees plus or minus the normal tolerance of the semiconductor industry.

[0012] The terms used herein are only for describing specific examples and are not intended to limit the present invention. As used herein, the singular forms "one", "an" and "said" are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "include" (and any form of including, such as "include" and "include"), "have" (and any form of having, such as "have" and "have"), "include" (and any form of including, such as "include" and "include") and "contain" (and any form of containing, such as "contain" and "contain") are all open linking verbs. As a result, the method or device of "include", "have", "include" or "contain" one or more steps or elements has these one or more steps or elements, but is not limited to having only these one or more steps or elements. Similarly, the steps or elements of the method of "include", "have", "include" or "contain" one or more features have these one or more features, but are not limited to having only these one or more features. In addition, the device or structure configured in a certain way is configured at least in this way, but can also be configured in an unlisted way.

[0013] As used herein, when used to refer to two physical elements, the term "connected" means a direct connection between the two physical elements. However, the term "coupled" can mean a direct connection or a connection through one or more intermediate elements.

[0014] As used herein, the terms "may" and "may be" indicate the possibility of occurring within a set of circumstances; possessing a specified attribute, characteristic, or function; and / or qualifying another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Thus, while taking into account that the modified term may sometimes not be appropriate, competent enough, or suitable in certain circumstances, the use of "may" and "may be" indicates that the modified term is clearly appropriate, competent enough, or suitable for the indicated ability, function, or use. For example, in some circumstances, an event or capability can be expected, while in other circumstances, the event or capability cannot occur - a distinction captured by the terms "may" and "may be".

[0015] Figure 1 A simplified cross-sectional view of a memory device 100 is shown in accordance with various non-limiting embodiments. The memory device 100 may include a RRAM device.

[0016] like Figure 1 As shown in FIG. 1 , the memory device 100 may include a base layer 102. The base layer 102 may be an interlayer dielectric (ILD) layer and may include an insulating material such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, or a combination thereof.

[0017] The memory device 100 may further include an insulating layer 104 disposed on the base layer 102. The insulating layer 104 may also be an interlayer dielectric (ILD) layer and may include an insulating material such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, or a combination thereof. Figure 1 As shown, the insulating layer 104 may include a top surface 104t and a recess 106. The recess 106 may have a bottom surface 106b and opposing sidewalls (including a first sidewall 106s1 and a second sidewall 106s2). The sidewalls 106s1, 106s2 may be vertical (in other words, may extend substantially perpendicular to the bottom surface 106b of the recess 106), or may optionally be inclined at an angle relative to the bottom surface 106b of the recess 106.

[0018] The first barrier layer 150 may be disposed between the insulating layer 104 and the base layer 102. The first barrier layer 150 may include a barrier material such as, but not limited to, Nblok (nitrogen doped silicon carbide).

[0019] The memory device 100 may further include a first electrode 108 disposed within the recess 106 of the insulating layer 104. The first electrode 108 may include a base surface 108b disposed along the bottom surface 106b of the recess 106 and a top surface 108t laterally aligned with the top surface 104t of the insulating layer 104. In addition, the first electrode 108 may be disposed along opposite sidewalls 106s1, 106s2 of the recess 106. Specifically, the first electrode 108 may include a first portion 1081 disposed along the first sidewall 106s1 and a second portion 1082 disposed along the second sidewall 106s2. The first portion 1081 and the second portion 1082 of the first electrode 108 may be separated from each other. Therefore, the base surface 108b and the top surface 108t of the first electrode 108 may each include a gap. The first electrode 108 may be an inert electrode and may include an inert electrode material such as, but not limited to, tungsten (W), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), alloys thereof, or combinations thereof.

[0020] The memory device 100 may further include a switching element 110 disposed within the recess 106 of the insulating layer 104 and disposed along the first electrode 108. The switching element 110 may include a base surface 110b disposed along the bottom surface 106b of the recess 106 and a top surface 110t laterally aligned with the top surface 104t of the insulating layer 104. In other words, the first electrode 108 and the base surfaces 108b, 110b of the switching element 110 may be laterally aligned. Similarly, the first electrode 108 and the top surfaces 108t, 110t of the switching element 110 may be laterally aligned. Figure 1 As shown, the switching element 110 may include a first portion 1101 closer to the first sidewall 106s1 of the recess 106 and a second portion 1102 closer to the second sidewall 106s2 of the recess 106. The first portion 1101 of the switching element 110 may be arranged along the first portion 1081 of the first electrode 108, and the second portion 1102 of the switching element 110 may be arranged along the second portion 1082 of the first electrode 108. Each of the first portion 1101 and the second portion 1102 of the switching element 110 may be similarly separated from each other. Therefore, the base surface 110b and the top surface 110t of the switching element 110 may each include a gap. The switching element 110 may include a switching material such as, but not limited to, magnesium oxide (MgO), tantalum oxide (TaO x ), hafnium oxide (HfO x ), titanium oxide (TiO x ), aluminum oxide (AlO x ), silicon dioxide (SiO x ), strontium oxide (SrOx), lanthanide oxides or a combination thereof.

[0021] The memory device 100 may further include a second electrode 112 disposed in the recess 106 of the insulating layer 104 and arranged along the switching element 110. Figure 1 , the second electrode 112 may include a liner arranged along the switching element 110, wherein the end 112e of the liner may be laterally aligned with the top surfaces 108t, 110t of the first electrode 108 and the switching element 110. The liner may also extend to and cross the first barrier layer 150 between the first portion 1101 and the second portion 1102 of the switching element 110. The liner may be thin, with a thickness ranging from about 5nm to about 15nm. This may help reduce the amount of electrode material used to manufacture the memory device 100, and thus reduce the cost of such manufacturing. The second electrode 112 may be an active electrode, and may include an active electrode material, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), alloys thereof, or combinations thereof.

[0022] The memory device 100 may further include a conductive member 114 disposed at least partially within the recess 106, wherein the conductive member 114 may be adjacent to the second electrode 112. Figure 1 As shown, the conductive member 114 may include a conductive layer 116 and a conductive region 118. The conductive layer 116 may be arranged along the entire length of the second electrode 112, and the conductive region 118 may be arranged on the conductive layer 116 to fill the remaining portion of the recess 106. Figure 1 , the conductive member 114 is depicted as being partially within the recess 106, wherein a portion of the conductive layer 116 extends to the first barrier layer 150, but the conductive member 114 may alternatively be completely within the recess 106. The conductive layer 116 and the conductive region 118 may each include a conductive material such as, but not limited to, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, cobalt, alloys thereof, or combinations thereof. For example, the conductive layer 116 may include tantalum, tantalum nitride, or cobalt, and the conductive region 118 may include copper. Alternatively, the conductive layer 116 may include titanium or titanium nitride, and the conductive region 118 may include tungsten. In Figure 1 , the conductive layer 116 and the conductive region 118 are shown as comprising different materials, but in alternative non-limiting embodiments, the conductive layer 116 and the conductive region 118 may comprise the same material.

[0023] The memory device 100 may further include a capping layer 120 disposed on the recess 106 of the insulating layer 104. Figure 1As shown, the cover layer 120 may extend continuously over the recess 106. The cover layer 120 may at least partially overlap the first electrode 108, the switching element 110, and the second electrode 112. Figure 1 , the cover layer 120 may span the entire width W of the recess 106 106 The capping layer 120 may overlap the entire top surfaces 108t, 110t of the first electrode 108 and the switching element 110 and the end 112e of the second electrode 112, and may also overlap the conductive member 114. The capping layer 120 may include an oxide layer, wherein the oxide layer may include an oxide of a material of at least one of the first electrode 108 and the second electrode 112. For example, if the first electrode 108 includes titanium nitride and the second electrode 112 includes tantalum, the oxide layer may include at least one of titanium oxynitride and tantalum oxide. The oxide layer may also include an oxide of a material of the switching element 110, an oxide of a material of the conductive layer 116, an oxide of a material of the conductive region 118, or a combination thereof. The thickness T of the capping layer 120 may be 100 mm / s. 120 For example, the thickness T of the cover layer 120 may be greater than or equal to 1 nm. 120 It may be in the range from about 1 nm to about 15 nm.

[0024] like Figure 1 As shown, the memory device 100 may further include a further insulating layer 122 disposed on the insulating layer 104. The further insulating layer 122 may be an interlayer dielectric (ILD) layer and may include an insulating material such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, or a combination thereof. The further insulating layer 122, the insulating layer 104, and the base layer 102 may include the same material, but optionally, at least two of these layers 102, 104, 122 may include different materials.

[0025] The memory device 100 may further include an intermediate layer 124 disposed between the insulating layer 104 and the further insulating layer 122. Figure 1 As shown, the base 124b of the intermediate layer 124 can be laterally aligned with the base 120b of the cover layer 120, and the thickness T of the intermediate layer 124 124 It can be approximately equal to the thickness T of the cover layer 120 120 However, the thickness T of the cover layer 120 is 120 It may optionally be smaller than the thickness T of the intermediate layer 124 124 The intermediate layer 124 may include a second barrier layer 152 and a protective layer 154 disposed on the second barrier layer 152. The thickness T of the protective layer 154 is 154 For example, the thickness T of the protective layer 154 may be greater than 5 nm. 154The thickness T of the second barrier layer 152 may be in the range of about 5 nm to about 15 nm. 152 may be equal to or less than the thickness T of the first barrier layer 150 150 The second barrier layer 152 may include a barrier material such as, but not limited to, Nblok (nitrogen-doped silicon carbide). The protective layer 154 may include an oxide layer. For example, the protective layer 154 may include an oxide of a protective material such as, but not limited to, silicon dioxide (SiO2), silicon oxynitride (SiON), or a combination thereof.

[0026] The memory device 100 may further include a plurality of contacts including a first contact 126, a second contact 128, a third contact 130, a fourth contact 132, a fifth contact 134, and a sixth contact 136. The memory device 100 may further include a plurality of connectors including a first connector 138, a second connector 140, a third connector 142, and a fourth connector 144. Figure 1 As shown, the first contact 126 and the second contact 128 can be arranged within the base layer 102 and can be electrically isolated from each other by a portion of the base layer 102. The first contact 126 can contact the second electrode 112; whereas, the second contact 128 can be electrically connected to the third contact 130 through the first connector 138. Specifically, the third contact 130 can be arranged within the insulating layer 104, and the first connector 138 can extend from the third contact 130 to the second contact 128 through the insulating layer 104 and the first barrier layer 150. The third contact 130 can in turn be connected to the fourth contact 132 through the second connector 140, wherein the second connector 140 can extend between the third contact 130 and the fourth contact 132 through another insulating layer 122, a protective layer 154, and a second barrier layer 152. In addition, as Figure 1 As shown, the fifth contact 134 can be electrically connected to the first portion 1081 of the first electrode 108 through the third connector 142; and the sixth contact 136 can be electrically connected to the second portion 1082 of the first electrode 108 through the fourth connector 144. The fifth and sixth contacts 134, 136 can be arranged in the further insulating layer 122, and the third and fourth connectors 142, 144 can extend through the further insulating layer 122, the protective layer 154 and the second barrier layer 152 to enter the insulating layer 104.

[0027] As described above, the first barrier layer 150 may be disposed between the insulating layer 104 and the base layer 102, and the second barrier layer 152 may be disposed between the further insulating layer 122 and the insulating layer 104. The first barrier layer 150 may help reduce the amount of conductive material diffused from the second contact 128 into the insulating layer 104; while the second barrier layer 152 may help reduce the amount of conductive material diffused from the third contact 130, the conductive layer 116, and the conductive region 118 into the further insulating layer 122. The first barrier layer 150 and the second barrier layer 152 may be optional. For example, the first barrier layer 150 may be omitted, and the second electrode 112 may extend along the bottom surface 106 b of the recess 106.

[0028] Figures 2A to 2M A simplified cross-sectional view illustrating a method for manufacturing a memory device 100 according to various non-limiting embodiments is shown. Figures 2A to 2M Some reference numerals are omitted.

[0029] refer to Figure 2A , the method may include providing a base layer 102, and forming first and second contacts 126, 128 in the base layer 102. For example, an insulating material may first be deposited on the surface on which the memory device 100 is to be formed, and then etched to form an opening. The opening may then be filled with a conductive material to form contacts 126, 128 in the base layer 102. The method may also include depositing a first barrier material 200 over the base layer 102.

[0030] refer to Figure 2B , 2C and 2D, the method may further include forming an insulating layer 104. Figure 2B As shown, an insulating material may be deposited on the base layer 102, specifically, on the first barrier material 200. Specifically, a first insulating material 202a may be deposited and then may be etched together with the first barrier material 200 to form an opening. Thereafter, a conductive material may be deposited into the opening to form the first connector 138. A second insulating material 202b may then be deposited on the first insulating material 202a and then etched to form an opening. A conductive material may then be deposited into the opening to form the third contact 130. As shown in FIG. Figure 2C As shown, the method may further include depositing a second barrier material 204 and a protective material 206 on the second insulating material 202b, wherein the protective material 206 is disposed on the second barrier material 204. Figure 2DAs shown, the method may further include etching the first insulating material 202a and the second insulating material 202b, the second barrier material 204, and the protective material 206. Thus, the insulating layer 104 having the recess 106 may be formed on the base layer 102 (specifically, on the first barrier material 200), wherein the second barrier material 204 and the protective material 206 are located above the insulating layer 104.

[0031] refer to Figure 2E The method may further include depositing an electrode material 208 over the insulating layer 104 (specifically, over the protective material 206 ) and into the recess 106 , such that the electrode material 208 may line the sidewalls 106 s 1 , 106 s 2 and the bottom surface 106 b of the recess 106 .

[0032] refer to Figure 2F The method may further include removing a portion of the electrode material 208 located above the protection material 206 and along the bottom surface 106b of the recess 106. This may be accomplished using an etching process, such as, but not limited to, a spacer etching process.

[0033] refer to Figure 2G The method may further include depositing a switching material 210 over the protective material 206 and into the recess 106 , such that the switching material 210 may line the electrode material 208 and a bottom surface 106 b of the recess 106 .

[0034] refer to Figure 2H The method may further include removing a portion of the switch material 210 located above the protection material 206 and along the bottom surface 106b of the recess 106. This may be accomplished using an etching process, such as, but not limited to, a spacer etching process.

[0035] refer to Fig.2I The method may further include etching the first barrier material 200 to form a first barrier layer 150 having a gap 150g, the gap 150g being vertically aligned with the recess 106. For clarity of illustration, the gap 150g is not marked in other drawings.

[0036] refer to Figure 2J The method may further include depositing an electrode liner 212 over the protective material 206 and into the recess 106 so that the electrode liner 212 may line the switching material 210. Figure 2JAs shown, the electrode liner 212 may extend to the first barrier layer 150 and cross the first barrier layer 150 (specifically, the gap 150g of the first barrier layer 150). The method may also include depositing a conductive liner 214 so that the conductive liner 214 may line the electrode liner 212. In addition, the method may include depositing a conductive material 216 over the conductive liner 214 and into the recess 106 so that the conductive material 216 may fill the remaining portion of the recess 106.

[0037] refer to Figure 2K The method may further include removing an upper portion of each of the conductive material 216, the conductive liner 214, the electrode liner 212, the protective material 206, the switch material 210, and the electrode material 208. This may be accomplished using a planarization process such as, but not limited to, a chemical mechanical polishing (CMP) process. Figure 2K As shown, a portion of the protective material 206 located above the second barrier material 204 may remain. The thickness T of the remaining portion of the protective material 206 is 206 For example, the thickness T of the remaining portion of the protective material 206 may be greater than 5 nm. 206 It may be in the range from about 5 nm to about 15 nm.

[0038] refer to Figure 2L , the method may further include forming a capping layer 120, a first electrode 108, a switching element 110, a second electrode 112, a conductive layer 116, and a conductive region 118 using a single oxidation process. Specifically, the method may include forming a capping layer 120 over the recess 106 by oxidizing a top portion of each of the conductive material 216, the conductive liner 214, the electrode liner 212, the switching material 210, and the electrode material 208 extending over the recess 106. The oxidized portions of these materials 208, 210, 212, 214, 216 may form the capping layer 120; and the remaining portions of these materials 208, 210, 212, 214, 216 may form the first electrode 108, the switching element 110, the second electrode 112, the conductive layer 116, and the conductive region 118, respectively. Oxidation of the top portion of each of materials 208, 210, 212, 214, 216 may further oxidize protective material 206 to form oxidized protective material 218. The thickness T of oxidized protective material 218 is 218 can be equal to the thickness T as described above 206 Alternatively, the thickness T 218 Can be greater than thickness T 206 , because the oxidation process may convert the top portion of the second barrier material 204 into a portion of the oxidized protective material 218. In this case, the resulting second barrier layer 152 may have a thickness T less than the first barrier layer 150. 150Thickness T 152 .

[0039] refer to Figure 2M , the method may further include depositing a third insulating material on top of the oxidized protective material 218. The method may further include etching the third insulating material, the oxidized protective material 218, the second barrier material 204, and the insulating layer 104 to form openings. These openings may then be filled with conductive materials to form the second, third, and fourth connectors 140, 142, 144. The remaining oxidized protective material 218 and the remaining second barrier material 204 may form a protective layer 154 and a second barrier layer 152, respectively. The method may further include depositing a fourth insulating material on top of the third insulating material, and etching the fourth insulating material to form openings. These openings may then be filled with conductive materials to form the fourth, fifth, and sixth contacts 132, 134, 136. The remaining third and fourth insulating materials may then form a further insulating layer 122.

[0040] The above order of the above method is intended to be illustrative only, and the method is not limited to the above specific described order unless specifically stated otherwise.

[0041] In use, when a sufficiently high potential difference is applied between the first portion 1081 of the first electrode 108 and the second electrode 112 (e.g., using the first and fifth contacts 126, 134), a conductive filament between the first portion 1081 of the first electrode 108 and the second electrode 112 may be formed within the first portion 1101 of the switching element 110. Similarly, when a sufficiently high potential difference is applied between the second portion 1082 of the first electrode 108 and the second electrode 112 (e.g., using the first and sixth contacts 126, 136), a conductive filament between the second portion 1082 of the first electrode 108 and the second electrode 112 may be formed within the second portion 1102 of the switching element 110. The formation of the conductive filament between the first portion 1081 of the first electrode 108 and the second electrode 112 may be independent of the formation of the conductive filament between the second portion 1082 of the first electrode 108 and the second electrode 112.

[0042] As reference Figure 2KAs described, the process (e.g., CMP process) for removing the upper portion of each of the materials 208, 210, 212 may damage the top portion of one or more of the materials 208, 210, 212. Oxidizing the top portion of each of the materials 208, 210, 212 extending above the recess 106 may help limit the formation of conductive filaments to the lower portions of the materials 208, 210, 212 that are less likely to be damaged. Thus, the performance of the memory device 100 may be improved. In addition, prior to the oxidation process, a portion of the protective material 206 may be retained over the second barrier material 204. This retained portion of the protective material 206 may help protect the second barrier material 204, and thereby protect the contact 130 thereunder from damage during the oxidation process.

[0043] The present invention may be embodied in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the foregoing embodiments are considered to be illustrative in all respects, rather than limiting the present invention described herein. Therefore, the scope of the present invention is indicated by the appended claims rather than the foregoing description, and all changes within the meaning and scope of the equivalents of the claims are intended to be included therein.

Claims

1. A memory device, comprising: Basal layer; an insulating layer disposed over the base layer, wherein the insulating layer includes a recess having opposing sidewalls; a first electrode disposed along the opposing sidewalls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a cover layer arranged over the recess, wherein the cover layer at least partially overlaps the first electrode, the switching element and the second electrode, The cover layer includes an oxide layer, and the oxide layer includes oxidized portions of materials of the first electrode, the switching element, and the second electrode.

2. The memory device according to claim 1, wherein: The cover layer extends laterally across the entire width of the recess.

3. The memory device according to claim 1, wherein: The cover layer extends continuously over the recess.

4. The memory device according to claim 1, wherein: The thickness of the covering layer is greater than or equal to 1 nm.

5. The memory device according to claim 1, further comprising a conductive member disposed at least partially within the recess and disposed adjacent to the second electrode, and wherein, The cover layer also overlaps the conductive member.

6. The memory device according to claim 1, further comprising: a further insulating layer disposed above the insulating layer; as well as An intermediate layer is arranged between the insulating layer and the further insulating layer, wherein the intermediate layer comprises a barrier layer and a protective layer located on the barrier layer.

7. The memory device according to claim 6, wherein: The thickness of the cover layer is approximately equal to or less than the thickness of the intermediate layer.

8. The memory device according to claim 6, wherein: The thickness of the protective layer is greater than 5 nm.

9. The memory device according to claim 6, wherein: The protection layer includes an oxide layer.

10. The memory device according to claim 1, wherein: The first electrode is an inert electrode, and the second electrode is an active electrode.

11. The memory device according to claim 1, wherein: The memory device includes a resistance random access memory device.

12. A method of forming a memory device, the method comprising: Provides a base layer; forming an insulating layer over the base layer, wherein the insulating layer includes a recess having opposing sidewalls; forming a first electrode along the opposite sidewalls of the recess; forming a switching element along the first electrode; forming a second electrode along the switching element; as well as forming a cover layer over the recess, wherein the cover layer at least partially overlaps the first electrode, the switching element, and the second electrode, The cover layer includes an oxide layer, and the oxide layer includes oxidized portions of materials of the first electrode, the switching element, and the second electrode.

13. The method according to claim 12, wherein: The capping layer, the first electrode, the switching element, and the second electrode can be formed using a single oxidation process.

14. The method according to claim 12, wherein: Forming the cover layer, the first electrode, the switching element, and the second electrode further includes: depositing an electrode material over the insulating layer to line the opposing sidewalls of the recess; depositing a switching material to line the electrode material; depositing an electrode lining to line the switching material; and A top portion of each of the electrode material, the switching material, and the electrode liner extending over the recess is oxidized.

15. The method according to claim 14, wherein: Forming the insulating layer includes depositing an insulating material over the base layer, and the method further includes depositing a protective material over the insulating material.

16. The method according to claim 15, wherein: Oxidizing the top portion of each of the electrode material, the switching material, and the electrode liner further oxidizes the protective material.

17. The method according to claim 15, wherein: An upper portion of the protective material is removed before the oxidation process such that a remaining portion of the protective material has a thickness greater than 5 nm.

Images