Power supply control device, driving module and switching power supply device

Abstract

The present application realizes the confirmation function of the connection of the control terminal while inhibiting the increase of the number of terminals. The present application relates to a power supply control device, a driving module and a switching power supply device. The power supply control device of the present application has: a control terminal for inputting and outputting a control signal to a driving module; an enable output terminal for outputting an enable signal to the driving module; a control circuit; and an input and output circuit, which makes the control signal a first logic level when an output transistor is in an on state and a synchronous rectification transistor is in an off state, makes the control signal a second logic level when the output transistor is in an off state and the synchronous rectification transistor is in an on state, and can be in an input standby state according to the instruction from the control circuit; the control circuit transmits an enable signal with a level for starting the driving module to the driving module when the input and output circuit is in the input standby state, and confirms whether the control signal is a third logic level which is neither the first logic level nor the second logic level.

Description

Technical Field

[0001] This invention relates to a drive module and a power control device for a switching power supply. Background Technology

[0002] In recent years, as a component of switching power supply devices, the driver module (so-called DrMOS (Driver Metal-Oxide-Semiconductor Field Effect Transistor)) has been put into practical use. It integrates a pair of MOSFETs (metal-oxide-semiconductor field effect transistors) that form the switching output stage with the driving logic circuit used to drive the pair of MOSFETs into a single package.

[0003] Additionally, as an example of prior art related to the aforementioned content, Patent Document 1 can be cited.

[0004] [Existing technical documents]

[0005] [Patent Literature]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2017-195768 Summary of the Invention

[0007] [The problem the invention aims to solve]

[0008] Conventionally, the drive module is controlled by a power control device. The power control device has control terminals. The drive logic circuit drives the MOSFET to turn on and off according to the logic level of the control signal output from the control terminals.

[0009] Here, it is desirable that when the switching power supply is started, the power control device can identify the model of the drive module connected to the control terminals, or whether there is a poor connection at the control terminals. At this time, it is required to prevent the number of terminals of the power control device from increasing.

[0010] In view of the above situation, the object of the present invention is to provide a power control device, a drive module, and a switching power supply device that can suppress the increase of the number of terminals and realize the confirmation function related to the connection of the control terminals of the power control device.

[0011] [Technical means to solve the problem]

[0012] The power control device of the present invention is used in conjunction with a drive module that controls the on / off state of the drive output transistor and the synchronous rectifier transistor, and

[0013] It is configured as follows (the first configuration), that is, it has:

[0014] Control terminals are used to input and output control signals to the drive module;

[0015] The enable output terminal is used to output an enable signal to the drive module;

[0016] Control circuit; and

[0017] The input / output circuit, when the output transistor is turned on and the synchronous rectifier transistor is turned off, sets the control signal to a first logic level; when the output transistor is turned off and the synchronous rectifier transistor is turned on, sets the control signal to a second logic level, enabling it to enter an input standby state according to instructions from the control circuit; and

[0018] When the input / output circuit is in the input standby state, the control circuit transmits an enable signal of the level used to start the drive module to the drive module, and confirms whether the control signal is a third logic level that is neither the first logic level nor the second logic level.

[0019] Alternatively, it can be configured as follows (second configuration), where, in the first configuration, the enable signal can be any one of L (low) level, H (high) level, or M level between the L level and the H level.

[0020] The voltage level used to start the driver module is the M level.

[0021] Alternatively, it can be configured as follows (third configuration): in the first or second configuration, when the input / output circuit is in the input standby state and the enable signal is at a level indicating inactivity, after the control circuit confirms that the control signal has become the first logic level or the second logic level, the control circuit transmits an enable signal at a level used to start the drive module to the drive module.

[0022] Alternatively, it can be configured as follows (fourth configuration): in the third configuration, there are multiple control terminals, and when the input / output circuit is in the input standby state and the enable signal is at a level indicating prohibition, the control circuit confirms whether the combination of control signal levels is consistent with the allowed combination.

[0023] Alternatively, it can be configured as follows (fifth configuration), in which the voltage application terminal of the third logic level can be connected to the control terminal that is not used for connection with the drive module.

[0024] Alternatively, it can be configured as follows (the sixth configuration), in which, in any of the first to fifth configurations, there are multiple enable output terminals and multiple control terminals.

[0025] Furthermore, the driving module of the present invention drives the output transistor and the synchronous rectifier transistor to turn on / off, and

[0026] It is configured as follows (the 7th configuration), that is, it has the following characteristics when integrated into a single package:

[0027] The driving logic circuit turns on the output transistor and turns off the synchronous rectifier transistor when the control signal is at the first logic level, and turns off the output transistor and turns on the synchronous rectifier transistor when the control signal is at the second logic level.

[0028] The internal voltage generating unit generates an internal voltage and is activated by an enable signal.

[0029] The power-on reset unit resets and releases the drive logic circuit based on the internal voltage; and

[0030] The logic level switching circuit, upon reset release, switches the control signal to a third logic level that is neither the first logic level nor the second logic level, according to an instruction from the driving logic circuit.

[0031] Alternatively, it can be configured as follows (the 8th configuration), that is, in the 7th configuration,

[0032] The logic level switching circuit has the following features:

[0033] The first P-channel MOS transistor has a gate driven by the enable signal and a source connected to the power supply voltage application terminal;

[0034] A resistor having a first terminal connected to the drain of the first P-channel MOS transistor;

[0035] The second P-channel MOS transistor has a source connected to the second terminal of the resistor, a drain connected to the applied terminal of the ground voltage, and a gate driven by the internal voltage.

[0036] An N-channel MOS transistor has a gate connected to a node that connects the second terminal of the resistor to the source of the second P-channel MOS transistor, and a source connected to the application terminal of the control signal; and

[0037] The third P-channel MOS transistor has a source connected to the power supply voltage application terminal, a drain connected to the drain of the N-channel MOS transistor, and a gate to which a gate signal output from the drive logic circuit is applied.

[0038] Alternatively, it can be configured as follows (the 9th configuration), that is, in the 7th or 8th configuration, a logic level fixing circuit is also provided, which fixes the control signal to the logic level of each model when the enable signal indicates that the control signal is disabled.

[0039] Alternatively, it can be configured as follows (10th configuration): in any of the 7th to 9th configurations, a zero-crossing detection circuit is provided, which detects the zero-crossing of the inductor current flowing when the synchronous rectifier transistor is in the on state, and when the logic level switching circuit detects the zero-crossing, it switches the control signal to the 3rd logic level according to the instruction from the drive logic circuit.

[0040] Alternatively, it can be configured as follows (configuration 11), in any of the configurations from 7 to 10, the output transistor and the synchronous rectifier transistor are also integrated into the package.

[0041] Furthermore, the switching power supply device of the present invention includes a drive module and a power control device. The drive module drives the output transistor and the synchronous rectifier transistor to turn on / off, and is configured as follows:

[0042] The power control device has:

[0043] Control terminals are used to input and output control signals to the drive module;

[0044] The enable output terminal is used to output an enable signal to the drive module;

[0045] Control circuit; and

[0046] The input / output circuit, in order to turn the output transistor and the synchronous rectifier transistor on and off, can set the control signal to the first logic level or the second logic level, and become an input standby state according to the instruction from the control circuit;

[0047] When the input / output circuit is in the input standby state, the control circuit transmits an enable signal of the level used to start the drive module to the drive module, and confirms whether the control signal is a third logic level that is neither the first logic level nor the second logic level.

[0048] The driver module is integrated into a single package and has the following features:

[0049] The driving logic circuit, when the control signal is the first logic level, turns on the output transistor and turns off the synchronous rectifier transistor; when the control signal is the second logic level, turns off the output transistor and turns on the synchronous rectifier transistor.

[0050] An internal voltage generating unit generates an internal voltage and is activated by the aforementioned enable signal;

[0051] The power-on reset unit resets and releases the drive logic circuit based on the internal voltage; and

[0052] The logic level switching circuit switches the control signal to the third logic level according to the instruction from the driving logic circuit when the reset is released.

[0053] [Invention Effects]

[0054] According to the present invention, it is possible to achieve a connection confirmation function related to the control terminals of the power control device while suppressing the increase in the number of terminals. Attached Figure Description

[0055] Figure 1 This is a diagram showing the overall configuration of a switching power supply device according to an exemplary embodiment.

[0056] Figure 2 This is a diagram illustrating an example of the internal structure of the drive module of a switching power supply device.

[0057] Figure 3 This is a diagram illustrating an example of a pull-down logic level fixed circuit.

[0058] Figure 4 This is a diagram illustrating an example of a pull-up logic level fixed circuit.

[0059] Figure 5 This is a diagram illustrating an example of the configuration of a logic level switching circuit.

[0060] Figure 6 This is a diagram showing an example of the configuration of an input / output circuit.

[0061] Figure 7 This is a flowchart related to the startup sequence of a switching power supply device.

[0062] Figure 8 This is a timing diagram representing the first example of the startup sequence of a switching power supply device (an example of normal startup).

[0063] Figure 9 This is the second example of a timing diagram showing the startup sequence of a switching power supply device (an example of an error).

[0064] Figure 10This is the third example of a timing diagram showing the startup sequence of a switching power supply device (an example of an error).

[0065] Figure 11 This is a diagram showing the overall configuration of a switching power supply device with variations.

[0066] Figure 12 It means Figure 11 The timing diagram shown is an example of a startup sequence. Detailed Implementation

[0067] <Overall Composition of Switching Power Supply Device>

[0068] Figure 1 This is a diagram showing the overall configuration of the switching power supply device. The switching power supply device 1 in this configuration example is a multi-phase (4-phase in this figure) step-down DC / DC (Direct Current to Direct Current) converter that generates an output voltage Vout from the input voltage Pvin and supplies it to a load Z (CPU [central processing unit], etc.) not shown. It also has four parallel-connected drive modules 10(1) to 10(4), a power control device 20, inductors L1(1) to L1(4), and capacitor Co.

[0069] Furthermore, the power control device 20, as described below, has control terminals Tp1 to Tp8, and can connect one to eight drive modules 10 to the power control device 20 depending on the connection configuration of the drive modules 10. In other words, it can form a step-down DC / DC converter with one to eight phases. Figure 1 In this example, control terminals Tp1 to Tp4 are used to connect to the drive module 10, while other control terminals Tp5 to Tp8 are not used.

[0070] The drive modules 10(1) to 10(4) are semiconductor devices (DrMOS) that integrate a pair of MOSFETs forming a switch output stage and a drive logic circuit (not shown) for driving the pair of MOSFETs into a single package.

[0071] The pair of MOSFETs are connected between the input voltage Pvin and the ground voltage PGND, and are essentially controlled to be turned on / off according to the control signals PWM1 to PWM4. As a result, the drive modules 10(1) to 10(4) output switching voltages SW(1) to SW(4) that are pulse-driven between the input voltage Pvin and the ground voltage PGND. These switching voltages are accumulated, rectified and smoothed by inductors L1(1) to L1(4) and capacitor Co, thereby generating the output voltage Vout input to the load Z.

[0072] Furthermore, by using drive modules 10(1) to 10(4), the circuit size of the switching power supply device 1 can be significantly reduced compared to cases where each pair of MOSFETs or drive logic circuits is individually provided.

[0073] The power control device 20 is a semiconductor device (so-called PMIC [power management IC, integrated circuit]) that serves as the control unit of the switching power supply device 1. The power control device 20 has a control circuit 21, an input / output circuit 22, an internal voltage generation unit 23, and a MOS switch 24 integrated into a single package.

[0074] In addition, the power control device 20 has control terminals Tp1 to Tp8, enable output terminal Tden, drive input terminal Ten, standby terminal Tst, internal voltage output terminal Treg, internal voltage input terminal Tregin, interrupt terminal Tint, feedback input terminals Ts+ and Ts-, power supply terminal Tcc, and ground terminal Tgd as external terminals for establishing electrical connection with the outside.

[0075] The control circuit 21 is the main body for output feedback control (duty-free control) of the control signal PWM to obtain the desired output voltage Vout from the input voltage Pvin. The control circuit 21 instructs the input / output circuit 22 based on the voltage between the two ends of the load Z detected by remote sensing (the difference between the remote sensing signals S+ and S-), causing the input / output circuit 22 to generate control signals PWM(1) to PWM(4) for each of the drive modules 10(1) to 10(4), thus performing the output feedback control. The remote sensing signals S+ and S- are input to the feedback input terminals Ts+ and Ts-. The generated control signals PWM(1) to PWM(4) are output from the control terminals Tp1 to Tp4 to the drive modules 10(1) to 10(4).

[0076] In addition, the control circuit 21 also has the following functions (details will be described below): to put the input / output circuit 22 into input standby state, to monitor the logic level of the control signal PWM, to switch the operating mode of the switching power supply device 1 according to the monitoring results, or to identify or determine the model of the drive module 10.

[0077] The input / output circuit 22 is a circuit block that inputs and outputs the control signal PWM. Based on instructions from the control circuit 21, it switches its operating state (output state or input standby state). When the input / output circuit 22 is in output state, it outputs a control signal PWM at either H (High) or L (Low) level, thereby controlling the on / off state of the pair of MOSFETs (described later) included in the drive module 10. Conversely, when the input / output circuit 22 is in input standby state, it detects the logic level (H / L / M (Middle)) of the control signal PWM and outputs the detection result to the control circuit 21 (details will be described below).

[0078] In addition, the control circuit 21 also has the function of outputting an enable signal DREN with three values ​​(H / M / L) common to each of the drive modules 10(1) to 10(4). The enable signal DREN is output to the drive modules 10(1) to 10(4) from the enable output terminal Tden.

[0079] When DREN = L (e.g., GND), drive modules 10(1) to 10(4) are disabled.

[0080] When DREN = H (e.g., Vcc), drive modules 10(1) to 10(4) start in the first operating mode (i.e., the pulse drive mode that always corresponds to the control signals PWM1 to PWM4 to drive the switching voltages SW(1) to SW(4)).

[0081] In addition, when DREN = M (e.g., Vcc / 2), the drive modules 10(1) to 10(4) start in the second operating mode (when the zero crossover detection of the inductor current IL(1) to IL(4) is performed, the control signals PWM1 to PWM4 are automatically switched to the M level, and the switching voltages SW(1) to SW(4) are automatically set to the output high impedance state (HiZ) operating mode).

[0082] Furthermore, the control circuit 21 also has the following functions (details will be described below): when DREN=L or DREN=M, the input / output circuit 22 is appropriately set to the input standby state of the control signals PWM1 to PWM4, and each logic level is detected, thereby performing the transfer process from heavy load mode (PWM [pulse width modulation] mode) to light load mode (PFM [pulse frequency modulation] mode), or performing the model identification or connection determination of the drive modules 10(1) to 10(4).

[0083] Furthermore, the internal voltage generation unit 23 is a circuit that generates and outputs an internal voltage Vreg15 based on the power supply voltage Vcc applied to the power supply terminal Tcc. For example, it may include an LDO (Low Dropout). As an example, Vcc = 3V, and Vreg = 1.5V. The internal voltage Vreg15 is output to the outside from the internal voltage output terminal Treg. Additionally, the internal voltage Vreg15 output to the outside is input to the internal voltage input terminal Tregin and supplied to the control circuit 21.

[0084] MOS switch 24 contains an NMOS transistor. The source of MOS switch 24 is connected to the applied ground voltage GND, and the drain is connected to the interrupt terminal Tint. The interrupt terminal Tint is pulled up. The MOS switch 24 is controlled to turn on and off by control circuit 21. When MOS switch 24 is off, the interrupt signal INTB generated by the interrupt terminal Tint is at a high level (H); when it is on, the interrupt signal INTB is at a low level (L). Control circuit 21 can notify the outside of abnormal conditions through the interrupt signal INTB. In the event of an abnormal condition, for example, the interrupt signal INTB is set to a low level (L).

[0085] The first terminal of each inductor L1(1) to L1(4) is connected to the output terminal of each of the drive modules 10(1) to 10(4). The second terminal of each inductor L1(1) to L1(4) is connected to the application terminal of the output voltage Vout (= the high potential terminal of the load Z). In addition, since inductor currents IL(1) to IL(4) flow through inductors L1(1) to L1(4) respectively, the load Z can be supplied with an output current Io (= IL(1) + IL(2) + IL(3) + IL(4)) obtained by adding the inductor currents IL(1) to IL(4).

[0086] Capacitor Co is connected between the terminal where the output voltage Vout is applied and the terminal where the ground voltage PGND is applied (= the two ends of the load Z), making the output voltage Vout smooth.

[0087] In addition, unused terminals among the control terminals Tp1 to Tp8 are externally connected to the terminal where the internal voltage Vreg15 is applied. Figure 1 In this example, since control terminals Tp5 to Tp8 are not used, the control terminals are connected to the application terminal of the internal voltage Vreg15.

[0088] In addition, the grounding terminal Tgd is connected to the terminal where the grounding voltage GND is applied.

[0089] In addition to the circuit block mentioned above, the power control device 20 may also integrate various protection circuits (UVLO [under voltage lockout]), OCP [over current protection], and TSD [thermal shut down, etc.).

[0090] <Internal Structure of the Driver Module>

[0091] Figure 2 This is a diagram showing an example of the internal configuration of the drive module 10 of the switching power supply device 1. Alternatively, the drive module 10 can also be understood as any one of the four-phase drive modules 10(1) to 10(4). Similarly, the control signal PWM, the switching voltage SW, the inductor L1, and the inductor current IL are respectively equivalent to any one of the control signals PWM1 to PWM4, the switching voltage SW(1) to SW(4), the inductor L1(1) to L1(4), and the inductor current IL(1) to IL(4).

[0092] The drive module 10 in this embodiment integrates a switch output stage 11, a drive logic circuit 12, a zero-crossing detection circuit 13, a logic level switching circuit 14, a logic level fixing circuit 15, an LDO 16, and a power-on reset unit 17 into a single package. Furthermore, the drive module 10 has a control terminal TPWM, an enable input terminal TEN, a switch terminal TSW, a power supply terminal TCC, an input voltage terminal TVIN, and a ground terminal TGD as external terminals for establishing electrical connections to the outside world.

[0093] The switching output stage 11 includes an output transistor M1, for example, a P-channel MOS transistor, and a synchronous rectifier transistor M2, for example, an N-channel MOS transistor. The source of transistor M1 is connected to the input voltage PVPin via the input voltage terminal TVIN. The drains of transistors M1 and M2 are connected to the switching terminal TSW, which is the application terminal of the switching voltage SW (i.e., the output terminal of the drive module 10). The source of transistor M2 is connected to the application terminal of the ground voltage PGND via the ground terminal TGD.

[0094] Gate signals G1 and G2 are input to the gates of transistors M1 and M2, respectively. Transistor M1 is in the ON state when G1 = L and in the OFF state when G1 = H. Similarly, transistor M2 is in the OFF state when G2 = L and in the ON state when G2 = H.

[0095] For example, when transistor M1 is turned on and transistor M2 is turned off, SW = H (≒PVin). Conversely, when transistor M1 is turned off and transistor M2 is turned on, SW = L (≒PGND). Furthermore, when both transistors M1 and M2 are turned off, SW = HiZ (high impedance output state).

[0096] Alternatively, an N-channel MOS transistor can be used instead of a P-channel MOS transistor for transistor M1. However, in this case, a boost mechanism (charge pump circuit or bootstrap circuit) is required to make the H level of the gate signal G1 higher than the input voltage PVin.

[0097] In addition, transistors M1 and M2 can also be externally mounted on the rear section of the drive module 10.

[0098] The drive logic circuit 12 generates gate signals G1 and G2 in response to the control signal PWM and the zero-crossing detection signal ZX. Additionally, the control signal PWM is input from the power control device 20 via the control terminal TPWM. More specifically, the drive logic circuit 12 is essentially such that when PWM = H (e.g., Vcc), G1 = G2 = L, transistor M1 is on, and transistor M2 is off; conversely, when PWM = L (e.g., GND), G1 = G2 = H, transistor M1 is off, and transistor M2 is on.

[0099] However, during the conduction period of transistor M2 (PWM=L, G1=G2=H), as the logic level during zero-crossing detection, when the zero-crossing detection signal ZX is, for example, at level H, the drive logic circuit 12 is G1=H, G2=L, and both transistors M1 and M2 are in the off state.

[0100] The zero-crossing detection circuit 13 detects the zero-crossing of the inductor current IL flowing when transistor M2 is in the on state (i.e., the inductor current IL is at or near zero), and generates a zero-crossing detection signal ZX as its detection result. For example, the zero-crossing detection signal ZX is at level L when no zero-crossing is detected, and at level H when a zero-crossing is detected.

[0101] An enable signal DREN is input to the drive logic circuit 12 from the power control device 20 via the enable input terminal TEN. When DREN = H, the drive logic circuit 12 always operates in a pulse drive mode corresponding to the control signal PWM for the switching voltage SW.

[0102] Furthermore, when DREN = M, the drive logic circuit 12 sets the switching voltage SW to a high-impedance output state (HiZ) during zero-crossing detection of the inductor current IL, and instructs the logic level switching circuit 14 to switch the logic level. The instructed logic level switching circuit 14 switches the control signal PWM to an M level (e.g., Vcc / 2) that is neither H level (e.g., Vcc) nor L level (e.g., GND) (details will be described below).

[0103] In addition, the logic level switching circuit 14 also performs the action of switching the control signal PWM to M level when the drive module 10 starts (details will be described below).

[0104] The logic level fixing circuit 15 is a mechanism for transmitting identification information for each model of the power control device 20 (e.g., information used to identify whether the drive module 10 is a high-current output type or a low-current output type) (details will be described below).

[0105] The LDO16 is an example of an internal voltage generation unit that generates an internal voltage REG15 based on the power supply voltage Vcc. The internal voltage REG15 is supplied to the drive logic circuit 12, etc. Furthermore, the internal voltage REG15 is, for example, 1.5V, where REG15 = Vcc / 2.

[0106] The power-on reset unit 17 is a circuit that resets and releases the drive logic circuit 12 by means of a reset signal when the internal voltage REG15 rises during the startup of LDO16 reaches a specified voltage.

[0107] In addition to integrating the aforementioned circuit blocks, the drive module 10 may also integrate various protection circuits (UVLO, OCP, and TSD, etc.).

[0108] <Logic Level Fixed Circuit>

[0109] As described above, the drive module 10 is provided with a drop-down type ( Figure 3 ) or pull-up type ( Figure 4 The logic level fixed circuit 15 serves as a mechanism for notifying the power control device 20 of the identification information for each model. The structure and operation of each circuit will be explained below with reference to the figures.

[0110] Figure 3 This diagram illustrates a first configuration example (pull-down type) of the logic level fixed circuit 15. The logic level fixed circuit 15 in this configuration example is, for example, a circuit block integrated into a high-current output type (e.g., Io = 15A) drive module 10, including a resistor 151, an inverter 152, an N-channel MOS transistor 153, and an inverter 154.

[0111] Terminal 1 of resistor 151 is connected to the input terminal of the control signal PWM. Terminal 2 of resistor 151 is connected to the drain of transistor 153 via the input terminal of inverter 152. The output terminal of inverter 152 is connected to the input terminal of drive logic circuit 12. The source and back gate of transistor 153 are connected to the input terminal of ground voltage PGND. The gate of transistor 153 is connected to the output terminal of inverter 154. The input terminal of inverter 154 is connected to the input terminal of enable signal DREN.

[0112] When the enable signal DREN is at level H or level M (the logic level when the drive module 10 is started, such as Vcc or Vcc / 2), transistor 153 is turned off. Therefore, the control signal PWM is not pulled down and input to the drive logic circuit 12.

[0113] On the other hand, when the enable signal DREN is at level L (the logic level when the drive module 10 is disabled, such as GND), transistor 153 is turned on. Therefore, the control signal PWM is pulled down to level L (≒GND).

[0114] Figure 4 This diagram illustrates a second configuration example (pull-up type) of a logic level fixed circuit. The logic level fixed circuit 15 in this configuration example is, for example, a circuit block integrated into a low-current output type (e.g., Io = 5A) drive module 10, and includes a resistor 151, an inverter 152, and a P-channel MOS transistor 155.

[0115] Terminal 1 of resistor 151 is connected to the input terminal of the control signal PWM. Terminal 2 of resistor 151 is connected to the drain of transistor 155 via the input terminal of inverter 152. The output terminal of inverter 152 is connected to the input terminal of drive logic circuit 12. The source and back gate of transistor 155 are connected to the input terminal of power supply voltage Vcc. The gate of transistor 155 is connected to the input terminal of enable signal DREN.

[0116] When the enable signal DREN is at level H or level M (the logic level when the drive module 10 is started, such as Vcc or Vcc / 2), transistor 155 is turned off. Therefore, the control signal PWM is not pulled up and input to the drive logic circuit 12.

[0117] On the other hand, when the enable signal DREN is at level L (the logic level when the drive module 10 is disabled, such as GND), transistor 155 is turned on. Therefore, the control signal PWM is pulled up to level H (≒Vcc).

[0118] Thus, the logic level fixing circuit 15 fixes the control signal PWM to the logic level (H level or L level) of each model during the period when the drive module 10 is disabled (DREN=L), in other words, until the drive module 10 is enabled (DREN=H or DREN=M).

[0119] <Logic Level Switching Circuit (M-Level Output Circuit)>

[0120] Figure 5 This is a diagram illustrating one configuration example of a logic level switching circuit 14. The logic level switching circuit 14 includes a P-channel MOS transistor 141, a resistor 142, a P-channel MOS transistor 143, an N-channel MOS transistor 144, a P-channel MOS transistor 145, and an inverter 146.

[0121] The source and back gate of transistor 141 are connected to the power supply voltage Vcc. The gate of transistor 141 is connected to the output of inverter 146. The input of inverter 146 is connected to the enable signal DREN. The drain of transistor 141 is connected to the first terminal of resistor 142. Node N14, which connects the second terminal of resistor 142 to the source and back gate of transistor 143, is connected to the gate of transistor 144. The gate of transistor 143 is connected to the output of LDO 16. That is, the internal voltage REG15 output from LDO 16 is applied to the gate of transistor 143. The drain of transistor 143 is connected to the ground voltage PGND. The source and back gate of transistor 145 are connected to the power supply voltage Vcc. The drain of transistor 145 is connected to the drain of transistor 144. The source and back gate of transistor 144 are connected to the control signal PWM. The gate of transistor 145 is driven by the gate signal G12 output from the drive logic circuit 12.

[0122] In addition, such as Figure 5 As shown, the zero-crossing detection circuit 13 includes a comparator 131. The non-inverting input (+) of the comparator 131 is connected to the applied terminal of the switching voltage SW. The inverting input (-) of the comparator 131 is connected to the applied terminal of the ground voltage PGND.

[0123] During the conduction period of transistor M2 (PWM = L, G1 = G2 = H), when an inductor current IL flows in the positive direction (from transistor M2 towards inductor L1), ZX = L because SW < PGND. In this case, since the drive logic circuit 12 makes the gate signal G12 H, transistor 145 is in the off state, no drain current flows in transistor 144, and the state of PWM = L (e.g., GND) is maintained.

[0124] On the other hand, when the inductor current IL starts flowing in the negative direction (from inductor L1 towards transistor M2), ZX = H because SW > PGND. In this case, since the drive logic circuit 12 sets the gate signal G12 to L, transistor 145 is turned on, drain current flows through transistor 144, and its source is biased towards the intermediate voltage VM (= REG15 + Vth - Vth). Through this action, the control signal PWM switches from L level (GND) to M level (VM). M level = REG15 = Vcc / 2.

[0125] In addition, when the drive module 10 starts up, it also uses the drive logic circuit 12 to switch the control signal PWM to the M level. This will be described below.

[0126] <Input / Output Circuit>

[0127] Figure 6 This is a diagram illustrating one configuration example of the input / output circuit 22. The input / output circuit 22 of this configuration example includes a P-channel MOS transistor 221, N-channel MOS transistors 222 and 223, a resistor 224, and a logic level detection unit 225.

[0128] The source and back gate of transistor 221 are connected to the applied power supply voltage Vcc. The drains of transistors 221 and 222 are connected to the first terminal of resistor 224 at the input / output terminals of the control signal PWM. The second terminal of resistor 224 is connected to the drain of transistor 223. The source and back gate of transistors 222 and 223 are connected to the applied ground voltage GND.

[0129] In addition, gate signals S1 to S3 are input to the gates of transistors 221 to 223 from the control circuit 21.

[0130] For example, when the output control signal PWM is at level H, S1 = S2 = S3 = L. As a result, transistor 221 becomes on, while transistors 222 and 223 become off, so PWM = H (≒ Vcc). On the other hand, when the output control signal PWM is at level L, S1 = S2 = H and S3 = L. As a result, transistor 222 becomes on, while transistors 221 and 223 become off, so PWM = L (≒ GND).

[0131] Furthermore, when the PWM control signal is in standby mode, S1 = S3 = H and S2 = L. As a result, transistors 221 and 222 are off, and transistor 223 is on, so the PWM control signal is pulled down via resistor 224. Therefore, the PWM control signal becomes analogous to logic level switching circuit 14 (…). Figure 5 ) or logic level fixed circuit 15 ( Figure 3 , Figure 4 The logic level corresponding to the action state of the (details will be described below).

[0132] When the input / output circuit 22 is in input standby mode, the logic level detection unit 225 detects the logic level (H / L / M) of the control signal PWM and outputs the detection result as the logic level detection signal S4 to the control circuit 21.

[0133] <Startup Procedure>

[0134] Here, the startup sequence of the switching power supply device 1 is referred to... Figure 7 The flowchart shown and Figures 8-10 The timing diagram shown is used for illustration.

[0135] in addition, Figures 8-10 The waveforms of the power supply voltage Vcc, standby signal STBY, internal voltage Vreg15 (power control device 20), enable signal EN, status of control circuit 21, interrupt signal INTB, internal voltage REG15 (drive module 10), enable signal DREN, and control signals PWM1 to PWM8 are shown in order from top to bottom.

[0136] First, according to Figure 7 The flowchart shown is explained. Figure 8 The timing diagram shown. Figure 8 This indicates an example where the driver module scan described below is determined to be normal. Additionally, Figure 8 The connection configuration of the drive module 10 relative to the power control device 20 is as follows: Figure 1 The situation shown is as follows (that is, 4 drive modules 10 are connected).

[0137] exist Figure 8 At time t1, the power supply voltage Vcc begins to rise. Then, at time t2, when the power supply voltage Vcc reaches the UVLO release voltage, UVLO in the power control device 20 is released. Afterwards, at time t3, when the standby signal STBY rises to level H, the internal voltage Vreg15 begins to rise. Correspondingly, the control signals PWM5 to PWM8 generated by the control terminals Tp5 to Tp8 connected to the application terminal of the internal voltage Vreg15 also begin to rise. If the internal voltage Vreg15 rises to 1.5V, then the control signals PWM5 to PWM8 also rise to 1.5V.

[0138] Furthermore, at time t4, control circuit 21 transitions to the drive module scan state (DrMOS_SCAN). Figure 7 Step S1).

[0139] Subsequently, at time t5, control circuit 21 begins driving the module to perform a check process. Figure 7 Step S2). At time t5, the enable signal DREN is at level L. Here, Figure 8 In the example, the logic level fixing circuit 15 in the driver module 10 is a pull-down type. Figure 3 In this case, control signals PWM1 to PWM4 are pulled down to L level. Furthermore, control signals PWM5 to PWM8 are all set to 1.5V (M level).

[0140] During the drive module configuration check process, the control circuit 21 checks whether any of the control terminals Tp1 to Tp8 are used to connect to the drive module 10. More specifically, the control circuit 21 confirms whether the combination of the levels of the control signals PWM1 to PWM8 is consistent with the pre-defined allowed combination. At this time, since the input / output circuit 22 of the power control device 20 is in the input standby state, the logic level (H / L / M) of the control signal PWM is detected.

[0141] For example, when connecting one drive module 10, only control terminal Tp1 among control terminals Tp1 to Tp8 is allowed to be connected. Therefore, as a permissible combination of control signal levels, "control signal PWM = L or H, control signal other than PWM1 = M". Furthermore, when connecting two drive modules 10, only control terminals Tp1 and Tp2 among control terminals Tp1 to Tp8 are allowed to be connected. Therefore, as a permissible combination of control signal levels, "control signals PWM1 and PWM2 both = L or both = H, control signal other than PWM1 and PWM2 = M". Similarly, the permissible combinations for connecting up to eight drive modules 10 are pre-defined below.

[0142] If it is Figure 8 In the example, if the actual control signal PWM level combination is consistent with the allowed combinations such as "PWM1~4=L,PWM5~8=M" or "PWM1~4 all=L or all=H,Control signals other than PWM1~4=M", then it is determined that the control terminals Tp1~Tp4 are used for connection and no other terminals are used.

[0143] Here, since PWM=L, logic level fixing circuit 15 is a pull-down type ( Figure 3 Therefore, for example, the drive module 10 can be identified as a high-current output type. On the other hand, since the logic level fixing circuit 15 is a pull-up type when PWM=H, Figure 4 Therefore, for example, it is possible to identify the drive module 10 as a low-current output type. If it is Figure 8For example, if PWM1~4 = L, then it can be determined that each drive module 10 connected to the control terminals Tp1~Tp4 is a high-current output type. Furthermore, setting the allowed level combinations "all" to L or "all" to H, as described above, is to prevent the connection and use of some different models of drive modules 10.

[0144] By identifying the model of this drive module 10, the control parameters of the power control device 20 (such as the feedback coefficient or phase compensation amount of the output current feedback loop) can be switched to the optimal value.

[0145] Furthermore, since the actual number of driving phases can be determined ( Figure 8 In the example, there are 4 phases, so corresponding phase shift control can be performed (details will be described below).

[0146] Figure 8 In the above-mentioned process, the drive module configuration check ends at time t6. In this case, the drive module configuration is determined to be normal. Figure 7 If step S3 is "Yes" (Y), the control circuit 21 transfers to the drive module connection check process. Figure 7 Step S4).

[0147] Here, even if the drive module configuration check process determines that it is normal, a connection problem may still occur at the control terminals (Tp1 to Tp8). For example, the connection between the control terminals and the drive module 10 may be broken, or the control terminals may have an open circuit fault. In such cases, during the drive module configuration check process, the level of the control signal may occasionally be the level that is considered normal. Figure 8 For example, even though at least one of the control terminals Tp1 to Tp4 actually has a poor connection, the level of the control signals PWM1 to PWM4 may occasionally become L.

[0148] Therefore, in this embodiment, after the drive module configuration check process, the drive module connection check process is performed to confirm whether there is a connection problem with the control terminal. Figure 8 If the drive module connection check process begins, then at time t7, the control circuit 21 causes the enable signal DREN to rise to the M level. Consequently, LDP16 in the drive module 10 starts, and the internal voltage REG15 begins to rise.

[0149] Using the enable signal DREN, which becomes the M level, logic level switching circuit 14 ( Figure 5In the circuit 14, transistor 141 is turned on. This causes the constant current circuit, which includes transistor 141 and resistor 142, to conduct. Furthermore, because the internal voltage REG15 rises to 1.5V, the voltage at the gate of transistor 143 in the logic level switching circuit 14 (= internal voltage REG15) also rises to 1.5V.

[0150] When the internal voltage REG15 reaches a specified voltage below 1.5V, the power-on reset unit 17 uses a reset signal to release the reset of the drive logic circuit 12. At this time, after the internal processing time of the power-on reset unit 17 following the delay from when the internal voltage REG15 reaches the specified voltage, the drive logic circuit 12 is released from reset.

[0151] When the reset of the drive logic circuit 12 is released at time t8, the drive logic circuit 12 outputs the L-level gate signal G12 to the logic level switching circuit 14. As a result, transistor 145 is turned on, and the control signal PWM is switched to M level.

[0152] At this time, since the input / output circuit 22 of the power control device 20 is in the input standby state, the logic level (H / L / M) of the control signal PWM is detected. The control circuit 21 confirms whether all the control signals PWM of the control terminals used in the previous drive module configuration check process are at the M level. If all are at the M level, it is determined that there is no connection problem at the control terminals used, and the condition is normal. Figure 8 In the example, since the control signals PWM1 to PWM4 of the control terminals Tp1 to Tp4 are all at the M level, it is determined to be in a normal state.

[0153] Furthermore, after the drive logic circuit 12 sets the gate signal G12 to L level, it switches to H level. Therefore, the control signal PWM remains at M level only by utilizing the source capability of the logic level switching circuit 14. Thus, it does not interfere with the behavior of the subsequent control signal PWM.

[0154] Figure 8 At time t9, the control circuit 21 causes the enable signal DREN to drop to the L level, so LDO16 stops and the internal voltage REG15 drops. As a result, the drive logic circuit 12 is reset by the power-on reset unit 17. In addition, since the enable signal DREN is dropped to the L level, the control signals PWM1 to PWM4 become the L level through the logic level fixing circuit 15.

[0155] like Figure 8 As shown, when the driver module connection check process determines that it is normal ( Figure 7 Step S5 is yes), the control circuit 21 switches to standby mode. Figure 7Step S6, time point t10).

[0156] Subsequently, when the enable signal EN rises to level H, the control circuit 21 transitions to the power-on state (POWER_ON). Figure 7 Step S7, time point t11). Furthermore... Figure 8 After transitioning to the power-on state, at time t12, the control circuit 21 causes the enable signal DREN to rise to the M level. Then, similar to the operation at time t7, the internal voltage REG15 begins to rise, and at time t13, delayed from time t12, the power-on reset unit 17 releases the reset of the drive logic circuit 12. Consequently, as described above, based on the L-level gate signal G12 output by the drive logic circuit 12, the logic level switching circuit 14 switches the control signal PWM to the M level. Furthermore, after the drive logic circuit 12 sets the gate signal G12 to the L level, it switches to the H level. Thus, the control signal PWM is maintained at the M level solely using the source capability of the logic level switching circuit 14. Therefore, it does not interfere with the subsequent behavior of the control signal PWM.

[0157] At time t14, which is later than time t13, control circuit 21 causes the enable signal DREN to rise to level H. Therefore, the input / output circuit 22 of power control device 20 is fixed in the aforementioned output state (= Figure 6 The transistor 223 is turned off, and the logic level detection unit 225 is in an invalid state. Furthermore, the drive logic circuit 12 operates in the first operating mode (i.e., the operating mode that continuously drives the switching voltage SW according to the control signal PWM pulse). Switching pulses of the control signal PWM are continuously generated at a fixed switching frequency, and the drive logic circuit 12 drives the switching output stage 11 according to the level of the control signal PWM. Therefore, even if the load Z becomes lighter, the switching power supply device 1 will not switch from the heavy load mode (PWM mode) to the light load mode (PFM mode).

[0158] In another place, such as Figure 8 As shown, phase shift control is performed, that is, a control signal PWM is generated while shifting the phase.

[0159] also, Figure 8 Although not illustrated, when the enable signal DREN switches from H level to M level, the drive module 10 starts in the second operating mode (when the zero crossover detection of the inductor current IL is performed, the control signal PWM automatically switches to M level, and the switching voltage SW automatically becomes the output high impedance state (Hiz) operating mode).

[0160] In the aforementioned case, after the control signal PWM switches from H level to L level, the input / output circuit 22 of the power control device 20 switches to the input standby state at an appropriate time point, becoming a state that detects the logic level (H / L / M) of the control signal PWM.

[0161] Since the control signal PWM is at level L, when transistor M2 is in the on state, the zero-crossing detection signal ZX rises to level H. When the zero-crossing of the switching voltage SW is detected, the drive logic circuit 12 makes the gate signal G12 become level L. Therefore, the logic level switching circuit 14 switches the control signal PWM to level M.

[0162] When the control signal PWM switches from L level to M level, the control circuit 21 detects the zero-crossing of the inductor current IL in the drive module 10, enabling the switching power supply device 1 to switch from heavy load mode (PWM mode) to light load mode (PFW mode) without delay. Therefore, it can reduce the switching pulses of the control signal PWM and improve efficiency under light load.

[0163] Furthermore, when the drive module 10 is started in the second operating mode (DREN=M), as long as the zero crossover detection signal ZX rises to the H level, the control signal PWM does not need to be switched to the M level, and the switching power supply device 1 does not need to switch from the heavy load mode (PWM mode) to the light load mode (PFM mode).

[0164] Next, regarding Figure 9 The timing diagram shown is used for illustration. Figure 9 During the process, the drive module begins its check at time t51. However, due to a faulty connection at control terminal Tp3, the control signal PWM3 will not reach the low level. Therefore, control circuit 21 determines that the level combinations of control signals PWM1 to PWM8 do not match any of the pre-defined allowed combinations, classifying it as an abnormal state. Figure 7 Step S3 is not (N, No)).

[0165] thus, Figure 9 At time t52, control circuit 21 transitions to an error state (ERROR) and turns on MOS switch 24, thereby causing the interrupt signal INTB to drop to the L level. The interrupt signal INTB serves as an external notification of the abnormality.

[0166] After that, as Figure 9 As shown, although the enable signal EN rises to the H level (time point t110), the control circuit 21 is still in an error state. Therefore, the enable signal DREN is maintained at the L level, so that the drive module 10 does not start and does not perform the switching action of the switching power supply device 1.

[0167] Furthermore, even when, for example, a drive module 10 with a pull-up logic level fixing circuit 15 is connected to the control terminal Tp3 corresponding to the control signal PWM3, the control signal PWM3 is at level H, so during the drive module configuration check process, it is determined to be an abnormal state.

[0168] Thus, during the drive module configuration inspection process, when it is determined that the control terminal is in an unauthorized usage state, the switching action of the switching power supply device 1 can be avoided.

[0169] Next, regarding Figure 10 The timing diagram shown is used for illustration. Figure 10 During the process, the drive module begins its check and processing at time t51. However, at this time, all control signals PWM1 to PWM4 are at low level. Therefore, control circuit 21 determines that the combination of each level of control signals PWM1 to PWM8 is consistent with the pre-defined allowed combination, and judges it as a normal state. Figure 7 Step S3 is (Yes).

[0170] However, Figure 10 In the example shown, the control terminal Tp4 of the control signal PWM4 actually has a poor connection. During the check process of the drive module, the control signal PWM4 occasionally becomes L level.

[0171] At time t53, the driver module configuration check process ends, and the driver module connection check process begins. Figure 7 Step S4). At time t71, the enable signal DREN rises to level M, and through the reset drive logic circuit 12, the logic level switching circuit 14 switches the control signal PWM to level M (time t81). However, Figure 10 As mentioned above, due to a poor connection at control terminal Tp4, the control signal PWM4 experiences an abnormal drop in level from level M. Therefore, control circuit 21 is determined to be in an abnormal state. Figure 7 No (N) in step S5.

[0172] After the control circuit 21 causes the enable signal DERN to drop to the L level, it transitions to the error state at time t82. Figure 7 Step S8).

[0173] Because of the transition to the error state, even if the enable signal EN rises to the H level (at time t110), the control circuit 21 will maintain the enable signal DREN at the L level, preventing the drive module 10 from starting and the switching operation of the power supply device 1 from being performed.

[0174] In this way, even if the drive module configuration check process occasionally determines that the connection is normal, the connection failure can still be detected in the drive module connection check process if the control terminal has a poor connection, thus preventing the switching action of the power supply device 1.

[0175] As explained above, in this embodiment, by misappropriating the control signal PWM to perform drive module configuration check processing and drive module connection check processing, it is possible to confirm the usage status of the control terminals, the model of the connected drive module, and whether there are any control terminal connection problems. Furthermore, the control signal PWM can be misappropriated to perform zero-crossing detection notification from the drive module 10 to the power control device 20. Therefore, it is possible to suppress the increase in the number of terminals of the power control device 20 and the drive module 10.

[0176] Multi-channel power control device

[0177] Furthermore, as a variation of the implementation, the power control device 20 can also control the drive module 10 in the multi-channel configuration. This will be explained below.

[0178] Figure 11 This is a diagram illustrating the configuration of a switching power supply device 1, which includes a power control device 20 for controlling the drive module 10 in multiple channels. Figure 11 The power control device 20 shown is an example, corresponding to 2 channels. Furthermore, a channel refers to the number of times an enable signal DREN can be output.

[0179] Figure 11 The power control device 20 shown has enable output terminals Tden1 and Tden2. The control circuit 21 can output an enable signal DREN1 from the enable output terminal Tden1 and an enable signal DREN2 from the enable output terminal Tden2. Furthermore... Figure 11 The power control device 20, for example, has control terminals Tp1 to Tp4, and can output control signals PWM1 to PWM4 via the control terminals Tp1 to Tp4. In other words, the power control device 20 can use two channels to control the four-phase drive module 10.

[0180] also, Figure 11 In this example, control terminals Tp1 to Tp3 are connected to drive modules 10(1) to 10(3) which are connected to the enable output terminal Tden1 (1ch). In addition, control terminal Tp4 is connected to drive module 10(4) which is connected to the enable output terminal Tden2 (2ch). That is, 3 phases (1ch) + 1 phase (2ch) are used.

[0181] Drive modules 10(1) to 10(3), which are in the same channel (1ch), are connected to the first terminals of inductors L1(1) to L1(3), respectively. The second terminals of inductors L1(1) to L1(3) are all connected to the first terminal of capacitor Co1. The first terminal of capacitor Co1 becomes the application terminal of output voltage Vout1. In addition, drive module 10(4), which is in the same channel (2ch), is connected to the first terminal of inductor L1(4). The second terminal of inductor L1(4) is all connected to the first terminal of capacitor Co2. The first terminal of capacitor Co2 becomes the application terminal of output voltage Vout2. That is to say, each channel constitutes a DC / DC converter.

[0182] In addition, Figure 11 In addition to the configuration shown, other connection configurations of the drive module 10, such as 4-phase (1ch) + 0-phase (2ch not used) or 2-phase (1ch) + 2-phase (2ch), can also be used. Furthermore, for the unused terminals among the control terminals Tp1 to Tp4, the internal voltage Vreg15 can be connected to the terminal for application, just as in the embodiment described above, to set the control signal PWM to the M level.

[0183] Here, Figure 12 It means Figure 11 The timing diagram shows an example of the startup sequence in the configuration. Figure 12 The waveforms of the internal voltage REG15, enable signals DREN1 and DREN2, and control signals PWM1 to PWM4 on the drive module 10 side are shown in order from top to bottom.

[0184] exist Figure 12 At time t15, the drive module configuration check process begins. At this time, since both enable signals DREN1 and DREN2 are at low level, the logic level fixing circuit 15 on the drive module 10 side notifies the control circuit 21 of the level of control signals PWM1 to PWM4 via the input / output circuit 22 which is in input standby state. Figure 12 In, it means Figure 11 In the configuration shown, the drive modules 10(1) to 10(4) all have examples of pull-down logic level fixed circuits 15, and the control signals PWM1 to PWM4 are all at the L level.

[0185] During the drive module configuration check process, as described above, the control circuit 21 confirms whether the combination of the levels of the control signal PWM is consistent with the allowed combination. Figure 12 In this case, since the combination of control signals PWM1 to PWM4 all being L is consistent with the allowed combination, it is determined to be a normal state. Alternatively, if the combination of control signals PWM1 to PWM4 is inconsistent with the allowed combination, it is determined to be an abnormal state, and similarly to the previous implementation, the control circuit 21 transitions to an error state.

[0186] Figure 12 At time t16, the drive module configuration check process ends, and then the drive module connection check process begins. Then, at time t17, the control circuit 21 only raises DREN1 of the enable signals DREN1 and DREN2 to the M level. As a result, the internal voltage REG15 of each drive module 10(1) to 10(3) corresponding to the enable signal DREN1 rises, the reset of each drive logic circuit 12 is released, and the control signals PWM1 to PWM3 are switched to the M level through each logic level switching circuit 14. As a result, the drive module 10 that can be identified is connected to the control terminals Tp1 to Tp3.

[0187] At time t19, using control circuit 21, enable signal DREN1 drops to L level, and control signals PWM1 to PWM3 drop to L level. Then, at time t20, control circuit 21 only raises DREN2 of enable signals DREN1 and DREN2 to M level. As a result, the internal voltage REG15 in drive module 10(4) corresponding to enable signal DREN2 rises, the drive logic circuit 12 is reset, and the logic level switching circuit 14 switches control signal PWM4 to M level (time t21). Thus, drive module 10, which can identify 2ch, is connected to control terminal Tp4.

[0188] Thus, in this embodiment, by misappropriating the control signal PWM, the number of drive modules 10 or connection terminals of each channel can be automatically identified, and the increase in the number of terminals of the power control device 20 and the drive modules 10 can be suppressed. For example, in the power control device 20, the following method is also considered: setting a new setting terminal, applying a divided voltage to the terminal by changing the external resistor voltage division ratio, monitoring the divided voltage using the ADC (AD converter) inside the power control device 20, thereby detecting the connection status, but the number of terminals will increase accordingly with the new number of terminals.

[0189] Furthermore, in this embodiment, even if the number of channels or phases increases, there is no need to increase the number of terminals.

[0190] <Other>

[0191] Furthermore, the various technical features disclosed in this specification, in addition to the described embodiments, can be modified in various ways without departing from the spirit of the invention. That is, all aspects of the described embodiments should be considered illustrative rather than restrictive, and it should be understood that the technical scope of the invention is not limited to the described embodiments, but includes all modifications within the scope and meaning equivalent to the claims.

[0192] For example, in the drive module connection check process, it is not limited to the control circuit 21 setting the enable signal DREN (DREN1, DREN2) to the M level. As long as it is a level that can start the drive module 10, it can also rise to, for example, the H level.

[0193] Furthermore, the switching power supply device of the present invention is preferably designed for use in vehicles, for example. From the perspective of the fact that fault detection related to control terminals is required by the international standard ISO 26262 for functional safety of automotive electrical / electronic components, the effectiveness of the present invention is significant.

[0194] [Industry availability]

[0195] The present invention can be used in, for example, multiphase switching power supply devices for supplying power to loads (such as CPUs) that consume large current.

[0196] [Symbol Explanation]

[0197] 1 Switching power supply device

[0198] 10, 10(1)~10(4) DrMOS Drive Module

[0199] 11 Switching Output Stage

[0200] 12. Driver Logic Circuit

[0201] 13 Zero-crossing detection circuit

[0202] 131 comparator

[0203] 14 Logic Level Switching Circuit

[0204] 141 P-channel MOS transistor

[0205] 142 resistor

[0206] 143 P-channel MOS transistor

[0207] 144 N-channel MOS transistor

[0208] 145 P-channel MOS transistor

[0209] 146 Inverter

[0210] 15. Fixed logic level circuit

[0211] 151 resistor

[0212] 152 Inverter

[0213] 153 N-channel MOS transistor

[0214] 154 inverters

[0215] 155 P-channel MOS transistor

[0216] 16 LDO

[0217] 17 Power-on reset section

[0218] 20 Power Control Device (PMIC)

[0219] 21 Control Circuit

[0220] 22 Input / Output Circuit

[0221] 221 P-channel MOS transistor

[0222] 222, 223 N-channel MOS transistors

[0223] 224 resistor

[0224] 225 Logic Level Detection Unit

[0225] 23 Internal voltage generation unit

[0226] 24 MOS Switch (N-channel MOS Transistor)

[0227] Co capacitor

[0228] L1, L1(1)~L1(4) inductors

[0229] M1 Output Transistor (P-channel MO Transistor)

[0230] M2 Synchronous Rectifier Transistor (N-channel MOS Transistor)

[0231] Tp1~Tp8 control terminals

[0232] Tden, Tden1, Tden2 Enable Output Terminals

[0233] Tcc power terminals

[0234] Tst standby terminal

[0235] Ten Enable Input Terminal

[0236] Treg internal voltage output terminal

[0237] Tregin internal voltage input terminals

[0238] Tint interrupt terminal

[0239] Tgd grounding terminal

[0240] Ts+, Ts- Feedback Input Terminals

[0241] TPWM control terminals

[0242] TEN Enable Input Terminal

[0243] TCC power terminals

[0244] TVIN Input Voltage Terminal

[0245] TSW switch terminals

[0246] TGD grounding terminal.

Claims

1. A power supply control device used with a drive module that drives on / off of an output transistor and a synchronous rectification transistor, and having: a control terminal for inputting and outputting a control signal to and from the drive module; an enable output terminal for outputting an enable signal to the drive module; a control circuit; and an input / output circuit that makes the control signal a first logic level when the output transistor is made on and the synchronous rectification transistor is made off, makes the control signal a second logic level when the output transistor is made off and the synchronous rectification transistor is made on, and can become an input standby state according to an instruction from the control circuit; and the control circuit, when the input / output circuit is in the input standby state, transmits an enable signal for activating a level of the drive module to the drive module, and confirms whether the control signal is a third logic level that is neither the first logic level nor the second logic level.

2. The power supply control device according to claim 1, wherein the enable signal can be any one of a low level, a high level, and an M level between the low level and the high level, and the level for activating the drive module is the M level.

3. The power supply control device according to claim 1 or 2, wherein when the input / output circuit is in the input standby state and the enable signal is a level indicating prohibition, the control circuit confirms that the control signal becomes the first logic level or the second logic level, and then transmits an enable signal for activating a level of the drive module to the drive module.

4. The power supply control device according to claim 3, wherein the control terminal is plural, and when the input / output circuit is in the input standby state and the enable signal is a level indicating prohibition, the control circuit confirms whether a combination of levels of the control signals coincides with an allowed combination.

5. The power supply control device according to claim 4, wherein an application terminal of a voltage of the third logic level is connected to the control terminal that is not used in connection with the drive module.

6. The power supply control device according to claim 1 or 2, wherein the enable output terminal is plural, and the control terminal is plural.

7. A drive module that drives on / off of an output transistor and a synchronous rectification transistor, and has, in a manner integrated as a single package: a drive logic circuit that makes the output transistor on and the synchronous rectification transistor off when a control signal is a first logic level, and makes the output transistor off and the synchronous rectification transistor on when the control signal is a second logic level; an internal voltage generation section that generates an internal voltage using an enable signal for activation; a power-on reset section that releases a reset of the drive logic circuit based on the internal voltage; and ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The logic level switching circuit, upon reset release, switches the control signal to a third logic level that is neither the first logic level nor the second logic level, according to an instruction from the driving logic circuit.

8. The driving module according to claim 7, wherein The logic level switching circuit has the following features: The first P-channel MOS transistor has a gate driven by the enable signal and a source connected to the power supply voltage application terminal; A resistor having a first terminal connected to the drain of the first P-channel MOS transistor; The second P-channel MOS transistor has a source connected to the second terminal of the resistor, a drain connected to the applied terminal of the ground voltage, and a gate driven by the internal voltage. An N-channel MOS transistor has a gate connected to a node that connects the second terminal of the resistor to the source of the second P-channel MOS transistor, and a source connected to the terminal where the control signal is applied. and The third P-channel MOS transistor has a source connected to the power supply voltage application terminal, a drain connected to the drain of the N-channel MOS transistor, and a gate to which a gate signal output from the drive logic circuit is applied.

9. The drive module according to claim 7 or 8, further comprising a logic level fixing circuit, wherein the logic level fixing circuit fixes the control signal to the logic level of each model when the enable signal indicates prohibition.

10. The drive module according to claim 7 or 8, further comprising a zero-crossing detection circuit that detects zero-crossing of the inductor current flowing when the synchronous rectifier transistor is in the on state. When the zero-crossing is detected, the logic level switching circuit switches the control signal to the third logic level according to the instruction from the driving logic circuit.

11. The drive module according to claim 7 or 8, which also has the output transistor and the synchronous rectifier transistor integrated into the package.

12. A switching power supply device, comprising a drive module and a power control device, wherein the drive module drives the output transistor and the synchronous rectifier transistor to turn on / off, and The power control device has: Control terminals are used to input and output control signals between the driver module and the driver module. The enable output terminal is used to output an enable signal to the drive module; Control circuit; and The input / output circuit, in order to turn the output transistor and the synchronous rectifier transistor on and off, can set the control signal to the first logic level or the second logic level, and become an input standby state according to the instruction from the control circuit; When the input / output circuit is in the input standby state, the control circuit transmits an enable signal of the level used to start the drive module to the drive module, and confirms whether the control signal is a third logic level that is neither the first logic level nor the second logic level. The driver module is integrated into a single package and has the following features: drive logic circuitry which, when the control signal is the first logic level, causes the output transistor to be in an on state and the synchronous rectification transistor to be in an off state, and which, when the control signal is a second logic level, causes the output transistor to be in an off state and the synchronous rectification transistor to be in an on state; internal voltage generation section which generates an internal voltage and activates using the enable signal; power-on reset section which, based on the internal voltage, releases a reset of the drive logic circuitry; and logic level switching circuitry which, upon release of the reset, switches the control signal to the third logic level in accordance with an instruction from the drive logic circuitry. ​

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