Method for controlling dead time of pwm signal, controller and related electronic device

Abstract

This invention discloses a method, controller, and related electronic equipment for controlling the dead time of a PWM signal. The method includes the following steps: S1, starting a first PWM waveform generator to output a first signal; the first PWM waveform generator is negative polarity; S2, waiting for a predetermined time; S3, starting a second PWM waveform generator to output a second signal; the second PWM waveform generator is positive polarity. This invention ensures that after the falling edge of the first signal output by the first PWM signal generator appears, a dead time is waited before the second PWM signal generator outputs a high level signal. Furthermore, by controlling the duty cycle of the output signals of the two PWM signal generators, it is guaranteed that at least a dead time elapses after the falling edge of the second signal before the first signal appears high. The two dead times ensure that the signals output by the two PWM signal generators will not be simultaneously high.

Description

Technical Field

[0001] This invention relates to a method for controlling the dead time of a PWM signal, and also to a controller and related electronic equipment for controlling the dead time of a PWM signal, belonging to the field of electrical pulse technology. Background Technology

[0002] PWM (Pulse Width Modulation) is an abbreviation for pulse width modulation. It modulates the width of a series of pulses to produce the desired waveform (including shape and amplitude), digitally encoding the analog signal level. In other words, it regulates changes in signal and energy by adjusting the duty cycle.

[0003] In recent years, the smart home industry has become a new hot trend. In the smart home field, PWM (Pulse Width Modulation) applications are becoming increasingly widespread, such as in smart lighting. The requirements for PWM signals in smart homes are also becoming more stringent. Smart home appliances often use two power devices, one before and one after. Power devices generally experience a delay in switching on / off due to junction capacitance. This delay can cause the two devices to turn on simultaneously, resulting in high current and potential damage to the equipment. To precisely control the dead time, smart home appliances often use PWM signals to control the power devices. Dead time is a protective time designed to prevent the two devices from turning on simultaneously. If the dead time is too small, there is still a risk of high current due to inter-chip differences; if the dead time is too large, it will reduce the efficiency of the power devices.

[0004] Chinese invention patent CN110557013B discloses a PWM dead-time control system. This system includes a controllable charging / discharging current generation module, a dead-time generation module, and a logic circuit module, primarily utilizing analog circuitry to generate and control the PWM dead time. However, this system employs a relatively large number of PMOS transistors, NMOS transistors, and logic gates, resulting in a complex circuit. How to control the dead time of two PWM signal generators with fewer components remains a pressing problem in this field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for controlling the dead time of a PWM signal.

[0006] Another technical problem to be solved by the present invention is a controller for controlling the dead time of a PWM signal.

[0007] Another technical problem to be solved by the present invention is to provide an electronic device for controlling the dead time of a PWM signal.

[0008] According to a first aspect of the present invention, a method for controlling the dead time of a PWM signal is provided, comprising the following steps:

[0009] Step S1: Start the first PWM waveform generator so that the first PWM waveform generator outputs a first signal; the first PWM waveform generator is negative polarity;

[0010] Step S2, wait for the scheduled time;

[0011] Step S3: Start the second PWM waveform generator so that the second PWM waveform generator outputs a second signal; the second PWM waveform generator is positive.

[0012] Wherein, the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time of execution step S3; the dead time, the duty cycle of the first signal, and the duty cycle of the second signal satisfy the following condition: D1+D2+(2×T1) / T2≤1; where D1 is the duty cycle of the first signal, D2 is the duty cycle of the second signal, T1 is the dead time, and T2 is the period of the first signal.

[0013] The preferred step, S2, includes the following steps:

[0014] Use a loop to wait for a predetermined time;

[0015] The preferred step, S3, includes the following steps:

[0016] Enable the second PWM waveform generator;

[0017] In a preferred embodiment, the following steps are included before step S1:

[0018] Initialize the second PWM waveform generator;

[0019] Configure the frequency and duty cycle of the second PWM waveform generator.

[0020] In a preferred embodiment, the following steps are included before step S1:

[0021] Read the first control value from the control register of the second PWM waveform generator into the buffer;

[0022] Rewrite the first control value in the cache with the second control value;

[0023] To enable the second PWM waveform generator, the following steps are included:

[0024] Write the second control value into the control register of the second PWM waveform generator;

[0025] In the first control value, the control bit used to enable the PWM waveform generator is in a disabled state, while in the second control value, the control bit used to enable the PWM waveform generator is in an enabled state.

[0026] According to a second aspect of the present invention, a controller for controlling the dead time of a PWM signal is provided, comprising:

[0027] The first startup module is used to start the first PWM waveform generator so that the first PWM waveform generator outputs a first signal; the first PWM waveform generator is negative polarity.

[0028] The waiting module is used to wait for a scheduled time.

[0029] The second startup module is used to start the second PWM waveform generator so that the second PWM waveform generator outputs a second signal; the second PWM waveform generator is positive.

[0030] Wherein, the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time of execution step S3; the dead time, the duty cycle of the first signal, and the duty cycle of the second signal satisfy the following condition: D1+D2+(2×T1) / T2≤1; where D1 is the duty cycle of the first signal, D2 is the duty cycle of the second signal, T1 is the dead time, and T2 is the period of the first signal.

[0031] Among the better waiting modules are:

[0032] The wait submodule is used to wait for a predetermined time using loop statements;

[0033] The preferred second startup module includes:

[0034] The enable submodule is used to enable the second PWM waveform generator;

[0035] In a preferred embodiment, the controller further includes:

[0036] An initialization module is used to initialize the second PWM waveform generator.

[0037] The configuration module is used to configure the frequency and duty cycle of the second PWM waveform generator.

[0038] In a preferred embodiment, the controller further includes:

[0039] The read module is used to read the first control value of the control register of the second PWM waveform generator into the buffer;

[0040] The rewrite module is used to rewrite the first control value in the cache to the second control value;

[0041] The enabling submodule includes:

[0042] The write submodule is used to write the second control value into the control register of the second PWM waveform generator;

[0043] In the first control value, the control bit used to enable the PWM waveform generator is in a disabled state, while in the second control value, the control bit used to enable the PWM waveform generator is in an enabled state.

[0044] According to a third aspect of the present invention, an electronic device is provided, comprising any of the controllers described above.

[0045] Compared with the prior art, the present invention, after the falling edge of the first signal output by the first PWM signal generator appears, waits for a dead time before allowing the second PWM signal generator to output a high level of the second signal. Furthermore, by controlling the duty cycle of the output signals of the two PWM signal generators, it is ensured that at least a dead time has elapsed after the falling edge of the second signal before the first signal appears at a high level. The two dead times ensure that the signals output by the two PWM signal generators will not be at a high level simultaneously. Attached Figure Description

[0046] Figure 1 A flowchart of a method for controlling the dead time of a PWM signal provided by the present invention;

[0047] Figure 2 This is a schematic diagram illustrating the arrangement of two dead time zones in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram illustrating the time consumed in step S3 in an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram illustrating the time difference between the output waveforms of two PWM signal generators that are started consecutively in the prior art.

[0050] Figure 5 A schematic diagram of a controller for controlling the dead time of a PWM signal provided by the present invention;

[0051] Figure 6 This is a flowchart illustrating the method for controlling the dead time of a PWM signal in intelligent lighting fixtures. Detailed Implementation

[0052] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0053] Figure 1 A flowchart illustrating a method for controlling the dead time of a PWM signal according to a first embodiment of the present invention. The method includes at least the following steps:

[0054] Step S1: Start the first PWM waveform generator so that the first PWM waveform generator outputs a first signal; the first PWM waveform generator is negative polarity;

[0055] Step S2, wait for the scheduled time;

[0056] Step S3: Start the second PWM waveform generator so that the second PWM waveform generator outputs a second signal; the second PWM waveform generator is positive.

[0057] Wherein, the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time of execution step S3; the dead time, the duty cycle of the first signal, and the duty cycle of the second signal satisfy the following condition: D1+D2+(2×T1) / T2≤1; where D1 is the duty cycle of the first signal, D2 is the duty cycle of the second signal, T1 is the dead time, and T2 is the period of the first signal.

[0058] The executing entity of this invention is a controller (Central Processing Unit), which controls the startup of the PWM waveform generator through instructions. The two PWM waveform generators in this invention operate at the same frequency.

[0059] PWM waveform generators are divided into negative and positive polarity types. A negative polarity PWM waveform generator outputs a low-level signal upon startup (generating a falling edge from high to low), while a positive polarity PWM waveform generator outputs a high-level signal upon startup (generating a rising edge from low to high). Furthermore, the signals output by both PWM waveform generators have the same frequency. Therefore, as long as the first and second signals in one cycle meet the dead-time requirement, the first and second signals in all subsequent cycles will also meet the dead-time requirement.

[0060] In certain application scenarios, devices controlled by two PWM signals cannot operate simultaneously. For example, due to power supply limitations, two LED bulbs in a lighting fixture, each controlled by a separate PWM signal generator, cannot operate at the same time. If they operate simultaneously (dead zone), neither bulb will operate at full power, resulting in dim brightness or other malfunctions. In this case, the two PWM signal generators need to coordinate. When one PWM signal generator outputs a high level to activate a relay and turn on a bulb, the other PWM signal generator must output a low level to turn off the other bulb.

[0061] Logically, the controller should avoid this situation when controlling the output signals of two PWM waveform generators (the control logic of the two PWM signal generators should not be high at the same time). However, objectively, hardware limitations may cause the output signal of one PWM signal generator to be in an uncertain state for a certain period of time. For example, when the controller controls the first signal to have a falling edge, the signal cannot immediately change from high to low level; there is a switching process, during which the output signal is in an uncertain state. If, during this period, the other PWM signal generator outputs a high-level signal, it is possible that both PWM signal generators output high levels simultaneously. Therefore, it is usually necessary to wait for the uncertain signal to stabilize at a low level before changing the other signal to a high level. This waiting period is called the dead time. In short, the dead time is the time that one PWM signal generator must wait for the output signal of the other signal generator to stabilize from high to low level before outputting a high-level signal.

[0062] In practical applications, the dead time may be longer than the time it takes for a signal to stabilize from high to low and output a stable low level. This is because the purpose of dead time is to prevent two power devices controlled by PWM signals from operating simultaneously. PWM signals are typically used to control the switching of power devices. Even if the PWM signal is stable, the power device still needs some time to stabilize. In practical applications, the dead time is the sum of the time required for the signal to stabilize and for the power device to stabilize its switching state. The dead time is determined by hardware performance; some hardware switches between high and low levels quickly, resulting in a shorter dead time, and vice versa.

[0063] Figure 2 This is a schematic diagram illustrating the arrangement of two dead time zones in an embodiment of the present invention, as shown below. Figure 2 As shown, PWM1 is the first PWM signal, PWM2 is the second PWM signal, and A1-B1 is the time difference between the two PWM signals. In the diagram, "1" represents the region where the first dead time is scheduled, and "2" represents the region where the second dead time is scheduled. This invention first starts the first PWM signal generator to output the first signal. After successful startup, the first signal exhibits its first falling edge, changing from a high level to a low level. At this time, the signal is unstable, and the second PWM signal generator waits for the first dead time (…). Figure 2 After the "1" in the middle is restarted, the second signal output by the second PWM signal generator changes from low level to high level.

[0064] The hardware of the negative-polarity first PWM waveform generator outputs a first signal whose level is unstable for a certain period after generating a falling edge. To prevent the second signal output by the positive-polarity second PWM waveform generator from being high simultaneously with the first signal, this invention waits for the first signal to stabilize at a low level (i.e., the dead time) before starting to output a high level. This waiting ensures that the first signal is stable at a low level before outputting a high level for the second signal. This prevents the second signal from also being high when the first signal's state is uncertain and it may output a high level.

[0065] The first dead time is formed by staggering the start-up times of the two PWM signal generators. The negative-polarity first PWM signal generator starts first, and its first signal changes from high to low. After the dead time, the second PWM signal generator outputs its second signal, which then changes from low to high. The first dead time consists of two parts: the first part is the predetermined waiting time in step S2, and the second part is the time required to start the second PWM signal generator in step S3. The predetermined time can be set by the user as needed, while existing technologies typically require three steps to start the second PWM signal generator.

[0066] 1. Initialize the second PWM signal generator;

[0067] 2. Configure the frequency and duty cycle of the second PWM signal generator;

[0068] 3. Enable the second PWM signal generator.

[0069] The first step is to initialize the PWM waveform generator, which may include enabling the PWM clock gating and switching the timer to PWM mode. The second step is to configure the duty cycle and frequency of the PWM waveform generator, which requires writing to the registers storing this information in the PWM waveform generator.

[0070] The timing of starting the second PWM signal generator is a random value. Figure 4In the prior art, it is a schematic diagram of the time difference between the output waveforms of two continuously started PWM signal generators. Both of these two PWM signal generators are of positive polarity. PWM1 is the waveform of the output signal of the PWM waveform generator started first, and PWM2 is the waveform of the output signal of the PWM waveform generator started later. The time difference between the start of the high-level output of PWM1 and the start of the high-level output of PWM2 (A1 - A2 in the figure) is the time required to complete the above three steps (excluding the predetermined time waited in step S2). The time difference at the starting position of the normal software process PWM waveform period is a random value because enabling PWM1 and enabling PWM2 are not continuous operations but three steps. After the program is compiled, other operations may be inserted in the non - continuous operations due to efficiency reasons.

[0071] Therefore, a part of the dead - time is controllable (predetermined time), and another part is uncontrollable (the time to start the second PWM signal generator). However, through optimization, the proportion of the uncontrollable part in the dead - time can be reduced, and the accuracy of controlling the dead - time can be improved.

[0072] Based on the above first embodiment, the second embodiment of the present invention further provides an improved method, that is:

[0073] Step S2 further includes the following steps:

[0074] Use a loop statement to wait for a predetermined time;

[0075] Step S3 further includes the following steps:

[0076] Enable the second PWM waveform generator;

[0077] Before step S1, the following steps are further included:

[0078] Initialize the second PWM waveform generator;

[0079] Configure the frequency and duty cycle of the second PWM waveform generator.

[0080] In practical applications, the loop statement for waiting time can be while(--delay) or for(i = 0; i < delay; i++). Here, delay is a time - difference parameter that can be operated by the user to set the predetermined time and has a fixed corresponding relationship with the predetermined time. The control accuracy of the while(--delay) statement is higher than that of for(i = 0; i < delay; i++) for the predetermined time. It is recommended to use the while(--delay) statement.

[0081] If it is a while(--delay), and delay is 1, the C language code of this while(--delay) can be compiled into the following assembly statements:

[0082] LOOP:

[0083] SUBS R0,#1

[0084] BNE LOOP

[0085] In this context, R0 represents delay. R0 decreases by 1 for each loop iteration. If R0 > 0, the BNE statement jumps to the LOOP; otherwise, the loop terminates. The SUBS statement executes in one controller clock cycle. The BNE statement takes three controller clock cycles to execute if it jumps to the LOOP, and one controller clock cycle if it doesn't. Therefore, each loop iteration with a jump takes four controller clock cycles, and the loop terminates in the last iteration. Execution time without a jump is two controller clock cycles. The total execution time of `while(--delay)` is (delay × 4 – 2) controller clock cycles (the predetermined time).

[0086] The second embodiment changes the order of steps to start the PWM signal generator, moving steps 1 and 2 to start the second PWM signal generator before step S1. This shortens the time of step S3, thereby reducing the proportion of the dead time occupied by the uncontrollable part and improving the accuracy of the control dead time. Figure 3 The diagram illustrates the time consumption of step S3 in the second embodiment. Steps 1 and 2 are moved before step S1. The execution time of step S3 is theoretically 8 controller clock cycles.

[0087] In practical applications, the execution time of step S3 can be further shortened by improving the execution efficiency of the C language code, thereby improving the control precision of the dead time.

[0088] Based on the second embodiment, the present invention further provides a method, namely, prior to step S1, including the following steps:

[0089] Read the first control value from the control register of the second PWM waveform generator into the buffer;

[0090] Rewrite the first control value in the cache with the second control value;

[0091] To enable the second PWM waveform generator, the following steps are included:

[0092] Write the second control value into the control register of the second PWM waveform generator;

[0093] In the first control value, the control bit used to enable the PWM waveform generator is in a disabled state, while in the second control value, the control bit used to enable the PWM waveform generator is in an enabled state.

[0094] In practical applications, the C language statement to enable the second PWM waveform generator is:

[0095] PWM2->CR|=1;

[0096] After compilation by the compiler, from the perspective of assembly instructions, the expanded result is the following three instructions:

[0097] 1) Read the value of the PWM2 control register;

[0098] 2) Change the enable bit to 1;

[0099] 3) Write the new PWM2 value into the PWM2 control register.

[0100] Based on the above breakdown, the C language code can be split into two lines:

[0101] pwm2_val = PWM2->CR|1;

[0102] PWM2->CR = pwm2_val.

[0103] Where pwm2_val is an intermediate variable in the cache. In this embodiment, steps 1) and 2) are moved to be executed before step S1 (theoretically 6 controller clock cycles), and then step 3) is executed only in step S3, which can further compress the time of step S3 to 2 controller clock cycles (theoretical value).

[0104] Ignoring step S2, the C code for steps S1 and S3 can be adjusted as follows:

[0105] pwm1_val = PWM1->CR|1;

[0106] pwm2_val = PWM2->CR|1; (before step S1)

[0107] Step S1: PWM1->CR = pwm1_val;

[0108] Step S3: PWM2->CR = pwm2_val.

[0109] The loop statement in step S2 is placed between steps S1 and S3. During compilation, this prevents the compiler from inserting other operations between steps S1 and S3, ensuring that the start time of the second PWM signal generator is no longer random but a fixed time. Therefore, if step S2 uses a while(--delay) statement, the relationship between the dead time and the delay parameter is (4×delay-2+2)×controller clock cycle = 4×delay×controller clock cycle, which is the time difference between starting the output signal of the first PWM signal generator and starting the output signal of the second PWM signal generator. If the controller clock is 32MHz, the dead time is delay×0.125μs.

[0110] The above describes the formation and improvement of the first dead time. This invention also includes a second dead time (…). Figure 2 (referring to the "2" in the original text). After the falling edge of the second signal, the first signal needs to output a high level at least after the dead time.

[0111] To create a second dead time, the duty cycles of the two PWM signal generators need to be controlled to allow a dead time to be inserted at position "2". In the extreme case, there are two dead times, one high-level pulse time of the first signal, and one high-level pulse time of the second signal within the period of the first signal (equal to the period of the second signal). That is, the first dead time + the high-level pulse time of the second signal + the high-level pulse time of the second signal = the time of one period of the first signal. Therefore, D1 + D2 + (2 × T1) / T2 = 1; where D1 is the duty cycle of the first signal (since the first signal is negative, a high level is equivalent to no duty for the first signal), D2 is the duty cycle of the second signal, T1 is the dead time, and T2 is the period of the first signal. If D1 + D2 + (2 × T1) / T2 < 1, then after the second dead time in region "2", the first signal will need to wait for a certain period of time before becoming high, and the high levels of the two PWM signals will not "overlap". If D1+D2+(2×T1) / T2>1, then region “2” cannot meet the dead time requirement. Alternatively, the high levels of the first and second signals may overlap in region “2”.

[0112] Alternatively, the first PWM signal generator can also be positive, followed by an inverter gate. In this case, in D1+D2+(2×T1) / T2≤1, D1 is the duty cycle of the first signal. Since the inverter gate is very fast, the signal delay is on the order of nanoseconds. Given that the time difference between the two PWM signals is on the order of microseconds, this can be disregarded when calculating whether the dead time condition is met.

[0113] Since the time difference between starting the output signal of the first PWM signal generator and starting the output signal of the second PWM signal generator can be accurately set in this embodiment of the invention, it is possible to determine whether the two PWM signals meet the dead time condition by using the signal time difference, the duty cycle of the first PWM signal, and the duty cycle of the second PWM signal. That is, D1+D2+(2×T1) / T2≤1.

[0114] In this invention, after the first signal output by the first PWM signal generator has a falling edge, the second PWM signal generator is allowed to output a high level signal by waiting for a dead time. Furthermore, by controlling the duty cycle of the output signals of the two PWM signal generators, it is ensured that at least a dead time has elapsed after the falling edge of the second signal before the first signal becomes high. The two dead times ensure that the output signals of the two PWM signal generators will not be high at the same time.

[0115] Figure 5 A controller for controlling the dead time of a PWM signal, provided in the fourth embodiment of the present invention, includes at least:

[0116] The first startup module is used to start the first PWM waveform generator so that the first PWM waveform generator outputs a first signal; the first PWM waveform generator is negative polarity.

[0117] The waiting module is used to wait for a scheduled time.

[0118] The second startup module is used to start the second PWM waveform generator so that the second PWM waveform generator outputs a second signal; the second PWM waveform generator is positive.

[0119] Wherein, the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time of execution step S3; the dead time, the duty cycle of the first signal, and the duty cycle of the second signal satisfy the following condition: D1+D2+(2×T1) / T2≤1; where D1 is the duty cycle of the first signal, D2 is the duty cycle of the second signal, T1 is the dead time, and T2 is the period of the first signal.

[0120] Based on the fourth embodiment, the present invention further provides a controller. In this controller, the waiting module specifically includes:

[0121] The wait submodule is used to wait for a predetermined time using loop statements;

[0122] The second startup module specifically includes:

[0123] The enable submodule is used to enable the second PWM waveform generator;

[0124] The controller also includes:

[0125] An initialization module is used to initialize the second PWM waveform generator.

[0126] The configuration module is used to configure the frequency and duty cycle of the second PWM waveform generator.

[0127] Based on the fourth embodiment, the present invention further provides a controller, which also includes:

[0128] The read module is used to read the first control value of the control register of the second PWM waveform generator into the buffer;

[0129] The rewrite module is used to rewrite the first control value in the cache to the second control value;

[0130] The enabling submodule includes:

[0131] The write submodule is used to write the second control value into the control register of the second PWM waveform generator;

[0132] In the first control value, the control bit used to enable the PWM waveform generator is in a disabled state, while in the second control value, the control bit used to enable the PWM waveform generator is in an enabled state.

[0133] A fifth embodiment of the present invention provides an electronic device including any of the controllers described above.

[0134] The electronic device in this embodiment of the invention can be a smart lamp, which may have a remote communication module such as Wi-Fi, Bluetooth, or infrared. The communication module can communicate with a terminal. The terminal can be a computer, mobile phone, or remote control.

[0135] Below, we will use a terminal as a remote control, two PWM signal generators to control the on / off state of two light bulbs, and a dead time setting as an example, combined with... Figure 6 This document describes the method for controlling the dead time of a PWM signal in intelligent lighting fixtures. Specifically, it includes the following steps:

[0136] Step S1: The remote control sets the PWM duty cycle of lamp 1, the PWM duty cycle brightness and time difference parameters of lamp 2, sends them to the controller, and requests the controller to enable the PWM signal generators of lamp 1 and lamp 2.

[0137] Step S2: The controller determines whether the dead time condition is met based on the above parameters. If not, it sends a notification to the remote control, requesting the user to change the data, and returns to step S1; if the condition is met, it proceeds to step S4.

[0138] Step S3: Send a notification to the remote control, requesting the user to change the data, then proceed to step S1;

[0139] Step S4: The controller initializes the first PWM signal generator of lamp 1 and the second signal generator of lamp 2, and sets the duty cycle and frequency of the first PWM signal generator and the second PWM signal generator.

[0140] Step S5: The controller reads the data from the control register of the first PWM signal generator and the data from the control register of the second PWM signal generator into the buffer, and modifies the state of the enable bits of the two buffer data to "enable".

[0141] Step S6: The controller writes data enabling the first PWM signal generator from the buffer to the control register of the first PWM signal generator, thereby enabling the first PWM signal generator;

[0142] Step S7: The controller waits for a predetermined time.

[0143] Step S8: The controller writes data enabling the second PWM signal generator from the buffer to the control register of the second PWM signal generator, thereby enabling the second PWM signal generator.

[0144] The method, controller, and related electronic equipment for controlling the dead time of a PWM signal provided by this invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A method for controlling the dead time of a PWM signal, characterized in that... Includes the following steps: Step S1: Initialize the second PWM waveform generator, configure the frequency and duty cycle of the second PWM waveform generator; start the first PWM waveform generator so that the first PWM waveform generator outputs a first signal; the first PWM waveform generator is negative polarity; Step S2: Use a loop statement to wait for a predetermined time; Step S3: Start and enable the second PWM waveform generator so that the second PWM waveform generator outputs a second signal; the second PWM waveform generator is positive. Wherein, the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time of step S3; the dead time, the duty cycle of the first signal, and the duty cycle of the second signal satisfy the following condition: D1+D2+(2×T1) / T2≤1; where D1 is the duty cycle of the first signal, D2 is the duty cycle of the second signal, T1 is the dead time, and T2 is the period of the first signal.

2. The method as described in claim 1, characterized in that, Step S1 further includes the following steps: Read the first control value from the control register of the second PWM waveform generator into the buffer; The first control value in the cache is rewritten to the second control value; Enabling the second PWM waveform generator includes the following steps: Write the second control value into the control register of the second PWM waveform generator; In the first control value, the control bit used to enable the PWM waveform generator is in a disabled state, while in the second control value, the control bit used to enable the PWM waveform generator is in an enabled state.

3. A controller for controlling the dead time of a PWM signal, characterized in that... include: An initialization module is used to initialize the second PWM waveform generator. The configuration module is used to configure the frequency and duty cycle of the second PWM waveform generator; The first startup module is used to start the first PWM waveform generator so that the first PWM waveform generator outputs a first signal; the first PWM waveform generator is negative polarity. The wait module is used to wait for a predetermined time using loop statements; The second startup module is used to start the second PWM waveform generator so that the second PWM waveform generator outputs a second signal; The second PWM waveform generator is positive polarity; The second startup module also includes an enable submodule for enabling the second PWM waveform generator; Wherein, the frequency of the first signal is the same as the frequency of the second signal, and the dead time is the sum of the predetermined time and the execution time of the second startup module; the dead time, the idle percentage of the first signal, and the idle percentage of the second signal satisfy the following condition: D1+D2+(2×T1) / T2≤1; where D1 is the idle percentage of the first signal, D2 is the duty cycle of the second signal, T1 is the dead time, and T2 is the period of the first signal.

4. The controller as described in claim 3, characterized in that... Also includes: The read module is used to read the first control value of the control register of the second PWM waveform generator into the buffer; The rewrite module is used to rewrite the first control value in the cache into a second control value; The enabling submodule includes: The write submodule is used to write the second control value into the control register of the second PWM waveform generator; In the first control value, the control bit used to enable the PWM waveform generator is in a disabled state, while in the second control value, the control bit used to enable the PWM waveform generator is in an enabled state.

5. An electronic device, characterized in that... Includes the controller as described in claim 3 or 4.

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