Source-synchronous interface with selectable source-side and destination-side delay control

Abstract

The present disclosure discloses a source synchronous interface with selectable source-end delay and destination-end delay control. A transmitter circuit for a source synchronous interface includes a trigger having a data input configured to receive serial data, a clock input configured to receive a source clock, and a data output coupled to a data line. A first multiplexer has a first input configured to receive a source clock, a second input configured to receive a phase-shifted clock (90 degrees offset from the source clock), and a clock output coupled to a clock line. A control circuit operates to control the selection of the source clock by the first multiplexer as a transmission clock sent on the clock line for a delay on the clock when the destination is implemented. Optionally, if the system is configured for a delay on the clock when the source is implemented, the control circuit causes the first multiplexer to select the phase-shifted clock as the transmission clock sent through the clock line.

Description

Technical Field

[0001] The present invention relates generally to source synchronous interface circuits, and more particularly to a source synchronous interface with enhanced configurability for selecting source-side delay (DoS) and destination-side delay (DoD) timing. Background Art

[0002] See also Figure 1 , which shows a block diagram of a source synchronous interface. A first device 10 is interconnected with a second device 12. In this illustration, the first device 10 acts as a transmitter and the second device 12 acts as a receiver. As an example, the first device 10 may include media access control (MAC) circuitry and the second device 12 may include physical layer (PHY) circuitry. The transmitter (first) device 10 transmits both data (TXDATA) and clock (TXCLK) via a wired interconnect 16 including one or more data lines 16d and a clock line 16c. For example, the lines 16d, 16c may each include a single physical wiring (referenced to a common ground), or alternatively, each support complementary (or differential) signaling using two physical wirings.

[0003] In order to achieve correct capture of the data TXDATA at the second device 12, the clock used for data capture at the second device 12 (referred to herein as the destination clock DSTCLK) is preferably shifted 90 degrees in phase from the clock used for generating data at the first device 10 (referred to herein as the source clock SRCCLK). This phase shift can be achieved in a variety of ways.

[0004] Figure 2A One option, referred to herein as source-ended delay (DoS), is shown, in which a delay circuit 20 in the first device 10 generates a transmit clock TXCLK by applying a 90-degree phase shift to the source clock SRCCLK. The source clock SRCCLK is used to clock a flip-flop 22, whose input serially receives the data to be transmitted (Data), and whose output generates transmit data TXDATA to be applied to the interface 16. In this implementation, since the transmit clock TXCLK has been phase-shifted 90 degrees relative to the source clock SRCCLK, the transmit clock TXCLK received by the second device 12 is the destination clock DSTCLK. The destination clock DSTCLK is used to clock a flip-flop 24 in the second device 12, whose input serially receives the transmit data TXDATA from the interconnect 16, and whose output generates the data (Data).

[0005] Figure 2BAnother option is shown, referred to herein as destination delay (DoD), in which a delay circuit 26 in the second device 12 generates a destination clock DSTCLK by applying a 90-degree phase shift to the transmit clock TXCLK received via the interface 16. The source clock SRCCLK in the first device 10 is used to clock a flip-flop 22, the input of which serially receives the data to be transmitted (Data), and the output of the flip-flop 22 generates the transmit data TXDATA to be applied to the interface 16. In this implementation, the transmit clock TXCLK is the source clock SRCCLK. The destination clock DSTCLK is used to clock a flip-flop 24 in the second device 12, the input of which serially receives the transmit data TXDATA from the interconnect 16, and the output of the flip-flop 24 generates the data (Data). Summary of the Invention

[0006] In one embodiment, a system utilizes a source synchronous interface and includes: a transmitter circuit; and a receiver circuit; wherein the transmitter circuit is coupled to the receiver circuit using a source synchronous interface including a data line and a clock line. The transmitter circuit includes: a first flip-flop having a data input configured to receive serial data, a clock input configured to receive a source clock, and a data output coupled to the data line; a first multiplexer having a first input configured to receive the source clock, a second input configured to receive a phase-shifted clock, and a first clock output coupled to the clock line, wherein the phase-shifted clock is offset 90 degrees from the source clock; and a control circuit configured to: if the system is configured to delay the clock at the destination in the receiver circuit, control the first multiplexer to select the source clock as the transmit clock sent over the clock line; and if the system is configured to delay the clock at the source in the transmitter circuit, control the first multiplexer to select the phase-shifted clock as the transmit clock sent over the clock line.

[0007] In one embodiment, a transmitter circuit for a source synchronous interface includes: a first flip-flop having a data input configured to receive serial data, a clock input configured to receive a source clock, and a data output coupled to a data line; a first multiplexer having a first input configured to receive the source clock, a second input configured to receive a phase-shifted clock, and a clock output coupled to a clock line, wherein the phase-shifted clock is offset 90 degrees from the source clock; and a control circuit configured to control the first multiplexer to select the source clock as a transmission clock sent on the clock line for clock delay at a destination configuration, and to control the first multiplexer to select the phase-shifted clock as a transmission clock sent on the clock line for clock delay at a source configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0009] Figure 1 shows a block diagram of a source synchronous interface;

[0010] Figure 2A Shows the source-side delay (DoS) implementation of a source-synchronous interface;

[0011] Figure 2B shows the Destination Delay (DoD) implementation for a source synchronous interface;

[0012] Figure 3 shows a block diagram of a source synchronous interface;

[0013] Figure 4 Shown Figure 3 A more detailed circuit implementation of a transmitter device; and

[0014] Figure 5 A circuit diagram of a two-bit Johnson counter circuit is shown. DETAILED DESCRIPTION

[0015] See also Figure 3 , which shows a block diagram of a source synchronous interface. A first device 110 is interconnected with a second device 112. In this illustration, the first device 110 acts as a transmitter and the second device 112 acts as a receiver. As an example, the first device 110 may include a media access control (MAC) circuit and the second device 112 may include a physical layer (PHY) circuit. The transmitter (first) device 110 sends both data (TXDATA) and clock (TXCLK) via a wired interconnect 116 including one or more data lines 116d and a clock line 116c. For example, lines 116d, 116c can each include a single physical wiring (referenced to a common ground), or alternatively, each supports complementary (or differential) signaling using two physical wirings.

[0016] Transmitter (first) device 110 includes a clock generator (source) circuit 102 configured to generate a source clock (SRCCLK). Source clock SRCCLK is used to clock flip-flop 122, whose input serially receives the data to be transmitted (Data). The output of flip-flop 122 generates transmit data TXDATA, which is applied to data line 116d of interface 116. If multiple data lines 116d are used, there will be one clocked flip-flop 122 for each line, along with multiple data inputs. Source clock SRCCLK is also applied to a first input of multiplexer circuit 104 and an input of delay circuit 120. Delay circuit 120 generates a phase-shifted clock (PHSCLK) by applying a 90-degree phase shift to source clock SRCCLK. Phase-shifted clock PHSCLK is applied to a second input of multiplexer circuit 104. The selection operation performed by multiplexer circuit 104 is controlled by control signal DLY_SEL. If the control signal dly_sel is in a first state, the multiplexer circuit 104 selects the source clock SRCCLK from the first input to output as the transmission clock TXCLK through the clock line 116 c of the wired interconnect 116 (this is consistent with the destination-side clock delay (DoD) operation). Conversely, if the control signal dly_sel is in a second state, the multiplexer circuit 104 selects the phase-shifted clock PHSCLK from the second input to output as the transmission clock TXCLK through the clock line 116 c of the wired interconnect 116 (this is consistent with the source-side clock delay (DoS) operation).

[0017] The control signal dly_sel is generated by the control circuit 106. In one embodiment, the control circuit 106 may include a bit in a data register that is set to a first state or a second state depending on whether the delay on the clock is provided by the transmitter (first) device 110 (i.e., DoS) or the receiver (second) device 112 (i.e., DoD). For example, in a clock source-side delay (DoS) configuration (where the receiver (second) device 112 does not include a clock phase shift function), the control signal dly_sel is in the second state, causing the multiplexer circuit 104 to select the phase-shifted clock PHSCLK as the transmit clock TXCLK. In a clock destination-side delay (DoD) configuration (where the receiver (second) device 112 does include a clock phase shift function), the control signal dly_sel is in the first state, causing the multiplexer circuit 104 to select the source clock SRCCLK as the transmit clock TXCLK. The setting of the state of the control signal dly_sel may be performed by the control circuit 106 itself, or may be performed by another circuit of the transmitter (first) device 110 and transmitted to the control circuit 106 .

[0018] Now refer to Figure 4 , which shows a more detailed circuit implementation of the clock generator (source) circuit 102 and delay circuit 120 of the transmitter (first) device 110. A phase-locked loop (PLL) circuit 130 generates a clock signal PHICLK at a frequency fphi, which is an integer multiple N of the highest required frequency ftx of the transmit clock TXCLK of the interface 116 (i.e., fphi = N*ftx). In this embodiment, n = 4 due to the further divide-by-four operation performed by the delay circuit 120 (as will be described). The clock signal PHICLK is applied to a first input of a multiplexer 132 and further to the inputs of a plurality of frequency divider circuits 134. The outputs of the frequency divider circuits 134 are provided to respective inputs of a multiplexer 140, whose divided clock DIVCLK output is applied to a second input of the multiplexer 132. The output of the multiplexer 132 provides the selected clock SELCLK. The selected clock SELCLK is used to clock the N-divided Johnson counter circuit 142, which outputs the source clock SRCCLK and the phase-shifted clock PHSCLK (in this case, as described above, having a 90-degree phase shift relative to the source clock SRCCLK), each clock having a frequency that is 1 / N of the frequency of the selected clock SELCLK.

[0019] The selection operation performed by the multiplexer circuit 140 is controlled by the control signal speed_sel. If the control signal speed_sel has a first state, the multiplexer circuit 140 selects the clock signal (divided by A) output from the DIV / A divider circuit 134 as the divided clock DIVCLK to be applied to the second input of the multiplexer 132. If the control signal speed_sel has a second state, the multiplexer circuit 140 selects the clock signal (divided by B) output from the DIV / B divider circuit 134 as the divided clock DIVCLK to be applied to the second input of the multiplexer 132. If the control signal speed_sel has a third state, the multiplexer circuit 140 selects the clock signal (divided by C) output from the DIV / C divider circuit 134 as the divided clock DIVCLK to be applied to the second input of the multiplexer 132.

[0020] The control signal speed_sel is generated by the control circuit 106. In an embodiment, the control circuit 106 may include another set of bits in the data register that are set to a first state, a second state, or a third state (e.g., two bits set to <0,0>, <0,1>, or <1,0>, respectively) depending on the desired speed (i.e., rate) of data communication on the interface 116.

[0021] The selection operation performed by the multiplexer circuit 132 is controlled by the control signal clk_sel. If the control signal clk_sel has a first state, the multiplexer circuit 132 selects the clock signal PHICLK for output as the selected clock SELCLK. If the control signal clk_sel has a second state, the multiplexer circuit 132 selects the divided clock DIVCLK from the multiplexer 140 as the selected clock SELCLK for output.

[0022] The control signal clk_sel is also generated by the control circuit 106. In an embodiment, the control circuit 106 may include another bit of the data register that is set to a first state or a second state depending on whether the clock signal PHICLK (to be divided by N) or the divided clock DIVCLK (to be divided by N) is to be used to generate the transmit clock TXCLK.

[0023] Each divider circuit 134 is configured to divide the frequency of the clock signal PHICLK by an integer value (indicated herein as those integer values ​​A, B, and C in embodiments where three divider circuits 134 are provided). In an embodiment, A=50, B=5, and C=1; however, it should be understood that this is merely an example, and the values ​​of A, B, and C may be selected as desired for a given application. In an example embodiment, the values ​​of A=50, B=5, and C=1 are selected in conjunction with an implementation supporting an Ethernet RGMII interface between the transmitter (first) device 110 and the receiver (second) device 112 that can operate at three different speeds: 10 Mbps, 100 Mbps, and 1000 Mbps. In this implementation, the clock signal PHICLK is generated by the PLL 130 at a frequency fphi of 500 MHz. For illustration, in an implementation with four data lines 116d and one clock line 116c, dividing by four gives 125 MHz, and when the four data lines are sampled on both the rising and falling edges of the clock, the total data rate is 1000 Mbps. Alternatively, dividing by five again gives a clock frequency of 25 MHz, and sampling the four data lines only on the rising edge of the clock, for a total data rate of 100 Mbps.

[0024] Thus, for the divider circuit 134 implemented with an integer divider value A=50, support is provided for Ethernet RGMII interface operation at 10 Mbps (by generating the divided clock DIVCLK at a frequency of 10 MHz). The clock frequency at the output of the Johnson counter will be 2.5 MHz, and in the case of four transmission lines, the total data speed will be 10 Mbps. In the case of the divider circuit 134 implemented with an integer divider value B=5, support is provided for Ethernet RGMII interface operation at 100 Mbps (by generating the divided clock DIVCLK at a frequency of 100 MHz). The clock frequency at the output of the Johnson counter will be 25 MHz, and in the case of four transmission lines, the total data speed will be 100 Mbps. Similarly, for the divider circuit 134 implemented with an integer divider value C=1, support is provided for Ethernet RGMII interface operation at 100 Mbps (by generating the divided clock DIVCLK at a frequency of 500 MHz). The clock frequency at the output of the Johnson counter will be 125 MHz, and using four transmission lines (and sampling on both rising and falling edges) gives a total data rate of 1000 Mbps.

[0025] Now refer to Figure 5 , Figure 5 A circuit diagram of Johnson counter circuit 142 is shown. Johnson counter circuit 142 is a two-bit twisted-ring counter that includes flip-flops 150 and 152 and a logic inverter 154 (NOT gate). The clock inputs of flip-flops 150 and 152 both receive a selected clock, SELCLK. The data output Q of flip-flop 150 is applied to the data input D of flip-flop 152. The data output Q of flip-flop 152 is inverted by logic inverter 154 and applied to the data input D of flip-flop 150. The data output Q of flip-flop 150 provides the source clock, SRCCLK, and the data output Q of flip-flop 152 provides the phase-shifted clock, PHSCLK (in this case, with a 90-degree phase shift relative to the source clock, SRCCLK, as described above). Optionally, the inverted data output / Q of flip-flop 152 is applied to the data input D of flip-flop 150 (see 158). The two-bit implementation of Johnson counter circuit 142 is effectively a divide-by-four circuit, so the frequencies of the source clock, SRCCLK, and the phase-shifted clock, PHSCLK, are one-quarter the frequency of the selected clock, SELCLK. Using N=4 to set the frequency fphi for the clock signal PHICLK supports 90 degree phase shift operation using only the same edge clock flip-flops. Clocking flip-flops 150 and 152 on the same edge of the selected clock SELCLK advantageously provides some margin for clock re-convergence pessimism removal (CRPR).

[0026] The transmitter (first) device 110 is supported to operate in multiple modes. First, consider the case of Ethernet RGMII interface operation. In this operating scenario, the control circuit 106 sets the state of the control signal clk_sel to cause the multiplexer 132 to select the divided clock DIVCLK for application to the Johnson counter 142 (because the integer division provided by the divider circuit 134 is specifically selected to support the Ethernet RGMII interface speed). The transmitter (first) device 110 will negotiate with the receiver (second) device 112 to determine a data transmission rate at one of three different speeds: 10 Mbps, 100 Mbps, and 500 Mbps. This negotiation can be performed, for example, by the control circuit 106, or can be performed by another circuit of the transmitter (first) device 110 and transmitted to the control circuit 106 for setting the state of the control signal speed_sel. If the negotiated rate is 10 Mbps, the control signal speed_sel is set to a first state, and the clock signal with an integer divider value A=50 output by the divider circuit 134 is selected by the multiplexer 140 as the divided clock DIVCLK and passes through the multiplexer 132 to provide the selected clock SELCLK. If the negotiated rate is 100 Mbps, the control signal speed_sel is set to a second state, and the clock signal with an integer divider value B=5 output by the divider circuit 134 is selected by the multiplexer 140 as the divided clock DIVCLK and passes through the multiplexer 132 to provide the selected clock SELCLK. If the negotiated rate is 1000 Mbps, the control signal speed_sel is set to a first state, and the clock signal with an integer divider value C=1 output by the divider circuit 134 is selected by the multiplexer 140 as the divided clock DIVCLK and passes through the multiplexer 132 to provide the selected clock SELCLK.

[0027] Next, consider another interface operation (e.g., non-Ethernet RGMII or interfacing at non-standard Ethernet speeds) with a desired frequency ftx of the transmit clock TXCLK. PLL circuit 130 is controlled to set the frequency fphi of clock PHICLK to four times the frequency ftx. This control operation can be implemented, for example, by control circuit 106 or by another circuit in transmitter (first) device 110. In this operational scenario, the state of control signal clk_sel is set so that multiplexer 132 selects clock PHICLK for application to Johnson counter 142.

[0028] Although the present invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A system utilizing a source synchronous interface, comprising: transmitter circuit; as well as Receiver circuit; wherein the transmitter circuit is coupled to the receiver circuit using a source synchronous interface including a data line and a clock line; The transmitter circuit includes: A first flip-flop having: a data input configured to receive serial data; a clock input configured to receive a source clock; and a data output coupled to the data line; a first multiplexer having: a first input configured to receive the source clock; a second input configured to receive a phase-shifted clock; and a first clock output coupled to the clock line, wherein the phase-shifted clock is shifted 90 degrees from the source clock; and a control circuit configured to: control the first multiplexer to select the source clock as the transmission clock sent through the clock line if the system is configured for delaying the clock at the destination in the receiver circuit, and control the first multiplexer to select the phase-shifted clock as the transmission clock sent through the clock line if the system is configured for delaying the clock at the source in the transmitter circuit.

2. The system of claim 1 , wherein the receiver circuit comprises a second flip-flop having: a data input coupled to receive the transmit data sent via the data line; and a clock input coupled to receive the transmit clock sent via the clock line.

3. The system of claim 1 , further comprising a Johnson counter having: an input configured to receive a selected clock; a first output to generate the source clock from the selected clock; and a second output to generate the phase-shifted clock from the selected clock. The system of claim 3 , wherein the Johnson counter is a two-bit counter. 5 . The system of claim 3 , wherein the Johnson counter implements dividing the selected clock by an integer N to generate the source clock and the phase-shifted clock. 6 . The system of claim 5 , wherein the source clock has a frequency that is N times greater than a required frequency of the transmit clock to achieve a desired data transfer rate between the transmitter circuit and the receiver circuit over the source synchronous interface.

7. The system according to claim 3, further comprising: A second multiplexer having: a first input configured to receive a first clock; a second input configured to receive a second clock; and a second clock output that generates the selected clock and is coupled to the input of the Johnson counter, wherein the first clock and the second clock are at different frequencies.

8. The system of claim 7 , wherein the control circuit is further configured to control the second multiplexer to select the first clock for the selected clock in combination with the first operating mode of the source synchronous interface, and to control the second multiplexer to select the second clock for the selected clock in combination with the second operating mode of the source synchronous interface.

9. The system of claim 8, wherein the first operating mode of the source synchronous interface is a standard speed associated with Ethernet RGMII interface operation, and the second operating mode of the source synchronous interface is a non-standard speed associated with Ethernet operation.

10. The system of claim 9 , further comprising a third multiplexer having: a first input configured to receive a third clock; a second input configured to receive a fourth clock; and a third clock output that generates the first clock and is coupled to the first input of the second multiplexer, wherein the third clock and the fourth clock are at different frequencies, and wherein the frequencies of the third clock and the fourth clock are associated with different standard speeds for operation of the Ethernet RGMII interface.

11. The system of claim 10 , wherein the control circuit is further configured to control selection of the third clock by the third multiplexer in conjunction with a first standard speed for operation of the Ethernet RGMII interface, and to control selection of the fourth clock by the third multiplexer in conjunction with a second, different standard speed for operation of the Ethernet RGMII interface.

12. The system of claim 10, further comprising: A first frequency divider having: an input configured to receive the second clock; and an output generating said third clock and coupled to a first input of said third multiplexer; as well as A second frequency divider having: an input configured to receive the second clock; and an output, generating the fourth clock, and coupled to the second input of the third multiplexer.

13. The system of claim 12, further comprising: The phase-locked loop is configured to generate the second clock.

14. The system of claim 1 , further comprising a clock division and phase shift circuit having: an input configured to receive a selected clock; a first output to generate the source clock divided from the selected clock; and a second output to generate the phase-shifted clock divided from the selected clock.

15. The system of claim 14, wherein the clock division and phase shifting circuit implements dividing the selected clock by an integer N to generate the source clock and the phase-shifted clock.

16. The system of claim 15, wherein the source clock has a frequency that is N times greater than a desired frequency of the transmit clock to achieve a desired data transfer rate between the transmitter circuit and the receiver circuit over the source synchronous interface.

17. The system of claim 14, further comprising: A second multiplexer having: a first input configured to receive a first clock; a second input configured to receive a second clock; and a second clock output generating the selected clock and coupled to the input of the clock division and phase shifting circuit, wherein the first clock and the second clock are at different frequencies.

18. The system of claim 17 , wherein the control circuit is further configured to control the second multiplexer to select the first clock for the selected clock in combination with the first operating mode of the source synchronous interface, and to control the second multiplexer to select the second clock for the selected clock in combination with the second operating mode of the source synchronous interface.

19. The system of claim 18, wherein the first operating mode of the source synchronous interface is a standard speed associated with Ethernet RGMII interface operation, and the second operating mode of the source synchronous interface is a non-standard speed associated with Ethernet operation.

20. The system of claim 19, further comprising a third multiplexer having: a first input configured to receive a third clock; a second input configured to receive a fourth clock; and a third clock output that generates the first clock and is coupled to the first input of the second multiplexer, wherein the third clock and the fourth clock are at different frequencies, and wherein the frequencies of the third clock and the fourth clock are associated with different standard speeds for operation of the Ethernet RGMII interface.

21. The system of claim 20 , wherein the control circuit is further configured to control selection of the third clock by the third multiplexer in conjunction with a first standard speed for operation of the Ethernet RGMII interface, and to control selection of the fourth clock by the third multiplexer in conjunction with a second, different standard speed for operation of the Ethernet RGMII interface.

22. The system of claim 20, further comprising: A first frequency divider having: an input configured to receive the second clock; and an output generating said third clock and coupled to a first input of said third multiplexer; as well as A second frequency divider having: an input configured to receive the second clock; and an output, generating the fourth clock, and coupled to the second input of the third multiplexer.

23. The system of claim 22, further comprising: The phase-locked loop is configured to generate the second clock.

24. A transmitter circuit for a source synchronous interface, comprising: A first flip-flop having: a data input configured to receive serial data; Clock input, configured to receive the source clock; and a data output coupled to the data line; A first multiplexer having: a first input configured to receive the source clock; a second input configured to receive a phase-shifted clock; and a clock output coupled to a clock line, wherein the phase-shifted clock is offset by 90 degrees from the source clock; as well as The control circuit is configured to control the first multiplexer to select the source clock as the transmission clock sent on the clock line for delaying the clock at the destination configuration, and to control the first multiplexer to select the phase-shifted clock as the transmission clock sent on the clock line for delaying the clock at the source configuration.

25. The transmitter circuit of claim 24 , further comprising a clock division and phase shift circuit having: an input configured to receive a selected clock; a first output generating the source clock divided from the selected clock; and a second output generating the phase-shifted clock divided from the selected clock.

26. The transmitter circuit of claim 25, wherein the clock division and phase shifting circuit implements dividing the selected clock by an integer N to generate the source clock and the phase-shifted clock.

27. The transmitter circuit of claim 26, wherein the source clock has a frequency that is N times greater than a required frequency of the transmit clock to achieve a desired data transfer rate from the transmitter circuit over the source synchronous interface.

28. The transmitter circuit of claim 25, further comprising: A second multiplexer having: a first input configured to receive a first clock; a second input configured to receive a second clock; and a second clock output generating the selected clock and coupled to the input of the clock division and phase shifting circuit, wherein the first clock and the second clock are at different frequencies.

29. The transmitter circuit of claim 28 , wherein the control circuit is further configured to control the second multiplexer to select the first clock for the selected clock in combination with the first operating mode of the source synchronous interface, and to control the second multiplexer to select the second clock for the selected clock in combination with the second operating mode of the source synchronous interface.

30. The transmitter circuit of claim 29, wherein the first operating mode of the source synchronous interface is a standard speed associated with Ethernet RGMII interface operation, and the second operating mode of the source synchronous interface is a non-standard speed associated with Ethernet operation.

31. The transmitter circuit of claim 30 , further comprising a third multiplexer having: a first input configured to receive a third clock; a second input configured to receive a fourth clock; and a third clock output that generates the first clock and is coupled to the first input of the second multiplexer, wherein the third clock and the fourth clock are at different frequencies, and wherein the frequencies of the third clock and the fourth clock are associated with different standard speeds for operation of the Ethernet RGMII interface.

32. The transmitter circuit of claim 31 , wherein the control circuit is further configured to control selection of the third clock by the third multiplexer in conjunction with a first standard speed for operation of the Ethernet RGMII interface, and to control selection of the fourth clock by the third multiplexer in conjunction with a second, different standard speed for operation of the Ethernet RGMII interface.

33. The transmitter circuit of claim 31 , further comprising: A first frequency divider having: an input configured to receive the second clock; and an output generating said third clock and coupled to a first input of said third multiplexer; as well as A second frequency divider having: an input configured to receive the second clock; and an output that generates the fourth clock and is coupled to the second input of the third multiplexer.

34. The transmitter circuit of claim 33 , further comprising: The phase-locked loop is configured to generate the second clock.

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