Low bit rate decoder

Abstract

The present application discloses a low-rate decoder, which includes a variable node processing unit, a check node processing unit, a variable node information storage module, a check node information storage module, a decoding control module, a decoding output unit, etc. The low-rate decoder provided by the present application can be implemented based on FPGA, and has the advantages of high speed and high error correction capability, and the maximum operating frequency can reach 235.76MHz, and the throughput can reach 225.54Mb / s, which can effectively improve the rate of the error correction process in the superlattice key distribution system, improve the key distribution rate of the entire superlattice key distribution system, and enable the superlattice key distribution system to have high error correction capability in the secure sketch process, thereby well meeting the requirements of the superlattice key distribution system for error correction capability of special communication channels in the secure sketch process.

Description

Technical Field

[0001] The present application relates to a decoder, and in particular to a high-speed, low-code-rate decoder with high error correction capability implemented based on FPGA and its use. Background Art

[0002] Information security has become increasingly important. Semiconductor superlattice devices can generate high-quality random numbers at a very high speed, so some people apply them in the field of information security. A key distribution technology based on semiconductor superlattice devices is proposed as a new solution to achieve unconditional security of symmetric encryption. In the key distribution system of superlattice devices currently under development, in order to achieve complete data synchronization at both ends of key negotiation, the confidential communication party A first generates a key through the generator, and generates a help file (helpdata) with the help of the secure sketch (a fuzzy extractor process) and transmits it to the party B. The party B can recover the data sequence exactly the same as that of the party A by using the help file and the reconstructor that is chaotically synchronized with the generator. Among them, the secure sketch process is the step of constructing a fuzzy extractor in the superlattice key distribution system. Its meaning in the superlattice key distribution system is that the key generator generates public information (help data) about the input w without leaking the information of w, and the reconstructor that is chaotically synchronized with the generator can generate a value w′ close to w. Using w′ and the help data received from the public channel, w can be accurately recovered.

[0003] The secure sketch process in the superlattice key distribution system is similar to the structure of the data communication system. From the perspective of error correction code, the secure sketch process can be regarded as a process of correcting errors in signals that are subject to certain interference in a special communication channel and restoring the source signal. Error correction code technology is widely used in the secure sketch process of the superlattice key distribution system as an effective means to ensure reliable information transmission. The error correction scheme currently used in the superlattice key distribution system is to implement BCH decoding for error correction through Matlab. The decoding speed of this scheme is only 1Kb / s, which is too slow, affecting the superlattice key distribution rate, and is dependent on the host and not easy to integrate. Therefore, it is necessary to design other decoding schemes to improve the current problems.

[0004] To improve the error correction scheme of the superlattice key distribution system, it is very important to choose a suitable error correction code. LDPC (Low Density Parity Check) code was first proposed by Gallager in 1962. It is a type of linear block code with a sparse check matrix. It not only has good performance close to the Shannon limit, but also has the advantages of flexible structure, low decoding complexity, and easy implementation on FPGA. It is one of the hot spots in the field of channel coding in recent years. QC-LDPC (quasi-cyclic LDPC) code is widely used in the field of channel coding because its check matrix has quasi-cyclicity and lower hardware implementation complexity. BP (belief propagation) decoding algorithm is a common soft decision decoding algorithm for LDPC code. It not only has good decoding performance, but also is a parallel decoding algorithm that can greatly improve the decoding speed. However, since the BP decoding algorithm requires a large number of multiplication calculation units, the hardware implementation consumes more resources. Although it can achieve high performance, it is difficult to apply to various actual communication occasions. In order to optimize the algorithm, the LLR-BP (logarithmic domain BP) decoding algorithm was introduced. By taking the logarithm, the multiplication calculation can be converted into the addition calculation in the logarithmic domain, which is conducive to hardware implementation. The LLR-BP decoding algorithm reduces the complexity of the BP decoding algorithm to a certain extent, but it involves operations such as tangent functions. As the code length increases, the complexity of the LLR-BP decoding algorithm is still relatively large. In order to further simplify the complexity of the decoding algorithm, the MS (minimum sum) decoding algorithm was generated. Although the MS decoding algorithm has the lowest complexity, its decoding performance is affected to a certain extent because it uses approximate calculations in the decoding algorithm process, which will cause large errors. Some researchers have introduced the NMS (normalized minimum sum) decoding algorithm, which effectively improves the performance of the MS decoding algorithm by multiplying the normalization factor, but it still cannot meet the requirements of high error correction capability of the superlattice key distribution system. Summary of the invention

[0005] The main purpose of the present application is to provide a low bit rate decoder and its use, so as to overcome the deficiencies of the prior art.

[0006] In order to achieve the aforementioned invention objectives, the present application adopts the following scheme:

[0007] An embodiment of the present application provides a low bit rate decoder, which includes: a variable node processing unit, a check node processing unit, a variable node information storage module, a check node information storage module, a decoding control module and a decoding output unit; the check node information storage module accesses external data and is respectively connected to the input end of the variable node processing unit, the output end of the check node processing unit, and the output end of the decoding control module, the variable node information storage module is respectively connected to the output end of the variable node processing unit, the input end of the check node processing unit, and the output end of the decoding control module, and the variable node information storage module is also connected to the input end of the decoding output unit.

[0008] In some embodiments, the low bit rate decoder further includes a signal input buffer module, which is connected to the external data and has an output end connected to an input end of the check node information storage module, and the signal input buffer module is also connected to a decoding control module.

[0009] In some embodiments, the decoding output unit includes a decoding storage module and a decoding output module; the input end of the decoding storage module is connected to the output end of the variable node information storage module, and the output end is used to output the decoding result; the decoding storage module is also connected to the decoding control module via the decoding output module.

[0010] The embodiment of the present application provides a low bit rate decoder, which includes:

[0011] A variable node processing unit, used to process the information from the check node information storage module and then transmit it to the variable node information storage module, and to transmit the data to the decoding output unit via the variable node information storage module for caching when the last iteration is completed;

[0012] A check node processing unit, used to process the information from the variable node information storage module and then transmit it to the check node information storage module;

[0013] A variable node information storage module, used to receive information from the variable node processing unit, the iteration control instruction and the read / write address input by the decoding control module, and to transmit information to the check node processing unit and the decoding output unit respectively;

[0014] A check node information storage module, used to receive external data, calculation control instructions and read / write addresses input by the decoding control module, information output by the check node processing unit, and to transmit information to the variable node processing unit;

[0015] A decoding control module, used to enable the decoder to perform decoding after the external data is input, and to transmit calculation control instructions and read-write addresses, iteration control instructions and read-write addresses, and iteration end instructions to the check node information storage module, the variable node information storage module, and the decoding output unit respectively;

[0016] The decoding output unit is used to receive the iteration end instruction from the decoding control module and the information from the variable node information storage module, and to output the decoding result.

[0017] In some implementations, the low bit rate decoder further includes:

[0018] The signal input buffer module is used to receive the external data and transmit it to the verification node information storage module, and is used to send a feedback signal to the decoding control module after receiving the external data, so as to start the decoding work.

[0019] In some implementations, the decoding output unit includes:

[0020] A decoding storage module, used to cache the decoded data after the decoding iteration is completed;

[0021] The decoding output module is used to send an enable signal and a frame header to the decoding storage module after receiving the iteration end instruction, so that the decoding storage module outputs the cached decoding result.

[0022] In some implementations, the variable node processing unit includes a plurality of variable node processing unit modules, the plurality of variable node processing modules are arranged in parallel, and each variable node processing module processes data serially when operating.

[0023] In some implementations, the check node processing unit includes a plurality of check node processing unit modules, the plurality of check node processing modules are arranged in parallel, and each check node processing module processes data serially when operating.

[0024] In some embodiments, one or more of the variable node processing unit, the check node processing unit, the variable node information storage module, the check node information storage module, the decoding control module and the decoding output unit adopts FPGA (Field-Programmable Gate Array).

[0025] Preferably, the variable node processing unit, the check node processing unit, the variable node information storage module, the check node information storage module, the decoding control module and the decoding output unit are all implemented using FPGA.

[0026] In some implementations, the method by which the variable node processing unit module and the check node processing unit module process input data includes:

[0027] 1) Initialize according to the following formula:

[0028]

[0029] 2) Perform horizontal iteration according to the following formula to update the check node C j :

[0030]

[0031] 3) Perform vertical iteration according to the following formula to update the variable node V i :

[0032]

[0033] 4) Update the posterior information according to the following formula:

[0034]

[0035] 5) Make a decoding decision, where L (k) (q i ) is greater than 0, decoding output When L (k) (q i ) is less than 0, decoding output And, if the decoding result satisfy Or the maximum number of iterations is reached, the decoding is terminated and Output as the decoding result, otherwise return to step 2) to continue iteration;

[0036] The above L(P i ) indicates a channel initialization message; L k (r ij ) represents the check message transmitted by the ith check node to the ith variable node in the kth iteration; L k (q ij ) represents the variable message transmitted from the i-th variable node to the i-th check node in the k-th iteration; L k (q i ) represents the posterior message of the i-th variable node at the k-th iteration; y i is the received signal; σ is the Gaussian white noise variance; α is the normalization factor; R j \i means except V i In addition, with C j The set of all adjacent V; C i \j means except C j Outside, with Vi The set of all adjacent Cs.

[0037] Preferably, the value of the normalization factor is 0.75.

[0038] An embodiment of the present application provides a superlattice key distribution system, including a security sketch unit, and the security sketch unit includes the low bit rate decoder.

[0039] Compared with the prior art, the low-bit-rate decoder provided in the present application can be implemented based on FPGA, and has the advantages of high speed and high error correction capability. When applied, it can enable the superlattice key distribution system to have high error correction capability during the security sketching process. At the same time, the maximum operating frequency of the decoder can reach 235.76MHz, and the throughput of the decoder can reach 225.54Mb / s. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 It is a comparison chart of bit error rate simulation of various decoding algorithms in the prior art;

[0042] Figure 2 This is a simulation comparison chart of bit error rate under different normalization factors of the NMS algorithm;

[0043] Figure 3 is an overall structural diagram of an LDPC decoder in a typical embodiment of the present application;

[0044] Figure 4 This is a schematic diagram of the working principle of a variable node processing unit module in a typical embodiment of the present application;

[0045] Explanation of the accompanying drawings: 1-variable node processing unit 1, 2-check node processing unit, 3-variable node information storage module, 4-check node information storage module, 5-decoding control module, 6-decoding output unit, 61-decoding storage module, 62-decoding output module 62, 7-signal input buffer module, a-code word input, b-receive input data, c-one frame data buffer, d-read and write address, e-calculation control instruction, f-iteration control instruction, g-read and write address, h-iteration end instruction, j-frame header, k-enable, L-decoding result. DETAILED DESCRIPTION

[0046] As mentioned above, the transmission channel error rate of the superlattice key distribution system is higher than that of the conventional communication system, and higher error correction capability is required. However, the existing superlattice key distribution system mainly implements BCH decoding and error correction through Matlab. The decoding speed of such a scheme is only 1Kb / s. The decoding speed is too slow, which affects the superlattice key distribution rate. In addition, it needs to rely on the host environment and is not easy to integrate.

[0047] In view of the defects of the prior art, the inventor of this application was able to propose the technical solution of this application after long-term research and extensive practice.

[0048] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the technical solution of the present application is further described in detail below through embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] A typical embodiment of the present application provides a low code rate decoder (LDPC decoder), the structure of which is shown in FIG. Figure 3 As shown, it includes: a signal input buffer module 7, a variable node processing unit 1, a check node processing unit 2, a variable node information storage module 3, a check node information storage module 4, a decoding control module 5 and a decoding output unit 6; the check node information storage module is connected to external data, and is respectively connected to the input end of the variable node processing unit, the output end of the check node processing unit, and the output end of the decoding control module, the variable node information storage module is respectively connected to the output end of the variable node processing unit, the input end of the check node processing unit, and the output end of the decoding control module, and the variable node information storage module is also connected to the input end of the decoding output unit; the signal input buffer module is connected to the external data, and the output end is connected to the input end of the check node information storage module, and the signal input buffer module is also connected to the decoding control module.

[0050] Furthermore, the decoding output unit includes a decoding storage module 61 and a decoding output module 62; the input end of the decoding storage module is connected to the output end of the variable node information storage module, and the output end is used to output the decoding result; the decoding storage module is also connected to the decoding control module via the decoding output module.

[0051] Please continue reading Figure 3 In this embodiment, the variable node processing unit is used to process the information from the check node information storage module and then transmit it to the variable node information storage module, and is used to transmit the data to the decoding output unit via the variable node information storage module for caching when the last iteration is completed.

[0052] In this embodiment, the check node processing unit is used to process the information from the variable node information storage module and then transmit it to the check node information storage module.

[0053] In this embodiment, the variable node information storage module is used to receive information from the variable node processing unit, the iteration control instructions and read / write addresses input by the decoding control module, and to transmit information to the check node processing unit and the decoding output unit respectively.

[0054] In this embodiment, the check node information storage module is used to receive external data, calculation control instructions and read / write addresses input by the decoding control module, information output by the check node processing unit, and to transmit information to the variable node processing unit.

[0055] In this embodiment, the decoding control module is used to enable the decoder to perform decoding after the external data input is completed, and is used to transmit calculation control instructions and read-write addresses, iteration control instructions and read-write addresses, and iteration end instructions to the check node information storage module, the variable node information storage module, and the decoding output unit respectively.

[0056] In this embodiment, the decoding output unit is used to receive the iteration end instruction from the decoding control module and the information from the variable node information storage module, and to output the decoding result.

[0057] In this embodiment, the signal input buffer module is used to receive the external data and transmit it to the check node information storage module, and is used to send a feedback signal to the decoding control module after receiving the external data, so as to start the decoding work.

[0058] In this embodiment, the decoding storage module is used to cache the decoding data after the decoding iteration is completed, and the decoding output module is used to send an enable signal and a frame header to the decoding storage module after receiving the iteration end instruction, so that the decoding storage module outputs the cached decoding results.

[0059] In this embodiment, the variable node processing unit includes a plurality of variable node processing unit modules (VNU1, ..., VNUt). The plurality of variable node processing modules are arranged in parallel, and each variable node processing module processes data in series when working.

[0060] In this embodiment, the check node processing unit includes a plurality of check node processing unit modules (CNU1, ..., CNUt). The plurality of check node processing modules are arranged in parallel, and each check node processing module processes data in series when working.

[0061] In this embodiment, the variable node processing unit, the check node processing unit, the variable node information storage module, the check node information storage module, the decoding control module and the decoding output unit can all be implemented by FPGA. That is, in this embodiment, the LDPC decoder is implemented based on FPGA.

[0062] The FPGA-based LDPC decoder provided in this embodiment can achieve a code length of 8192 and a code rate of 1 / 8, which can be used for error correction in a superlattice key distribution system and meet the required high error correction capability.

[0063] In this embodiment, by comprehensively considering the hardware implementation complexity and decoder performance, the NMS decoding algorithm is used as the decoder algorithm. Its complexity is similar to that of the MS decoding algorithm, but the decoding performance is significantly improved (see Figure 1 ), and compared with the BP and LLR-BP decoding algorithms, it only loses a little performance but greatly simplifies the complexity of hardware implementation.

[0064] The specific steps of the NMS decoding algorithm adopted by the LDPC decoder of this embodiment are as follows:

[0065] (1) Initialization:

[0066]

[0067] (2) Horizontal iteration, update the check node C j :

[0068]

[0069] (3) Vertical iteration, update variable node V i :

[0070]

[0071] (4) Update of posterior information:

[0072]

[0073] (5) Decoding decision: When L (k) (q i ) is greater than 0, decoding output When L (k) (q i ) is less than 0, decoding output Final decoding result If satisfied Or the maximum number of iterations is reached, the decoding is terminated and Output as the decoding result, otherwise return to step (2) to continue iteration. i) indicates the channel initialization message, L k (r ij ) represents the check message transmitted from the i-th check node to the j-th variable node in the k-th iteration, L k (q ij ) represents the variable message transmitted from the i-th variable node to the j-th check node in the k-th iteration, L k (q i ) represents the posterior message of the i-th variable node at the k-th iteration. i is the received signal, σ is the Gaussian white noise variance, α is the normalization factor, R j \i means except V i In addition, with C j The set of all adjacent V, C i \j means except C j Outside, with V i The set of all adjacent Cs.

[0074] The above steps (1), (3), (4) and (5) can be performed in the variable node processing unit module, and step (2) can be performed in the check node processing unit module.

[0075] In the NMS decoding algorithm used in this embodiment, the normalization factor is introduced to improve the error caused by the use of approximate calculation in the minimum sum algorithm process. However, if an inappropriate normalization factor is selected, it may cause a larger error. Matlab is used to simulate five different normalization factors of 0.7, 0.75, 0.8, 0.9, and 1 (see Figure 2 ), the normalization factor used in this embodiment is determined to be 0.75, which can be realized in hardware by simple shift and addition.

[0076] The LDPC decoder provided in this embodiment is an (8192, 1024) decoder, and its code length is relatively long. There are some shortcomings in selecting serial structure decoding or full parallel structure decoding. For example, although serial structure decoding is simple to implement, it can only update the CNU (check node processing unit) or VNU (variable node processing unit) module once in one clock cycle, and the decoding rate is too slow. When the code length is relatively long, the resource consumption of full parallel structure decoding increases quadratically. Please refer to Figure 3 ,This embodiment adopts a partially parallel structure decoding to balance the decoder throughput and ,hardware resource consumption.

[0077] See also Figure 4In the LDPC decoder provided in this embodiment, the three steps of initialization of the NMS decoding algorithm, variable node update (vertical update), and decoding decision are designed in the VNU module. Therefore, in the process of implementing the LDPC decoder with FPGA, there is no need to additionally design an initialization module and a decoding decision module, which not only improves the versatility of the module, but also saves hardware resource consumption.

[0078] The decoder based on FPGA provided in this embodiment has the advantages of high speed and high error correction capability. Its maximum operating frequency can reach 235.76MHz and its throughput can reach 225.54Mb / s. It can effectively improve the rate of the error correction process in the superlattice key distribution system and improve the key distribution rate of the entire superlattice key distribution system, so that the superlattice key distribution system has high error correction capability in the security sketching process, thereby meeting the error correction capability requirements of special communication channels of the superlattice key distribution system in the security sketching process.

[0079] It is obvious to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

[0080] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A superlattice key distribution system, comprising a security sketch unit, wherein the security sketch unit comprises a low bit rate decoder, characterized in that: The low bit rate decoder comprises: A variable node processing unit, used to process the information from the check node information storage module and then transmit it to the variable node information storage module, and to transmit the data to the decoding output unit via the variable node information storage module for caching when the last iteration is completed; A check node processing unit, used to process the information from the variable node information storage module and then transmit it to the check node information storage module; The variable node information storage module is used to receive information from the variable node processing unit, the iteration control instruction and the read / write address input by the decoding control module, and to transmit information to the check node processing unit and the decoding output unit respectively; A check node information storage module, used to receive external data, calculation control instructions and read / write addresses input by the decoding control module, information output by the check node processing unit, and to transmit information to the variable node processing unit; A decoding control module, used to enable the decoder to perform decoding after the external data is input, and to transmit calculation control instructions and read-write addresses, iteration control instructions and read-write addresses, and iteration end instructions to the check node information storage module, the variable node information storage module, and the decoding output unit respectively; A decoding output unit, used for receiving an iteration end instruction from a decoding control module and information from a variable node information storage module, and for outputting a decoding result; Furthermore, one or more of the variable node processing unit, the check node processing unit, the variable node information storage module, the check node information storage module, the decoding control module and the decoding output unit adopts FPGA; And, the method for the variable node processing unit module and the check node processing unit module to process input data includes: 1) Initialize according to the following formula: 2) Perform horizontal iteration according to the following formula to update the check node C j : 3) Perform vertical iteration according to the following formula to update the variable node V i : 4) Update the posterior information according to the following formula: 5) Make a decoding decision, where L (k) (q i ) is greater than 0, decoding output When L (k) (q i ) is less than 0, decoding output And, if the decoding result satisfy Or the maximum number of iterations is reached, the decoding is terminated and Output as the decoding result, otherwise return to step 2) to continue iteration; The above L(P i ) indicates a channel initialization message; L k (r ij ) represents the check message transmitted by the i-th check node to the j-th variable node in the k-th iteration; L k (q ij ) represents the variable message transmitted from the i-th variable node to the j-th check node in the k-th iteration; L k (q i ) represents the posterior message of the i-th variable node at the k-th iteration; y i is the received signal; σ is the variance of Gaussian white noise; α is the normalization factor, which is 0.75; R j \i means except V i In addition, with C j The set of all adjacent V; C i \j means except C j Outside, with V i The set of all adjacent C.

2. The superlattice key distribution system according to claim 1, characterized in that: The low bit rate decoder also includes: The signal input buffer module is used to receive the external data and transmit it to the verification node information storage module, and is used to send a feedback signal to the decoding control module after receiving the external data, so as to start the decoding work.

3. The superlattice key distribution system according to claim 1, characterized in that: The decoding output unit comprises: A decoding storage module, used to cache the decoded data after the decoding iteration is completed; The decoding output module is used to send an enable signal and a frame header to the decoding storage module after receiving the iteration end instruction, so that the decoding storage module outputs the cached decoding result.

4. The superlattice key distribution system according to claim 1, characterized in that: The variable node processing unit includes a plurality of variable node processing unit modules. The plurality of variable node processing modules are arranged in parallel, and each variable node processing module processes data in series when working.

5. The superlattice key distribution system according to claim 1, characterized in that: The check node processing unit includes a plurality of check node processing unit modules, the plurality of check node processing modules are arranged in parallel, and each check node processing module processes data in series when working.

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