Storage device and operation method thereof

Abstract

The present technology relates to an electronic device. More particularly, the present technology relates to a storage device and an operating method thereof. The memory device according to an embodiment includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a programming operation; a programming verifier configured to calculate difference values ​​when the programming operation is completed, each of the difference values ​​being a difference between a first pass cycle count and a second pass cycle count of a respective programming state in a programming state, and outputting a pass state or a fail state according to whether at least one of the difference values ​​exceeds a reference value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0069433, filed on Jun. 9, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a storage device and an operating method thereof. Background Art

[0004] The storage device stores data under the control of the host device. The storage device may include a memory device for storing data and a memory controller for controlling the memory device. The memory device may be a volatile memory device or a non-volatile memory device.

[0005] A volatile memory device stores data only when it receives power from a power source. When the power source is cut off, the data stored in the volatile memory device may be lost. Examples of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] In a nonvolatile memory device, the stored data will not be lost even when power is not supplied. Examples of nonvolatile memory devices include read-only memory (ROM), programmable memory (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the invention

[0007] Embodiments of the present disclosure provide a storage device capable of preventing read failure and an operating method thereof.

[0008] A memory device according to an embodiment of the present disclosure may include: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a programming operation, the programming operation increasing the threshold voltages of the plurality of memory cells so that the threshold voltages of the plurality of memory cells are included in any one of a plurality of programming states separated according to the voltage magnitudes of the programming states; a cycle count storage device configured to store first pass cycle counts and second pass cycle counts for the plurality of programming states, respectively, and determine the programming state while performing the programming operation; and a program verifier configured to calculate difference values ​​when the programming operation is completed, each of the difference values ​​being the difference between the first pass cycle count and the second pass cycle count of a corresponding one of the programming states, and output a result of the programming operation according to whether at least one of the difference values ​​exceeds a reference value, the result of the programming operation indicating a pass state or a fail state.

[0009] A method for operating a memory device according to another embodiment of the present disclosure may include: performing a programming operation that increases threshold voltages of a plurality of memory cells so that the threshold voltages of the plurality of memory cells in a memory cell array are included in any one of a plurality of programming states separated according to voltage magnitudes of the programming states; storing first pass cycle counts and second pass cycle counts for the plurality of programming states, respectively, and determining the programming state while performing the programming operation; when the programming operation is completed, calculating difference values, each of the difference values ​​being a difference between a first pass cycle count and a second pass cycle count of a corresponding one of the programming states, and determining whether the programming operation passes or fails based on whether at least one of the difference values ​​exceeds a reference value.

[0010] A memory device according to an embodiment of the present disclosure may include: a plurality of memory cells; a peripheral circuit configured to perform a programming operation that increases threshold voltages of the plurality of memory cells so that the threshold voltages of the plurality of memory cells are included in any one of a plurality of programming states separated according to voltage magnitudes of the programming states; and a control logic configured to determine whether the programming operation is passed based on whether a difference between a programming loop of memory cells initially sensed to have passed verification operations respectively corresponding to the plurality of programming states and a programming loop that completes verification of each of the plurality of programming states exceeds a reference value.

[0011] A memory device according to an embodiment of the present disclosure may include: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a programming operation on the plurality of memory cells to indicate any one of a plurality of programming states, the programming operation including a plurality of programming loops with different programming voltages; and a programming operation controller. The programming operation controller is configured to determine a first pass loop count and a second pass loop count for each of a plurality of programming states, calculate a difference between the corresponding first pass loop count and the second pass loop count, and determine whether the programming operation is passed or failed based on the difference of the plurality of programming states. The first pass loop count indicates a programming loop among the programming loops that passes the verification operation. The second pass loop count indicates a programming loop among the programming loops that completes the verification of the target programming state.

[0012] According to the present technology, there are provided a storage device capable of preventing a read failure and an operation method thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram illustrating a storage system according to an embodiment of the present disclosure;

[0014] Figure 2 It is shown Figure 1 A diagram of an embodiment of a memory device is shown;

[0015] Figure 3 It is shown Figure 2 A diagram of an embodiment of a representative memory block structure is shown;

[0016] Figure 4 is a diagram illustrating a program operation and a verification operation executed in a program loop according to an embodiment of the present disclosure;

[0017] Figure 5 is a diagram showing a programming state according to an embodiment of the present disclosure;

[0018] Figure 6 is a diagram illustrating a pass loop count according to an embodiment of the present disclosure;

[0019] Figure 7 It is shown Figure 2 A diagram of an embodiment of a programming operation controller is shown;

[0020] Figure 8 It is shown in Figure 7 a diagram of a first pass cycle count and a second pass cycle count stored in a cycle count storage device;

[0021] Fig. 9 is to show operations such as Figure 1 A flowchart of an embodiment of a method of a memory device is shown;

[0022] Fig.10 It shows that Figure 1 A diagram of an embodiment of a memory controller is shown;

[0023] Fig.11 is a block diagram illustrating a memory card system to which a storage device is applied according to an embodiment of the present disclosure;

[0024] Fig.12 is a block diagram illustrating a solid state drive (SSD) system to which a storage device is applied according to an embodiment of the present disclosure;

[0025] Fig.13 is a block diagram illustrating a user system of an application storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] To describe the embodiments of the present disclosure, specific structural and functional descriptions are provided herein. However, the present invention can be implemented in various ways and in various forms. Therefore, the present invention is not limited to or by any disclosed embodiment, nor is it limited to any specific details provided herein. Throughout the specification, references to "an embodiment", "another embodiment" are not necessarily directed to only one embodiment, and different expressions of any similar wording are not necessarily directed to the same embodiment.

[0027] Figure 1 is a diagram illustrating a storage system according to an embodiment of the present disclosure.

[0028] Reference Figure 1 The storage system can be implemented as a personal computer (PC), a data center, an enterprise data storage system, a data processing system including a direct attached storage (DAS), a data processing system including a storage area network (SAN), a data processing system including a network attached storage (NAS), etc.

[0029] The storage system may include a storage device 1000 and a host 400 .

[0030] The storage device 1000 may store data under the control of a host 400 such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0031] The storage device 1000 may be manufactured or configured as any of various types of storage devices according to a host interface defining a communication protocol with the host 400. For example, the storage device 1000 may be configured as any of an SSD, a multimedia card in the form of MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of SD, mini SD, and micro SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a high-speed PCI (PCI-e or PCIe) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0032] The memory device 1000 may be manufactured as any of various types of packages. For example, the memory device 1000 may be manufactured as any of a stacked package (POP), a system-in-package (SIP), a system-on-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabrication package (WFP), and a wafer-level stacked package (WSP).

[0033] The memory device 1000 may include a memory device 100 and a memory controller 200 .

[0034] The memory device 100 may operate in response to the control of the memory controller 200. Specifically, the memory device 100 may receive a command and an address from the memory controller 200 and access a memory cell selected by the address in a memory cell array (not shown). The memory device 100 may perform an operation indicated by the command on the memory cell selected by the address.

[0035] The command may be, for example, a program command, a read command, or an erase command, and the operation indicated by the command may be, for example, a program operation (or a write operation), a read operation, or an erase operation.

[0036] For example, the memory device 100 may receive a program command, an address, and data, and program the data in a memory cell selected by the address.

[0037] For example, the memory device 100 may receive a read command and an address, and read data from a region selected by the address in the memory cell array.

[0038] For example, the memory device 100 may receive an erase command and an address, and erase data stored in a region selected by the address.

[0039] For example, the memory device 100 may be implemented as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory, or a spin transfer torque random access memory (STT-RAM), etc.

[0040] In this specification, the present invention is described in a case where the memory device 100 is a NAND flash memory as an example.

[0041] The memory device 100 may store data under the control of the memory controller 200 or provide the stored data to the memory controller 200 .

[0042] The memory device 100 may include a memory cell array (not shown) including memory cells storing data.

[0043] The memory cell array (not shown) may include a plurality of memory blocks (not shown). The memory block may be a unit for performing an erase operation of erasing data.

[0044] The memory block may include a plurality of pages (not shown). A page may be a unit for performing a program operation of storing data or a read operation of sensing stored data.

[0045] The memory device 100 may include a program operation controller 131 .

[0046] The program operation controller 131 may control the memory device 100 to perform a program operation of storing data in selected memory cells in response to a program command provided by the memory controller 200 .

[0047] The program operation controller 131 may store the result of the program operation. The memory controller 200 may request the program operation result from the memory device 100. Further, the memory controller 200 may determine whether the program operation is successfully performed based on the program operation result received from the memory device 100.

[0048] The programming operation may include increasing the threshold voltage of the selected memory cell so that the threshold voltage of the selected memory cell is included in any one of a plurality of programming states. The programming state of the memory cell being programmed may be determined based on the data to be stored in the corresponding memory cell. That is, the target programming state may be determined based on the data to be stored in the memory cell.

[0049] The program operation may be performed in units of pages. A page may be a plurality of memory cells connected to the same word line.

[0050] The number of programming states can be determined according to the number of bits of data stored in the memory cell. For example, the memory cell can be configured as a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, and a quad-level cell (QLC) storing four bits of data.

[0051] In SLC, the target programming state may be the first programming state or the second programming state. In MLC, the target programming state may be any one of the first to fourth programming states. In TLC, the target programming state may be any one of the first to eighth programming states. In QLC, the target programming state may be any one of the first to sixteenth programming states.

[0052] The program operation may include a plurality of program loops. The program loop may include a program voltage applying operation and a verification operation.

[0053] The program voltage applying operation may include applying a program voltage to a selected word line, the selected word line being a word line commonly connected to the selected memory cells.

[0054] The verification operation may include determining whether the threshold voltage of the memory cell reaches the target threshold voltage corresponding to the target programming state. In the verification operation, the verification voltage corresponding to the target programming state may be applied to the selected word line. When the threshold voltage of the memory cell is greater than the verification voltage, it may be determined that the verification operation passes. When the threshold voltage of the memory cell is less than or equal to the verification voltage, it may be determined that the verification operation fails. When the verification operation of a set number of memory cells among the memory cells having the same target programming state passes, the verification of the corresponding target programming state may be completed.

[0055] When verification of all target program states is completed, the program operation may be completed. When the program operation is completed, it may be determined that the program operation is passed.

[0056] When the program operation does not pass within a set reference time, the program operation may be determined to have failed. Alternatively, when the program operation does not pass even after executing a maximum allowed number of program loops indicated by a set maximum loop count, the program operation may be determined to have failed.

[0057] According to an embodiment of the present disclosure, the program operation controller 131 may determine that the program operation fails even if verification of all target program states is completed.

[0058] Specifically, while performing a program operation, the program operation controller 131 may store a first pass loop count and a second pass loop count corresponding to each of a plurality of program states.

[0059] When the program operation is completed, the program operation controller 131 may calculate the difference between the first pass loop count and the second pass loop count. Further, the program operation controller 131 may determine whether the program operation is passed or failed according to whether any of the differences exceeds a set reference value.

[0060] The first pass loop count may indicate a program loop in which memory cells having passed a verification operation respectively corresponding to each program state are first sensed.

[0061] The second pass loop count may indicate a program loop that completes verification of a target program state.

[0062] Refer to the following Figure 7 The programming operation controller 131 is described in detail.

[0063] The memory controller 200 may control the overall operations of the memory device 1000 .

[0064] When power is supplied to the memory device 1000, the memory controller 200 may execute firmware. When the memory device 1000 is a flash memory device, the firmware may include a host interface layer, a flash translation layer, and a flash interface layer.

[0065] The host interface layer may control operations between the host 400 and the memory controller 200 .

[0066] The flash translation layer may convert a logical address provided by the host 400 into a physical address. To this end, the memory controller 200 may store mapping data indicating a relationship between a logical address and a physical address.

[0067] The flash interface layer may control communication between the memory controller 200 and the memory device 100 .

[0068] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, and an erase operation, respectively, in response to a write request, a read request, and an erase request from the host 400 .

[0069] During a program operation, the memory controller 200 may provide a write command, a physical address, and data to the memory device 100 .

[0070] During a read operation, the memory controller 200 may provide a read command and a physical address to the memory device 100 .

[0071] During an erase operation, the memory controller 200 may provide an erase command and a physical address to the memory device 100 .

[0072] The memory controller 200 may autonomously generate a command, an address, and data without a request provided by the host 400. The memory controller 200 may transmit the autonomously generated command, address, and data to the memory device 100.

[0073] For example, the memory controller 200 may generate a command, an address, and data for performing a background operation. In addition, the memory controller 200 may provide the command, the address, and the data to the memory device 100.

[0074] Background operations can be wear leveling, read reclamation, and / or garbage collection.

[0075] The memory controller 200 may control two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operation performance.

[0076] The interleaving method may be a method of performing control so that operations on two or more memory devices 100 overlap.

[0077] The host 400 may communicate with the storage device 1000 through an interface (not shown).

[0078] The interface may be implemented as a Serial Advanced Technology Attachment (SATA) interface, a high-speed SATA (SATA express) interface, a serial small computer system interface (SAS) interface, a high-speed peripheral component interconnect (PCIe) interface, a high-speed non-volatile memory (NVMe) interface, an advanced host controller interface (AHCI) or a multimedia card interface. However, the interface is not limited thereto.

[0079] The host 400 may communicate with the storage device 1000 to store data in the storage device 1000 or obtain data stored in the storage device 1000 .

[0080] In an embodiment, the host 400 may provide a write request to the storage device 1000 to request data to be stored in the storage device 1000. In addition, the host 400 may provide a write request, data, and a logical address identifying data to be written (stored) in the storage device 1000.

[0081] The memory device 1000 may store data provided by the host 400 in the memory device 100 in response to a write request provided by the host 400 and provide a storage completion response to the host 400 .

[0082] In an embodiment, the host 400 may provide a read request to the memory device 1000 to request that data stored in the memory device 1000 be transmitted to the host 400. In addition, the host 400 may provide the memory device 1000 with a read request and a read address.

[0083] The memory device 1000 may read data corresponding to a read address provided by the host 400 from the memory device 100 in response to a read request from the host 400 and provide the read data to the host 400 in response to the read request.

[0084] Figure 2 Is used to describe Figure 1 A diagram of an embodiment of a memory device 100 is shown.

[0085] Reference Figure 1 and Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0086] The memory cell array 110 may include a plurality of memory blocks MB1 to MBk (where k is a positive integer).

[0087] Each of the memory blocks MB1 to MBk may be connected to a local line LL and bit lines BL1 to BLn (where n is a positive integer).

[0088] The local line LL may be connected to each of the memory blocks MB1 to MBk.

[0089] Although not shown, the local line LL may include a first selection line, a second selection line, and a plurality of word lines disposed between the first selection line and the second selection line.

[0090] Although not shown, the local line LL may further include a dummy line disposed between the first selection line and the word line, a dummy line disposed between the second selection line and the word line, and a pipe line.

[0091] The bit lines BL1 to BLn may be commonly connected to the memory blocks MB1 to MBk.

[0092] The memory blocks MB1 to MBk may be implemented in a two-dimensional or three-dimensional structure.

[0093] In the memory blocks MB1 to MBk of a two-dimensional structure, memory cells may be arranged in a direction parallel to a substrate.

[0094] In the memory blocks MB1 to MBk of the three-dimensional structure, memory cells may be stacked in a vertical direction on a substrate.

[0095] The peripheral circuit 120 may include a voltage generator 121 , a row decoder 122 , a page buffer group 123 , a column decoder 124 , an input / output (I / O) circuit 125 , and a sensing circuit 126 .

[0096] The voltage generator 121 may generate various operation voltages Vop for programming, reading, and erasing operations in response to the operation signal OP_CMD. In addition, the voltage generator 121 may selectively discharge the local line LL in response to the operation signal OP_CMD. For example, the voltage generator 121 may generate a program voltage, a verification voltage, a pass voltage, a turn-on voltage, a read voltage, an erase voltage, a source line voltage, etc. under the control of the control logic 130.

[0097] In an embodiment, the voltage generator 121 may regulate an external power supply voltage to generate an internal power supply voltage. The internal power supply voltage generated by the voltage generator 121 is used as an operating voltage of the memory device 100.

[0098] In an embodiment, the voltage generator 121 may generate a plurality of operating voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 121 may include a plurality of pumping capacitors receiving the internal power supply voltage, and may generate a plurality of voltages by selectively enabling the plurality of pumping capacitors in response to the control of the control logic 130. The plurality of generated voltages may be supplied to the memory cell array 110 through the row decoder 122.

[0099] The row decoder 122 may transfer the operating voltage Vop to the local line LL in response to the row address RADD. The operating voltage Vop may be transferred to the selected memory block through the local line LL.

[0100] During a program operation, row decoder 122 may apply a program voltage to a selected word line and apply a program pass voltage having a level less than the program voltage to unselected word lines. During a program verification operation, row decoder 122 may apply a verification voltage to a selected word line and apply a verification pass voltage greater than the verification voltage to unselected word lines.

[0101] During a read operation, the row decoder 122 may apply a read voltage to a selected word line and apply a read pass voltage greater than the read voltage to unselected word lines.

[0102] During an erase operation, the row decoder 122 may select a memory block according to a decoded address. Further, the row decoder 122 may apply a ground voltage to a word line connected to the selected memory block.

[0103] The page buffer group 123 may include first to nth page buffers PB1 to PBn, which may be connected to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn may operate in response to the control of the control logic 130.

[0104] Specifically, the first to nth page buffers PB1 to PBn may operate in response to the page buffer control signal PBSIGNALS. For example, during a read operation or a verification operation, the first to nth page buffers PB1 to PBn may temporarily store data received through the first to nth bit lines BL1 to BLn, or may sense voltages or currents of the bit lines BL1 to BLn.

[0105] During a programming operation, when a programming voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn may transmit data DATA received through the column decoder 124 and the input / output circuit 125 to the selected memory cells through the first to nth bit lines BL1 to BLn. The memory cells of the selected page are programmed according to the transmitted data DATA. The memory cells connected to the bit lines to which a programming enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a programming inhibit voltage (e.g., a power supply voltage) is applied may be maintained.

[0106] During a verification operation, the first to nth page buffers PB1 to PBn may sense data stored in memory cells selected from among selected memory cells through the first to nth bit lines BL1 to BLn.

[0107] During a read operation, the first to nth page buffers PB1 to PBn may sense data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124 .

[0108] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn.

[0109] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0110] The input / output circuit 125 may transfer a command CMD and an address ADD received from the memory controller 200 to the control logic 130 , or may exchange data DATA with the column decoder 124 .

[0111] During a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to the enable bit signal VRY_BIT<#>. Further, the sensing circuit 126 may compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0112] The control logic 130 may output an operation signal OP_CMD, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRY_BIT<#> in response to a command CMD and an address ADD to control the peripheral circuit 120 .

[0113] The control logic 130 may include a program operation controller 131 .

[0114] Even if verification of all target program states is completed, the program operation controller 131 may determine that the program operation fails.

[0115] Specifically, while performing a program operation, the program operation controller 131 may store a first pass loop count and a second pass loop count corresponding to each of a plurality of program states.

[0116] When the program operation is completed, the program operation controller 131 may respectively calculate the difference between the first pass loop count and the second pass loop count. Further, the program operation controller 131 may determine whether the program operation is passed or failed according to whether any of the differences exceeds a set reference value.

[0117] The first pass loop count may indicate a program loop in which memory cells having passed a verification operation respectively corresponding to each program state are first sensed.

[0118] The second pass loop count may indicate a program loop that completes verification of a target program state.

[0119] Figure 3 It is shown Figure 2 A diagram of an embodiment of a structure of a representative memory block MBi of a plurality of memory blocks is shown.

[0120] Reference Figure 2 and Figure 3 , Figure 3 The memory blocks MBi shown may be Figure 2 Any one of the storage blocks MB1 to MBk.

[0121] The memory block MBi may include a first selection line, a second selection line, a plurality of word lines WL1 to WL16 , a source line SL, a plurality of bit lines BL1 to BLn, and a plurality of strings ST.

[0122] The first selection line may be, for example, a source selection line SSL. Hereinafter, it is assumed that the first selection line is the source selection line SSL.

[0123] The second selection line may be, for example, a drain selection line DSL. Hereinafter, it is assumed that the second selection line is the drain selection line DSL.

[0124] A plurality of word lines WL1 to WL16 may be arranged in parallel between the source select line SSL and the drain select line DSL.

[0125] Figure 3 The number of word lines WL1 to WL16 shown is an example, and the number of word lines is not limited to 16. Hereinafter, it is assumed that the number of the plurality of word lines is 16 as an example.

[0126] The source lines SL may be commonly connected to the plurality of strings ST.

[0127] A plurality of bit lines BL1 to BLn may be connected to the strings ST, respectively.

[0128] The plurality of strings ST may be connected to bit lines BL1 to BLn and a source line SL.

[0129] Since the strings ST may be configured identically to one another, the string ST connected to the first bit line BL1 is described in detail as an example.

[0130] The string ST may include a plurality of memory cells MC1 to MC16 , at least one first selection transistor, and at least one second selection transistor.

[0131] The plurality of memory cells MC1 to MC16 may be connected in series between the source select transistor SST and the drain select transistor DST.

[0132] The gates of the memory cells MC1 to MC16 may be connected to a plurality of word lines WL1 to WL16, respectively. Therefore, the number of memory cells MC1 to MC16 included in one string ST may be the same as the number of word lines WL1 to WL16. Hereinafter, as an example, it is assumed that there are 16 memory cells, the same as the number of word lines WL1 to WL16.

[0133] Any one of the plurality of memory cells MC1 to MC16 may be configured as any one of SLC, MLC, TLC, and QLC.

[0134] A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PG. Therefore, the memory block MBi may include a physical page PG corresponding to the number of word lines WL1 to WL16. Hereinafter, it is assumed that the memory cell (e.g., MC3) included in the physical page PG is the selected memory cell.

[0135] The first selection transistor may be, for example, a source selection transistor SST. Hereinafter, it is assumed that the first selection transistor is a source selection transistor SST.

[0136] A first electrode of the source select transistor SST may be connected to a source line SL. A second electrode of the source select transistor SST may be connected to a first memory cell MC1 among a plurality of memory cells MC1 to MC16. A gate electrode of the source select transistor SST may be connected to a source select line SSL.

[0137] The second selection transistor may be, for example, a drain selection transistor DST. Hereinafter, it is assumed that the second selection transistor is a drain selection transistor DST.

[0138] A first electrode of the drain select transistor DST may be connected to a sixteenth memory cell MC16 among the plurality of memory cells MC1 to MC16. A second electrode of the drain select transistor DST may be connected to a first bit line BL1. A gate electrode of the drain select transistor DST may be connected to a drain select line DSL.

[0139] Figure 4 2 is a diagram illustrating a program operation and a verification operation executed in a program loop according to an embodiment of the present disclosure.

[0140] Reference Figure 4 , a programming operation may include multiple programming cycles.

[0141] The value of each programming loop may be its programming loop count. For example, the value of the first programming loop may be 1, the value of the second programming loop may be 2, and the value of the third programming loop may be 3.

[0142] Each program loop may include a program voltage applying operation and a verification operation.

[0143] The program voltage applying operation may include applying a program voltage Vpgm to a selected word line.

[0144] For example, when the first programming state is the erased state, the first programming voltage application operation in the first programming loop may include applying the first programming voltage Vpgm1 to the memory cell programmed with the second programming state as the target programming state. For example, the second programming voltage application operation in the second programming loop may include applying the second programming voltage Vpgm2 to the memory cell programmed with the third programming state as the target programming state. For example, the third programming voltage application operation in the third programming loop may include applying the third programming voltage Vpgm3 to the memory cell programmed with the fourth programming state as the target programming state.

[0145] The verification operation may include determining whether a threshold voltage Vth of a memory cell reaches a target threshold voltage. In the verification operation, a verification voltage Vfy corresponding to a target program state may be applied to a selected word line.

[0146] For example, when the first programming state is the erased state, the first verification operation in each of the first programming loop to the third programming loop may be an operation of determining whether the threshold voltage Vth of the memory cell reaches the target threshold voltage corresponding to the second programming state as the target programming state. In addition, in the first verification operation, a first verification voltage Vfy1 corresponding to the second programming state may be applied. The second verification operation in each of the first programming loop to the third programming loop may be an operation of determining whether the threshold voltage Vth of the memory cell reaches the target threshold voltage corresponding to the third programming state as the target programming state. In addition, in the second verification operation, a second verification voltage Vfy2 corresponding to the third programming state may be applied. However, the present disclosure is not limited thereto.

[0147] When the threshold voltage Vth of the memory cell is greater than the verification voltage Vfy, the verification operation passes. When the threshold voltage Vth of the memory cell is less than or equal to the verification voltage Vfy, the verification operation fails.

[0148] When verification operations on a set number of memory cells among memory cells having the same target program state are passed, verification of the corresponding target program state may be completed.

[0149] When verification of all target program states is completed, the program operation may be completed. When the program operation is completed, it may be determined that the program operation is passed.

[0150] When the program operation does not pass within the set reference time, the program operation may be determined to have failed. Alternatively, when the program operation does not pass even after performing the maximum number of program loops indicated by the set maximum loop count Max, the program operation may be determined to have failed.

[0151] The program voltage Vpgm may be provided according to an incremental step pulse programming (ISPP) method. Each time a program loop is repeated, the program voltage Vpgm may increase by a set step voltage ΔV. That is, the program voltage Vpgm may sequentially increase from a first program voltage Vpgm1 to an Mth program voltage VpgmM.

[0152] After applying the program voltage Vpgm, at least one verification voltage Vfy in one programming loop may be applied. Specifically, in the programming loop, after applying the program voltage Vpgm, at least one verification voltage (eg, Vfy1) among a plurality of verification voltages Vfy1 to Vfy7 may be applied.

[0153] The program voltages Vpgm1 to VpgmM and the verification voltages Vfy1 to Vfy7 may be repeatedly applied until a maximum loop count Max is reached.

[0154] Figure 5 is a diagram illustrating a programming state according to an embodiment of the present disclosure.

[0155] In the case of TLC storing 3-bit data, Figure 5 Give a description.

[0156] Reference Figure 5 The target programming state may be any one of a plurality of programming states, namely, P1 to P8. The first programming state P1 may be, for example, an erase state.

[0157] The memory cell may have a threshold voltage belonging to a threshold voltage distribution corresponding to any one of program states P1 to P8 through a program operation.

[0158] Before performing a program operation, the memory cell may be in a first program state P1. In an embodiment, the first program state P1 may be a state of the memory cell after performing an erase operation.

[0159] Because the programming voltage Vpgm increases by the set step voltage ΔV each time the continuous programming loop is repeated, the threshold voltage Vth of the memory cell can be changed according to the programming voltage Vpgm. The threshold voltage Vth of the memory cell can increase as the programming voltage application operation proceeds. In addition, the threshold voltage distribution corresponding to the state of the memory cell after the erase operation is performed can change as the programming voltage application operation proceeds. Specifically, the threshold voltage distribution corresponding to the state of the memory cell after the erase operation is performed can change (or move) in the direction of the increase of the threshold voltage Vth.

[0160] As the program voltage applying operation proceeds, verification operations may be sequentially performed from the second program state P2 to the eighth program state P8 .

[0161] The verification operation corresponding to the second programming state P2 may include determining whether the threshold voltage of the memory cell reaches a target threshold voltage corresponding to the second programming state P2 as a target programming state. The verification voltage corresponding to the second programming state P2 may be a first verification voltage Vfy1. That is, the target threshold voltage corresponding to the second programming state P2 may be the first verification voltage Vfy1. During the verification operation using the first verification voltage Vfy1, a memory cell having a threshold voltage Vth greater than the first verification voltage Vfy1 may be in an off state (or may be an off cell). During the verification operation using the first verification voltage Vfy1, a memory cell having a threshold voltage Vth less than or equal to the first verification voltage Vfy1 may be in an on state (or may be an on cell).

[0162] The verification operation corresponding to the third programming state P3 to the eighth programming state P8 may include determining whether the threshold voltage of the memory cell reaches the target threshold voltage corresponding to the target programming state (e.g., the third programming state P3 to the eighth programming state P8). In this case, the verification voltage corresponding to the third programming state P3 to the eighth programming state P8 may be the second verification voltage Vfy2 to the seventh verification voltage Vfy7.

[0163] Figure 6 is a diagram illustrating passing cycle counting according to an embodiment of the present disclosure.

[0164] Reference Figure 6 , a threshold voltage distribution corresponding to any one programming state (eg, P3) among the second programming state P2 to the eighth programming state P8 is described.

[0165] exist Figure 6 In the embodiment, as programming loops are repeated, each programming loop includes a programming voltage applying operation of applying a programming voltage (e.g., Vpgm2) for a programming state (e.g., P3) and a verification operation of applying a verification voltage (e.g., Vfy2) for the programming state (e.g., P3), the threshold voltage distribution VTHD of the memory cell can be changed in an order from a first threshold voltage distribution VTHD_1 to a kth threshold voltage distribution VTHD_k.

[0166] In an embodiment, the first pass loop count may be a value of a program loop in which memory cells passing a verification operation corresponding to each program state are initially sensed.

[0167] Reference Figures 4 to 6 , for example, according to a second program voltage applying operation in a second program loop, a second program voltage Vpgm2 may be applied to the selected memory cells.

[0168] The threshold voltage distribution VTHD of memory cells to be programmed to the third program state P3 may be changed from a target voltage distribution corresponding to the state (eg, P1 ) of the memory cells after performing an erase operation to the first threshold voltage distribution VTHD_1 .

[0169] In the second verification operation in the second programming loop, a target threshold voltage Vth_target corresponding to the third programming state P3, that is, a second verification voltage Vfy2 for verifying the third programming state P3 may be applied to the selected memory cell. At least one memory cell having a threshold voltage Vth greater than the second verification voltage Vfy2 among the threshold voltages Vth belonging to the first threshold voltage distribution VTHD_1 may be initially sensed. That is, the second verification operation in the second programming loop may be initially passed. In this case, the first pass loop count may be 2, which is the value of the second programming loop.

[0170] In an embodiment, the first passed loop count may be a value of a program loop in which a verification operation on a first set reference number of memory cells among memory cells having the same target program state passes.

[0171] For example, during the second verification operation in the second programming loop, a number of memory cells less than the first reference number among the memory cells to be programmed to the third programming state passes the second verification operation. During the second verification operation in the third programming loop, when a first reference number of memory cells among the memory cells to be programmed to the third programming state passes the second verification operation, the first pass loop count may be 3, which is a value of the third programming loop.

[0172] In an embodiment, the second pass loop count may be a value of a programming loop at which verification of a target programming state is completed. When verification operations of a second reference number of memory cells among memory cells having the same target programming state are passed, verification of the corresponding target programming state may be completed.

[0173] Reference Figures 4 to 6 , for example, according to a third program voltage applying operation in a third program loop, a third program voltage Vpgm3 may be applied to the selected memory cells.

[0174] The threshold voltage distribution VTHD of memory cells to be programmed to the third program state P3 may be changed from a target voltage distribution corresponding to the state (eg, P1) of the memory cells after performing an erase operation to a kth threshold voltage distribution VTHD_k.

[0175] In the second verification operation included in the third programming loop, a second verification voltage Vfy2 may be applied to the selected memory cell. Among the threshold voltages Vth belonging to the kth threshold voltage distribution VTHD_k, a second reference number of memory cells having a threshold voltage Vth greater than the second verification voltage Vfy2 may be sensed. That is, the second verification operation in the third programming loop may be passed last. Therefore, since the verification for the third programming state is completed, the second pass loop count may be 3, which is the value of the third programming loop.

[0176] In an embodiment, the first reference number may be smaller than the second reference number.

[0177] Figure 7 It is shown Figure 2 A diagram of an embodiment of a programming operation controller 131 is shown.

[0178] Reference Figure 7 , the program operation controller 131 may include a program verifier 131_1 , a loop count storage device 131_2 , and a status register 131_3 .

[0179] Program verifier 131_1 may receive a pass signal PASS or a fail signal FAIL.

[0180] Program verifier 131_1 may detect first and second pass loop counts PLC1 and PLC2 corresponding to one program state in response to pass signal PASS or fail signal FAIL. In addition, program verifier 131_1 may detect first and second pass loop counts PLC1 and PLC2 corresponding to a plurality of program states.

[0181] The program verifier 131_1 may provide the first pass loop count PLC1 and the second pass loop count PLC2 to the loop count storage device 131_2 .

[0182] The loop count storage device 131_2 may store a first pass loop count PLC1 and a second pass loop count PLC2 corresponding to each of a plurality of program states determined while performing a program operation.

[0183] When the program operation is completed, the program verifier 131_1 may receive the first pass loop count PLC1 and the second pass loop count PLC2 stored in the loop count storage 131_2 .

[0184] When the program operation is completed, program verifier 131_1 may calculate a difference between first and second pass loop counts PLC1 and PLC2 corresponding to one program state. That is, program verifier 131_1 may calculate a difference between corresponding pairs of PLC1 and PLC2 for a plurality of program states.

[0185] The program verifier 131_1 may output a result of performing a program operation according to whether there is a difference value exceeding a set reference value among the difference values. The result of performing a program operation may indicate any one of a pass state PS and a fail state FS.

[0186] The reference value may be stored in the program verifier 131_1 , but the present invention is not limited thereto.

[0187] In an embodiment, program verifier 131_1 may output a result of performing a program operation indicating a fail state FS in response to the presence of a difference value exceeding a reference value. That is, when there is at least one difference value exceeding a reference value, program verifier 131_1 may output a result of performing a program operation indicating a fail state FS.

[0188] In an embodiment, program verifier 131_1 may output a result of performing a program operation indicating a pass state PS in response to all difference values ​​being less than or equal to a reference value.

[0189] Program verifier 131_1 may provide a result of performing a program operation indicating a pass state PS or a fail state FS to status register 131_3 .

[0190] The status register 131_3 may store a result of performing a program operation, which may indicate a pass status PS or a fail status FS.

[0191] Figure 8 It is shown Figure 7 A diagram of first pass cycle counts and second pass cycle counts stored in a cycle count storage device is shown.

[0192] exist Figure 8 PV1 to PV7 can correspond to reference Figure 5 The second programming state P2 to the eighth programming state P8 are described.

[0193] In the description Figure 8 When, as above reference Figure 5 As described above, the selected memory cell is a triple-level cell, and thus the present embodiment is described in the case where the number of the plurality of programming states is eight.

[0194] Reference Figure 7 and Figure 8, the loop count storage device 131_2 may store a first pass loop count PLC1 and a second pass loop count PLC2 for each of a plurality of programming states P1 to P8. In addition, the first pass loop count PLC1 and the second pass loop count PLC2 have values ​​of programming loops.

[0195] For example, the first pass loop count PLC1 of the second programming state P2 or PV1 may be x1, and the second pass loop count PLC2 of the second programming state P2 or PV1 may be y1. For example, the first pass loop count PLC1 of the third programming state P3 or PV2 may be x2, and the second pass loop count PLC2 of the third programming state P3 or PV2 may be y2. For example, the first pass loop count PLC1 of the fourth programming state P4 or PV3 may be x3, and the second pass loop count PLC2 of the fourth programming state P4 or PV3 may be y3. For example, the first pass loop count PLC1 of the fifth programming state P5 or PV4 may be x4, and the second pass loop count PLC2 of the fifth programming state P5 or PV4 may be y4. For example, the first pass loop count PLC1 of the sixth programming state P6 or PV5 may be x5, and the second pass loop count PLC2 of the sixth programming state P6 or PV5 may be y5. For example, the first pass loop count PLC1 of the seventh programming state P7 or PV6 may be x6, and the second pass loop count PLC2 of the seventh programming state P7 or PV6 may be y6. For example, the first pass loop count PLC1 of the eighth program state P8 or PV7 may be x7, and the second pass loop count PLC2 of the eighth program state P8 or PV7 may be y7.

[0196] When the programming operation is completed, the program verifier 131_1 may calculate the difference (|PLC1-PLC2|) between the corresponding first pass loop count PLC1 and the second pass loop count PLC2 from the loop count storage device 131_2. In an embodiment, the second pass loop count PLC2 may be greater than or equal to the first pass loop count PLC1. In the following, it is assumed that the second pass loop count PLC2 is greater than or equal to the first pass loop count PLC1.

[0197] For example, the program verifier 131_1 may calculate the difference (y1-x1) between the first pass loop count PLC1 and the second pass loop count PLC2 for the second programming state P2 or PV1. For example, the program verifier 131_1 may calculate the difference (y2-x2) between the first pass loop count PLC1 and the second pass loop count PLC2 for the third programming state P3 or PV2. For example, the program verifier 131_1 may calculate the difference (y3-x3) between the first pass loop count PLC1 and the second pass loop count PLC2 for the fourth programming state P4 or PV3. For example, the program verifier 131_1 may calculate the difference (y4-x4) between the first pass loop count PLC1 and the second pass loop count PLC2 for the fifth programming state P5 or PV4. For example, the program verifier 131_1 may calculate the difference (y5-x5) between the first pass loop count PLC1 and the second pass loop count PLC2 for the sixth programming state P6 or PV5. For example, the program verifier 131_1 may calculate the difference (y6-x6) between the first pass loop count PLC1 and the second pass loop count PLC2 for the seventh program state P7 or PV6. For example, the program verifier 131_1 may calculate the difference (y7-x7) between the first pass loop count PLC1 and the second pass loop count PLC2 for the eighth program state P8 or PV7.

[0198] Program verifier 131_1 may store the result of performing a programming operation in status register 131_3 depending on whether a difference exceeding a set reference value exists among the difference values ​​(y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7).

[0199] For example, the program verifier 131_1 may store the result of executing the programming operation indicating a failed state FS in the status register 131_3 based on at least one difference value among the difference values ​​(y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7) exceeding a set reference value.

[0200] For example, program verifier 131_1 may store a result indicating the execution of a program operation through state PS in state register 131_3 based on all difference values ​​(y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7) being less than or equal to a reference value.

[0201] Fig. 9 It shows the operation Figure 1 A flow chart of an embodiment of a method of a memory device 100 is shown.

[0202] Reference Fig. 9 , while performing programming operations, such as Figure 8 As shown, the memory device 100 stores a first pass loop count PLC1 and a second pass loop count PLC2 corresponding to each of a plurality of program states (S110).

[0203] When the programming operation is completed, such as Figure 8 As shown, the memory device 100 calculates differences (y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7) between the first pass loop count PLC1 and the second pass loop count PLC2 (S120).

[0204] The memory device 100 determines whether at least one of the difference values ​​among the difference values ​​(y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7) exceeds a set reference value (S130).

[0205] When at least one of the difference values ​​exceeds the reference value ( S130 , Yes), the memory device 100 stores the result of performing the program operation indicating the fail state FS ( S140 ).

[0206] When no difference value exceeds the reference value, that is, each of the difference values ​​(y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6) and (y7-x7) is less than or equal to the reference value (S130, No), the memory device 100 stores a result indicating the execution of the programming operation through state PS (S150).

[0207] Fig.10 Is used to describe Figure 1 A diagram of an embodiment of a memory controller 200 is shown.

[0208] Reference Figure 1 and Fig.10 , the memory controller 200 may include a processor 210 , a random access memory (RAM) 220 , an error correction circuit (ie, an ECC circuit) 230 , a read only memory (ROM) 260 , a host interface 270 , and a flash memory interface 280 .

[0209] The processor 210 may control the overall operation of the memory controller 200. The RAM 220 may be used as a buffer memory, a cache memory, and an operation memory of the memory controller 200. In addition to the RAM 220, a static random access memory (SRAM) may be used as a buffer memory.

[0210] The ROM 260 may store various information for the memory controller 200 to operate via firmware.

[0211] The memory controller 200 may communicate with an external device (eg, the host 400 , an application processor, etc.) through the host interface 270 .

[0212] The memory controller 200 may communicate with the memory device 100 through the flash interface 280. The memory controller 200 may transmit a command CMD, an address ADDR, and a control signal CTRL to the memory device 100 through the flash interface 280 and receive data DATA.

[0213] For example, flash memory interface 280 may include a NAND interface.

[0214] Fig.11 is a block diagram illustrating a memory card system 2000 to which a storage device is applied according to an embodiment of the present disclosure.

[0215] Reference Figure 1 and Fig.11 , the memory card system 2000 includes a memory device 2100 , a memory controller 2200 , and a connector 2300 .

[0216] For example, the memory device 2100 may be configured as any of a variety of non-volatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque magnetic RAM (STT-MRAM).

[0217] The memory controller 2200 is connected to the memory device 2100. The memory controller 2200 is configured to access the memory device 2100. For example, the memory controller 2200 may be configured to control a read operation, a write operation, an erase operation, and a background operation of the memory device 2100. The memory controller 2200 is configured to provide an interface between the memory device 2100 and the host 400. The memory controller 2200 is configured to drive firmware for controlling the memory device 2100. The memory controller 2200 may be implemented as a reference Figure 1 The memory controller 200 described is the same.

[0218] For example, the memory controller 2200 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error correction circuit.

[0219] The memory controller 2200 may communicate with an external device through the connector 2300. The memory controller 2200 may communicate with an external device (e.g., the host 400) according to a specific communication standard. For example, the memory controller 2200 is configured to communicate with an external device through at least one of various communication standards such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the various communication standards described above.

[0220] The memory device 2100 and the memory controller 2200 can be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (e.g., SM or SMC), a Memory Stick, a Multimedia Card (e.g., MMC, RS-MMC, Micro MMC, or eMMC), a Secure Digital (SD) card (e.g., SD, Mini SD, Micro SD, or SDHC), and / or Universal Flash Storage (UFS).

[0221] Fig.12 is a block diagram illustrating a solid state drive (SSD) system 3000 to which a storage device is applied according to an embodiment of the present disclosure.

[0222] Reference Fig.12 , the SSD system includes a host 400 and an SSD 3000 .

[0223] The SSD 3000 exchanges a signal SIG with the host 400 through the signal connector 3001 and receives power PWR through the power connector 3002. The SSD 3000 includes an SSD controller 3200, a plurality of flash memories 3100_1, 3100_2, and 3100_n, an auxiliary power supply device 3300, and a buffer memory 3400.

[0224] According to an embodiment of the present disclosure, the SSD controller 3200 may perform a reference Figure 1 The functions of the memory controller 200 are described.

[0225] The SSD controller 3200 may control the plurality of flash memories 3100_1, 3100_2, and 3100_n in response to a signal SIG received from the host 400. For example, the signal SIG may include a signal based on an interface between the host 400 and the SSD 3000. For example, the signal SIG may be defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), high-speed PCI (PCI-e or PCIe), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an electronic integrated drive (IDE), a firewire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0226] The auxiliary power supply device 3300 is connected to the host 400 through the power connector 3002. The auxiliary power supply device 3300 can receive power PWR from the host 400 and can charge power. When the power supply from the host 400 is not stable, the auxiliary power supply device 3300 can supply power to the SSD 3000. For example, the auxiliary power supply device 3300 can be set in or outside the SSD 3000. For example, the auxiliary power supply device 3300 can be set on the mainboard and can provide auxiliary power to the SSD 3000.

[0227] The buffer memory 3400 may temporarily store data. For example, the buffer memory 3400 may temporarily store data received from the host 400 or data received from the plurality of flash memories 3100_1, 3100_2, and 3100_n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3100_1, 3100_2, and 3100_n. The buffer memory 3400 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0228] Fig.13 is a block diagram illustrating a user system 4000 of an application storage device according to an embodiment of the present disclosure.

[0229] The user system 4000 includes an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0230] The application processor 4100 may drive components included in the user system 4000, an operating system (OS), a user program, etc. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. that controls components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0231] The memory module 4200 may operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a nonvolatile random access memory such as FRAM, ReRAM, MRAM, and PRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a stacked package (POP) and provided as one semiconductor package.

[0232] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0233] The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may transmit the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 may be implemented as a non-volatile semiconductor memory element such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, and a three-dimensional NAND flash memory. For example, the storage module 4400 may be configured as a removable storage device (removable drive), such as a memory card and an external drive of the user system 4000.

[0234] For example, the storage module 4400 may be configured to be Figure 1 The storage module 4400 may include a plurality of nonvolatile memory devices, and each of the plurality of nonvolatile memory devices may be configured in the same manner as in the reference 1000. Figure 1 The memory device 100 operates in the same manner as described.

[0235] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0236] While the invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes and / or modifications in form and details may be made in any disclosed embodiments without departing from the spirit and scope of the invention.

[0237] For example, it is not necessary to perform all steps in the order stated, and in some cases, one or more steps or parts thereof may be omitted. Moreover, the specific terms used in this article are intended to explain the embodiments of the present disclosure, rather than to limit the present invention. Therefore, the present invention encompasses all changes and modifications that fall within the scope of the claims.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cells; a peripheral circuit that performs a programming operation including a plurality of programming loops to respectively increase the threshold voltages of the plurality of memory cells so as to fall within a threshold voltage range corresponding to a target programming state among a plurality of programming states; a loop count storage device storing a first pass loop count and a second pass loop count for each of the plurality of programming states; as well as a program verifier that outputs a result of the program operation when at least one of a difference between a first pass loop count and a second pass loop count of each of the plurality of program states exceeds a reference value, the result of the program operation indicating a fail state, wherein the first pass loop count indicates a program loop when memory cells that have passed verification operations respectively corresponding to the plurality of program states exceed a first reference number, and The second passed loop count indicates a program loop when memory cells having passed verification operations respectively corresponding to the plurality of program states exceed a second reference number in verification for each target program state, the second reference number being greater than the first reference number. 2 . The memory device of claim 1 , wherein when memory cells that have passed the verification operation corresponding to the target program state exceed the second reference number, the verification operation for the target program state is completed.

3. The memory device according to claim 1, further comprising: A status register stores the result of the programming operation.

4. A memory device comprising: a memory cell array comprising a plurality of memory cells; a peripheral circuit that performs a programming operation including a plurality of programming loops to respectively increase the threshold voltages of the plurality of memory cells so as to fall within a threshold voltage range corresponding to a target programming state among a plurality of programming states; a loop count storage device storing a first pass loop count and a second pass loop count for each of the plurality of programming states; as well as a program verifier that outputs a result of the program operation when at least one of a difference between a first pass loop count and a second pass loop count of each of the plurality of program states exceeds a reference value, the result of the program operation indicating a fail state, wherein the first pass loop count indicates a program loop when memory cells that have passed verification operations respectively corresponding to the plurality of program states are initially sensed, and The second pass loop count indicates a program loop that completes a verification operation for each of the plurality of program states.

5. A method of operating a memory device, the method comprising: performing a programming operation that respectively increases the threshold voltages of the plurality of memory cells to fall within a threshold voltage range corresponding to a target programming state among the plurality of programming states; storing first pass loop counts and second pass loop counts for the plurality of programming states, respectively; outputting a result of the programming operation according to whether at least one of the differences between the first pass loop count and the second pass loop count of each of the plurality of programming states exceeds a reference value, the result of the programming operation indicating a fail state, wherein the first pass loop count indicates a program loop when memory cells that have passed verification operations respectively corresponding to the plurality of program states exceed a first reference number, and The second passed loop count indicates a program loop when memory cells having passed verification operations respectively corresponding to the plurality of program states exceed a second reference number in verification for each target program state, the second reference number being greater than the first reference number.

6. The method of claim 5, wherein the output comprises: generating a result of the programming operation indicating a failure of the programming operation in response to the at least one of the difference values ​​exceeding the reference value; and The result of performing the programming operation is stored in a status register.

7. A memory device comprising: a plurality of memory cells; a peripheral circuit that performs a programming operation that increases the threshold voltages of the plurality of memory cells so that the threshold voltages of the plurality of memory cells are included in any one of a plurality of programming states separated according to voltage magnitudes of the programming states; as well as The control logic outputs a result of the programming operation when at least one of the differences between the programming loops of the memory cells having passed the verification operations respectively corresponding to the plurality of programming states and the programming loops completing the verification operations for each of the plurality of programming states initially sensed to exceed a reference value, the result of the programming operation indicating a fail state.

8. The memory device of claim 7, further comprising: A status register stores the result of the programming operation.

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