A self-aligned double patterning method

Abstract

The invention provides a self-aligned double pattern manufacturing method, which comprises providing a silicon substrate provided with a first oxide layer, an amorphous silicon layer and an organic layer, etching the organic layer and the amorphous silicon layer according to a photoresist pattern, exposing the upper surface of the first oxide layer, and covering the top and side walls of the amorphous silicon pattern with a first silicon nitride layer; etching and removing the first silicon nitride layer on the top of the amorphous silicon pattern, forming a first silicon nitride sidewall pattern on the side walls of the amorphous silicon pattern; removing the amorphous silicon pattern between the first silicon nitride sidewall patterns; defining the morphology of a fin-type transistor, etching the first oxide layer and the silicon substrate to form a core pattern, and covering the core pattern with a thin silicon nitride layer; depositing a second oxide layer and grinding until the thin silicon nitride layer is exposed; defining the height of the fin-type transistor, etching back the second oxide layer until the height of the exposed core pattern meets the defined height of the fin-type transistor; removing the thin silicon nitride layer; and depositing a third oxide layer to cover the top and side walls of the exposed core pattern.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, in particular to a self-aligned double pattern manufacturing method. Background Art

[0002] The general process of the fin transistor logic chip process in the prior art is as follows (eg Figures 1 to 13 ): 1. Forming a first oxide layer 02, a silicon nitride hard mask layer A, a silicon oxide hard mask layer B, an amorphous silicon layer 03, and an organic layer 04 on a silicon substrate 01 in sequence; 2. Forming a photoresist pattern 05 on the organic layer; 3. Etching the organic layer and the amorphous silicon layer according to the photoresist pattern to form an amorphous silicon pattern 06; 4. Covering the amorphous silicon pattern with a first silicon nitride layer 07; 5. Etching the first silicon nitride layer 07 to expose the top of the amorphous silicon pattern; 5. Removing the amorphous silicon pattern and retaining the silicon nitride layer on the side wall of the amorphous silicon pattern to form a first silicon nitride sidewall pattern 08; 6. Etching the silicon oxide hard mask layer B and the silicon nitride hard mask layer A as well as the first oxide layer 02 and the silicon substrate according to the first silicon nitride sidewall pattern to form a core pattern 10 of the silicon substrate and a silicon nitride layer on the core pattern 10 7. Deposit a thin oxide layer 110; 8. Cover and fill the gaps between the silicon substrate patterns with a second oxide layer 12; 9. Grind the second oxide layer to the top of the silicon nitride hard mask pattern Aa; 10. Etch back the second oxide layer 12 to the top of the first oxide layer pattern 021 to expose the silicon nitride hard mask pattern Aa; 11. Remove the silicon nitride hard mask pattern; 12. Define the height of the fin transistor and etch back the second oxide layer 12 to expose a core pattern 10 of a portion of the silicon substrate; 13. Deposit a third oxide layer 13 on the sidewall and top of the exposed core pattern. In the prior art, the height of amorphous silicon defined by the core etching process is relatively high, resulting in a relatively high height of silicon nitride on the sidewall, which reduces the process window for filling the photoresist gap, and the production efficiency is low and the production cost is increased due to the complex process flow.

[0003] Therefore, it is necessary to propose a new self-aligned double patterning process to solve the above problems. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a self-aligned double patterning method for solving the problems in the prior art.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a method for producing a self-aligned double pattern, which comprises at least the following steps:

[0006] Step 1, providing a silicon substrate, wherein a first oxide layer is disposed on the silicon substrate; an amorphous silicon layer is disposed on the first oxide layer; and an organic layer is disposed on the amorphous silicon layer;

[0007] Step 2: using a mask plate to define the critical dimensions of polysilicon, then coating photoresist on the organic layer, and forming a photoresist pattern according to the critical dimensions of polysilicon;

[0008] Step 3, defining the height and critical dimensions of the amorphous silicon pattern, etching the organic layer and the amorphous silicon layer according to the photoresist pattern, etching until the upper surface of the first oxide layer is exposed, and forming the amorphous silicon pattern with the defined height and critical dimensions;

[0009] Step 4: Covering the top and sidewalls of the amorphous silicon pattern and the exposed upper surface of the first oxide layer with a first silicon nitride layer;

[0010] Step 5: etching and removing the first silicon nitride layer on the top of the amorphous silicon pattern to expose the top of the amorphous silicon pattern, and forming a first silicon nitride sidewall pattern on the sidewall of the amorphous silicon pattern;

[0011] Step six, removing the amorphous silicon pattern between the first silicon nitride sidewall patterns;

[0012] Step 7: define the fin transistor morphology, etch the first oxide layer and the silicon substrate along the first silicon nitride sidewall pattern, and form a core pattern of the silicon substrate with the defined fin transistor morphology and a first oxide layer pattern located on the core pattern;

[0013] Step eight, removing the first oxide layer pattern;

[0014] Step nine, covering the core pattern with a thin silicon nitride layer;

[0015] Step 10, depositing a second oxide layer covering the thin silicon nitride layer and filling the gaps between the core patterns;

[0016] Step 11, grinding the second oxide layer until the thin silicon nitride layer on the top of the core pattern is exposed;

[0017] Step 12, defining the height of the fin-type transistor, etching back the second oxide layer until the height of the exposed core pattern meets the defined height of the fin-type transistor;

[0018] Step 13: removing the exposed sidewalls and top thin silicon nitride layer of the core pattern;

[0019] Step 14: depositing a third oxide layer to cover the exposed top and sidewalls of the core pattern.

[0020] Preferably, the first oxide layer provided on the silicon substrate in step 1 is a silicon oxide layer, and the silicon oxide layer is formed by oxidizing the upper surface of the silicon substrate to form a silicon oxide layer.

[0021] Preferably, in step 1, the method for forming the amorphous silicon layer on the first oxide layer is: depositing amorphous silicon on the first oxide layer to form the amorphous silicon layer.

[0022] Preferably, the photoresist pattern in step 2 is a plurality of strip structures spaced apart from each other.

[0023] Preferably, the organic layer on the amorphous silicon pattern in step three is completely removed.

[0024] Preferably, the method for forming the first silicon nitride layer in step 4 is atomic layer deposition.

[0025] Preferably, in step nine, the method of covering the core pattern with the thin silicon nitride layer is an atomic layer deposition method.

[0026] Preferably, the method of depositing the second oxide layer in step ten is fluid chemical vapor deposition.

[0027] Preferably, in step eleven, the method of polishing the second oxide layer is chemical mechanical polishing.

[0028] Preferably, in step thirteen, phosphoric acid is used to remove the exposed sidewalls and the thin silicon nitride layer on the top of the core pattern.

[0029] As described above, the self-aligned double patterning method of the present invention has the following beneficial effects: the self-aligned double patterning method of the present invention defines amorphous silicon and silicon oxide hard masks with relatively low heights, defines a self-aligned double patterning hard mask with relatively low heights, and performs atomic deposition of a silicon nitride cutoff layer after the fin-type transistor process, and uses the morphology of silicon oxide and amorphous silicon to replace the structure of silicon oxide / silicon nitride / silicon oxide / amorphous silicon in the prior art, and uses atomic deposition technology to perform a cutoff layer of a silicon nitride deposition chemical mechanical polishing process after the fin-type transistor etching process, replacing the original silicon nitride deposition as a cutoff layer before the core etching process, and increases the fine filling process window between photoresists, effectively simplifying the self-aligned double production process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 13 Shown are schematic diagrams of various structures formed in the process flow of self-aligned double patterning in the prior art;

[0031] Figures 14 to 26 Shown are schematic diagrams of various structures formed in the process flow of self-aligned double patterning in the present invention;

[0032] Fig. 27 Shown is a flow chart of the self-aligned double patterning method of the present invention. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] See also Figures 14 to 27 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] like Fig. 27 As shown, Fig. 27 The flowchart of the self-aligned double patterning method of the present invention is shown. The present invention provides a self-aligned double patterning method, which at least includes the following steps:

[0036] Step 1: Provide a silicon substrate, on which a first oxide layer is disposed; on which an amorphous silicon layer is disposed; on which an organic layer is disposed; in step 1, the first oxide layer disposed on the silicon substrate is a silicon oxide layer, and the silicon oxide layer is formed by oxidizing the upper surface of the silicon substrate to form a silicon oxide layer. Fig.14 As shown, Fig.14 The structure schematic diagram of the present invention shows that a first oxide layer, an amorphous silicon layer, an organic layer and a photoresist pattern are provided on a silicon substrate. That is, the first oxide layer 02 is provided on the silicon substrate 01, an amorphous silicon layer 03 covering the upper surface of the first oxide layer 02 is provided on the first oxide layer 02, and the organic layer 04 is provided on the upper surface of the amorphous silicon layer 03. Further, in the present invention, the method for forming the amorphous silicon layer 03 on the first oxide layer 02 in step 1 of this embodiment is: depositing amorphous silicon on the first oxide layer 02 to form the amorphous silicon layer 03.

[0037] Step 2: using a mask plate to define the critical dimensions of polysilicon, then coating photoresist on the organic layer, and forming a photoresist pattern according to the critical dimensions of polysilicon; Fig.14 As shown, the present invention further comprises that the photoresist pattern 05 in step 2 of this embodiment is a plurality of strip structures spaced apart from each other.

[0038] Step 3: defining the height and critical dimensions of the amorphous silicon pattern, etching the organic layer and the amorphous silicon layer according to the photoresist pattern until the upper surface of the first oxide layer is exposed, and forming the amorphous silicon pattern with the defined height and critical dimensions; Fig.15 As shown, Fig.15 It is a schematic diagram of the structure of etching to form an amorphous silicon pattern. In step three, the organic layer 04 and the amorphous silicon layer 03 are etched according to the photoresist pattern 05 to form an amorphous silicon pattern 06 on the first oxide layer 02. The height and critical dimensions of the amorphous silicon pattern meet the height and critical dimensions defined in this step before etching. Further, in step three of the present embodiment, the organic layer on the amorphous silicon pattern 06 is completely removed, that is, after etching to form the amorphous silicon pattern 06, the organic layer 04 has been completely consumed, forming a Fig.15 The structure shown.

[0039] Step 4: Covering the top and sidewalls of the amorphous silicon pattern and the exposed upper surface of the first oxide layer with a first silicon nitride layer; Fig.16 As shown, Fig.16 It is a schematic diagram of the structure after the first silicon nitride layer is covered on the amorphous silicon pattern and the first oxide layer. Further, in the present invention, the method for forming the first silicon nitride layer 07 in step 4 of this embodiment is an atomic layer deposition method. That is, in this step, an atomic layer deposition method is used to simultaneously deposit a first silicon nitride layer 07 on the top and sidewalls of the amorphous silicon pattern 06 and the upper surface of the first oxide layer 02.

[0040] Step 5: etching and removing the first silicon nitride layer on the top of the amorphous silicon pattern to expose the top of the amorphous silicon pattern, and forming a first silicon nitride sidewall pattern on the sidewall of the amorphous silicon pattern; Fig.17 As shown, Fig.17 The schematic diagram of the structure after the first silicon nitride layer on the top of the amorphous silicon pattern is removed is shown. In this step, the first silicon nitride layer on the top of the amorphous silicon pattern 06 is removed by etching, and the first silicon nitride layer on the side wall of the amorphous silicon pattern 06 is retained. The first silicon nitride layer attached to the side wall of the amorphous silicon pattern 06 forms independent structures attached to the side wall of the amorphous silicon pattern, namely, the first silicon nitride side wall pattern 08.

[0041] Step 6: removing the amorphous silicon pattern between the first silicon nitride sidewall patterns; Fig.18 As stated, Fig.18The structure diagram of the present invention after removing the amorphous silicon pattern is shown. After removing the amorphous silicon pattern, the first silicon nitride sidewall pattern forms independent structures. In the subsequent process, further self-aligned double patterning is performed according to the first silicon nitride sidewall pattern 08.

[0042] Step 7: define the fin transistor morphology, etch the first oxide layer and the silicon substrate along the first silicon nitride sidewall pattern, and form a core pattern of the silicon substrate with the defined fin transistor morphology and a first oxide layer pattern located on the core pattern; Fig.19 As shown, the first oxide layer 02 and the silicon substrate 01 are etched downward along the first silicon nitride sidewall pattern 08 to form Fig.19 The core graphic 10 shown and the first oxide layer graphic 09 located on the core graphic 10, after the etching of step seven is completed, the height of the core graphic is determined by the morphology of the fin-type transistor, the first silicon nitride sidewall graphic 08 is completely consumed, while the first oxide layer is not completely consumed, and the remaining first oxide layer forms the first oxide layer graphic 09.

[0043] Step eight, removing the first oxide layer pattern; Fig. 20 As shown, after removing the first oxide layer pattern 09, only the core pattern 10 of the silicon substrate is retained.

[0044] Step nine, covering the core pattern with a thin silicon nitride layer; specifically, in step nine, the method for covering the core pattern with the thin silicon nitride layer is an atomic layer deposition method. Fig.21 As shown, Fig.21 The structure diagram is shown as a thin silicon nitride layer covering the core pattern. The ninth step adopts the atomic layer deposition method to deposit a thin silicon nitride layer 11 on the core pattern 10.

[0045] Step 10: depositing a second oxide layer covering the thin silicon nitride layer and filling the gaps between the core patterns; specifically, in this embodiment, the method for depositing the second oxide layer in step 10 is fluid chemical vapor deposition. Fig. 22 As shown, the deposited second oxide layer 12 not only covers the surface of the thin silicon nitride layer 11 , but also fills the gaps between the core patterns 10 with the second oxide layer 12 .

[0046] Step 11, grinding the second oxide layer until the thin silicon nitride layer on the top of the core pattern is exposed; further, in step 11, the method for grinding the second oxide layer is chemical mechanical polishing. In this step, the second oxide layer 12 above the thin silicon nitride layer 11 on the top of the core pattern is ground by chemical mechanical polishing until the thin silicon nitride layer 11 on the top of the core pattern 10 is exposed.

[0047] Step 12: define the height of the fin transistor, and perform back etching on the second oxide layer until the height of the exposed core pattern meets the defined height of the fin transistor; Fig.24 As shown, Fig.24 It is a schematic diagram of the structure after the second oxide layer is etched back.

[0048] Step 13, removing the exposed sidewalls and top thin silicon nitride layer of the core pattern; further, step 13, using phosphoric acid to remove the exposed sidewalls and top thin silicon nitride layer of the core pattern. Fig.25 As shown, Fig.25 The schematic diagram of the structure after the thin silicon nitride layer on the sidewall and top of the core pattern is removed is shown in the present invention. After the exposed sidewall and top of the core pattern are removed, a portion of the core pattern is left exposed.

[0049] Step 14: depositing a third oxide layer to cover the exposed top and sidewalls of the core pattern. Fig.26 As shown, Fig.26 The structure schematic diagram shows that a third oxide layer is formed on the top and sidewall of the exposed core pattern. After deposition, the third oxide layer 13 covers the top and sidewall of the exposed core pattern, but does not fill the gaps between the exposed core patterns.

[0050] In summary, the self-aligned double patterning method of the present invention defines amorphous silicon and silicon oxide hard masks with relatively low height, defines a self-aligned double patterning hard mask with relatively low height, and performs atomic deposition of silicon nitride cut-off layer after the fin transistor process, uses silicon oxide and amorphous silicon to replace the structure of silicon oxide / silicon nitride / silicon oxide / amorphous silicon in the prior art, uses atomic deposition technology to perform a cut-off layer of the chemical mechanical polishing process of silicon nitride deposition after the fin transistor etching process, replaces the original silicon nitride deposition as a cut-off layer before the core etching process, increases the fine filling process window between photoresists, and effectively simplifies the self-aligned double manufacturing process flow. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A self-aligned double patterning method, characterized in that: At least the following steps are included: Step 1, providing a silicon substrate, wherein a first oxide layer is disposed on the silicon substrate; an amorphous silicon layer is disposed on the first oxide layer; and an organic layer is disposed on the amorphous silicon layer; Step 2: using a mask plate to define the critical dimensions of polysilicon, then coating photoresist on the organic layer, and forming a photoresist pattern according to the critical dimensions of polysilicon; Step 3, defining the height and critical dimensions of the amorphous silicon pattern, etching the organic layer and the amorphous silicon layer according to the photoresist pattern, etching until the upper surface of the first oxide layer is exposed, and forming the amorphous silicon pattern with the defined height and critical dimensions; Step 4: Covering the top and sidewalls of the amorphous silicon pattern and the exposed upper surface of the first oxide layer with a first silicon nitride layer; Step 5: etching and removing the first silicon nitride layer on the top of the amorphous silicon pattern to expose the top of the amorphous silicon pattern, and forming a first silicon nitride sidewall pattern on the sidewall of the amorphous silicon pattern; Step six, removing the amorphous silicon pattern between the first silicon nitride sidewall patterns; Step 7: define the fin transistor morphology, etch the first oxide layer and the silicon substrate along the first silicon nitride sidewall pattern, and form a core pattern of the silicon substrate with the defined fin transistor morphology and a first oxide layer pattern located on the core pattern; Step eight, removing the first oxide layer pattern; Step nine, covering the core pattern with a thin silicon nitride layer; Step 10, depositing a second oxide layer covering the thin silicon nitride layer and filling the gaps between the core patterns; Step 11, grinding the second oxide layer until the thin silicon nitride layer on the top of the core pattern is exposed; Step 12, defining the height of the fin-type transistor, etching back the second oxide layer until the height of the exposed core pattern meets the defined height of the fin-type transistor; Step 13: removing the exposed sidewalls and top thin silicon nitride layer of the core pattern; Step 14: depositing a third oxide layer to cover the exposed top and sidewalls of the core pattern.

2. The self-aligned double patterning method according to claim 1, characterized in that: The first oxide layer provided on the silicon substrate in step 1 is a silicon oxide layer, and the silicon oxide layer is formed by oxidizing the upper surface of the silicon substrate to form a silicon oxide layer.

3. The self-aligned double patterning method according to claim 1, characterized in that: The method for forming the amorphous silicon layer on the first oxide layer in step 1 is: depositing amorphous silicon on the first oxide layer to form the amorphous silicon layer.

4. The self-aligned double patterning method according to claim 1, characterized in that: The photoresist pattern in step 2 is a plurality of strip structures spaced apart from each other.

5. The self-aligned double patterning method according to claim 1, characterized in that: The organic layer on the amorphous silicon pattern in step three is completely removed.

6. The self-aligned double patterning method according to claim 1, characterized in that: The method for forming the first silicon nitride layer in step 4 is atomic layer deposition.

7. The self-aligned double patterning method according to claim 1, characterized in that: In step nine, the method for covering the core pattern with the thin silicon nitride layer is an atomic layer deposition method.

8. The self-aligned double patterning method according to claim 1, characterized in that: The method for depositing the second oxide layer in step 10 is fluid chemical vapor deposition.

9. The self-aligned double patterning method according to claim 1, characterized in that: Step 11: The method of polishing the second oxide layer is chemical mechanical polishing.

10. The self-aligned double patterning method according to claim 1, characterized in that: Step thirteen: using phosphoric acid to remove the exposed sidewalls and top thin silicon nitride layer of the core pattern.

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