Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer having a second opening penetrating the first interlayer dielectric layer, the second opening fixing the formation position of the contact hole structure; forming an etching barrier layer on the sidewall, bottom surface and surface of the first interlayer dielectric layer of the second opening; forming a second interlayer dielectric layer on the etching barrier layer. The semiconductor structure and the method for forming the same in the present application can solve the problem of increased contact resistance or bridging caused by contact hole position offset in the prior art, and can also improve the process window, improve process accuracy, and significantly improve product yield.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the development of semiconductor technology, the requirements for the integration of integrated circuit chips are getting higher and higher, and the requirements for process accuracy are also increasing accordingly, especially the accuracy of interconnect structures is particularly important.

[0003] Currently, semiconductor technology has developed to nodes below 10nm, and the problem of contact hole "landing" has become increasingly critical. If the position of the contact hole formed by etching is offset, the contact resistance (Rc) will increase, resulting in poor device performance.

[0004] If the problem of contact hole offset is solved by increasing the size of the contact hole to improve the process window, it may also cause additional bridging problems, resulting in device failure. Summary of the invention

[0005] The technical problem solved by the technical solution of the present application is to provide a semiconductor structure and a method for forming the same, so as to solve the problems of increased resistance and bridging caused by the position deviation of the contact holes.

[0006] The method for forming a semiconductor structure of the present application includes: providing a substrate; forming a first interlayer dielectric layer on the substrate, wherein the first interlayer dielectric layer has a second opening that penetrates the first interlayer dielectric layer, and the second opening fixes the formation position of a contact hole structure; forming an etching stop layer on the side wall, the bottom surface and the surface of the first interlayer dielectric layer of the second opening; and forming a second interlayer dielectric layer on the etching stop layer.

[0007] In an embodiment of the present application, the substrate includes a front dielectric layer and a front metal layer extending through the front dielectric layer, wherein the top surface of the front metal layer and the top surface of the front dielectric layer are coplanar, wherein the bottom of the second opening is aligned with the top of the front metal layer.

[0008] In an embodiment of the present application, the width of the second opening decreases linearly from the top surface to the bottom surface.

[0009] In an embodiment of the present application, a top width of the second opening is 10 nm to 30 nm, a bottom width of the second opening is 2 nm to 20 nm, and a height of the second opening is 1 nm to 10 nm.

[0010] In an embodiment of the present application, the process of forming a first interlayer dielectric layer on the substrate includes: forming a conductive layer on the substrate, wherein the bottom of the conductive layer is aligned with the top of the previous metal layer; forming a first interlayer dielectric layer on the substrate, wherein the first interlayer dielectric layer fills the first opening between the conductive layers; and removing the conductive layer to form the first interlayer dielectric layer having the second opening.

[0011] In an embodiment of the present application, a conductive layer is formed on the substrate by a selective deposition method.

[0012] In an embodiment of the present application, a first interlayer dielectric layer is formed on the substrate by a selective deposition method.

[0013] In an embodiment of the present application, the method for forming the semiconductor substrate also includes: forming a mask layer on the surface of the second interlayer dielectric layer; removing part of the mask layer, part of the second interlayer dielectric layer and part of the etching barrier layer to form a groove, wherein the groove completely exposes the side wall and bottom surface of the second opening.

[0014] In an embodiment of the present application, the process of forming the groove includes: etching part of the mask layer and part of the second interlayer dielectric layer to expose the etch barrier layer at the sidewall and bottom of the second opening; etching the exposed etch barrier layer to form a groove.

[0015] In an embodiment of the present application, the groove also exposes a portion of the surface of the first interlayer dielectric layer, and the process of forming the groove includes: etching a portion of the mask layer and a portion of the second interlayer dielectric layer to expose the sidewalls and bottom etching barrier layer of the second opening, and a portion of the etching barrier layer on the surface of the first interlayer dielectric layer; etching the exposed etching barrier layer to form a groove, and the groove completely exposes the second opening and a portion of the surface of the first interlayer dielectric layer.

[0016] In an embodiment of the present application, the process of forming a groove includes: etching a portion of the mask layer to form a third opening, the third opening defining the position of the first part of the groove, forming a photoresist layer on the surface of the mask layer and in the third opening, and patterning the photoresist layer to define the position of the through hole; using the photoresist layer as a mask, etching a portion of the second interlayer dielectric layer to form a through hole, and removing the photoresist layer; continuing to etch the second interlayer dielectric layer so that a portion of the through hole expands laterally to form the first part of the groove, and the remaining through holes expand longitudinally to expose the etch barrier layer; etching the exposed etch barrier layer so that the remaining through holes and the second opening constitute the second part of the groove.

[0017] In an embodiment of the present application, the method for forming the semiconductor structure also includes: forming a diffusion barrier layer on the sidewalls and bottom of the first part of the trench and the second part of the trench, and on the surface of the mask layer; forming a seed layer on the surface of the diffusion barrier layer; depositing a second conductive material on the seed layer, and the top surface of the second conductive material is higher than the highest top surface of the seed layer; and planarizing the second conductive material until the top surface of the second conductive material is coplanar with the top surface of the second interlayer dielectric layer to form a second conductive layer.

[0018] In an embodiment of the present application, before forming the second conductive layer, the method further includes: forming a wetting layer on the surface of the seed layer.

[0019] The present application also provides a semiconductor structure, including: a substrate; a first interlayer dielectric layer, located on the substrate and having a second opening penetrating the first interlayer dielectric layer, the second opening constituting a part of a contact hole; an etch stop layer, located on a surface of a portion of the first interlayer dielectric layer and exposing the sidewalls and bottom surface of the second opening; and a second interlayer dielectric layer, located on the etch stop layer.

[0020] In an embodiment of the present application, the substrate includes a front dielectric layer and a front metal layer extending through the front dielectric layer, wherein the top surface of the front metal layer and the top surface of the front dielectric layer are coplanar, wherein the bottom of the second opening is aligned with the top of the front metal layer.

[0021] In an embodiment of the present application, the width of the second opening decreases linearly from the top surface to the bottom surface.

[0022] In an embodiment of the present application, a top width of the second opening is 10 nm to 30 nm, a bottom width of the second opening is 2 nm to 20 nm, and a height of the second opening is 1 nm to 10 nm.

[0023] In an embodiment of the present application, a groove is provided in the second interlayer dielectric layer, and the groove completely exposes the sidewall and bottom surface of the second opening.

[0024] In an embodiment of the present application, the groove further exposes a portion of the surface of the first interlayer dielectric layer.

[0025] In an embodiment of the present application, the groove includes: a first part of the groove and a second part of the groove, the second part of the groove is located at the bottom of the first part of the groove; wherein the second part of the groove is composed of a through hole and the second opening, the through hole connects the first part of the groove and the second opening, and the diameter of the through hole is larger than the top surface width of the second opening, but smaller than the width of the first part of the groove.

[0026] In an embodiment of the present application, the semiconductor structure also includes: a diffusion barrier layer, located on the side walls and bottom of the first part of the groove and the second part of the groove; a seed layer, located on the surface of the diffusion barrier layer; a second conductive layer, located on the seed layer, and the top surface of the second conductive layer is coplanar with the top surface of the second interlayer dielectric layer.

[0027] In an embodiment of the present application, the semiconductor structure further includes: a wetting layer, and the wetting layer is located on a surface of the seed layer.

[0028] Compared with the prior art, the technical solution of this application has at least the following beneficial effects:

[0029] The technical solution of the present application forms a first interlayer dielectric layer before forming an etching barrier layer on the substrate. The first interlayer dielectric layer has a second opening that penetrates the first interlayer dielectric layer. The second opening fixes the formation position of the contact hole structure and is completely aligned with the previous metal layer, effectively avoiding the problem of contact hole position deviation caused by low etching accuracy when etching to form the contact hole. At the same time, due to the limitation of the first interlayer dielectric layer, the formed contact hole will not connect to the adjacent conductive structure, preventing the occurrence of "bridging" phenomenon.

[0030] Before forming the first interlayer dielectric layer, a conductive layer is first deposited on the surface of the front metal layer by a selective deposition method. The selective deposition method can grow a conductive layer only on the surface of the front metal layer without the need for an additional etching step. Therefore, the problem of inaccurate deposition due to etching process errors will not occur, thereby improving the accuracy of the process.

[0031] When the first interlayer dielectric layer is deposited by a selective deposition process, it can be deposited only in the first opening between the conductive layers, and not on the surface of the conductive layer. Therefore, when removing the conductive layer, there is no need to add an additional step of removing the first interlayer dielectric layer on the surface of the conductive layer, thereby reducing the process steps.

[0032] Furthermore, the cross-sectional width of the conductive layer formed by the selective deposition method decreases linearly from the top surface to the bottom surface, so the cross-sectional width of the second opening also decreases linearly from the top surface to the bottom surface. This structure of being wide at the top and narrow at the bottom can increase the area of ​​the contact hole, thereby increasing the width of the metal connection and reducing Rc.

[0033] Part of the mask layer and part of the second interlayer dielectric layer are removed, and the formed trench includes a first portion of the trench and a second portion of the trench. The first portion of the trench and the second portion of the trench constitute a contact hole of a dual Damascene structure, further improving the process window.

[0034] In summary, the semiconductor structure and its formation method of the present application can solve the problem of increased contact resistance or bridging caused by contact hole position offset in the prior art, and at the same time can improve the process window, improve process accuracy, and significantly improve product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0036] Figures 1A to 1C It is a structural schematic diagram corresponding to each step of a method for forming a semiconductor structure;

[0037] Figure 2 A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present application;

[0038] Figures 3A to 3J 4A to 4D are structural schematic diagrams corresponding to the steps of the semiconductor structure forming method according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0040] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0041] Reference Figure 1A , a method for forming a semiconductor structure, comprising: providing a substrate. The substrate comprises a semiconductor base 100, in which a semiconductor device, a shallow trench isolation structure (not shown in the figure), etc. may be formed. The substrate further comprises a conductive layer 110 and a first dielectric layer 120, wherein the conductive layer 110 is located in the first dielectric layer 120, and the top surface of the conductive layer 110 is flush with the top surface of the first dielectric layer 120. An etching stop layer 130, a low dielectric constant or ultra-low dielectric constant material layer 140, and a mask material layer 150 are sequentially formed on the surfaces of the conductive layer 110 and the first dielectric layer 120.

[0042] Reference Figure 1B , forming a contact hole of a damascene structure consisting of a groove 160 and a through hole 170. As the size of the through hole 170 is further reduced, when etching to form the groove 160 and the through hole 170, the difficulty of accurately controlling the etching process increases, which may cause the position of the through hole 170 to shift, resulting in the formed through hole 170 not being able to fully align with the corresponding portion of the conductive layer 110, thereby reducing the effective contact hole area, increasing the contact resistance, and causing the device performance to deteriorate.

[0043] Please refer to Figure 1C If the problem caused by contact hole offset is reduced by increasing the size of the through hole 170 to improve the process window, it is very likely that a bridging problem will occur due to the contact hole being too large, resulting in device failure.

[0044] Based on this, an embodiment of the present application provides a semiconductor structure and a method for forming the same. Before forming an etching stop layer, a dielectric layer with an opening is formed. The opening of the dielectric layer fixes the formation position of the contact hole, thereby effectively avoiding the problem of contact hole position deviation caused by low etching accuracy when etching to form the contact hole. At the same time, due to the limitation of the dielectric layer, the formed contact hole will not connect to the adjacent conductive structure, thereby preventing the occurrence of "bridging" phenomenon.

[0045] Reference Figure 2 , a method for forming a semiconductor according to an embodiment of the present application comprises:

[0046] Step S1, providing a substrate;

[0047] Step S2, forming a first interlayer dielectric layer on the substrate, wherein the first interlayer dielectric layer has a second opening penetrating through the first interlayer dielectric layer, and the second opening fixes the formation position of the contact hole structure;

[0048] Step S3, forming an etching stop layer on the sidewalls and bottom surface of the second opening and the surface of the first interlayer dielectric layer;

[0049] Step S4, forming a second interlayer dielectric layer on the surface of the etching stop layer.

[0050] Reference Figure 2 and Figure 3A , providing a substrate 200. The substrate 200 may include a semiconductor base 210, in which a semiconductor device, a shallow trench isolation structure (not shown in the figure), etc. may be formed. The substrate 200 also includes a conductive structure formed on the semiconductor base 210, and the conductive structure is, for example, a metal layer. The embodiments of the present application are described by taking the metal layer as an example, hereinafter referred to as the front metal layer 220.

[0051] A front dielectric layer 230 may be formed on both sides of the front metal layer 220, and the top surface of the front metal layer 220 is coplanar with the top surface of the front dielectric layer 230. The material of the front metal layer 220 may include at least one of W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and TaSiN. The material of the front dielectric layer 230 may include at least one of silicon nitride, silicon oxide, silicon oxynitride and silicon oxycarbonitride.

[0052] Then, a first interlayer dielectric layer 240 is formed on the substrate 200, wherein the first interlayer dielectric layer 240 has a second opening 250 penetrating the first interlayer dielectric layer 240. Specifically, the following processes may be included:

[0053] Reference Figure 3B First, a conductive layer 260 is formed on the substrate 200. The conductive layer 260 is located on the top surface of the front metal layer 220. Furthermore, the bottom of the conductive layer 260 is completely aligned with the top surface of the front metal layer 220. Since the front metal layer 220 is separately located in the front dielectric layer 230, the conductive layer 260 is separately located on the substrate 200, and the conductive layer 260 has a first opening 270 that penetrates the conductive layer 260. The first opening 270 exposes the front dielectric layer 230, and the bottom of the first opening 270 is completely aligned with the top of the interlayer dielectric layer 230. The bottom of the conductive layer 260 is completely aligned with the front metal layer 220, and the first opening 270 between the conductive layers 260 is completely aligned with the front dielectric layer 230, ensuring that the first interlayer dielectric layer 240 formed in the subsequent first opening 270 can be completely aligned with the front dielectric layer 230. The second opening 250 formed between adjacent first interlayer dielectric layers 240 directly constitutes part of the structure of the contact hole and can accurately expose the front metal layer 220, solving the problem of contact hole position offset.

[0054] The method for forming the conductive layer 260 includes: selectively depositing the conductive layer 260 on the substrate 200. In some embodiments, the precursor for selective deposition may be a metal organic compound or a metal compound, for example, cyclopentadihydroxycobalt or tungsten hexafluoride, etc. The conductive layer 260 may include a metal material, for example, at least one of Co, W, CoW, Ru, Al, Cu, Ag or Au. Co is preferably used as the material for the conductive layer 260. On the one hand, cobalt has a good selective deposition effect; on the other hand, Co has good coverage performance. The temperature during selective deposition may be 200°C to 400°C, and the pressure may be 0.1Torr to 20Torr. Under the above process conditions, the conductive layer 260 may be deposited only on the surface of the front metal layer 220, and will not be deposited on the surface of the interlayer dielectric layer 230 on both sides of the front metal layer 220.

[0055] The embodiment of the present application adopts a selective deposition method, which can grow the conductive layer 260 only on the surface of the front metal layer 220 without adding an additional etching step. Therefore, the problem of inaccurate deposition due to etching process errors will not occur, thereby improving the accuracy of the process.

[0056] Furthermore, the cross-sectional width of the conductive layer 260 formed by the selective deposition method of the embodiment of the present application decreases linearly from the top surface to the bottom surface, for example, an inverted trapezoidal structure. Since the shape of the conductive layer 260 represents the partial structural shape of the contact hole formed subsequently, the structure with a wide top and a narrow bottom can increase the area of ​​the contact hole, thereby increasing the width of the metal connection and reducing Rc. In some embodiments, the top surface width of the conductive layer 260 can be 10nm to 30nm, the bottom surface width of the conductive layer 260 can be 2nm to 20nm, and the height of the conductive layer 260 can be 1nm to 10nm. In some embodiments, the angle between the side wall and the bottom surface of the conductive layer 260 can be an obtuse angle, for example, 135° to 165°, which is conducive to increasing the area of ​​the contact hole and reducing Rc.

[0057] Since the shapes of the conductive layer 260 and the first opening 270 are complementary, the cross-sectional width of the first opening 270 increases linearly from the top surface to the bottom surface, for example, a trapezoidal structure. That is, the top surface width of the first opening 270 may be 2nm to 20nm, the bottom surface width of the first opening 270 may be 10nm to 30nm, and the height of the first opening 270 may be 1nm to 10nm. The angle between the sidewall and the top surface of the first opening 270 may be an acute angle, for example, 25° to 55°.

[0058] Reference Figure 3C, a first interlayer dielectric layer 240 is formed on the surface of the substrate 200, and the first interlayer dielectric layer 240 fills the first opening 270. In some embodiments, the first interlayer dielectric layer 240 can be formed by a selective deposition process, the temperature of the selective deposition can be 200° C. to 400° C., the pressure can be 0.1 Torr to 20 Torr, and the precursor can include a metal organic compound containing Hf, Ti and Ta, such as PDMAT (penta(dimethylamino)tantalum). The material of the first interlayer dielectric layer 240 can include at least one of SiO2, SiN, HfO2, HfN, Al2O3, AlN, SiCN or SiOC.

[0059] The first interlayer dielectric layer 240 is selectively deposited on the surface of the front dielectric layer 230, which only fills the first opening 270, and does not form the first interlayer dielectric layer 240 on the surface of the conductive layer 260. Therefore, when removing the conductive layer 260, there is no need to add an additional step of removing the first interlayer dielectric layer 240 on the surface of the conductive layer 260, thereby reducing the process steps. Of course, in other embodiments, commonly used deposition methods may also be used, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0060] Reference Figure 3D , remove the conductive layer 260, and form a second opening 250 at a corresponding position. In some embodiments, the conductive layer 260 can be removed by dry etching or wet etching. For example, when the conductive layer 260 is a metal material, the etching method used needs to have a high selectivity to the previous metal layer 220. In some embodiments, a wet etching process is used to remove the conductive layer 260, and the etching solvent may include an aqueous solution of HF, HCl or H2SO4, the temperature is below 100°C, and the etching time may be 10 seconds to 1 minute. In some embodiments, a dry etching process is used to remove the conductive layer 260, and the etching gas used may include plasma gases such as CF4 and CCl4.

[0061] The position of the second opening 250 is the position of the partial contact hole formed subsequently. Since the position of the conductive layer 260 is completely aligned with the position of the front metal layer 220, the position of the second opening 250 is also completely aligned with the position of the front metal layer 220. When the contact hole is formed subsequently, the first interlayer dielectric layer 240 limits the etching position to the second opening 250, which can effectively solve the problem of contact hole position deviation.

[0062] Since the second opening 250 is naturally formed by removing the conductive layer 260, the shape of the second opening 250 is the same as that of the conductive layer 260 and is complementary to the first interlayer dielectric layer 240. The cross-sectional width of the second opening 250 decreases linearly from the top surface to the bottom surface, for example, an inverted trapezoidal structure. This structure of the second opening 250, which is wide at the top and narrow at the bottom, can increase the area of ​​the contact hole and reduce Rc.

[0063] In some embodiments, the top width of the second opening 250 may be 10 nm to 30 nm, the bottom width of the second opening 250 may be 2 nm to 20 nm, and the height of the second opening 250 may be 1 nm to 10 nm. In some embodiments, the angle between the sidewall and the bottom of the second opening 250 may be an obtuse angle, for example, 135° to 165°.

[0064] Since the conductive layer 260 is deposited by selective deposition, the structure of the conductive layer 260 is wide at the top and narrow at the bottom, similar to an inverted trapezoid, so the second opening 250 formed after removing the conductive layer 260 is also an inverted trapezoid. When the angle between the side wall and the bottom surface of the second opening 250 is an obtuse angle, compared with an acute angle or a right angle, the area of ​​the second opening 250 can be increased, and the area of ​​the contact hole formed is increased accordingly, thereby reducing the Rc of the contact hole. The angle between the side wall and the bottom surface of the second opening 250 is designed to be between 135° and 165°, which can reduce the Rc while meeting the requirements of the semiconductor structure size.

[0065] Reference Figure 3E , an etching stopper layer 280 is formed on the sidewalls and bottom surface of the second opening 250 and the surface of the first interlayer dielectric layer 240. The etching stopper layer 280 is a stop layer in the contact hole etching process, which can make the etching process of all contact holes consistent and improve the uniformity of the contact hole depth. In some embodiments, deposition can be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating or other applicable methods.

[0066] In order to achieve a higher etching selectivity ratio in subsequent etching, the material of the etching stop layer 280 is different from the material of the first interlayer dielectric layer 240, and the material of the etching stop layer 280 may include at least one of SiCN, SiOC, Al2O3, AlN and SiN. In some embodiments, the thickness of the etching stop layer may be designed according to the actual process, for example, 2nm to 20nm.

[0067] Continue to refer to Figure 3E, forming a second interlayer dielectric layer 290 on the surface of the etch stop layer 280, and forming a mask layer 300 on the surface of the second interlayer dielectric layer 290. The method of forming the second interlayer dielectric layer 290 and the mask layer 300 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating or other applicable methods. In some embodiments, the material of the second interlayer dielectric layer 290 may include a low dielectric constant (low K) material, and the dielectric constant of the low dielectric constant material may be, for example, between 2 and 3, for example, including at least one of SiOCH, SiOC, SiO2, SiN and SiON. In some embodiments, the thickness T of the second interlayer dielectric layer 290 may be 400 angstroms to 2000 angstroms, and the thickness T refers to the distance between the top surface of the second interlayer dielectric layer 290 and the etch stop layer 280 on the surface of the first interlayer dielectric layer 240.

[0068] In some embodiments, the material of the mask layer 300 may include at least one of SiO 2 , SiN, SiOC, SiON, TiN, AlN, and Al 2 O 3 . The thickness of the mask layer 300 may be 100 angstroms to 500 angstroms.

[0069] Then, a portion of the mask layer 300, a portion of the second interlayer dielectric layer 290, and a portion of the etch stop layer 280 are removed to form a groove, and the groove completely exposes the sidewall and bottom surface of the second opening 250. In order to increase the contact hole area, a portion of the etch stop layer 280 on the surface of the first interlayer dielectric layer 240 may also be exposed. In the embodiment of the present application, the groove completely exposes the sidewall and bottom surface of the second opening 250 and a portion of the etch stop layer 280 on the surface of the first interlayer dielectric layer 240.

[0070] Reference Figure 3F and Figure 3G , etching a portion of the mask layer 300 to form a third opening 440, the third opening 440 defining the position of the first portion 311 of the groove. When etching a portion of the mask layer 300, etching may be performed by anisotropic dry etching processes, the etching gas may include CF4 plasma gas, the radio frequency power may be 50W to 500W, and the temperature may be 20°C to 200°C. Then, a photoresist layer 450 is formed on the surface of the mask layer 300 and in the third opening 440, and the photoresist layer 450 is patterned to define the position of the through hole 313.

[0071] Reference Figure 3H, using the photoresist layer 450 as a mask, etching part of the second interlayer dielectric layer 290 to form a through hole 313, and removing the photoresist layer 450. When etching part of the second interlayer dielectric layer 290, anisotropic dry etching can be used, and the etching gas can include CF4, CCl4, C4F8 plasma, etc. When removing the photoresist layer 450, an ashing process can be used.

[0072] Reference Fig. 3I , using the mask layer 300 with the third opening 440 as a mask, the second dielectric layer 290 is continuously etched, so that the through hole 313 is longitudinally extended to expose the sidewall of the second opening 250, the etching barrier layer 280 at the bottom, and part of the etching barrier layer on the surface of the first interlayer dielectric layer 290, and part of the through hole 313 is transversely extended to form the first part 311 of the groove. In the process of continuing to longitudinally etch the through hole 313, a protective film will be formed on the sidewall, resulting in a smaller and smaller lateral etching rate, so the sidewall of the through hole 313 shown in the figure has a certain inclination.

[0073] refer to Figure 3J , the exposed etching stopper layer 280 is etched so that the through hole 313 and the second opening 250 constitute the second part 312 of the groove. In some embodiments, after etching the second interlayer dielectric layer 290, residual byproducts (not shown in the figure) will be formed on the surface of the etching stopper layer 280, so before removing the etching stopper layer 280, the residual byproducts must be removed first. The residual byproducts and the etching stopper layer 280 to be removed can be removed by a wet etching process, and the etching solvent can include at least one of a hydrofluoric acid aqueous solution, an ammonia solution, a sulfuric acid solution, and a hydrochloric acid solution. The etching temperature can be 20°C to 70°C, and the etching time can be controlled to be 1min to 5min.

[0074] The width and height of the first portion 311 of the groove and the second portion 312 of the groove are designed according to actual conditions and are not particularly limited herein.

[0075] The first portion 311 of the groove and the second portion 312 of the groove constitute a contact hole of a dual damascene structure. On the one hand, the process window can be greatly increased and the operation accuracy can be improved. On the other hand, the dual damascene structure can increase the area of ​​the contact hole and reduce Rc.

[0076] In summary, the method for forming a semiconductor structure provided by the embodiment of the present application forms a first interlayer dielectric layer with a second opening before forming an etching stop layer. The first interlayer dielectric layer limits part of the structure of the contact hole at the second opening and accurately exposes the front metal layer, thereby solving the problem of contact hole offset caused by low etching accuracy in the prior art and avoiding the occurrence of bridging. The contact hole structure of the dual Damascus structure formed by the first part of the groove and the second part of the groove can expand the process window, improve process accuracy, reduce Rc, and improve product yield.

[0077] After the above process is completed, the following process steps may also be included:

[0078] refer to Figure 4A A diffusion barrier layer 400 is formed on the sidewalls and bottom of the first portion 311 of the trench and the second portion 312 of the trench, and on the surface of the mask layer 300. In some embodiments, the material of the diffusion barrier layer 400 may include at least one of TaN, Ta and TiN, and the thickness of the diffusion barrier layer 400 may be 1 nm to 5 nm. The diffusion barrier layer 400 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating or other applicable methods.

[0079] refer to Figure 4B , forming a seed layer 410 on the surface of the diffusion barrier layer 400. In some embodiments, the material of the seed layer 410 may include at least one of Cu, CuMn and CuAl, and the thickness of the seed layer 410 may be 2nm to 10nm. The seed layer 410 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating or other applicable methods. The formation of the seed layer 410 is conducive to the subsequent electroplating (ECP) to form a conductive material. In other embodiments, a wetting layer (not shown in the figure) may also be formed on the surface of the seed layer 410, and the material of the wetting layer may include cobalt and / or ruthenium.

[0080] refer to Figure 4C , a second conductive material 420 is deposited on the seed layer 410, and the top surface of the second conductive material 420 is higher than the highest top surface of the seed layer; the second conductive material 420 may include at least one of Cu, CuMn and CuAl. For example, the second conductive material 420 may be deposited by electroplating (ECP), with copper as the second conductive material 420. The material used for the second conductive material 420 may be the same as that of the seed layer 410, so no distinction is made in the figure.

[0081] Afterwards, refer to Figure 4DThe second conductive material 420 may also be planarized, such as by chemical mechanical polishing (CMP), so that the top surface of the second conductive material 420 is coplanar with the top surface of the second interlayer dielectric layer 290 to form a second conductive layer 430. During the CMP process, the mask layer 300 on the surface of the second interlayer dielectric layer 290 is removed.

[0082] Continue to refer to Figure 3J Accordingly, an embodiment of the present application further provides a semiconductor structure, including: a substrate 200; a first interlayer dielectric layer 240, located on the substrate 200 and having a second opening 250 penetrating the first interlayer dielectric layer 240, wherein the second opening 250 constitutes a part of a contact hole; an etch stop layer 280, located on a surface of a portion of the first interlayer dielectric layer 240, and exposing the sidewalls and bottom surface of the second opening 250; and a second interlayer dielectric layer 290, located on the etch stop layer 280.

[0083] In some embodiments, the substrate 200 may include a semiconductor base 210, in which a semiconductor device, a shallow trench isolation structure (not shown in the figure), etc. may be formed. The substrate 200 may also include a front dielectric layer 230 located on the semiconductor base 210 and a front metal layer 220 penetrating the front dielectric layer 230, wherein the top surface of the front metal layer 220 is coplanar with the top surface of the front dielectric layer 230, wherein the bottom of the second opening 250 is aligned with the top of the front metal layer 220.

[0084] In some embodiments, the width of the second opening 250 decreases linearly from the top surface to the bottom surface.

[0085] In some embodiments, the top width of the second opening 250 is 10 nm to 30 nm, the bottom width of the second opening 250 is 2 nm to 20 nm, and the height of the second opening 250 is 1 nm to 10 nm.

[0086] In some embodiments, the angle between the side wall of the second opening and the bottom surface is an obtuse angle, for example, may be 135° to 165°.

[0087] Continue to refer to Figure 3GIn some embodiments, the second interlayer dielectric layer 290 has a groove therein, and the groove completely exposes the sidewall and bottom surface of the second opening 250. In some embodiments, the groove may also expose a portion of the surface of the first interlayer dielectric layer 240. The groove includes: a first portion 311 of the groove and a second portion 312 of the groove, wherein the second portion 312 of the groove is located at the bottom of the first portion 311 of the groove; wherein the second portion 312 of the groove is composed of a through hole 313 and the second opening 250, wherein the through hole 313 connects the first portion 311 of the groove with the second opening 250, and the diameter of the through hole 313 is greater than the top surface width of the second opening 250, but smaller than the width of the first portion 311 of the groove.

[0088] refer to Figure 4D The semiconductor structure further includes: a diffusion barrier layer 400, located on the sidewalls and bottom surfaces of the first portion 311 of the groove and the second portion 312 of the groove; a seed layer (not distinguished from the second conductive layer 430 in the figure), located on the surface of the diffusion barrier layer 400; and a second conductive layer 430, located on the seed layer 410, and the top surface of the second conductive layer 430 is coplanar with the top surface of the second interlayer dielectric layer 290.

[0089] In other embodiments, a wetting layer (not shown in the figure) may be further included, and the wetting layer is located on the surface of the seed layer 410 .

[0090] In the semiconductor structure provided by the embodiment of the present application, the contact hole structure formed by the first part 311 of the groove and the second part 312 of the groove is completely located on the front metal layer 220, and will not deviate from the front metal layer 220, thus solving the problem of increased contact resistance or bridging caused by the position offset of the contact hole in the prior art. The contact hole formed by the dual Damascus structure has a large contact hole area and a small Rc, and can improve the process window, improve the process accuracy, and greatly improve the product yield.

[0091] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0092] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may also be present.

[0093] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0094] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0095] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a front dielectric layer and a front metal layer penetrating the front dielectric layer, wherein a top surface of the front metal layer is coplanar with a top surface of the front dielectric layer; A first interlayer dielectric layer is formed on the substrate, wherein the first interlayer dielectric layer has a second opening penetrating through the first interlayer dielectric layer, and the second opening fixes the formation position of the contact hole structure. The process of forming the first interlayer dielectric layer on the substrate comprises: forming a conductive layer on the substrate, wherein the bottom of the conductive layer is aligned with the top of the front metal layer; forming the first interlayer dielectric layer on the substrate, wherein the first interlayer dielectric layer fills the first opening between the conductive layers; removing the conductive layer to form the first interlayer dielectric layer having the second opening; forming an etching stop layer on the sidewalls and bottom surface of the second opening and the surface of the first interlayer dielectric layer; A second interlayer dielectric layer is formed on the etch stop layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The width of the second opening decreases linearly from the top surface to the bottom surface.

3. The method for forming a semiconductor structure according to claim 2, wherein: The width of the top surface of the second opening is 10 nm to 30 nm, the width of the bottom surface of the second opening is 2 nm to 20 nm, and the height of the second opening is 1 nm to 10 nm.

4. The method for forming a semiconductor structure according to claim 1, wherein: A conductive layer is formed on the substrate by a selective deposition method.

5. The method for forming a semiconductor structure according to claim 1, wherein: A first interlayer dielectric layer is formed on the substrate by a selective deposition method.

6. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming a mask layer on a surface of the second interlayer dielectric layer; A portion of the mask layer, a portion of the second interlayer dielectric layer, and a portion of the etching stop layer are removed to form a trench, wherein the trench completely exposes the sidewall and the bottom surface of the second opening.

7. The method for forming a semiconductor structure according to claim 6, wherein: The process of forming the trench includes: Etching a portion of the mask layer and a portion of the second interlayer dielectric layer to expose the sidewalls and the bottom etching stop layer of the second opening; The exposed etch stop layer is etched to form a trench.

8. The method for forming a semiconductor structure according to claim 6, wherein: The groove also exposes a portion of the surface of the first interlayer dielectric layer. The process of forming the groove includes: Etching a portion of the mask layer and a portion of the second interlayer dielectric layer to expose the sidewalls and the etching stop layer at the bottom of the second opening, and a portion of the etching stop layer on the surface of the first interlayer dielectric layer; The exposed etch barrier layer is etched to form a groove, wherein the groove completely exposes the second opening and a portion of the surface of the first interlayer dielectric layer.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: The process of forming the trench includes: Etching a portion of the mask layer to form a third opening, wherein the third opening defines the position of the first portion of the trench, forming a photoresist layer on the surface of the mask layer and in the third opening, and patterning the photoresist layer to define the position of the through hole; Using the photoresist layer as a mask, etching a portion of the second interlayer dielectric layer to form a through hole, and removing the photoresist layer; Using the mask layer with the third opening as a mask, continue etching the second interlayer dielectric layer, so that the through hole is longitudinally extended to expose the sidewall of the second opening, the etching barrier layer at the bottom, and a portion of the etching barrier layer on the surface of the first interlayer dielectric layer, and a portion of the through hole is laterally extended to form a first portion of a trench; The exposed etch stop layer is etched so that the through hole and the second opening form a second portion of the trench.

10. The method for forming a semiconductor structure according to claim 9, characterized in that: Also includes: forming a diffusion barrier layer on the sidewalls and the bottom of the first portion of the trench and the second portion of the trench, and on the surface of the mask layer; forming a seed layer on the surface of the diffusion barrier layer; Depositing a second conductive material on the seed layer, wherein a top surface of the second conductive material is higher than a highest top surface of the seed layer; The second conductive material is planarized until a top surface of the second conductive material is coplanar with a top surface of the second interlayer dielectric layer to form a second conductive layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: Before forming the second conductive layer, the method further includes: forming a wetting layer on the surface of the seed layer.

12. A semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 11, characterized in that: include: Substrate: The substrate comprises a front dielectric layer and a front metal layer penetrating the front dielectric layer, wherein the top surface of the front metal layer is coplanar with the top surface of the front dielectric layer; A first interlayer dielectric layer is located on the substrate and has a second opening penetrating the first interlayer dielectric layer, the second opening constitutes a part of the contact hole, and the bottom of the second opening is aligned with the top of the front metal layer; an etching stop layer, located on a surface of a portion of the first interlayer dielectric layer and exposing a sidewall and a bottom surface of the second opening; The second interlayer dielectric layer is located on the etching stop layer.

13. The semiconductor structure according to claim 12, characterized in that: The width of the second opening decreases linearly from the top surface to the bottom surface.

14. The semiconductor structure according to claim 13, characterized in that: The width of the top surface of the second opening is 10 nm to 30 nm, the width of the bottom surface of the second opening is 2 nm to 20 nm, and the height of the second opening is 1 nm to 10 nm.

15. The semiconductor structure according to claim 12, characterized in that: The second interlayer dielectric layer has a groove therein, and the groove completely exposes the sidewall and bottom surface of the second opening.

16. The semiconductor structure according to claim 15, characterized in that The groove also exposes a portion of the surface of the first interlayer dielectric layer.

17. The semiconductor structure according to claim 16, characterized in that: The groove comprises: a first portion of the groove and a second portion of the groove, wherein the second portion of the groove is located at a bottom of the first portion of the groove; The second part of the groove is composed of a through hole and the second opening, the through hole connects the first part of the groove and the second opening, and the diameter of the through hole is larger than the top surface width of the second opening and smaller than the width of the first part of the groove.

18. The semiconductor structure according to claim 17, characterized in that: Also includes: a diffusion barrier layer disposed on the sidewalls and bottom surface of the first portion of the trench and the second portion of the trench; A seed layer, located on the surface of the diffusion barrier layer; The second conductive layer is located on the seed layer, and the top surface of the second conductive layer is coplanar with the top surface of the second interlayer dielectric layer.

19. The semiconductor structure according to claim 18, characterized in that Also includes: The wetting layer is located on the surface of the seed layer.

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