Integrating ramp circuit with reduced ramp settling time

Abstract

The present invention relates to an integrating ramp circuit with reduced ramp settling time. A ramp generator includes an integrator, the integrator including a first stage and a second stage, wherein the first stage has a first input terminal and a second input terminal, and a first output terminal and a second output terminal, and the second stage includes a first transistor and a second transistor coupled between a power rail and ground. A node between the first transistor and the second transistor is coupled to an output terminal of an integrator amplifier. A control terminal of the first transistor is coupled to a first output terminal of the first stage, and a control terminal of the second transistor is coupled to a second output terminal of the first stage. During a ramp event in a ramp signal generated from the output terminal, a first current flows from the output terminal to ground. A trimming circuit is coupled to the output terminal of the integrator amplifier to provide a second current to the output terminal of the integrator amplifier in response to a trimming input. The second current substantially matches the first current.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with application date of March 10, 2020, application number 202010161040.X, and invention name “Integrating ramp circuit with reduced ramp settling time”. Technical Field

[0003] The present invention relates generally to image sensors and, in particular but not limited to, to a comparator output circuit for analog-to-digital conversion in an image sensor. Background Art

[0004] Image sensors have become ubiquitous. They are widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. The technology used to manufacture image sensors has been developing at a high speed. For example, the demand for higher resolution and lower power consumption encourages further miniaturization and integration of these devices.

[0005] An image sensor typically receives light on an array of pixels, which generates an electric charge in the pixels. The intensity of the light can affect the amount of charge generated in each pixel, with higher intensities generating higher amounts of charge. An analog-to-digital converter (ADC) is often used in a CMOS image sensor (CIS) to convert the charge into a digital representation of the charge by the image sensor. The ADC generates a digital representation of the charge based on a comparison of the image charge signal with a reference voltage signal. The reference voltage signal can typically be a ramp signal provided by a ramp generator, and can typically be compared by a comparator, which provides an output that can be used with a counter to generate a digital representation of the image charge.

[0006] It can be understood that the ramp stabilization time or delay of the ramp signal generated by the ramp generator and received by the comparator can limit the maximum frame rate of the image sensor. Therefore, reducing the ramp stabilization time of the ramp signal can increase the maximum frame rate, thereby enhancing the performance of the image sensor. Summary of the invention

[0007] In some embodiments, a ramp generator includes an integrator amplifier having first and second inputs and an output for generating a ramp signal, wherein the integrator amplifier includes: a first stage having first and second inputs and first and second outputs, wherein the first and second inputs of the first stage are coupled to the first and second inputs of the integrator amplifier; a second stage including: a first transistor and a second transistor coupled between a power rail and ground, wherein a node between the first and second transistors is coupled to the output of the integrator amplifier, wherein a control terminal of the first transistor is coupled to the first output of the first stage, and wherein a control terminal of the second transistor is coupled to the second output of the first stage, wherein during a ramp event in the ramp signal generated from the output of the integrator amplifier, a first current flows from the output of the integrator amplifier through the integrator amplifier to ground; and a trimming circuit coupled between the power rail and the output of the integrator amplifier, wherein the trimming circuit is coupled to provide a second current to the output of the integrator amplifier in response to a trimming input, wherein the second current substantially matches the first current.

[0008] In some embodiments, an imaging system includes a pixel array for receiving image light and generating an image charge voltage signal in response; and a readout circuit coupled to receive the image charge voltage signal from the pixel array and provide a digital representation of the image charge voltage signal in response, the readout circuit including a comparator for receiving image charge, comparing the image charge voltage signal with a ramp signal from a ramp generator, and providing a digital representation of the image charge voltage signal in response, wherein the ramp generator includes: an integrator amplifier having a first input and a second input and an output for generating the ramp signal, wherein the integrator amplifier includes: a first stage having a first input and a second input and a first output and a second output, wherein the first input and the second input of the first stage are coupled to the integrator a first input terminal and a second input terminal of a divider amplifier; a second stage, comprising: a first transistor and a second transistor coupled between a power rail and ground, wherein a node between the first transistor and the second transistor is coupled to an output terminal of an integrator amplifier, wherein a control terminal of the first transistor is coupled to a first output terminal of the first stage, and wherein a control terminal of the second transistor is coupled to a second output terminal of the first stage, wherein during a ramp event in a ramp signal generated from the output terminal of the integrator amplifier, a first current flows from the output terminal of the integrator amplifier through the integrator amplifier to ground; and a trimming circuit coupled between the power rail and the output terminal of the integrator amplifier, wherein the trimming circuit is coupled to provide a second current to the output terminal of the integrator amplifier in response to a trimming input, wherein the second current substantially matches the first current.

[0009] In another embodiment, a ramp generator includes: an operational amplifier having a first input terminal and a second input terminal and an output terminal for generating a ramp signal; an integrator capacitor coupled between the first input terminal and the output terminal of the operational amplifier; a current source coupled to the first input terminal of the operational amplifier; a reference voltage capacitor coupled to the second input terminal of the operational amplifier; a sampling switch coupled between the reference voltage and the reference voltage capacitor, wherein the sampling switch is configured to sample the reference voltage onto the reference voltage capacitor; and a tuning circuit coupled to the second input terminal of the operational amplifier, wherein the tuning circuit is coupled to reduce the reference voltage sampled onto the reference voltage capacitor during a ramp event in the ramp signal to reduce a delay of a ramp event in the ramp signal.

[0010] In another embodiment, an imaging system includes: a pixel array for receiving image light and generating an image charge voltage signal in response; and a readout circuit coupled to receive the image charge voltage signal from the pixel array and provide a digital representation of the image charge voltage signal in response, the readout circuit including a comparator for receiving the image charge, comparing the image charge voltage signal with a ramp signal from a ramp generator, and providing a digital representation of the image charge voltage signal in response, wherein the ramp generator includes: an operational amplifier having a first input and a second input and an output that generates the ramp signal; an integrator capacitor coupled between the first input and the output of the operational amplifier; a current source coupled to the first input of the operational amplifier; a reference voltage capacitor coupled to the second input of the operational amplifier; a sampling switch coupled between the reference voltage and the reference voltage capacitor, wherein the sampling switch is configured to sample the reference voltage onto the reference voltage capacitor; and a tuning circuit coupled to the second input of the operational amplifier, wherein the tuning circuit is coupled to reduce the reference voltage sampled onto the reference voltage capacitor during a ramp event in the ramp signal to reduce a delay of the ramp event in the ramp signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0012] Figure 1 One example of an imaging system in accordance with the teachings of the present invention is shown.

[0013] Figure 2A A schematic diagram of an example of a ramp generator having a trim input for an output stage of the ramp generator for use with an analog-to-digital converter in an image sensor in accordance with the teachings of the present invention is shown.

[0014] Figure 2B It is shown that the teachings of the present invention are included in Figure 2A Schematic diagram of an example of an operational amplifier with output stage trimming circuitry in a ramp generator for use with an analog-to-digital converter in an image sensor is shown.

[0015] Figure 3A is a timing diagram showing some of the signals in a ramp generator without an output stage trimming circuit in accordance with the teachings of the present invention.

[0016] Figure 3B is a timing diagram showing some of the signals in a ramp generator with an output stage trimming circuit in accordance with the teachings of the present invention.

[0017] Figure 4A schematic diagram is shown of another example of a ramp generator having an adjustable input circuit for use with an analog-to-digital converter in an image sensor in accordance with the teachings of the present invention.

[0018] Figure 5A is a timing diagram illustrating some of the signals in a ramp generator without an adjustable input in accordance with the teachings of the present invention.

[0019] Figure 5B is a timing diagram illustrating some of the signals in a ramp generator with an adjustable input circuit in accordance with the teachings of the present invention.

[0020] In the several views of the accompanying drawings, corresponding reference numerals indicate corresponding parts. It will be appreciated by those skilled in the art that the elements in the accompanying drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the size of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the various embodiments of the present invention. Moreover, common but well-known elements that are useful or necessary in commercially feasible embodiments are generally not described to facilitate better viewing of these different embodiments of the present invention. DETAILED DESCRIPTION

[0021] Examples for a ramp generator are described herein that provide a ramp signal with a reduced ramp settling time. In the following description, various specific details are set forth to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein may be practiced without one or more of the specific details or using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0022] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present invention. Therefore, the phrases "in one example" or "in one embodiment" appearing throughout this specification do not necessarily all refer to the same example. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0023] Throughout the specification, several technical terms are used. Unless specifically defined herein or the context in which they are used clearly implies otherwise, their common meanings in the art to which these terms belong are adopted. It should be noted that element names and symbols can be used interchangeably herein (e.g., Si / silicon); however, both have the same meaning.

[0024] Figure 1An example of an imaging system 100 according to an embodiment of the present disclosure is shown. The imaging system 100 includes a pixel array 102, a control circuit 104, a readout circuit 108, and a function logic 106. In one example, the pixel array 102 is a two-dimensional (2D) array of photodiodes or image sensor pixels (e.g., pixels P1, P2...Pn). As shown, the photodiodes are arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to present a 2D image of the person, place, object, etc. However, the photodiodes do not have to be arranged in rows and columns, and other configurations can be used.

[0025] In one example, after each image sensor photodiode / pixel in pixel array 102 has acquired its image data or image charge, the image data is read out by readout circuitry 108 and then transferred to function logic 106. Readout circuitry 108 may be coupled to read out image data from a plurality of photodiodes in pixel array 102. In various examples, readout circuitry 108 may include amplification circuitry, analog-to-digital conversion (ADC) circuitry, or other circuitry. In some embodiments, one or more comparators 112 may be included for each readout column. For example, one or more comparators 112 may be included in a corresponding analog-to-digital converter (ADC) included in readout circuitry 108. In one example, the ADC may be a single slope ADC. Function logic 106 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, etc.). In one example, readout circuitry 108 may read out image data one row at a time along readout column lines (shown), or may use various other techniques (not shown) to read out image data, such as simultaneous serial readout or fully parallel readout of all pixels.

[0026] For example, to perform ADC, readout circuit 108 may receive reference voltage ramp signal VRAMP 130 from ramp generator circuit 110. VRAMP 130 may be received by comparator 112, which may also receive image charge signals from pixels of pixel array 102. Comparator 112 may use a counter to determine a digital representation of the image charge based on a comparison of VRAMP 130 with the image charge voltage level. In one example, when the input VRAMP 130 voltage reaches the input image charge voltage level, the output circuit of comparator 112 transitions from a first state to a second state. In the example, the value in the counter of the comparator coupled to the ADC may be used to generate a digital representation of the image charge. In accordance with the teachings of the present invention, in one example, a ramp settling time or delay of ramp signal VRAMP 130 generated by ramp generator 110 and received by comparator 112 is reduced to increase the maximum frame rate, thereby improving the performance of imaging system 100.

[0027] In one example, the control circuit 104 is coupled to the pixel array 102 to control the operation of the plurality of photodiodes in the pixel array 102. For example, the control circuit 104 can generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within the pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal to sequentially enable each row, column, or pixel group during consecutive acquisition windows. In another example, image acquisition is synchronized with a lighting effect such as a flash.

[0028] In one example, the imaging system 100 may be included in a digital camera, a cellular phone, a laptop computer, etc. In addition, the imaging system 200 may be coupled to other hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), a light / flash, an electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and / or a display. The other hardware may pass instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate image data provided by the imaging system 100.

[0029] Figure 2A A schematic diagram of an example of a ramp generator 210 having a trim input for an output stage of a ramp generator for use with an analog-to-digital converter in an image sensor in accordance with the teachings of the present invention is shown. Note that Figure 2A The ramp generator 210 may be Figure 1An example of a ramp generator 110 is provided, and similarly named and numbered elements referenced below are coupled and function similarly to those described above. As shown in the depicted example, the ramp generator 210 includes an operational amplifier (op amp) 214 configured as an integrator amplifier, wherein an integrating capacitor Cint 216 is coupled between the output and inverting input of the operational amplifier 214. A switch Intg_sw 218 is also coupled between the output and inverting input of the operational amplifier 214 to enable and disable the integrator. The inverting input of the operational amplifier 214 is coupled to receive a feedback input voltage vinteg 236, and is also coupled to a current source 220 that provides an integrator current i_integ. The non-inverting input of the operational amplifier 214 is coupled to receive a reference input voltage VREF_DAC_SMP 238. The reference voltage capacitor Cvref 222 is coupled to the non-inverting input of the operational amplifier 214 to sample the reference voltage VREF_DAC 226 to the reference voltage capacitor Cvref 222 through the sampling switch SAMP_SW 224. The output of the operational amplifier 214 is coupled to generate an output ramp signal VRAMP 230 across the load capacitor Cload 234.

[0030] In operation, the switch Intg_sw 218 is closed (e.g., turned on) to disable and reset the ramp generator 210 by resetting the voltage across Cint 216. The switch Intg_sw 218 is opened (e.g., turned off), which enables the integrator current i_integ to flow from the current source 220 into the capacitor Cint 216 to begin the ramping of the ramp signal VRAMP 230 at the output of the operational amplifier 210. At the beginning stage of the ramp in the ramp signal VRAMP 230, due to the presence of the capacitance Cload 234 representing the capacitance distributed in the column stage circuit of the imaging system, during the ramp event in the ramp signal VRAMP 230 output of the operational amplifier 214, the current Ipull 232 is brought into the operational amplifier 214 through the output stage or second stage of the operational amplifier 214 to ground. The presence of capacitance Cload and resulting current Ipull 232 may be a major cause of delay in the ramp of ramp signal VRAMP 230, which increases the ramp settling time of ramp signal VRAMP 230. In the depicted example, op amp 214 is also coupled to receive a trim input DACI_cut[3:0] 288, which is coupled to be received by a trim circuit in the output stage of op amp 214 to compensate for current Ipull 232 and improve the ramp settling time of VRAMP 230 in accordance with the teachings of the present invention.

[0031] Figure 2BIt is shown that the teachings of the present invention are included in Figure 2A Schematic diagram of an example of an operational amplifier with an output stage trimming circuit in a ramp generator shown, the ramp generator being used with an analog-to-digital converter in an image sensor. It should be noted that Figure 2B The operational amplifier 214 may be Figure 2A An example of an operational amplifier 214 with increased detail is shown, and similarly named and numbered elements referenced below are coupled and function similarly to those described above. As shown in the depicted example, the operational amplifier 214 includes an input stage or first stage 240, which includes an operational amplifier 240 having an inverting input terminal coupled to receive a feedback voltage vinteg 236 and a non-inverting input terminal coupled to receive a sampled reference input voltage VREF_DAC_SMP 238. The operational amplifier 240 has a first output terminal vp coupled to the gate of a PMOS transistor 242 and a second output terminal vn coupled to the gate of an NMOS transistor 244.

[0032] exist Figure 2B In the example shown, the output stage or second stage of the operational amplifier 214 includes transistors 242 and 244 coupled between a power rail and ground. The node between transistors 242 and 244 is the output node of the second stage and is configured to generate an output ramp signal VRAMP 230. As previously described, at the beginning of the ramp of the ramp signal VRAMP 230, the current Ipull 232 is brought into the operational amplifier 214 through the second stage of the operational amplifier 214 and grounded through the transistor 244.

[0033] In accordance with the teachings of the present invention, in order to compensate for the current Ipull 232, the operational amplifier 240 further includes a trimming circuit 246 in the second stage coupled to the output node of the second stage. As shown, the trimming circuit 246 includes a plurality of transistors 248-250 coupled between the power rail and the output terminal of the operational amplifier 214. It should be noted that although Figure 2B The illustrated example shows that the fine-tuning circuit 246 includes two transistors 248 and 250, but it should be understood that in other examples, the fine-tuning circuit 246 may include less than two or more than two transistors, each of which is coupled to be controlled in response to a corresponding one of the fine-tuning inputs DACI_cut[3:0] 228.

[0034] continue Figure 2BIn the example shown in , each of the plurality of transistors 248-250 includes a control terminal or gate terminal coupled to the control terminal or gate terminal of transistor 242 to receive the vp output of the first stage operational amplifier 240. In addition, each of the plurality of transistors 248-250 is also selectively coupled to the output node of the second stage of the operational amplifier 214 that generates VRAMP 230 in response to a respective one of the trim inputs DACI_cut[3:0] 228. In the depicted example, each of the plurality of transistors 248-250 is selectively coupled to the output node of the second stage of the operational amplifier 214 via a respective switch in response to the trim input DACI_cut[3:0] 228, as shown. In operation, each of the trim inputs DACI_cut[3:0] 228 individually controls an appropriate number of the plurality of transistors 248-250 of the trim circuit 246 at the start of a ramp event in VRAMP 230 to control a current Ipush 252 flowing through the trim circuit 246 to the output node generating VRAMP 230 and a compensation current Ipull 232 to reduce the delay in the ramp of VRAMP 230, thereby improving the ramp settling time of VRAMP 230, in accordance with the teachings of the present invention.

[0035] For illustration purposes, Figure 3A is an example showing an example according to the teaching of the present invention Figure 2A 2 is a timing diagram of some signals in a ramp generator without an output stage trimming circuit. As shown in the figure, the switch SAMP_SW 324 and the switch Intg_sw 318 are first closed to sample the VREF_DAC voltage 226 onto the reference voltage capacitor Cvref 222 and reset the voltage across the Cint 216 capacitor before the ramp starts. Then the sampling switch SAMP_SW 324 is turned off, and the reference input voltage VREF_DAC_SMP 238 has been sampled into the reference voltage capacitor Cvref 222. Then the switch Intg_sw 318 is turned off to start the ramp event in the output of VRAMP 330, as shown in the figure. However, at this time, due to the presence of the Cload 234 capacitor at the output of the ramp generator, the Ipull 332 current begins to flow into the output of the ramp generator to ground.

[0036] like Figure 3A As shown, the Ipull 332 current causes a delay in the ramp signal at the start of the ramp event. The "ideal line" (dashed line) of the ramp in VRAMP 330 can be characterized by a linear function:

[0037] Ideal line: Kt.

[0038] However, due to the influence of the load parasitic capacitance Cload and Ipull 332, the ramp signal is delayed, which can be represented by the following formula:

[0039] Delayed ramp signal:

[0040] The primary result of the delayed ramp signal caused by Ipull 332 is an increased ramp settling time, which increases the amount of time required to read image data from the image sensor, which reduces the possible maximum frame rate of the image sensor.

[0041] therefore, Figure 3B 318 is a timing diagram showing some of the signals in a ramp generator having an output stage trimming circuit for compensating for Ipull 332 in accordance with the teachings of the present invention. As shown, first, switch SAMP_SW 324 and switch Intg_sw 318 are closed to sample the VREF_DAC voltage 226 onto reference voltage capacitor Cvref 222 and reset the voltage across capacitor Cint 216 before the ramp begins. Then, sampling switch SAMP_SW 324 is closed, at which point the reference input voltage VREF_DAC_SMP 238 has been sampled onto reference voltage capacitor Cvref 222. Then, switch Intg_sw 318 is closed to begin initiating a ramp event in the output of VRAMP 330, as shown. For comparison purposes, Figure 3B The “original waveform” in FIG. 3 shows the slope in VRAMP 330 without compensating Ipull 332 .

[0042] However, Figure 3B It is also shown that the trim input DACI_cut[3:0] 328 also activates and controls the plurality of transistors 248-250 in the trim circuit 246 while turning off the switch Intg_sw 318 at the beginning of the ramp event in VRAMP 330. As will be shown, different DACI_cut[3:0] 328 bits may be trimmed to achieve a desired linear ramp (e.g., Figure 3A234). Specifically, at the beginning of a ramp event, in order to maintain the operating point, certain portions of the second stage of the operational amplifier 214 may be turned off in response to the trim input DACI_cut[3:0] 328. In this way, the current Ipush 252 flowing through the second stage of the operational amplifier 214 may substantially match Ipull 232. The value of Ipull may be determined by the slope and the Cload 234 value. Likewise, the feedback voltage vinteg 236 at the non-inverting input of the operational amplifier 214 may be stable, so that the slope in the VRAMP 230 signal may approach a linear "ideal line" slope. Therefore, in accordance with the teachings of the present invention, when switch Intg_sw 318 is turned off, the ramp “corrected waveform” in VRAMP 330 generated by the Ipush 252 current controlled in response to the fine-tuning input DACI_cut[3:0] 328 follows the linear characteristics of the “ideal line” of the ramp characterized by Kt in VRAMP 330 immediately after switch Intg_sw 318 is turned off.

[0043] For comparison, Figure 3B Also shown is "DACI_cut[3:0] too small" to demonstrate the slope in VRAMP 330 when not enough current flows through Ipush 252 current, and "DACI_cut[3:0] too large" to demonstrate the slope in VRAMP 330 when too much current flows through Ipush 252 current. Thus, according to the teachings of the present invention, the DACI_cut[3:0] signal may first be programmed to appropriately control the plurality of transistors 248-250 in the trimming circuit 246 to compensate for Ipull 332.

[0044] Figure 4 A schematic diagram of another example of a ramp generator 410 for use with an analog-to-digital converter in an image sensor in accordance with the teachings of the present invention is shown. Note that Figure 4 The ramp generator 410 may be Figure 2A The ramp generator 210 and / or Figure 1 The example of the ramp generator 110 is shown in FIG. 1 , and similarly named and numbered elements referenced below are coupled and function similarly to those described above. In addition, it should also be noted that Figure 4 The ramp generator 410 and Figure 2A The ramp generator 210 of FIG. 1 shares many similarities. However, Figure 4 The ramp generator 410 and Figure 2A One difference between the ramp generator 210 is that Figure 4 The exemplary ramp generator 410 of FIG. 4 does not receive a trim input DACI_cut[3:0] or a trim circuit in the output stage of the operational amplifier 414. Instead, according to the teachings of the present invention, Figure 4 The ramp generator 410 includes a tuning circuit 454 coupled to the non-inverting input of the operational amplifier 414 to tune the reference input voltage of the integrator amplifier to compensate for the current Ipull 432 .

[0045] As shown in the depicted example, the ramp generator 410 includes an operational amplifier 414 configured as an integrator amplifier having an integrator capacitor Cint 416 coupled between the output and inverting input of the operational amplifier 414. A switch Intg_sw 418 is also coupled between the output and inverting input of the operational amplifier 414 to enable and disable the integrator. The inverting input of the operational amplifier 414 is coupled to receive a feedback input voltage vinteg 436 and is also coupled to a current source 420 that provides a current i_integ. The non-inverting input of the operational amplifier 414 is coupled to receive a reference input voltage VREF_DAC_SMP 438. A reference voltage capacitor Cvref 422 is coupled to the non-inverting input of the operational amplifier 414 to sample a reference voltage VREF_DAC 426 onto the reference voltage capacitor Cvref 422 via a sampling switch SAMP_SW 424. As will be discussed, tuning circuit 454 tunes reference input voltage VREF_DAC_SMP 438 received at the non-inverting input of op amp 414 to compensate for Ipull 432 current in accordance with the teachings of the present invention. The output of op amp 414 is coupled to generate output ramp signal VRAMP 430 across load capacitor Cload 434.

[0046] As shown in the depicted example, the tuning circuit 454 includes a tuning capacitance implemented with a variable capacitance Cimp 462, wherein one end of the variable capacitance Cimp 462 is coupled to the non-inverting input of the operational amplifier 414. The other end of the variable capacitance Cimp 462 is coupled to a switching circuit including a switch 458 and a switch 460. In the depicted example, the switching circuit is configured to couple the variable capacitance Cimp 462 to the tuning voltage VREP_IMP 456 or to ground. Specifically, the switch 458 is configured to couple the variable capacitance Cimp 462 to the VREF_IMP 456 voltage in response to the signal IMP_SW, and the switch 460 is configured to couple the variable capacitance Cimp 462 to ground in response to the complementary signal IMP_SWB. In the depicted example, variable capacitance Cimp 462 is coupled to tuning voltage VREF_IMP 456 when the integrator amplifier is disabled, and is coupled to ground during ramp events in ramp signal VRAMP 430 when the integrator amplifier is enabled.

[0047] Figure 5Ais a diagram showing how the teachings of the present invention Figure 4 422 and reset the voltage across the Cint416 capacitor before the ramp begins. The sampling switch SAMP_SW 524 is then turned off, at which point the reference input voltage VREF_DAC_SMP 438 has been sampled into the reference voltage capacitor Cvref 422. The switch Intg_sw 518 is then turned off, and the ramp event in the output of VRAMP 530 as shown in the figure begins. However, at this point, due to the presence of the Cload 434 capacitor at the output of the ramp generator, the Ipull 532 current begins to flow into the output of the ramp generator to ground. The Ipull 332 current causes a delay in the ramp signal at the start of the ramp event. The "ideal line" of the ramp in VRAMP 330 is at Figure 5A The dashed line marked in has the following linear characteristics:

[0048] Kt.

[0049] However, due to the influence of Ipull 532, the ramp signal is delayed, and is characterized by:

[0050]

[0051] This increases the amount of time required to read image data from the image sensor and reduces the possible maximum frame rate of the image sensor.

[0052] therefore, Figure 5B 4 is a timing diagram showing some signals in a ramp generator with an adjustable input circuit according to the teachings of the present invention. As shown, the switch IMP_SWB 560 is first opened, which indicates that the switch IMP_SW 458 is first closed. In addition, the switch SAMP_SW 524 and the switch Intg_sw 518 are first closed. Therefore, the reference voltage capacitor Cvref 422 is first coupled to sample the reference voltage VREF_DAC 426 through the sampling switch SAMP_SW 424 to sample the voltage VREF_DAC_SMP 538 onto the reference voltage capacitor Cvref 422. In addition, one end of the variable capacitor Cimp 462 is first coupled to VREF_IMP 456, and the other end is coupled to VREF_DAC 426. Therefore, the voltage across the variable capacitor Cimp 462 is initialized to the difference between VREF_DAC 426 and VREF_IMP 456.

[0053] The sampling switch SAMP_SW 524 is then turned off, at which point the reference input voltage VREF_DAC_SMP 538 has been sampled into the reference voltage capacitor Cvref 422. The switch Intg_sw 518 is then turned off, and the switch 460 is turned on in response to IMP_SWB 560, which indicates that the switch 458 is turned off in response to IMP_SW 558. As shown in the example, the sampling switches SAMP_SW 524 and IMP_SWB 560 (and the complementary IMP_SW 458) are switched simultaneously. As shown, this begins to initiate a ramp event in the output of VRAMP 530. For comparison purposes, Figure 5B The “original waveform” in shows the slope in VRAMP 530 without compensating Ipull 432.

[0054] As shown, at the start of a ramp event in VRAMP 530, in response to IMP_SWB 560, variable capacitor Cimp 462 switches from being coupled to VREF_IMP 456 through switch 458 to being coupled to ground through switch 460. The other end of variable capacitor Cimp 462 is coupled to the non-inverting input of operational amplifier 414. As a result, reference input voltage VREF_DAC_SMP 538 is pulled down through variable capacitor Cimp 462, which is now coupled to ground through switch 460 at the start of a ramp event in VRAMP 530. In the depicted example, the values ​​of VREF_IMP 456 and variable capacitor Cimp 462 are flipped such that:

[0055]

[0056] In other words, if the values ​​of VREF_IMP, Cimp, and Cvref are chosen (e.g., by tuning Cimp) to substantially match –Kτ, the ramp event in ramp signal VRAMP 530 will be linear and nearly ideal. In other words, the product of tuning voltage VREF_IMP 456 and tuning capacitance Cimp 462 divided by the sum of tuning capacitance Cimp 462 and reference voltage capacitor Cvref 422 equals the constant –Kτ. For illustration purposes, Figure 5B The exemplary ramp event labeled “Corrected Waveform” in VRAMP 530 in FIG. 5 is due to VREF_IMP, Cimp, and Cvref being tuned such that:

[0057]

[0058] For comparison, Figure 5BAlso shown is “Cimp is too small” to show a slope in VRAMP 530 if the value selected for Cimp is too small, and “Cimp is too large” to show a slope in VRAMP 530 if the value selected for Cimp is too large.

[0059] The above description of exemplary embodiments of the present invention (including the content described in the Abstract) is not intended to be exhaustive or limit the present invention to the precise form disclosed. As will be appreciated by those skilled in the relevant art, although specific examples of the present invention are described herein for illustrative purposes, various modifications are possible within the scope of the present invention.

[0060] These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be interpreted as limiting the invention to the specific examples disclosed in the specification. Instead, the scope of the invention will be determined entirely by the appended claims, which will be interpreted in accordance with established principles of claim interpretation.

Claims

1. A method for reducing the delay of a ramp event in a ramp signal of a ramp generator, comprising: generating the ramp signal at an output of an operational amplifier having a first input and a second input, wherein the operational amplifier is included in the ramp generator; coupling an integrator capacitor between the first input and the output of the operational amplifier; coupling a current source to the first input terminal of the operational amplifier; capacitively coupling a reference voltage to the second input terminal of the operational amplifier; Sampling the reference voltage onto the reference voltage capacitor via a sampling switch coupled between the reference voltage and the reference voltage capacitor; as well as reducing the reference voltage sampled onto the reference voltage capacitor during the ramp event in the ramp signal by a tuning circuit coupled to the second input terminal of the operational amplifier to reduce the delay of the ramp event in the ramp signal, wherein the tuning circuit comprises: a tuning capacitor coupled to the second input of the operational amplifier; and a switching circuit coupled to the tuning capacitor, wherein the method further comprises: coupling the tuning capacitance to a tuning voltage through the switching circuit when the ramp generator is disabled; and The tuning capacitor is coupled to ground through the switching circuit when the ramp generator is enabled. 2 . The method of claim 1 , further comprising enabling and disabling the ramp generator via an enable switch coupled between the first input and the output of the operational amplifier.

3. The method according to claim 1, wherein the switching circuit comprises: a first switch coupled between the tuning voltage and the tuning capacitance; as well as A second switch is coupled between the tuning capacitor and ground. 4 . The method of claim 1 , wherein the tuning capacitor comprises a variable capacitor, wherein the method further comprises tuning the variable capacitor to make the ramp events in the ramp signal linear.

5. The method of claim 1, wherein the product of the tuning voltage and the tuning capacitance divided by the sum of the tuning capacitance and the reference voltage capacitance is equal to a constant.

6. A method for providing a ramp signal in an imaging system, comprising: receiving image light through a pixel array; generating an image charge voltage signal in response to receiving the image light; as well as receiving the image charge voltage signal via a readout circuit coupled to the pixel array; providing a digital representation of the image charge voltage signal in response to receiving the image charge voltage signal, wherein providing the digital representation comprises: comparing the image charge voltage signal with the ramp signal from the ramp generator by a comparator; providing the digital representation of the image charge voltage signal in response to comparing the image charge voltage signal to the ramp signal; generating the ramp signal at an output of an operational amplifier having a first input and a second input, wherein the operational amplifier is included in a ramp generator; coupling an integrator capacitor between the first input and the output of the operational amplifier; coupling a current source to the first input terminal of the operational amplifier; capacitively coupling a reference voltage to the second input terminal of the operational amplifier; Sampling the reference voltage onto the reference voltage capacitor via a sampling switch coupled between the reference voltage and the reference voltage capacitor; and reducing the reference voltage sampled onto the reference voltage capacitor during a ramp event in the ramp signal by a tuning circuit coupled to the second input terminal of the operational amplifier to reduce a delay of the ramp event in the ramp signal, wherein the tuning circuit comprises: a tuning capacitor coupled to the second input of the operational amplifier; and a switching circuit coupled to the tuning capacitor, wherein the method further comprises: coupling the tuning capacitance to a tuning voltage through the switching circuit when the ramp generator is disabled; and The tuning capacitance is coupled to ground when the ramp generator is enabled. 7 . The method of claim 6 , further comprising enabling and disabling an enable switch coupled between the first input and the output of the operational amplifier.

8. The method according to claim 6, wherein the switching circuit comprises: a first switch coupled between the tuning voltage and the tuning capacitance; as well as A second switch is coupled between the tuning capacitor and ground.

9. The method of claim 6, wherein the tuning capacitor comprises a variable capacitor, wherein the method further comprises tuning the variable capacitor to make the ramp events in the ramp signal linear.

10. The method of claim 6, wherein the product of the tuning voltage and the tuning capacitance divided by the sum of the tuning capacitance and the reference voltage capacitance is equal to a constant.

Images