Apparatus for controlling RRAM device using feedback circuit

Abstract

The disclosed embodiment discloses a device for controlling an RRAM device using a feedback circuit in a cross switch circuit. An exemplary device includes an RRAM cell for forming a channel, a MOSFET including a drain terminal, a source terminal, and a gate terminal, wherein the MOSFET is connected to the RRAM cell through the drain terminal; a TIA connected to the MOSFET through the source terminal; a first signal generator connected to the RRAM cell; a second signal generator connected to the MOSFET through the gate terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, wherein the comparator is connected to the TIA through the first input terminal, the second input terminal is connected to a reference voltage source, and the output terminal is connected to the first signal generator and the second signal generator. Thus, the process of forming a channel in the RRAM device is easier to control.

Description

Technical Field

[0001] The present disclosure relates to a feedback circuit, and more particularly to a device for controlling an RRAM device by using the feedback circuit in a crossbar switch circuit. Background Art

[0002] Conventional crossbar switch array circuits include horizontal metal line rows and vertical metal line columns (or other electrodes) that intersect each other and crossbar switch devices formed at their intersections. Crossbar switch arrays can be used for non-volatile solid-state memory, signal processing, control systems, high-speed image processing systems, neural network systems, and other applications.

[0003] Resistive random access memory (RRAM) cells are two-terminal passive devices that can change resistance in response to sufficient electrical stimulation and have attracted widespread attention in high-performance non-volatile memory applications. The resistance of RRAM can be electrically switched between two states: a high resistance state (HRS) and a low resistance state (LRS). The switching event from FIRS to LRS is usually called a "set" or "on" switch; the switching event from LRS to FIRS is usually called a "reset" or "off" switching process.

[0004] In order to enable the RRAM device to switch between these two resistance states, it can be achieved through a formation process. The formation process can form a channel or line in the RRAM device to provide switching characteristics. The formation process can be completed by applying a voltage or current to the RRAM device; the formation voltage or current is generally much higher than the read and write voltage.

[0005] However, the formation process is still technically challenging because it requires stronger control. If the formation voltage or current is too high, the RRAM device will turn into an over-conductive state, which will cause difficulties in the subsequent reset process. On the contrary, if the formation voltage or current is too low, the formation process may not be successful.

[0006] In addition, since the forming process is a self-accelerating process, over-forming may occur within a few nanoseconds, which poses a challenge to the traditional open-loop forming method. Summary of the invention

[0007] The embodiment of the present disclosure discloses a device for controlling an RRAM device by using a feedback circuit in a crossbar switch circuit.

[0008] In some embodiments, a device includes a RRAM cell for forming a channel; a MOSFET including a drain terminal, a source terminal, and a gate terminal, wherein the MOSEFT is connected to the RRAM cell through the drain terminal; a TIA connected to the MOSFET through the source terminal; a first signal generator connected to the RRAM cell; a second signal generator connected to the MOSEFT through the gate terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, wherein the comparator is connected to a Trans-Impedance Amplifier (TIA) through the first input terminal, the second input terminal is connected to a reference voltage source, and the output terminal is connected to the first signal generator and the second signal generator.

[0009] In some embodiments, the comparator is a voltage comparator. In some embodiments, the comparator is configured to turn off the first signal generator when the channel is formed.

[0010] In some embodiments, the first signal generator includes a DC ramp signal generator or a pulsed ramp signal generator.

[0011] In some embodiments, the second signal generator includes a DC ramp signal generator. In some embodiments, the second signal generator is configured to function as a current limiter.

[0012] In some embodiments, the combination of the TIA and the comparator has a propagation delay of less than 1 nanosecond. In some embodiments, the combination of the TIA and the comparator is configured to operate up to 40 gigahertz.

[0013] In some embodiments, the reference voltage source is configured to provide a reference voltage Vref, and the TIA is configured to output a TIA output voltage Vo; wherein when the channel is formed, Vo < Vref; when the channel is not formed, Vo > Vref.

[0014] In some embodiments, the RRAM cell further includes a bottom electrode, a channel formation layer prepared on the bottom electrode, and a top electrode prepared on the channel formation layer, wherein the channel formation layer is configured to form the channel.

[0015] In some embodiments, the RRAM cell further includes a bit line prepared on the bottom electrode and a word line prepared on the top electrode.

[0016] In some embodiments, the material of the bottom electrode or the top electrode is made of Pt, Ti, TiN, Pd, Ir, W, Ta, , Hf, Nb, V, TaN, NbN or a combination thereof, or an alloy of Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN and one or more other conductive materials.

[0017] In some embodiments, the material of the channel formation layer is made of one of TaOx (where x≤2.5), HfOx (where x≤2.0), TiOx (where x≤2.0), or a combination thereof.

[0018] In some embodiments, the channel comprises oxygen vacancy conductive filaments. In some embodiments, the channel is made of tantalum-rich, hafnium-rich, or titanium-rich oxides. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A is a block diagram of an exemplary crossbar switch array circuit in an embodiment of the present disclosure;

[0020] Figure 1B In the embodiment of the present disclosure Figure 1A a block diagram of a partially enlarged view of an exemplary crossbar circuit as shown;

[0021] Figure 2 is a block diagram of an RRAM cell in an embodiment of the present disclosure;

[0022] Figure 3 is a block diagram of a feedback circuit in an embodiment of the present disclosure;

[0023] Figure 4 is a timing diagram of different characteristics of an exemplary feedback circuit in an embodiment of the present disclosure;

[0024] The embodiments disclosed herein are illustrated by way of example and not by way of limitation in the accompanying drawings.Throughout the drawings, like reference numerals refer to corresponding parts. DETAILED DESCRIPTION

[0025] The embodiment of the present disclosure discloses a device for controlling an RRAM device using one or more feedback circuits in a crossbar switch circuit. The device provided by the embodiment of the present disclosure has the following beneficial effects:

[0026] First, the device disclosed in the embodiment of the present disclosure provides better control for RRAM channel formation. The formation process of the conventional RRAM channel provides insufficient control: the formation energy may be too strong or too weak, so that the channel cannot be formed well. The feedback circuit described in the present disclosure makes the formation voltage or current easier to control, and can automatically stop the formation process after the channel is formed. The technology disclosed in the present disclosure reduces or eliminates overload formation and can be fully automated.

[0027] Secondly, the technology described in this disclosure involves the use of transimpedance amplifiers and comparators, the combination of which can reduce latency to less than 1 nanosecond (or increase frequency to 40 GHz) while still maintaining low power consumption. The RRAM crossbar array circuit can also be trained faster and more accurately, thereby greatly enhancing the performance of the RRAM crossbar array circuit. The crossbar array circuit with improved performance is ideal for circuit implementation for real-time image recognition, neural computing, in-memory computing or other related applications.

[0028] Finally, the ramp signal generator using the disclosed technology can provide a scalable solution, thereby reducing the loss and area size of the RRAM crossbar switch circuit. The ramp signal generator can be shared by several word lines and select lines, and the TIA present at the output of each bit line can be used to provide additional functions, such as feedback functions.

[0029] Figure 1A FIG. 1 is a block diagram 1000 of an exemplary crossbar switch array circuit 100 in some embodiments of the present disclosure. Figure 1A As shown, the crossbar switch array circuit 100 includes a first word line 101 , a first bit line 102 and a crossbar circuit device 103 .

[0030] Figure 1B In some embodiments of the present disclosure Figure 1A FIG. 15 is a block diagram 1500 of a partially enlarged view of a crossbar circuit device 103. Figure 1B As shown, the crossover circuit device 103 is located at Figure 1A In the crossbar switch array circuit 100 shown, the first word line 101 and the first bit line 102 are located between the word lines 101 and 102 and are connected thereto.

[0031] In some embodiments, the crossbar device 103 includes a RRAM cell 1031. The RRAM cell 1031 can be a one-transistor-one-memory resistor (1T1R) stack, a one-selector-one-memory resistor (1S1R0), or one memory resistor.

[0032] Figure 2 is a block diagram 2000 of a RRAM cell 200 according to some embodiments of the present disclosure.

[0033] like Figure 2 As shown, the RRAM cell 200 includes a substrate 201, a bit line 203 prepared on the substrate 201, a bottom electrode 205 prepared on the bit line 203, a channel forming layer 207 prepared on the bottom electrode 205, a top electrode 209 prepared on the channel forming layer 207, and a word line 211 prepared on the top electrode 209.

[0034] In some embodiments, the substrate 301 is made of silicon (Si), silicon nitride (SiN), silicon dioxide (SiO2), aluminum oxide (Al2O3), or a combination thereof. In some embodiments, the bit line 201 is made of Ag, Al, Au, Cu, Fe, Ni, Mo, Pt, Pb, Ti, TiN, Sn, W, Zn, or a combination thereof, or an alloy of Ag, Al, Au, Cu, Fe, Ni, Mo, Pt, Pb, Ti, TiN, Sn, W, Zn, and one or more other conductive materials.

[0035] In some embodiments, the word line 211 is made of Ag, Al, Au, Cu, Fe, Ni, Mo, Pt, Pb, Ti, TiN, Sn, W, Zn or a combination thereof, or an alloy of Ag, Al, Au, Cu, Fe, Ni, Mo, Pt, Pb, Ti, TiN, Sn, W, Zn and one or more other conductive materials.

[0036] In some embodiments, the material of the bottom electrode 205 and / or the top electrode 209 includes Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN or a combination thereof, or an alloy with other conductive materials.

[0037] In some embodiments, the bottom electrode 205 is made of Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN, combinations thereof, or alloys of Pt, Ti, TiN, Pd, Ir, W, Ta, H, Nb, V, TaN, NbN, and one or more other conductive materials.

[0038] In some embodiments, the top electrode 209 is made of Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN, combinations thereof, or alloys of Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN and one or more other conductive materials.

[0039] In some embodiments, the channel forming layer is made of TaOx (where x≤2.5), HfOx (where x≤2.0), TiOx (where x≤2.0), or a combination thereof.

[0040] In some embodiments, the channel-forming layer 207 is configured to form a filament or channel 2071 within the channel-forming layer 207 in response to a forming voltage or current applied to the RRAM cell 2000 .

[0041] The channel or filament 2071 may include an oxygen vacancy conductive filament. In some embodiments, the channel or filament 2071 is made of tantalum-rich, hafnium-rich, or titanium-rich oxide material.

[0042] As described above, when the forming voltage or current is too high, the channel resistance may be kept too low. Conversely, if the forming voltage or current is too low, the forming may not be successful and the channel may not be formed correctly.

[0043] Furthermore, in an optimal formation process, the formation voltage or current should be stopped immediately (e.g., within a few nanoseconds or even picoseconds) after the channel is formed. Conventional formation processes are often not optimal: because the formation process is a self-accelerating process. For example, a high voltage or current will cause a stronger formation process, and the formation process will make the device more conductive; a more conductive device in turn will generate a larger current, thereby exacerbating the formation behavior.

[0044] Therefore, if the formation process is not stopped immediately after the channel is formed, overload formation may result. Therefore, a technique for stopping the formation process immediately after the channel formation is detected is advantageous.

[0045] Figure 3 is an exemplary block diagram 3000 of the feedback circuit 300 in some embodiments of the present disclosure.

[0046] like Figure 3 As shown, the feedback circuit 300 includes a RRAM cell 301, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) 305 connected to the RRAM cell 301, a transimpedance amplifier (TIA) 303 connected to the MOSFET 305, a comparator 311 connected to the TIA 303, a first signal generator 307 connected to the RRAM cell 301, and a second signal generator 309 connected to the MOSFET 305.

[0047] In some embodiments, the MOSFET 305 includes a first terminal 3051 connected to the second signal generator 309 , a second terminal 3053 connected to the RRAM cell 301 , and a third terminal 3055 connected to the TIA 303 .

[0048] In some embodiments, the first terminal 3051 is a gate terminal; the second terminal 3053 is a drain terminal; and the third terminal 3055 is a source terminal. The first terminal 3051 is connected to the second signal generator 309; the second terminal 3053 is connected to the RRAM cell 301; and the third terminal 3055 is connected to the TIA 303.

[0049] In some embodiments, the first signal generator 307 is used to provide a voltage Vset to the RRAM unit 301; in some embodiments, the second signal generator 309 is used to provide a voltage Vgate to the first end 3051 of the MOSFET 305; the first signal generator 306 may include a DC ramp signal generator or a pulse ramp signal generator.

[0050] The second signal generator 309 may include a ramp signal generator. The second signal generator and the MOSFET 305 may be implemented as a current limiter. This architecture may gradually increase the maximum current through the MOSFET 305 in saturation mode.

[0051] In some implementations, the TIA 303, the comparator 311, or both have a propagation delay of less than 1 nanosecond. In some implementations, the combination of the TIA 303 and the comparator 311 has a propagation delay of less than 1 nanosecond.

[0052] The comparator 311 includes a first input terminal 3114 , a second input terminal 3115 and an output terminal 3111 . The output terminal 3111 is connected to the first signal generator 307 and the second signal generator 309 .

[0053] In some embodiments, the comparator 311 includes a voltage comparator. A current comparator has a greater delay and higher power consumption than a voltage comparator. The comparator 311 is used to compare the TIA output voltage Vo of the TIA 303 with the voltage Vref of the reference voltage source. In some embodiments, the reference voltage Vref can be pre-set to 1 / 2 (high Vo+low Vo). If Vo is higher than Vref, the output terminal 3111 will be 1. If Vo is lower than Vref, the output terminal 3111 will be 0. This allows the comparator 311 to turn on and off the first signal generator 307 and the second signal generator 309 at the same time. The details of the signal processing can be referred to Figure 4 .

[0054] Figure 4 is a timing diagram 4000 of different characteristics of the feedback circuit 300 in some embodiments of the present disclosure.

[0055] like Figure 4 As shown, when the first signal generator 307 provides the boost signal Vset to the RRAM cell 301, energy (or heat) may gradually accumulate in the RRAM cell 301, resulting in the formation of a channel (or filament) inside the RRAM cell 301. Another boost signal Vgate provided by the second signal generator 309 may be used to limit current, which increases the maximum current flowing through the RRAM cell 301 and the MOSFET 305.

[0056] Vo may be the output voltage of the TIA 303. The current output from the MOSFET 305 may be converted to Vo. When the first signal generator 307 starts to boost and before the channel is formed, Vo remains high. Once the channel is formed, Vo decreases, causing Vcomp to increase. The comparator 311 then switches its digital output (e.g., from 0 to 1) by turning off the first signal generator 307 and the second signal generator 309. In some embodiments, when the first signal generator 307 is turned off, the boost voltage Vset decreases so that the channel formation process can be stopped as needed.

[0057] Using TIA and comparator in these ways can produce faster response, reducing latency to less than 1 nanosecond. A frequency of up to 40 GHz can be achieved with lower power consumption. Since the ramp signal generator can be shared by different word lines and select lines, the feedback circuit 300 can be used for fast array formation testing; existing TIA (located at each bit line output) can also be reused to provide feedback. These techniques make the feedback circuit more scalable and flexible.

[0058] Multiple instances may be provided for components, operations or structures described herein as single instances. Finally, the boundaries between individual components, operations and data stores are arbitrary to some extent, and specific operations are described in the context of specific illustrative configurations. Other allocations of functions are foreseeable and may fall within the scope of the subject matter of the present invention. In general, the structures and functions presented as separate components in the exemplary configuration may be implemented as combined structures or components. Similarly, the structures and functions presented as single components may be implemented as separate components. These and other variations, modifications, additions and improvements may fall within the scope of the subject matter of the present invention.

[0059] It should also be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first column can be called the second column, and similarly, the second column can be called the first column without changing the meaning of the description, as long as all occurrences of "first column" are renamed, and all occurrences of "second column" are renamed. The first column and the second column are both the s column, but they are not the same column.

[0060] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the claims. As used in the description of the embodiments and the appended claims, the singular forms "one", "an" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and covers any and all possible combinations of one or more associated listed items. It will also be understood that when the terms "include" and / or "comprising" are used in this specification, it specifies the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, such as integers, steps, operations, elements, components and / or groups thereof.

[0061] As used herein, the term "if" may be interpreted to mean "when" or "on" or "in response to determining" or "according to determining" or "in response to detecting", the conditional antecedent being true, depending on the context. Similarly, the phrase "if it is determined (the stated conditional antecedent is true)" or "if (the stated conditional antecedent is true)" or "when (the stated conditional antecedent is true)" may be interpreted to mean "upon". Depending on the context, "determining" or "in response to determining" or "according to determining" or "in response to detecting" or "in response to detecting" the conditional antecedent is true.

[0062] The foregoing description includes example systems, methods, techniques, instruction sequences, and computing machine program products that embody exemplary embodiments. For purposes of explanation, many specific details are set forth to provide an understanding of various implementations of the subject matter of the invention. However, it will be apparent to those skilled in the art that the embodiments of the subject matter of the invention may be practiced without these specific details. Typically, well-known instruction instances, protocols, structures, and techniques are not shown in detail.

[0063] For the purpose of illustration, the foregoing description has been described with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. In view of the above teachings, many modifications and variations are possible. The embodiments are selected and described in order to best explain the principles and their practical application, thereby enabling others skilled in the art to best utilize the embodiments and various embodiments with various modifications to suit the specific purpose intended.

Claims

1. An apparatus for controlling a resistive random access memory (RRAM) device using a feedback circuit, comprising: An RRAM cell for forming a channel; A metal oxide semiconductor field effect transistor (MOSFET) including a drain terminal, a source terminal, and a gate terminal, wherein the MOSFET is connected to the RRAM cell through the drain terminal; A transimpedance amplifier (TIA) connected to the MOSFET through the source terminal; A first signal generator connected to the RRAM cell; A second signal generator connected to the MOSFET through the gate terminal; A comparator including a first input terminal, a second input terminal, and an output terminal, wherein the comparator is connected to the TIA through the first input terminal, the second input terminal is connected to a reference voltage source, and the output terminal is connected to the first signal generator and the second signal generator.

2. The device according to claim 1, wherein: The comparator is a voltage comparator.

3. The apparatus according to claim 1, wherein the comparator is configured to turn off the first signal generator when the channel is formed.

4. The apparatus according to claim 1, wherein the first signal generator includes a DC ramp signal generator or a pulse ramp signal generator.

5. The apparatus according to claim 1, wherein the second signal generator includes a DC ramp signal generator.

6. The apparatus according to claim 1, wherein the second signal generator is configured to limit current.

7. The apparatus according to claim 1, wherein the combination of the TIA and the comparator has a propagation delay less than 1 nanosecond.

8. The apparatus according to claim 1, wherein the combination of the TIA and the comparator is configured to operate up to 40 GHz.

9. The apparatus according to claim 1, wherein the reference voltage source is configured to provide a reference voltage Vref, and the TIA is configured to output a TIA output voltage Vo; wherein when the channel is formed, Vo < Vref; when the channel is not formed, Vo > Vref.

10. The apparatus according to claim 1, wherein the RRAM cell includes a bottom electrode, a channel formation layer formed on the bottom electrode, and a top electrode formed on the channel formation layer, wherein the channel formation layer is configured to form the channel.

11. The apparatus according to claim 10, wherein the RRAM cell further includes a bit line formed under the bottom electrode and a word line formed on the top electrode.

12. The apparatus according to claim 10, wherein the material of the bottom electrode or the top electrode includes Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, TaN, NbN, or a combination thereof, or an alloy thereof with other conductive materials.

13. The apparatus according to claim 10, wherein the material of the channel formation layer includes TaOx (where x ≤ 2.5), HfOx (where x ≤ 2.0), TiOx (where x ≤ 2.0), or a combination thereof.

14. The apparatus according to claim 10, wherein the channel includes oxygen vacancy conductive filaments.

15. The device of claim 10, wherein a material of the channel comprises a tantalum-rich, hafnium-rich, or titanium-rich oxide material.

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