Analog-to-Digital Converter and Neuromorphic Computing Device Including the Same

Abstract

Provided is an analog-to-digital converter and a neuromorphic computing device including the analog-to-digital converter. The analog-to-digital converter is connected to a crossbar switch array including a plurality of resistive memory cells. Each of the plurality of resistive memory cells includes a resistive element. The analog-to-digital converter includes a voltage generator and a processing circuit. The voltage generator includes at least one resistive memory element having the same resistive material as the resistive elements included in the crossbar switch array. The voltage generator is configured to generate a first voltage based on a reference voltage and the at least one resistive memory element, and divide the first voltage to generate at least one divided voltage. The processing circuit is configured to: compare a signal voltage generated from the crossbar switch array with the at least one divided voltage to generate at least one comparison signal; and generate at least one digital signal corresponding to the signal voltage based on the at least one comparison signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0076349, filed on June 26, 2019, with the Korean Intellectual Property Office (KIPO), the content of which is incorporated herein by reference in its entirety. Technical field

[0003] Some example embodiments generally relate to semiconductor integrated circuits, and more particularly to analog - to - digital converters and neuromorphic computing devices including the analog - to - digital converter. Background art

[0004] Some applications related to deep - learning neural networks (NNs) or neuromorphic computing, such as image recognition, natural language processing, and more generally various pattern - matching or classification tasks, are rapidly becoming as important as general - purpose computing. The computational elements or neurons of an example NN multiply a set of input signals by a set of weights and sum the products. Thus, a neuron performs a vector - matrix multiplication or multiply - accumulate (MAC) operation. An NN can include a large number of interconnected neurons, each of which performs a MAC operation. Thus, the operations of an NN can be computationally intensive.

[0005] A neuromorphic computing device or neuromorphic chip is a semiconductor circuit fabricated by simulating, replicating, or mimicking information - processing methods using an artificial nervous system at the neuron level. A neuromorphic computing device can be used to implement an intelligent system that can adapt itself to a dynamic and / or uncertain environment. Summary of the invention

[0006] At least one example embodiment of the present disclosure includes an analog - to - digital converter capable of performing analog - to - digital conversion without temperature and time dependence.

[0007] At least one example embodiment of the present disclosure includes a neuromorphic computing device including an analog - to - digital converter.

[0008] According to some example embodiments, an analog-to-digital converter is connected to a crossbar array including a plurality of resistive memory cells. Each of the plurality of resistive memory cells includes a resistive element. The analog-to-digital converter includes a voltage generator and a processing circuit. The voltage generator includes at least one resistive memory element having a resistive material the same as that of the resistive elements included in the crossbar array; the voltage generator generates a first voltage based on a reference voltage and the at least one resistive memory element, and divides the first voltage to generate at least one divided voltage. The processing circuit may be configured to: compare a signal voltage from the crossbar array with the at least one divided voltage to generate at least one comparison signal; and generate at least one digital signal corresponding to the signal voltage based on the at least one comparison signal.

[0009] According to some example embodiments, a neuromorphic computing device includes a crossbar array and at least one analog-to-digital converter. The crossbar array includes a plurality of resistive memory cells that store at least one data and generate at least one signal voltage based on at least one input voltage and the at least one data. Each of the plurality of resistive memory cells includes a resistive element. The at least one analog-to-digital converter converts the at least one signal voltage into at least one digital signal. Each of the at least one analog-to-digital converters includes at least one resistive memory element having a resistive material the same as that of the resistive elements included in the crossbar array; each of the at least one analog-to-digital converters generates a first voltage based on a reference voltage and the at least one resistive memory element, divides the first voltage to generate at least one divided voltage, compares one of the at least one signal voltages with the at least one divided voltage to generate at least one comparison signal, and generates one of the at least one digital signals based on the at least one comparison signal.

[0010] According to some example embodiments, a neuromorphic computing device includes a crossbar array, a first switch matrix, a second switch matrix, a plurality of current-voltage converters, a plurality of analog-to-digital converters, a plurality of adders, and a plurality of shift registers. The crossbar array includes a plurality of resistive memory cells, and the crossbar array is configured to store a plurality of weights included in at least one layer of a neural network system and generate a plurality of read currents based on a plurality of input voltages and the plurality of weights. Each of the plurality of resistive memory cells includes a resistive element. The plurality of read currents represent the result of a multiply-accumulate operation performed by the neural network system. The first switch matrix is connected to rows of the crossbar array. The second switch matrix is connected to columns of the crossbar array. The plurality of current-voltage converters convert the plurality of read currents into a plurality of signal voltages. The plurality of analog-to-digital converters convert the plurality of signal voltages into a plurality of digital signals. The plurality of adders sum the plurality of digital signals. The plurality of shift registers generate final output data based on outputs of the plurality of adders. Each of the plurality of analog-to-digital converters includes a voltage generator and a processing circuit. The voltage generator includes at least one resistive memory element having a resistive material the same as that of the resistive elements included in the crossbar array; the voltage generator generates a first voltage based on a reference voltage and the at least one resistive memory element and divides the first voltage to generate at least one divided voltage. The reference voltage is a voltage independent of temperature and time. The processing circuit may be configured to compare one of the at least one signal voltages with the at least one divided voltage to generate at least one comparison signal and generate one of the at least one digital signals based on the at least one comparison signal.

[0011] In an analog-to-digital converter and a neuromorphic computing device according to some example embodiments, the analog-to-digital converter may include at least one resistive memory element having a resistive material the same as or similar to that of the resistive elements included in the crossbar array. Accordingly, a read current output from the crossbar array, a signal voltage corresponding to the read current, and a first voltage generated and used in the analog-to-digital converter may have the same or similar temperature and time dependencies, and when the output of the crossbar array is analog-to-digital converted, a digital signal that does not vary (or varies insignificantly) according to temperature and time may be generated. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Some illustrative, non-limiting example embodiments will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1is a block diagram showing a neuromorphic computing device according to some example embodiments.

[0014] Figure 2A and Figure 2B is a diagram for describing an example of a neural network system driven by a neuromorphic computing device according to some example embodiments.

[0015] Figure 3A 、 Figure 3B and Figure 3C is a diagram showing an example of a crossbar array included in a neuromorphic computing device according to some example embodiments.

[0016] Figure 4 is a block diagram showing an analog-to-digital converter according to some example embodiments.

[0017] Figure 5 is showing Figure 4 a circuit diagram of an example of an analog-to-digital converter.

[0018] Figure 6A 、 Figure 6B and Figure 6C is for describing Figure 5 an embodiment of a voltage generator included in the analog-to-digital converter.

[0019] Figure 7 、 Figure 8 、 Figure 9 and Figure 10 is showing Figure 5 other examples of a voltage generator included in the analog-to-digital converter.

[0020] Figure 11 is showing Figure 4 another example of an analog-to-digital converter.

[0021] Figure 12 is a block diagram showing a neuromorphic computing device according to some example embodiments.

[0022] Figure 13 is a block diagram showing an electronic system according to some example embodiments. Detailed Description

[0023] Various example embodiments will be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the some example embodiments set forth herein. Throughout the application, like reference numerals refer to like elements.

[0024] Figure 1 is a block diagram showing a neuromorphic computing device according to some example embodiments.

[0025] Reference Figure 1 , the neuromorphic computing device 100 includes a crossbar array 110 and an analog-to-digital conversion block 150. The neuromorphic computing device 100 may further include a first switch matrix 120, a second switch matrix 130, a current-voltage conversion block 140, an adder block 160, and a shift register block 170.

[0026] The crossbar array 110 includes a plurality of resistive memory cells RMC arranged in a matrix form. Each of the plurality of resistive memory cells RMC includes a resistive element RE. Each of the plurality of resistive memory cells RMC may be connected to a corresponding row among a plurality of rows RW1, RW2,..., RWN and a corresponding column among a plurality of columns CL1, CL2,..., CLM, where both N and M are natural numbers greater than or equal to 2. The detailed structure of the crossbar array 110 will be described with reference to Figure 3A and Figure 3C be described.

[0027] The crossbar array 110 stores a plurality of data. For example, a plurality of data may be stored in the plurality of resistive memory cells RMC by using the resistance change of the resistive element RE included in each of the plurality of resistive memory cells RMC. The crossbar array 110 generates a plurality of read currents Iread corresponding to a plurality of signal voltages Vsig based on a plurality of input voltages and a plurality of data.

[0028] For example, the plurality of input voltages may be input to the crossbar array 110 through the plurality of rows RW1, RW2,..., RWN.

[0029] In some example embodiments, as will be described with reference to Figure 2A and Figure 2BAs described, the neuromorphic computing device 100 can be used to drive at least one of various neural network systems and / or machine learning systems, such as, for example, an artificial neural network (ANN) system, a convolutional neural network (CNN) system, a deep neural network (DNN) system, a deep learning system, etc. Such machine learning systems can include various learning models, such as, for example, a convolutional neural network (CNN), a deconvolutional neural network, a recurrent neural network (RNN) optionally including long short-term memory (LSTM) units and / or gated recurrent units (GRU), a stacked neural network (SNN), a state space dynamic neural network (SSDNN), a deep belief network (DBN), a generative adversarial network (GAN), and / or a restricted Boltzmann machine (RBM). Alternatively or additionally, such machine learning systems can include other forms of machine learning models, such as, for example, linear regression and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems, and / or combinations thereof, examples of combinations including ensembles such as random forests. Such machine learning models can also be used to provide various services and / or applications that can be executed, run, or processed by the neuromorphic computing device 100, such as, for example, an image classification service, a user authentication service based on bioinformation or biometric data, an advanced driver assistance system (ADAS) service, a voice assistant service, an automatic speech recognition (ASR) service, etc.

[0030] In this example, the multiple data stored in the crossbar array 110 can represent the multiple weights included in at least one layer of the neural network system, and the multiple read currents Iread and the multiple signal voltages Vsig can represent the result of the multiply-accumulate operations performed by the neural network system. In other words, the crossbar array 110 can simultaneously perform a data storage operation and a data calculation (or operation) operation, which will be described with reference to Figure 3B this.

[0031] The first switch matrix 120 can be connected to the multiple rows RW1, RW2, ..., RWN of the crossbar array 110. Although not shown in detail, the first switch matrix 120 can drive the multiple rows RW1, RW2, ..., RWN based on a row selection signal for selecting at least one of the multiple rows RW1, RW2, ..., RWN and / or a row drive voltage for driving at least one of the multiple rows RW1, RW2, ..., RWN.

[0032] The second switch matrix 130 may be connected to multiple columns CL1, CL2, ..., CLM of the crossbar switch array 110. Although not shown in detail, the second switch matrix 130 may drive the multiple columns CL1, CL2, ..., CLM based on a column selection signal for selecting at least one of the multiple columns CL1, CL2, ..., CLM and / or a column drive voltage for driving at least one of the multiple columns CL1, CL2, ..., CLM.

[0033] The current-voltage conversion block 140 may include multiple current-voltage converters (IVC) 142. The multiple current-voltage converters 142 may convert multiple read currents Iread into multiple signal voltages Vsig. For example, each of the multiple current-voltage converters 142 may include a current mirror.

[0034] The analog-to-digital conversion block 150 includes multiple analog-to-digital converters (ADC) 152. The multiple analog-to-digital converters 152 convert the multiple signal voltages Vsig into multiple digital signals DS.

[0035] Each of the multiple analog-to-digital converters 152 includes at least one resistive memory element RME (the resistive material of the at least one resistive memory element RME is the same as or similar to the resistive material of the resistive element RE included in the crossbar switch array 110), generates a first voltage (e.g., Figure 4 the first voltage VFS in, such as a full scale voltage beyond the voltage range), divides the first voltage to generate at least one divided voltage (e.g., Figure 4 the multiple divided voltages VD in), compares one of the multiple signal voltages Vsig with the at least one divided voltage to generate at least one comparison signal (e.g., Figure 4 the multiple comparison signals CS in), and generates one of the multiple digital signals DS based on the at least one comparison signal. The detailed construction and operation of each of the multiple analog-to-digital converters 152 will be described with reference to Figures 4 to 11 The detailed construction and operation of each of the multiple analog-to-digital converters 152 will be described with reference to

[0036] The adder block 160 may include multiple adders (ADR) 162. The multiple adders 162 may sum the multiple digital signals DS to generate multiple summed digital signals ADS.

[0037] The shift register block 170 may include a plurality of shift registers (SR) 172. The plurality of shift registers 172 may generate final output data DAT based on the outputs of the plurality of adders 162 (e.g., based on the plurality of summed digital signals ADS). The final output data DAT may correspond to the final result of the multiply-accumulate operation performed by the neural network system.

[0038] In Figure 1 the example of, the number of the plurality of current-voltage converters 142, the number of the plurality of analog-to-digital converters 152, the number of the plurality of adders 162, and the number of the plurality of shift registers 172 may be substantially equal to the number of the plurality of columns CL1, CL2, ..., CLM of the crossbar array 110.

[0039] Although not shown in Figure 1 it, the neuromorphic computing device 100 may further include a timing controller or control circuit that generates control signals for controlling the operation timing of the first switch matrix 120, the second switch matrix 130, the current-voltage conversion block 140, the analog-to-digital conversion block 150, the adder block 160, the shift register block 170, etc., and / or may further include a voltage regulator that generates a row drive voltage, a column drive voltage, a reference voltage Vref, etc.

[0040] Typically, the plurality of resistive memory cells RMC included in the crossbar array 110 have temperature and time dependencies. For example, each resistive element RE included in each of the plurality of resistive memory cells RMC may have a temperature dependency, where the resistance decreases as the temperature increases and the resistance increases as the temperature decreases. Additionally, the resistive element RE may have a time dependency, including a retention characteristic where the resistance decreases over time, a drift characteristic where the resistance increases when a period of time (e.g., a predetermined, suitable, and / or advantageous period of time) elapses after a data write operation, etc. Thus, the read current Iread output from the crossbar array 110 may change according to temperature and time. To store accurate data and perform error-free calculations or operations, this temperature and time dependency must be reduced or eliminated.

[0041] A neuromorphic computing device 100 according to some example embodiments may include an analog-to-digital converter 152 that includes at least one resistive memory element RME, and the resistive material of the at least one resistive memory element RME is the same as or similar to the resistive material of the resistive elements RE included in the crossbar array 110. In the neuromorphic computing device 100 according to some example embodiments, the read current Iread output from the crossbar array 110, the signal voltage Vsig corresponding to the read current Iread, and the first voltage VFS used in the analog-to-digital converter 152 may have the same or similar temperature and time dependencies. Therefore, when the output of the crossbar array 110 is analog-to-digital converted, a digital signal DS that does not vary (or does not vary significantly) according to temperature and time can be generated without suppressing the temperature and time dependencies of the resistive elements RE included in the crossbar array 110.

[0042] For example, the analog-to-digital conversion and data calculation performed by some example embodiments can be effectively and / or errorlessly performed by reducing the inconsistency of the digital values generated in response to a fixed analog input (e.g., a fixed signal voltage) that may be caused by the time dependence and / or temperature dependence of other analog-to-digital conversion processes. In some example embodiments, the consistency achieved through such analog-to-digital conversion can enable a device incorporating such analog-to-digital conversion to reduce or omit other error detection and / or error correction mechanisms, e.g., additional circuitry or verification processes. In some example embodiments, the consistency achieved through such analog-to-digital conversion can enable a device incorporating such analog-to-digital conversion to reduce or omit redundant storage of data, e.g., checksum data and / or copies or backup copies of the stored data. In some example embodiments, the consistency achieved through such analog-to-digital conversion can enable a device incorporating such analog-to-digital conversion to complete read operations and / or write operations in a faster and / or more energy-efficient manner, e.g., by reducing or omitting subsequent verification. Generally, completing individual operations in a faster or more efficient manner can significantly improve the performance (e.g., speed or power efficiency) of artificial neural networks during operations such as inference, training, verification, and / or prediction in tasks such as classification and regression.

[0043] Figure 2A and Figure 2B is a diagram for describing an example of a neural network system driven by a neuromorphic computing device according to some example embodiments.

[0044] Referring to Figure 2A , a general neural network may include an input layer IL, multiple hidden layers HL1, HL2,..., HLn, and an output layer OL.

[0045] The input layer IL may include i input nodes x1, x2, ..., xi, where i is a natural number greater than 0. Input data of length i (e.g., vector input data) IDAT may be input to the input nodes x1, x2, ..., xi such that each element of the input data IDAT is input to a corresponding one of the input nodes x1, x2, ..., xi.

[0046] The multiple hidden layers HL1, HL2, ..., HLn may include n hidden layers, where n is a natural number greater than 0, and may include multiple hidden nodes h 1 1 、h 1 2 、h 1 3 、...、h 1 m 、h 2 1 、h 2 2 、h 2 3 、...、h 2 m 、h n 1 、h n 2 、h n 3 、...、h n m 。 For example, the hidden layer HL1 may include m hidden nodes h 1 1 、h 1 2 、h 1 3 、...、h 1 m , the hidden layer HL2 may include m hidden nodes h 2 1 、h 2 2 、h 2 3 、...、h 2 m , and the hidden layer HLn may include m hidden nodes h n 1 、h n 2 、h n 3 、...、h n m , where m is a natural number greater than 0.

[0047] The output layer OL may include j output nodes y1, y2, ..., yj, where j is a natural number greater than 0. Each output node y1, y2, ..., yj may correspond to a respective one of the categories to be classified. The output layer OL may be configured to produce an output value (e.g., a class score or a numerical output such as a regression variable) associated with the input data IDAT and / or output data ODAT for each category. In some example embodiments, the output layer OL may be a fully connected layer and may indicate, for example, the probability that the input data IDAT corresponds to a car.

[0048] Figure 2A The structure of the illustrated neural network may be represented by information on branches (or connections) illustrated as lines between nodes and weight values (not shown) assigned to each branch. In some neural network models, nodes within a layer may not be connected to each other, but nodes in different layers may be fully or partially connected to each other. In some other neural network models (e.g., restricted Boltzmann machines), at least some nodes within a layer may be connected to other nodes within the layer in addition to (or instead of) being connected to one or more nodes in other layers.

[0049] Each node (e.g., node h 1 1 ) may be configured to receive the outputs of previous nodes (e.g., nodes x1 to xi), may perform a computational operation, calculation, or computation on the received outputs, and may output the result of the computational operation, calculation, or computation as an input to the nodes of the next layer (e.g., nodes h 2 1 to h 2 m ), however, this is merely exemplary and the present invention is not limited thereto. Each node may be configured to calculate the value to be output by applying the input to a specific function (e.g., a non-linear function).

[0050] In some example embodiments, the structure of the neural network is preset, and data having known answers (sometimes referred to as "labels") as to which class the data belongs to is used to appropriately set the weight values for the connections between nodes. Data having known answers is sometimes referred to as "training data", and the process of determining the weight values is sometimes referred to as "training". The neural network "learns" to associate the data with the corresponding labels during the training process. A set of structures and weight values that can be independently trained is sometimes referred to as a "model", and the process of predicting the class to which the input data belongs by the model with the determined weight values and then outputting the predicted value is sometimes referred to as the "testing" process.

[0051] Refer to Figure 2B , which is shown in detail by Figure 2AAn example of the operation performed by a node ND included in a neural network.

[0052] Based on N inputs a 1 、a 2 、a 3 、...、a N provided to the node ND, the node ND can be configured to multiply the N inputs a 1 、a 2 、a 3 、...、a N with the corresponding N weights w 1 、w 2 、w 3 、...、w N respectively, sum the N values obtained by the multiplication, add the offset "b" to the sum value, and / or generate an output value (e.g., "z") by applying the value with the offset "b" to a specific function "σ".

[0053] In some example embodiments, as Figure 2B shown, Figure 2A a layer included in the neural network shown in

[0054] [Equation 1]

[0055] W*A = Z

[0056] In Equation 1, "W" represents the weights of all connections included in a layer and can be implemented in the form of an M×N matrix. "A" represents the N inputs a 1 、a 2 、a 3 、...、a N received by a layer and can be implemented in the form of an N×1 matrix. "Z" represents the M outputs z 1 、z 2 、z 3 、...、z M output from a layer and can be implemented in the form of an M×1 matrix.

[0057] Figure 3A 、 Figure 3B and Figure 3C are diagrams showing examples of a crossbar array included in a neuromorphic computing device according to some example embodiments.

[0058] Referring to Figure 3A , the crossbar array 110a includes multiple word lines WL1, WL2,..., WLN, multiple bit lines BL1, BL2,..., BLM, and multiple resistive memory cells RMC.

[0059] Figure 3A Multiple word lines WL1, WL2, ..., WLN in can correspond to Figure 1 Multiple rows RW1, RW2, ..., RWN in, Figure 3A Multiple bit lines BL1, BL2, ..., BLM in can correspond to Figure 1 Multiple columns CL1, CL2, ..., CLM in, and Figure 3A Multiple resistive memory cells RMC in can correspond to Figure 1 Multiple resistive memory cells RMC in. Each resistive memory cell in the multiple resistive memory cells RMC may include a resistive element RE and may be connected to a corresponding one of the multiple word lines WL1, WL2, ..., WLN and a corresponding one of the multiple bit lines BL1, BL2, ..., BLM.

[0060] The resistance of the resistive element RE can be changed based on a write voltage applied through the multiple word lines WL1, WL2, ..., WLN or the multiple bit lines BL1, BL2, ..., BLM, and the multiple resistive memory cells RMC can be configured to store multiple data through the change in the resistance of the resistive element RE. For example, based on a write voltage applied to a selected word line and a ground voltage (e.g., about 0V) applied to a selected bit line, the device can be configured to write the data "1" into the selected resistive memory cell. Based on a ground voltage applied to a selected word line and a write voltage applied to a selected bit line, the device can be configured to write the data "0" into the selected resistive memory cell. In addition, based on a read voltage applied to a selected word line and a ground voltage applied to a selected bit line, the device can be configured to read or retrieve the data written into the selected resistive memory cell.

[0061] In some example embodiments, each resistive memory cell in the multiple resistive memory cells RMC may include one of various resistive memory cells such as a phase change random access memory (PRAM) cell, a resistive random access memory (RRAM) cell, a magnetic random access memory (MRAM) cell, a ferroelectric random access memory (FRAM) cell, etc.

[0062] In some example embodiments, the resistive element RE may include a phase change material that changes its crystalline state according to the amount of electric current. The phase change material may include various materials, for example, GaSb, InSb, InSe, Sb2Te3, and GeTe formed by combining two elements, GeSbTe, GaSeTe, InSbTe, SnSb2Te4, and InSbGe formed by combining three elements, and AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and Te81Ge15Sb2S2 formed by combining four elements. In some other example embodiments, as an alternative to the phase change material, the resistive element RE may include a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material. However, the materials included in the resistive element RE are not limited thereto.

[0063] Referring to Figure 3B , an example embodiment is shown in which the crossbar switch array 110a performs the operations described with reference to Figure 3A and Figure 2A and Figure 2B .

[0064] Each resistive memory cell RMC may correspond to a synapse or connection in a neural network system and may store a weight. Therefore, the M×N data stored in the crossbar switch array 110a may correspond to a weight matrix including the weights included in one layer described with reference to Figure 2A and Figure 2B . In other words, the M×N data may correspond to the "W" implemented in the form of an M×N matrix in Equation 1.

[0065] The N input voltages V1, V2,..., VN applied through the multiple word lines WL1, WL2,..., WLN may correspond to an input matrix including the N inputs a Figure 2A and Figure 2B received by one layer described with reference to 1 , a 2 , a 3 ,..., a N . In other words, the N input voltages V1, V2,..., VN may correspond to the "A" implemented in the form of an N×1 matrix in Equation 1.

[0066] The M read currents I1, I2,..., IM output through the multiple bit lines BL1, BL2,..., BLM may correspond to an output matrix including the M outputs z Figure 2A and Figure 2B output from one layer described with reference to 1 , z 2 , z 3 ,..., z MThe output matrix. In other words, the M read currents I1, I2, ..., IM can correspond to the "Z" implemented in the form of an M×1 matrix in Equation 1.

[0067] Based on the crossbar array 110a implemented by storing multiple weights in matrix form in multiple resistive memory cells RMC, and based on the input voltages V1, V2, ..., VN corresponding to multiple inputs provided through multiple word lines WL1, WL2, ..., WLN, the device can be configured to generate read currents I1, I2, ..., IM output through multiple bit lines BL1, BL2, ..., BLM corresponding to the result of the product-sum operation performed by the neural network system. By implementing at least one layer in the neural network system in this way, the neuromorphic computing device can be configured to perform data storage and computing (or operation) operations simultaneously.

[0068] Referring to Figure 3C , the crossbar array 110b includes: multiple word lines WL1, WL2, ..., WLN, multiple bit lines BL1, BL2, ..., BLN, multiple source lines SL1, SL2, ..., SLM, and multiple resistive memory cells RMC'. Descriptions that are repeated with Figure 3A will be omitted.

[0069] Figure 3C The multiple word lines WL1, WL2, ..., WLN and multiple bit lines BL1, BL2, ..., BLN in Figure 1 can correspond to the multiple rows RW1, RW2, ..., RWN in Figure 3C The multiple source lines SL1, SL2, ..., SLM in Figure 1 can correspond to the multiple columns CL1, CL2, ..., CLM in Figure 3C and the multiple resistive memory cells RMC' in Figure 1 can correspond to the multiple resistive memory cells RMC in

[0070] Each of the multiple resistive memory cells RMC' may include a cell transistor CT and a resistive element RE, and may be connected to a corresponding one of a plurality of word lines WL1, WL2, ..., WLN, a corresponding one of a plurality of bit lines BL1, BL2, ..., BLN, and a corresponding one of a plurality of source lines SL1, SL2, ..., SLM. For example, the cell transistor CT may include a first electrode (e.g., drain, source, collector, or emitter) connected to one of the plurality of source lines SL1, SL2, ..., SLM, a third electrode (e.g., gate electrode or base electrode) connected to one of the plurality of word lines WL1, WL2, ..., WLN, and a second electrode (e.g., source, drain, collector, or emitter which may be the opposite end of the first electrode). The resistive element RE may be connected between the second electrode of the cell transistor CT and one of the plurality of bit lines BL1, BL2, ..., BLN.

[0071] For example, based on the supply voltage (e.g., VCC) applied to the selected word line, the write voltage applied to the selected bit line, and the ground voltage applied to the selected source line, the device may be configured to write data "1" into the selected resistive memory cell. Based on the supply voltage applied to the selected word line, the ground voltage applied to the selected bit line, and the write voltage applied to the selected source line, the device may be configured to write data "0" into the selected resistive memory cell. Further, based on the supply voltage applied to the selected word line, the read voltage applied to the selected bit line, and the ground voltage applied to the selected source line, the device may be configured to read or retrieve the data written in the selected resistive memory cell.

[0072] Although crossbar switch arrays 110a and 110b having a two-dimensional (2D) array structure are shown in Figure 3A , Figure 3B and Figure 3C , some example embodiments are not limited thereto, and the crossbar switch array may be included in a three-dimensional (3D) or vertical array structure. Additionally, according to some example embodiments, the construction of the resistive memory cells RMC and RMC' may be varied.

[0073] Figure 4 is a block diagram showing an analog-to-digital converter according to some example embodiments.

[0074] Referring to Figure 4 , the analog-to-digital converter 200 includes a voltage generator 210 and a processing circuit. In the example embodiment shown in Figure 4 , the processing circuit is shown as a comparison unit 220 and an encoding unit 230, but in some other example embodiments, the processing circuit may be organized in a different manner. The analog-to-digital converter 200 is Figure 1The analog-to-digital converter 152 included in the neuromorphic computing device 100 and is connected to the crossbar array 110 including a plurality of resistive memory cells RMC, and each resistive memory cell includes a resistive element RE.

[0075] The voltage generator 210 includes at least one resistive memory element RME (the resistive material of the at least one resistive memory element RME is the same as or similar to the resistive material of the resistive element RE included in the crossbar array 110), generates a first voltage VFS based on the reference voltage Vref and the at least one resistive memory element RME, and divides the first voltage VFS to generate at least one divided voltage VD. The reference voltage Vref can be a voltage independent of temperature and time (e.g., can have characteristics independent of temperature and time). The at least one resistive memory element RME can be used to generate the first voltage VFS, and thus can have temperature and time dependence.

[0076] In some example embodiments, as will be described with reference to Figure 5 the voltage generator 210 can be implemented in the form of a current mirror.

[0077] In Figure 1 the example embodiment shown, the comparison unit 220 compares the signal voltage Vsig from the crossbar array 110 with the plurality of divided voltages VD to generate a plurality of comparison signals CS. As will be described with reference to Figure 1 the signal voltage Vsig can be obtained by performing a current-voltage conversion on the read current Iread output from a column of the crossbar array 110, and has temperature and time dependence due to the resistive element RE included in the crossbar array 110.

[0078] The encoding unit 230 generates at least one digital signal DS corresponding to the signal voltage Vsig based on the plurality of comparison signals CS. As will be described with reference to Figure 5 and Figure 11 the configurations of the voltage generator 210, the comparison unit 220, and the encoding unit 230 can be changed according to the number of bits of the digital signal DS.

[0079] According to some example embodiments, an analog-to-digital converter 200 may include at least one resistive memory element RME, and the resistive material of the at least one resistive memory element RME is the same as or similar to the resistive material of the resistive elements RE included in the crossbar array 110. Therefore, the read current Iread output from the crossbar array 110, the signal voltage Vsig corresponding to the read current Iread, and the first voltage VFS generated and used in the analog-to-digital converter 200 may have the same or similar temperature and time dependencies, and when the output of the crossbar array 110 is analog-to-digital converted, a digital signal DS that does not change (or does not change significantly) according to temperature and time may be generated. Therefore, analog-to-digital conversion can be effectively performed without error.

[0080] In some example embodiments, the processing circuit that performs the comparison and generation of digital signals may include: hardware such as a logic circuit; a hardware / software combination, for example, a processor that executes software; or a combination thereof. For example, the processor may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. Additionally, in some example embodiments, the structure of the processing circuit may be different compared to some other example embodiments (for example, Figure 4 the example embodiments shown). In other example embodiments, without departing from the scope of the present disclosure, the processing circuit may include different structures of components, for example, renaming, rearranging, adding, dividing, copying, combining, and / or deleting components, sets of components, and the relationships between them. All such changes that are technically and logically feasible and do not conflict with other statements are intended to be included in the present disclosure, and the scope of the present disclosure should be understood to be limited only by the claims.

[0081] Figure 5 is a circuit diagram showing Figure 4 an example of an analog-to-digital converter.

[0082] Referring to Figure 5 , the analog-to-digital converter 200a includes a voltage generator 210a, a comparison unit 220a, and an encoding unit 230a. Figure 5 The analog-to-digital converter 200a of

[0083] may be a 2-bit flash analog-to-digital converter that generates a 2-bit digital signal DS. The voltage generator 210a may include a first transistor T1, a second transistor T2, a first resistive memory element RME1, and a plurality of resistors R11, R12, and R13.

[0084] The first transistor Tl may include a first electrode (e.g., a drain, source, collector, or emitter) that receives a reference voltage Vref, a second electrode (e.g., a gate or base) connected to each other, and a third electrode (e.g., a source, drain, emitter, or collector). The second transistor T2 may include a first electrode that receives the reference voltage Vref, a third electrode connected to the third electrode of the first transistor T1, and a second electrode that outputs a first voltage VFS. The first resistive memory element RME1 may be connected between the second electrode of the first transistor T1 and the ground voltage, and may include a resistive material that is the same as or similar to the resistive material of the resistive element RE included in the crossbar switch array 110. A plurality of resistors R11, R12, and R13 may be connected in series between the second electrode of the second transistor T2 and the ground voltage. Each of the plurality of resistors R11, R12, and R13 may have a fixed resistance.

[0085] As will be referred to Figure 6A and Figure 6B described, the voltage generator 210a may be implemented in the form of a current mirror, and may use the reference voltage Vref, the first resistive memory element RME1, and the current mirror structure that are independent of temperature and time to generate the first voltage VFS, and the first voltage VFS may have the same or similar temperature and time dependence as the resistive element RE included in the crossbar switch array 110.

[0086] In addition, the voltage generator 210a may be configured to generate a plurality of divided voltage signals VD11, VD12, and VD13 by dividing the first voltage VFS using the plurality of resistors R11, R12, and R13. In some example embodiments, the number of the plurality of resistors R11, R12, and R13 may be substantially equal to the number of the plurality of divided voltage signals VD11, VD12, and VD13, while in some other example embodiments, the number of the plurality of resistors may be different from the number of the plurality of divided voltage signals. The divided voltage signal VD13 having the highest level among the plurality of divided voltage signals VD11, VD12, and VD13 may have the same or similar level as the first voltage VFS.

[0087] In some example embodiments, the processing circuit (e.g., the comparison unit 220a) may include a plurality of comparators 222a, 222b, and 222c configured to generate a plurality of comparison signals CS11, CS12, and CS13.

[0088] In some example embodiments, a processing circuit (e.g., comparator 222a) may be configured to compare a signal voltage Vsig from the crossbar array 110 with a divided voltage VD11 to generate a comparison signal CS11. Comparator 222b may be configured to compare the signal voltage Vsig with a divided voltage VD12 to generate a comparison signal CS12. Comparator 222c may be configured to compare the signal voltage Vsig with a divided voltage VD13 to generate a comparison signal CS13. Each of the plurality of comparison signals CS11, CS12, and CS13 may have a value of "0" or "1". In some example embodiments, the signal voltage Vsig may be compared with a plurality of divided voltages VD11, VD12, and VD13 by a plurality of comparators 222a, 222b, and 222c to be divided into "0" or "1".

[0089] In some example embodiments, a processing circuit (e.g., encoding unit 230a) may include a priority encoder 232a configured to convert the plurality of comparison signals CS11, CS12, and CS13 into a binary value to generate a digital signal DS.

[0090] The priority encoder 232a may include a first input terminal IN10 receiving a power supply voltage VCC, a second input terminal IN11 receiving the comparison signal CS11, a third input terminal IN12 receiving the comparison signal CS12, a fourth input terminal IN13 receiving the comparison signal CS13, a first output terminal OUT10 outputting a first bit of the digital signal DS, and a second output terminal OUT11 outputting a second bit of the digital signal DS.

[0091] In some example embodiments, based on the number of bits of the digital signal DS being X, where X is a natural number greater than or equal to 2, the number of the plurality of comparators 222a, 222b, and 222c included in the comparison unit 220a, the number of the plurality of comparison signals CS11, CS12, and CS13 generated from the comparison unit 220a, and / or the number of the resistors R11, R12, and R13 included in the voltage generator 210a may be (2 X -1). In Figure 5 the example, X = 2.

[0092] Figure 6A 、 Figure 6B and Figure 6C are diagrams for describing Figure 5 the implementation manner of the voltage generator included in the analog-to-digital converter.

[0093] Referring to Figure 6A, in some example embodiments, the device is configured to use a reference voltage Vref and a first resistive memory element RME1 that are independent of temperature and time to generate a reference current Iref that can have temperature and / or time dependence, and use the reference current Iref to generate a first voltage VFS that has temperature and time dependence. The reference current Iref can be represented by Equation 2.

[0094] [Equation 2]

[0095] Iref = g × Vref × Temp(T) × Time(t)

[0096] In Equation 2, "g" represents the conductance of the first resistive memory element RME1, and Temp(T) and Time(t) represent functions of the temperature dependence and time dependence of the first resistive memory element RME1, respectively.

[0097] Referring to Figure 6B , to use the reference current Iref to generate the first voltage VFS, a current mirror structure that replicates the reference current Iref can be employed. Thus, a first voltage VFS that has temperature and / or time dependence can be generated based on the reference current Iref.

[0098] Referring to Figure 6C , CASE1 represents the voltage change according to temperature in an early state, CASE2 represents the drift characteristic and voltage change according to temperature, and CASE3 represents the retention characteristic and voltage change according to temperature. In Figure 6C , the dashed line represents the change of the first voltage VFS according to temperature, the bar graph represents the change of the signal voltage Vsig output from columns CL1 and CL2 according to temperature, CT represents the signal voltage Vsig at a relatively low temperature, and HT represents the signal voltage Vsig at a relatively high temperature.

[0099] To hide and / or compensate for the temperature and / or time dependence of the multiple resistive memory cells RMC and resistive elements RE included in the crossbar array 110 (e.g., to reduce the influence of temperature and / or time dependence), it would be advantageous to implement the device such that the first voltage VFS and the signal voltage Vsig have the same or similar temperature and time dependence in all or at least some cases as shown in Figure 6C .

[0100] In other words, for Figure 6CIn all cases of CASE1, the ratio of the amount of change of the signal voltage Vsig according to temperature and the ratio of the amount of change of the first voltage VFS according to temperature may be substantially the same (e.g., ΔVsig / Vsig=ΔVFS / VFS). For example, the ratio of the amount of change of the first voltage VFS1 according to temperature (e.g., ΔVFS1 / VFS1), the ratio of the amount of change of the signal voltage Vsig11 from the first column CL1 according to temperature (e.g., ΔVsig11 / Vsig11), and the ratio of the amount of change of the signal voltage Vsig12 from the second column CL2 according to temperature (e.g., ΔVsig12 / Vsig12) may be substantially the same as each other under CASE1. Similarly, the ratio of the amount of change according to temperature of the first voltage VFS2 (e.g., ΔVFS2 / VFS2), the ratio of the amount of change according to temperature of the signal voltage Vsig21 from the first column CL1 (e.g., ΔVsig21 / Vsig21), and the ratio of the amount of change according to temperature of the signal voltage Vsig22 from the second column CL2 (e.g., ΔVsig22 / Vsig22) may be substantially the same as each other under CASE 2. The ratio of the amount of change according to temperature of the first voltage VFS3 (e.g., ΔVFS3 / VFS3), the ratio of the amount of change according to temperature of the signal voltage Vsig31 from the first column CL1 (e.g., ΔVsig31 / Vsig31), and the ratio of the amount of change according to temperature of the signal voltage Vsig32 from the second column CL2 (e.g., ΔVsig32 / Vsig32) may be substantially the same as each other under CASE 3.

[0101] As described above, the signal voltage Vsig from the crossbar switch array 110 and the first voltage VFS generated and used in the analog-to-digital converter 200 can be implemented to have the same or similar temperature and time dependencies. Therefore, when the output of the crossbar switch array 110 is analog-to-digital converted, a digital signal DS that does not change (or does not significantly change) according to temperature and time can be generated.

[0102] Figure 7 , Figure 8 , Figure 9 and Figure 10 It is shown Figure 5 Circuit diagrams of other examples of voltage generators included in analog-to-digital converters will be omitted. Figure 5 Duplicate description.

[0103] Reference Figure 7 , the voltage generator 210 b may include a first transistor T1 , a second transistor T2 , a plurality of resistance storage elements RME1 , RME2 , and RME3 , and a plurality of resistors R11 , R12 , and R13 .

[0104] Apart from Figure 5One of the resistive memory elements RME1 in is changed to Figure 7 In addition to the multiple resistive memory elements RME1, RME2, and RME3 in Figure 7 The voltage generator 210b of can be the same as Figure 5 The voltage generator 210a in

[0105] The multiple resistive memory elements RME1, RME2, and RME3 can be connected in series between the second electrode of the first transistor T1 and the ground voltage. The resistive material of each of the multiple resistive memory elements RME1, RME2, and RME3 can be the same as or similar to the resistive material of the resistive element RE included in the crossbar switch array 110.

[0106] Similar to the multiple resistive memory cells RMC included in the crossbar switch array 110, the device can be configured to write data into the resistive memory element RME based on a voltage higher than or equal to a voltage level by the resistive memory element RME included in the analog-to-digital converter 200 (e.g., when a voltage higher than or equal to a predetermined level is applied to the resistive memory element RME). In some cases, according to the implementation of the analog-to-digital converter 200, the first voltage VFS can be higher than the allowable read voltage of the resistive memory element RME, and / or the resistance of the resistive memory element RME can be changed by the first voltage VFS during the operation of the analog-to-digital converter 200. In some exemplary embodiments, in order to prevent or reduce such resistance change, the multiple resistive memory elements RME1, RME2, and RME3 can be connected in series, and / or the number of the multiple resistive memory elements RME1, RME2, and RME3 can be adjusted when designing the chip to operate under a read voltage that meets or satisfies the product reliability standard. Additionally, the device with the multiple resistive memory elements RME1, RME2, and RME3 connected in series can exhibit the effect of reducing the influence of the manufacturing process variation.

[0107] In some exemplary embodiments, the number of the multiple resistive memory elements RME1, RME2, and RME3 can be based on the reference voltage Vref and the read voltage for reading the multiple resistive memory cells RMC included in the crossbar switch array 110 (e.g., the read voltage for reading the multiple resistive memory elements RME1, RME2, and RME3). For example, the number of the multiple resistive memory elements RME1, RME2, and RME3 can be obtained by Equation 3.

[0108] [Equation 3]

[0109] Y = Vref / Vread

[0110] In Equation 3, "Y" represents the number of multiple resistive memory elements RME1, RME2, and RME3, where Y is a natural number greater than or equal to 2, and Vread represents the read voltage. If Vref / Vread is not a natural number, then Y can be any natural number greater than Vref / Vread.

[0111] Referring to Figure 8 , the voltage generator 210c may include a first transistor T1, a second transistor T2, multiple resistive memory elements RME1, RME2, and RME3, multiple resistors R11, R12, and R13, a switch matrix 212, a write driver 214, and multiple switch elements SW1, SW2, and SW3.

[0112] In addition to Figure 8 the voltage generator 210c further includes a switch matrix 212, a write driver 214, and multiple switch elements SW1, SW2, and SW3, Figure 8 the voltage generator 210c may be substantially the same as Figure 7 the voltage generator 210b.

[0113] The write driver 214 may be connected to multiple resistive memory elements RME1, RME2, and RME3, and may perform a write operation of setting each of the multiple resistive memory elements RME1, RME2, and RME3 to a (at least approximately) target resistance. In other words, the write driver 214 may be configured to set each of the multiple resistive memory elements RME1, RME2, and RME3 to a resistance state (e.g., a predetermined, desired, and / or favorable resistance state). Although not shown in Figure 8 , the write driver 214 may be configured to receive a write voltage for the write operation from an external voltage regulator.

[0114] Multiple switch elements SW1, SW2, and SW3 may be located between the write driver 214 and the multiple resistive memory elements RME1, RME2, and RME3. The switch matrix 212 may be configured to control the multiple switch elements SW1, SW2, and SW3 to select a target resistive memory element to be subjected to the write operation among the multiple resistive memory elements RME1, RME2, and RME3. Although not shown in Figure 8 , the switch matrix 212 may be configured to receive a selection signal for selecting the target resistive memory element from an external timing controller or control circuit.

[0115] In some example embodiments, the write driver 214 may be configured to perform a write operation based on an update of a plurality of data stored in a plurality of resistive memory cells RMC included in the crossbar array 110. In other words, the write driver 214 may be configured to perform a write operation based on an update of a plurality of weights included in a neural network system. Constructing the device to perform a write operation on a plurality of resistive memory elements RME1, RME2, and RME3 simultaneously and / or in parallel with a plurality of data being written into the crossbar array 110 may further reduce the time dependence of the resistive memory elements.

[0116] In some example embodiments, the write driver 214 may be configured to perform a write operation of setting a plurality of resistive memory elements RME1, RME2, and RME3 to different resistances relative to each other.

[0117] Based on selecting some resistors according to the distribution of a plurality of data stored in the crossbar array 110, and based on performing a write operation on a plurality of resistive memory elements RME1, RME2, and RME3 connected in series to be set to different resistances relative to each other at each stage, the temperature and time dependence that vary according to the initial resistances of the plurality of resistive memory elements RME1, RME2, and RME3 can be averaged, thereby further suppressing the temperature and time dependence.

[0118] In some example embodiments, the write driver 214 may be configured to perform a write operation of setting at least one of the plurality of resistive memory elements RME1, RME2, and RME3 to a maximum resistance.

[0119] Referring to Figure 9 , the voltage generator 210d may include a first transistor T1, a second transistor T2, a plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23, and a plurality of resistors R11, R12, and R13.

[0120] Except that Figure 7 the plurality of resistive memory elements RME1, RME2, and RME3 in Figure 9 are changed to Figure 9 the plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23 in Figure 7 the voltage generator 210d of

[0121] A plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23 may include a first group of resistive memory elements RME11, RME12, and RME13 and a second group of resistive memory elements RME21, RME22, and RME23. The first group of resistive memory elements RME11, RME12, and RME13 may be connected in series between a second electrode of the first transistor T1 and a ground voltage. The second group of resistive memory elements RME21, RME22, and RME23 may be connected in series between the second electrode of the first transistor T1 and the ground voltage. The second group of resistive memory elements RME21, RME22, and RME23 and the first group of resistive memory elements RME11, RME12, and RME13 may be connected in parallel with each other. Additionally, each resistive memory element in the second group of resistive memory elements RME21, RME22, and RME23 and the corresponding resistive memory element in the first group of resistive memory elements RME11, RME12, and RME13 may be connected in parallel with each other.

[0122] An exemplary embodiment in which a plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23 are connected in series and each stage includes two or more resistive memory elements connected in parallel may exhibit an effect of further reducing the influence of manufacturing process variations.

[0123] Referring to Figure 10 , the voltage generator 210e may include a first transistor T1, a second transistor T2, a plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23, a plurality of resistors R11, R12, and R13, a switch matrix 212, a write driver 214, and a plurality of switch elements SW1, SW2, and SW3.

[0124] Except that Figure 8 the plurality of resistive memory elements RME1, RME2, and RME3 in Figure 10 are changed to the plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23 in Figure 10 , the voltage generator 210e of Figure 8 may be substantially the same as the voltage generator 210c of

[0125] The write driver 214 can be connected to a plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23, and can be configured to perform a write operation of setting each of the plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23 to a target resistance. A plurality of switching elements SW1, SW2, and SW3 can be located between the write driver 214 and the plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23. The switch matrix 212 can be configured to select a target resistive memory element to which a write operation is to be performed among the plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23.

[0126] In some example embodiments, the write driver 214 can be configured to perform a write operation of setting a first group of resistive memory elements RME11, RME12, and RME13 to have different resistances relative to each other and setting a second group of resistive memory elements RME21, RME22, and RME23 to have different resistances relative to each other. In addition, the write driver 214 can be configured to perform a write operation of setting each of the resistive memory elements in the first group of resistive memory elements RME11, RME12, and RME13, which are connected in parallel with each other, and a corresponding one of the resistive memory elements in the second group of resistive memory elements RME21, RME22, and RME23 to have the same or similar resistances relative to each other.

[0127] For example, the resistive memory elements RME11, RME12, and RME13 can have different resistances relative to each other, and the resistive memory elements RME21, RME22, and RME23 can have different resistances relative to each other. In addition, the resistive memory elements RME11 and RME21 connected in parallel at the same level can have the same or similar resistances relative to each other, the resistive memory elements RME12 and RME22 connected in parallel at the same level can have the same or similar resistances relative to each other, and the resistive memory elements RME13 and RME23 connected in parallel at the same level can have the same or similar resistances relative to each other. For example, the resistive memory elements RME11 and RME21 can have a relatively small first resistance, the resistive memory elements RME12 and RME22 can have a second resistance greater than the first resistance, and the resistive memory elements RME13 and RME23 can have a third resistance greater than the second resistance. Thus, the temperature and time dependencies that vary according to the initial resistances of the plurality of resistive memory elements RME11, RME12, RME13, RME21, RME22, and RME23 can be averaged, and thus the temperature and time dependencies can be further suppressed.

[0128] Although Figure 7 、 Figure 8 、 Figure 9 and Figure 10 show voltage generators 210b, 210c, 210d, and 210e including a specific number of resistive memory elements and a specific number of groups of resistive memory elements, some example embodiments are not limited thereto, and according to some example embodiments, the number of resistive memory elements and / or the number of groups of resistive memory elements may be changed.

[0129] Figure 11 is a circuit diagram showing Figure 4 another example of an analog-to-digital converter. Descriptions that are repeated with Figure 5 will be omitted.

[0130] Referring to Figure 11 , the analog-to-digital converter 200f includes a voltage generator 210f, a comparison unit 220f, and an encoding unit 230f. In some example embodiments, Figure 11 the analog-to-digital converter 200f of

[0131] the voltage generator 210f may include a first transistor T1, a second transistor T2, a first resistive memory element RME1, and a plurality of resistors R21, R22, R23, R24, R25, R26, and R27. Except for changing the number of the plurality of resistors R21, R22, R23, R24, R25, R26, and R27, Figure 11 the voltage generator 210f in Figure 5 may be substantially the same as the voltage generator 210a in Figure 7 、 Figure 8 、 Figure 9 and Figure 10 described. In some example embodiments, the number of the plurality of resistors R21, R22, R23, R24, R25, R26, and R27 may be substantially equal to the number of the plurality of divided voltage levels VD21, VD22, VD23, VD24, VD25, VD26, and VD27 generated by the voltage generator 210f. In some example embodiments, the configuration of the voltage generator 210f may be changed as described with reference to

[0132] The comparison unit 220f may include a plurality of comparators 224a, 224b, 224c, 224d, 224e, 224f, and 224g, which are configured to generate a plurality of comparison signals CS21, CS22, CS23, CS24, CS25, CS26, and CS27. Except for changing the number of the plurality of comparators 224a, 224b, 224c, 224d, 224e, 224f, and 224g,Figure 11 The comparison unit 220f in Figure 5 can be substantially the same as the comparison unit 220a in

[0133] The encoding unit 230f may include a priority encoder 232f configured to convert a plurality of comparison signals CS21, CS22, CS23, CS24, CS25, CS26, and CS27 into binary values to generate a digital signal DS. The priority encoder 232f may include a first input terminal IN20 receiving a power supply voltage VCC, a second input terminal IN21 receiving the comparison signal CS21, a third input terminal IN22 receiving the comparison signal CS22, a fourth input terminal IN23 receiving the comparison signal CS23, a fifth input terminal IN24 receiving the comparison signal CS24, a sixth input terminal IN25 receiving the comparison signal CS25, a seventh input terminal IN26 receiving the comparison signal CS26, an eighth input terminal IN27 receiving the comparison signal CS27, a first output terminal OUT20 outputting the first bit of the digital signal DS, a second output terminal OUT21 outputting the second bit of the digital signal DS, and a third output terminal OUT22 outputting the third bit of the digital signal DS.

[0134] In some example embodiments, based on the number of bits of the digital signal DS being X, where X is a natural number greater than or equal to 2, the number of a plurality of comparators 224a, 224b, 224c, 224d, 224e, 224f, and 224g included in the comparison unit 220f, the number of a plurality of comparison signals CS21, CS22, CS23, CS24, CS25, CS26, and CS27 generated from the comparison unit 220f, and / or the number of resistors R21, R22, R23, R24, R25, R26, and R27 included in the voltage generator 210f, all or at least some of them may be (2 X -1). In Figure 11 the example, X = 3.

[0135] Although the analog-to-digital converters 200a and 200f generating a 2-bit or 3-bit digital signal DS are shown in Figure 5 and Figure 11 , some example embodiments are not limited thereto, and according to some example embodiments, the number of bits of the digital signal DS can be changed.

[0136] Figure 12 is a block diagram showing a neuromorphic computing device according to some example embodiments. Descriptions that are repeated with Figure 1 will be omitted.

[0137] Referring to Figure 12, the neuromorphic computing device 100a includes a crossbar array 110 and an analog-to-digital conversion block 150a. The neuromorphic computing device 100a may also include a first switch matrix 120, a second switch matrix 130, a current-voltage conversion block 140, an adder block 160a, a shift register block 170a, a multiplexer (MUX) 180, and a multiplexer decoder 190.

[0138] Except that the neuromorphic computing device 100a further includes a multiplexer 180 and a multiplexer decoder 190, and except for changing the configurations of the analog-to-digital conversion block 150a, the adder block 160a, and the shift register block 170a, Figure 12 the neuromorphic computing device 100a may be substantially the same as Figure 1 the neuromorphic computing device 100.

[0139] In some example embodiments, as Figure 12 shown, the number of multiple analog-to-digital converters 152, the number of multiple adders 162, and the number of multiple shift registers 172 may be less than the number of multiple columns CL1, CL2,..., CLM of the crossbar array 110. For example, one analog-to-digital converter 152, one adder 162, and one shift register 172 may be shared by two or more columns, thus reducing the size of the neuromorphic computing device 100a.

[0140] The multiplexer decoder 190 may be configured to generate a selection signal SEL for controlling the operation of the multiplexer 180. The multiplexer 180 may be located between the crossbar array 110 and the analog-to-digital conversion block 150a (e.g., between the current-voltage conversion block 140 and the analog-to-digital conversion block 150a), and may connect one column (e.g., one current-voltage converter among multiple current-voltage converters 142 or one signal voltage among multiple signal voltages Vsig) of the multiple columns CL1, CL2,..., CLM of the crossbar array 110 to one of the multiple analog-to-digital converters 152.

[0141] For example, one analog-to-digital converter 152 may be shared by two columns CL1 and CL2, and the above operation may be first performed by connecting column CL1 to one analog-to-digital converter 152, and then, the above operation may be performed by connecting column CL2 to the same analog-to-digital converter 152.

[0142] Although not shown in Figure 12 , in some example embodiments, according to some example embodiments, the multiplexer 180 may be located between the crossbar array 110 and the current-voltage conversion block 140. In Figure 12In an example embodiment, a current-voltage converter 142, an analog-to-digital converter 152, an adder 162, and a shift register 172 may be shared by two or more columns.

[0143] Figure 13 is a block diagram showing an electronic system according to some example embodiments.

[0144] Referring to Figure 13 , the electronic system 1000 may include a processor 1010, a storage device 1020, a connection module 1030, an input / output (I / O) device 1040, a power supply 1050, and a neuromorphic computing device 1060. The electronic system 1000 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0145] The processor 1010 controls the operation of the electronic system 1000. In some example embodiments, the processor 1010 may include and / or serve as a processing circuit (e.g., a comparison unit 220 and / or an encoding unit 230), and vice versa. The processor 1010 may be configured to execute an operating system and at least one application to provide an Internet browser, a game, a video, and the like. The storage device 1020 may be configured to store data for the operation of the electronic system 1000. The connection module 1030 may be configured to communicate with external devices (not shown). The I / O device 1040 may include input devices such as a keyboard, a keypad, a mouse, a touchpad, a touch screen, a remote control, etc., and output devices such as a printer, a speaker, etc. The power supply 1050 may be configured to provide power for the operation of the electronic system 1000.

[0146] The neuromorphic computing device 1060 may be configured to drive and / or execute a neural network system, and may be a neuromorphic computing device 100 according to some example embodiments. The neuromorphic computing device 1060 may include an analog-to-digital converter 1062. The analog-to-digital converter 1062 may include at least one resistive memory element RME (the resistive material of the at least one resistive memory element RME is the same as or similar to the resistive material of the resistive element RE included in the crossbar switch array 110), and may be an analog-to-digital converter 200 according to some example embodiments.

[0147] Some example embodiments of some inventive concepts may include various electronic devices and / or systems that include neuromorphic computing devices and / or neural network systems. For example, some example embodiments of some inventive concepts may include systems such as mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, portable video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, and the like.

[0148] The foregoing is an illustration of some example embodiments and should not be construed as a limitation thereof. Although some example embodiments have been described, those skilled in the art will readily recognize that many modifications are possible in some example embodiments without materially departing from the teachings and potential advantages of such example embodiments. Accordingly, all such modifications are intended to be included within the scope of some example embodiments as defined by the claims. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as limited to the specific example embodiments disclosed, and is intended to include the disclosed example embodiments and modifications of some other example embodiments within the scope of the appended claims.

Claims

1. An analog-to-digital converter, the analog-to-digital converter being connected to a crossbar switch array including a plurality of resistive memory cells, each of the plurality of resistive memory cells including a resistive element, the analog-to-digital converter comprising: a voltage generator including at least one resistive memory element and a first transistor, the resistive material of the at least one resistive memory element being the same as the resistive material of the resistive element included in the crossbar switch array, the first transistor including a first electrode receiving a reference voltage, a second electrode and a third electrode connected to each other, the voltage generator being configured to generate a first voltage based on the reference voltage and the at least one resistive memory element, and divide the first voltage to generate at least one divided voltage; and a processing circuit configured to: compare a signal voltage from the crossbar switch array with the at least one divided voltage to generate at least one comparison signal; and generate at least one digital signal corresponding to the signal voltage based on the at least one comparison signal.

2. The analog-to-digital converter according to claim 1, wherein the voltage generator includes: a second transistor including a first electrode receiving the reference voltage, a third electrode connected to the third electrode of the first transistor, and a second electrode outputting the first voltage; a first resistive memory element connected between the second electrode of the first transistor and a ground voltage, the resistive material of the first resistive memory element being the same as the resistive material of the resistive element; and at least one resistor connected in series between the second electrode of the second transistor and the ground voltage.

3. The analog-to-digital converter according to claim 2, wherein the number of the at least one resistor is equal to the number of the at least one divided voltage.

4. The analog-to-digital converter according to claim 1, wherein the voltage generator includes: a second transistor including a first electrode receiving the reference voltage, a third electrode connected to the third electrode of the first transistor, and a second electrode outputting the first voltage; a plurality of resistive memory elements connected in series between the second electrode of the first transistor and a ground voltage, the resistive material of each of the plurality of resistive memory elements being the same as the resistive material of the resistive element; and at least one resistor connected in series between the second electrode of the second transistor and the ground voltage.

5. The analog-to-digital converter according to claim 4, wherein the number of the plurality of resistive memory elements is determined based on the reference voltage and a read voltage for reading the plurality of resistive memory cells included in the crossbar switch array.

6. The analog-to-digital converter according to claim 4, wherein the voltage generator further includes: A write driver, the write driver being connected to the plurality of resistive memory elements, the write driver being configured to perform a write operation to set each of the plurality of resistive memory elements to a target resistance.

7. The analog-to-digital converter according to claim 6, wherein, the write driver is further configured to perform the write operation based on an update of data stored in the plurality of resistive memory cells included in the crossbar array.

8. The analog-to-digital converter according to claim 6, wherein, the write driver is further configured to perform the write operation to set the plurality of resistive memory elements to different resistances from each other.

9. The analog-to-digital converter according to claim 6, wherein, the write driver is further configured to perform the write operation to set at least one of the plurality of resistive memory elements to a maximum resistance.

10. The analog-to-digital converter according to claim 6, wherein, the voltage generator further includes: a switch matrix configured to select a target resistive memory element among the plurality of resistive memory elements to which the write operation is to be performed.

11. The analog-to-digital converter according to claim 4, wherein, the plurality of resistive memory elements include: a first set of resistive memory elements connected in series between the second electrode of the first transistor and the ground voltage; and a second set of resistive memory elements connected in series between the second electrode of the first transistor and the ground voltage, the second set of resistive memory elements and the first set of resistive memory elements being connected in parallel with each other.

12. The analog-to-digital converter according to claim 11, wherein, the voltage generator further includes: a write driver, the write driver being connected to the plurality of resistive memory elements, the write driver being configured to perform a write operation to set each of the plurality of resistive memory elements to a target resistance.

13. The analog-to-digital converter according to claim 12, wherein: the write driver is further configured to perform the write operation to set the first set of resistive memory elements to different resistances from each other and to set the second set of resistive memory elements to different resistances from each other, and the write driver is further configured to perform the write operation to set each of the resistive memory elements in the first set and the corresponding resistive memory element in the second set, which are connected in parallel with each other, to the same resistance as each other.

14. The analog-to-digital converter according to claim 1, wherein: the processing circuit includes at least one comparator configured to generate at least one comparison signal; and When the number of bits of the digital signal is X, where X is a natural number greater than or equal to 2, the number of the at least one comparison signal and the number of the at least one comparator are (2 X - 1).

15. A neuromorphic computing device, comprising: A crossbar switch array, the crossbar switch array including a plurality of resistive memory cells, the crossbar switch array being configured to store a plurality of data and generate at least one signal voltage based on at least one input voltage and at least one data, each of the plurality of resistive memory cells including a resistive element; and at least one analog-to-digital converter, the at least one analog-to-digital converter being configured to convert the at least one signal voltage into at least one digital signal, wherein each of the at least one analog-to-digital converters includes at least one resistive memory element, the resistive material of the at least one resistive memory element being the same as the resistive material of the resistive element included in the crossbar switch array, and wherein each of the at least one analog-to-digital converters is configured to: generate a first voltage based on a reference voltage and the at least one resistive memory element, divide the first voltage to generate at least one divided voltage, compare one of the at least one signal voltages with the at least one divided voltage to generate at least one comparison signal, and generate one of the at least one digital signals based on the at least one comparison signal.

16. The neuromorphic computing device according to claim 15, wherein: each of the at least one data represents a weight included in at least one layer of a neural network system, and each of the at least one signal voltages represents a result of a multiply-accumulate operation performed by the neural network system.

17. The neuromorphic computing device according to claim 15, wherein, the number of the at least one analog-to-digital converters is equal to the number of columns of the crossbar switch array.

18. The neuromorphic computing device according to claim 15, wherein, the number of the at least one analog-to-digital converters is less than the number of columns of the crossbar switch array.

19. The neuromorphic computing device according to claim 18, the neuromorphic computing device further comprises: a multiplexer, the multiplexer being located between the crossbar switch array and the at least one analog-to-digital converter, the multiplexer being configured to connect one of the columns of the crossbar switch array to one of the at least one analog-to-digital converters.

20. A neuromorphic computing device, comprising: a crossbar switch array, the crossbar switch array including a plurality of resistive memory cells, the crossbar switch array being configured to store a plurality of weights included in at least one layer of a neural network system, and generate a plurality of read currents based on a plurality of input voltages and the plurality of weights, each of the plurality of resistive memory cells including a resistive element, the plurality of read currents representing a result of a multiply-accumulate operation performed by the neural network system; a first switch matrix connected to the rows of the crossbar switch array; a second switch matrix connected to the columns of the crossbar switch array; A plurality of current-voltage converters configured to convert the plurality of read currents into a plurality of signal voltages; A plurality of analog-to-digital converters configured to convert the plurality of signal voltages into a plurality of digital signals; A plurality of adders configured to sum the plurality of digital signals; And A plurality of shift registers configured to generate final output data based on the outputs of the plurality of adders, Each of the plurality of analog-to-digital converters includes: a voltage generator including at least one resistive memory element having the same resistive material as the resistive elements included in the crossbar array, the voltage generator being configured to generate a first voltage based on a reference voltage and the at least one resistive memory element and divide the first voltage to generate a plurality of divided voltages, the reference voltage being a voltage independent of temperature and time; a comparison unit configured to compare one of the plurality of signal voltages with the plurality of divided voltages to generate at least one comparison signal; and an encoding unit configured to generate one of the plurality of digital signals based on the at least one comparison signal.

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