A PWM control method and device

Abstract

The present application provides a PWM control method and device, the method comprising: obtaining the junction temperature of N power semiconductor devices in an inverter circuit, N being an integer greater than 1; when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than a first threshold, injecting a common-mode voltage into a modulation wave, the common-mode voltage being used to reduce the conduction duty cycle of K power semiconductor devices among the M power semiconductor devices, K being an integer greater than 0 and less than or equal to M, and M being an integer greater than 0 and less than or equal to N; and sending a control signal according to the modulation wave after the common-mode voltage is injected. In the above technical solution, by injecting a common-mode voltage into the modulation wave and adjusting the conduction duty cycle of the power semiconductor devices in the inverter circuit, it is possible to reasonably distribute the loss of the power semiconductor devices in the inverter circuit, which helps to reduce the probability of damage to the power semiconductor devices, thereby improving the safety of the system.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular, to a pulse width modulation (PWM) control method and device. Background Art

[0002] For systems using inverter circuits, when the modulation ratio, output power factor or output frequency of the inverter circuit is small, the current in the inverter circuit can be regarded as direct current, and some power semiconductor devices in the inverter circuit will continue to bear the current. The power semiconductor devices that bear the current will have a relatively large loss, while the power semiconductor devices that do not bear the current will have almost zero loss. In other words, the power loss in the inverter circuit is very uneven. This may cause the loss of individual power semiconductor devices to exceed the standard, which in turn may cause the junction temperature of the power semiconductor devices to be too high, causing damage to the power semiconductor devices and affecting the safety of the system. Summary of the invention

[0003] The present application provides a PWM control method and device, which can adjust the conduction duty cycle of power semiconductor devices in an inverter circuit, can reasonably distribute the losses of power semiconductor devices in the inverter circuit, help reduce the probability of damage to the power semiconductor devices, and thus improve the safety of the system.

[0004] In a first aspect, the present application provides a PWM control method, which can be executed by a PWM control device. The PWM control device can be an independently arranged module or unit, or can be integrated with other devices, which is not limited by the present application.

[0005] The method comprises:

[0006] Obtaining the junction temperature of N power semiconductor devices in the inverter circuit, where N is an integer greater than 1;

[0007] When the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than a first threshold, injecting a common-mode voltage into the modulation wave, the modulation wave is used to generate a signal for controlling the turning on or off of at least some of the N power semiconductor devices, and the common-mode voltage is used to reduce the on-duty cycle of K power semiconductor devices among the M power semiconductor devices, where K is an integer greater than 0 and less than or equal to M, and M is an integer greater than 0 and less than or equal to N;

[0008] A control signal is issued according to the modulated wave after the common mode voltage is injected, and the control signal is used to control the turning on or off of at least part of the power semiconductor devices.

[0009] The power semiconductor device in the inverter circuit of the present application may include at least one of the following: an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode, etc. At least some of the N power semiconductor devices may include at least one of the following: an IGBT and a MOSFET, etc.

[0010] In the above technical solution, by injecting common-mode voltage into the modulation wave, the conduction duty cycle of the power semiconductor devices in the inverter circuit can be reasonably distributed, so that the loss distribution of the power semiconductor devices in the inverter circuit is more reasonable, which helps to reduce the probability of damage to the power semiconductor devices, thereby improving the safety of the system. In addition, since the conduction duty cycle of the power semiconductor devices in the inverter circuit can be distributed by injecting common-mode voltage into the modulation wave, power semiconductor devices with smaller current levels can be used in the inverter circuit, which helps to reduce the cost of the inverter circuit.

[0011] In combination with the first aspect, in a possible implementation, the common-mode voltage may cause a change in the conduction duty cycle of the power semiconductor devices other than the M power semiconductor devices among the N power semiconductor devices while reducing the conduction duty cycle of the K power semiconductor devices.

[0012] For example, the common-mode voltage is used to reduce the conduction duty cycle of the K power semiconductor devices and also to increase the conduction duty cycle of the P power semiconductor devices, the P power semiconductor devices being power semiconductor devices other than the M power semiconductor devices among the N power semiconductor devices, and P being an integer greater than 0. It can be understood that the common-mode voltage is used to adjust the conduction duty cycle of the K power semiconductor devices and the P power semiconductor devices, so that the P power semiconductor devices share part of the current that should be borne by the K power semiconductor devices, thereby reducing the loss of the K power semiconductor devices and lowering the junction temperature of the K power semiconductor devices.

[0013] For another example, the common-mode voltage is used to reduce the on-duty ratio of the K power semiconductor devices and also to increase the on-duty ratio of the P power semiconductor devices. In addition, the common-mode voltage is also used to reduce the on-duty ratio of the R power semiconductor devices, the junction temperature of the R power semiconductor devices does not exceed the first threshold, and the R power semiconductor devices belong to the N power semiconductor devices but do not belong to the K power semiconductor devices and the P power semiconductor devices. It can be understood that the common-mode voltage can change the on-duty ratio of one or more power semiconductor devices whose junction temperature does not exceed the first threshold while reducing the on-duty ratio of the K power semiconductor devices and increasing the on-duty ratio of the P power semiconductor devices.

[0014] In combination with the first aspect or any possible implementation manner thereof, in another possible implementation manner, when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than a first threshold, injecting a common-mode voltage into the modulated wave includes: when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than the first threshold and the modulation ratio of the inverter circuit is lower than a second threshold, injecting the common-mode voltage into the modulated wave; or, when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than the first threshold and the output power factor of the inverter circuit is lower than a third threshold, injecting the common-mode voltage into the modulated wave; or, when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than the first threshold and the output frequency of the inverter circuit is lower than a fourth threshold, injecting the common-mode voltage into the modulated wave.

[0015] That is to say, the PWM control device will inject common-mode voltage into the modulation wave only when the modulation ratio of the inverter circuit, the output power factor of the inverter circuit, or the output frequency of the inverter circuit is low, thereby avoiding the influence of the common-mode voltage on the system under normal operating conditions.

[0016] In combination with the first aspect or any possible implementation manner thereof, in another possible implementation manner, the N power semiconductor devices correspond one by one to the N first thresholds, and the junction temperature of each of the M power semiconductor devices is greater than the first threshold corresponding to the power semiconductor device. In other words, the junction temperature of the M power semiconductor devices is greater than the first threshold, which can be understood as the junction temperatures of the M power semiconductor devices are respectively greater than the first threshold corresponding to the power semiconductor device.

[0017] The N first thresholds may be the same or different. For example, the first thresholds of power semiconductor devices of the same model may be the same, and the first thresholds of power semiconductor devices of different types or models may be different.

[0018] In combination with the first aspect or any possible implementation manner thereof, in another possible implementation manner, the inverter circuit is a single-phase or multi-phase inverter circuit.

[0019] In combination with the first aspect or any possible implementation manner thereof, in another possible implementation manner, the inverter circuit adopts a two-level topology structure or a multi-level topology structure.

[0020] In combination with the first aspect or any possible implementation manner thereof, in another possible implementation manner, the multi-level topology structure includes a neutral point clamped (NPC) three-level topology structure.

[0021] The NPC three-level topology may include an I-type three-level topology, a T-type three-level topology, and an active neutral point clamped (ANPC) three-level topology.

[0022] In combination with the first aspect or any possible implementation manner thereof, in another possible implementation manner, when the inverter circuit adopts an I-type three-level topology structure or a T-type three-level topology structure, the amplitude of the common-mode voltage is one quarter of the DC input voltage of the inverter circuit. In this way, the losses of the N power semiconductor devices can be reasonably distributed.

[0023] In the second aspect, the present application provides a PWM control device, which corresponds to the PWM control method of the first aspect, and thus can also achieve similar beneficial effects as the PWM control method of the first aspect. For a detailed description of the PWM control device, reference can be made to the first aspect.

[0024] The device comprises:

[0025] An acquisition unit, used to acquire the junction temperature of N power semiconductor devices in the inverter circuit, where N is an integer greater than 1;

[0026] a processing unit, configured to, when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than a first threshold, inject a common-mode voltage into a modulation wave, wherein the modulation wave is used to generate a signal for controlling the turning on or off of at least some of the N power semiconductor devices, and the common-mode voltage is used to reduce a conduction duty cycle of K power semiconductor devices among the M power semiconductor devices, where K is an integer greater than 0 and less than or equal to M, and M is an integer greater than 0 and less than or equal to N;

[0027] The processing unit is further used to send a control signal according to the modulated wave after the common mode voltage is injected, and the control signal is used to control the opening or closing of at least part of the power semiconductor devices.

[0028] In combination with the second aspect, in a possible implementation, the common-mode voltage is also used to increase the on-duty cycle of P power semiconductor devices, where the P power semiconductor devices are power semiconductor devices among the N power semiconductor devices except the M power semiconductor devices, and P is an integer greater than 0.

[0029] In combination with the second aspect or any possible implementation manner thereof, in another possible implementation manner, the processing unit is specifically used to: when the junction temperature of M of the N power semiconductor devices is greater than the first threshold and the modulation ratio of the inverter circuit is lower than the second threshold, inject the common-mode voltage into the modulated wave; or, when the junction temperature of M of the N power semiconductor devices is greater than the first threshold and the output power factor of the inverter circuit is lower than the third threshold, inject the common-mode voltage into the modulated wave; or, when the junction temperature of M of the N power semiconductor devices is greater than the first threshold and the output frequency of the inverter circuit is lower than the fourth threshold, inject the common-mode voltage into the modulated wave.

[0030] In combination with the second aspect or any possible implementation manner thereof, in another possible implementation manner, the N power semiconductor devices correspond one by one to the N first thresholds, and the junction temperature of each of the M power semiconductor devices is greater than the first threshold corresponding to the power semiconductor device. In other words, the junction temperature of the M power semiconductor devices is greater than the first threshold, which can be understood as the junction temperatures of the M power semiconductor devices are respectively greater than the first threshold corresponding to the power semiconductor device.

[0031] The N first thresholds may be the same or different. For example, the first thresholds of power semiconductor devices of the same model may be the same, and the first thresholds of power semiconductor devices of different types or models may be different.

[0032] In combination with the second aspect or any possible implementation manner thereof, in another possible implementation manner, the inverter circuit is a single-phase or multi-phase inverter circuit.

[0033] In combination with the second aspect or any possible implementation manner thereof, in another possible implementation manner, the inverter circuit adopts a two-level topology structure or a multi-level topology structure.

[0034] In combination with the second aspect or any possible implementation thereof, in another possible implementation, when the inverter circuit adopts an I-type three-level topology structure or a T-type three-level topology structure, the amplitude of the common-mode voltage is one quarter of the DC input voltage of the inverter circuit.

[0035] In a third aspect, the present application provides a PWM control device, which includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other devices outside the PWM control device and transmit them to the processor or send signals from the processor to other devices outside the PWM control device, and the processor is used to implement the method described in the first aspect or any possible implementation method thereof through logic circuits or execution of code instructions.

[0036] In a fourth aspect, the present application provides a PWM control device, which includes a processor for executing computer instructions stored in a memory so that the device performs the method described in the first aspect or any possible implementation thereof.

[0037] In a fifth aspect, the present application provides a motor controller, comprising the PWM control device described in the second aspect, the third aspect, the fourth aspect, or any possible implementation thereof.

[0038] In a sixth aspect, the present application provides a chip, comprising a processor, the processor being connected to a memory, the memory being used to store a computer program, and the processor being used to execute the computer program stored in the memory, so that the chip executes the method described in the first aspect or any possible implementation thereof.

[0039] In a seventh aspect, the present application provides a computer storage medium, in which a computer program or instructions are stored. When the computer program or instructions are executed by a computer, the method described in the first aspect or any possible implementation method thereof can be implemented.

[0040] In an eighth aspect, the present application provides a computer program product, including a computer program or instructions, which, when executed by a computer, can implement the method described in the first aspect or any possible implementation method thereof.

[0041] In a ninth aspect, the present application provides an electric drive system, the system comprising the PWM control device described in the second aspect, the third aspect, the fourth aspect, or any possible implementation thereof, or comprising the motor controller described in the fifth aspect, or comprising the chip described in the sixth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a structural block diagram of an electric drive system 100 to which the technical solution of the present application can be applied.

[0043] Figure 2 It is a schematic flow chart of the PWM control method 200 provided in the present application.

[0044] Figure 3It is a schematic diagram of a two-level topology.

[0045] Figure 4 It is a schematic diagram of the conduction duty cycle of S1 and D4.

[0046] Figure 5 It is the simulation waveform of the common-mode voltage injected into the two-level inverter modulation wave.

[0047] Figure 6 It is a schematic diagram of the NPC three-level topology.

[0048] Figure 7 S1, S2, D p1 , schematic diagram of the conduction duty cycle of D3 and D4.

[0049] Figure 8 It is a schematic diagram of a T-type three-level topology.

[0050] Fig. 9 It is a schematic diagram of the conduction duty cycle of S1, S3, D2 and D4.

[0051] Fig.10 It is a schematic diagram of the structure of the device provided in the embodiment of the present application.

[0052] Fig.11 It is another structural schematic diagram of the device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0054] The present application will present various aspects, embodiments or features around a system including multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all devices, components, modules, etc. discussed in conjunction with the figures. In addition, combinations of these schemes may also be used.

[0055] In addition, in the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0056] In the embodiments of the present application, "corresponding (corresponding, relevant)" and "corresponding (corresponding)" can sometimes be used interchangeably. It should be pointed out that when the distinction between them is not emphasized, the meanings they intend to express are consistent.

[0057] The scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that, with the evolution of scenarios and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0058] Unless otherwise defined, the technical terms or scientific terms used in this specification and claims should be understood by people with ordinary skills in the technical field to which the present invention belongs. "First" or "second" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. References to "one embodiment" or "some embodiments" described in this specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0059] In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0060] For systems using inverter circuits, when the modulation ratio, output power factor or output frequency of the inverter circuit is small, the current in the inverter circuit can be regarded as direct current, and some power semiconductor devices in the inverter circuit will continue to bear the current. The power semiconductor devices that bear the current will have a relatively large loss, while the power semiconductor devices that do not bear the current will have almost zero loss. In other words, the power loss in the inverter circuit is very uneven. This may cause the loss of individual power semiconductor devices to exceed the standard, which in turn may cause the junction temperature of the power semiconductor devices to be too high, causing damage to the power semiconductor devices and affecting the safety of the system.

[0061] In view of the above problems, being able to adjust the on-duty cycle of the power semiconductor devices in the inverter circuit can achieve a reasonable distribution of the losses of the power semiconductor devices in the inverter circuit, help reduce the probability of damage to the power semiconductor devices, and thus improve the safety of the system.

[0062] It should be noted that the technical solution of the present application can be applied to various systems using inverter circuits, and the present application is not limited thereto. As an example, the technical solution of the present application can be applied to an electric drive system, such as an electric drive system of a vehicle. For the convenience of description, the technical solution of the present application will be described below in conjunction with the electric drive system.

[0063] Figure 1 It is a structural block diagram of an electric drive system 100 to which the technical solution of the present application can be applied.

[0064] like Figure 1 As shown, the system 100 includes an inverter circuit, a motor, and a motor controller, wherein the inverter circuit is connected to the DC voltage, the motor, and the motor controller, respectively. The inverter circuit, which may also be referred to as an inverter, is a converter for converting DC power (e.g., a battery and a storage bottle, etc.) into AC power. A motor is a device for converting electrical energy into mechanical energy. The motor controller, which may also be referred to as a motor control unit (MCU), is used to control the conduction or shutdown of some power semiconductor devices in the inverter circuit according to the received signal wave and carrier. In the system 100, the motor controller controls the conduction or shutdown of some power semiconductor devices in the inverter circuit according to the signal wave and the carrier, so as to realize the conversion of the DC power input into the inverter circuit into AC power, and the AC power is converted into the mechanical energy of the motor rotation by electromagnetic induction after being input into the motor.

[0065] It should be noted that the present application does not limit the specific topology of the inverter circuit. For example, the inverter circuit may adopt a two-level topology or a multi-level topology. Among them, the multi-level topology may include an NPC three-level topology, etc. The present application also does not limit the number of phases of the inverter circuit. For example, the inverter circuit may be a single-phase or multi-phase inverter circuit.

[0066] It should be understood that the motor controller and the inverter circuit can be integrated into one device, or can be two independent devices, and this application does not specifically limit this. In other examples, the system 100 may include more, fewer, or different systems, and each system may include more, fewer, or different components. In addition, the systems and components shown can be combined or divided in any manner.

[0067] In the process of driving the motor to rotate, the motor may fail to start or stop rotating, that is, the motor is stalled. Motor stall is a situation in which the motor still outputs torque when the speed is 0 rpm, which is generally mechanical or man-made. For example, excessive motor load, mechanical failure of the towed machine, or bearing damage and bore sweeping may all cause the motor to stall. When the motor is running in stall, the problem of uneven power loss in the inverter circuit mentioned above will occur. Similarly, the low-speed operation of the motor can be regarded as a splicing of short-term stall conditions at different angles, and the above problems also exist.

[0068] The following is combined with Figures 2 to 8 The PWM control method provided in this application is described.

[0069] Figure 2 is a schematic flow chart of the PWM control method 200 provided in the present application. The method 200 can be applied to Figure 1 The method 200 may be performed by a PWM control device, which may be an independently configured module or unit, or may be connected to another device (e.g., Figure 1 The motor controller shown in the figure is integrated together, and this application is not limited to this.

[0070] Step 210: The PWM control device obtains the junction temperature of N power semiconductor devices in the inverter circuit, where N is an integer greater than 1.

[0071] The present application does not limit the specific topology of the inverter circuit. For example, the inverter circuit may adopt a two-level topology or a multi-level topology. Among them, the multi-level topology may include an NPC three-level topology, etc. The NPC three-level topology may include an I-type three-level topology, a T-type three-level topology, and an ANPC three-level topology, etc.

[0072] The present application also does not limit the number of phases of the inverter circuit. For example, the inverter circuit may be a single-phase or multi-phase inverter circuit.

[0073] The present application does not limit the manner in which the PWM control device obtains the junction temperatures of the N power semiconductor devices.

[0074] In some implementations, the PWM control device can obtain the voltage of the modulation wave, determine the conduction duty cycle of the N power semiconductor devices according to the voltage of the modulation wave, and then determine the loss of the N power semiconductor devices according to the conduction duty cycle of the N power semiconductor devices, and further determine the junction temperature of the N power semiconductor devices according to the loss of the N power semiconductor devices, wherein the modulation wave is used to generate a signal for controlling the opening or closing of at least part of the N power semiconductor devices, and the modulation wave can correspond to Figure 1 The signal wave shown. Taking the inverter circuit as a three-phase inverter circuit as an example, the PWM control device can obtain the phase voltage of the three-phase modulation wave of A, B and C, determine the conduction duty cycle of the N power semiconductor devices according to the phase voltage of the three-phase modulation wave of A, B and C, and then determine the loss of the N power semiconductor devices according to the conduction duty cycle of the N power semiconductor devices, and further determine the junction temperature of the N power semiconductor devices according to the loss of the N power semiconductor devices. The present application does not limit the way in which the PWM control device obtains the voltage of the modulation wave, for example, it can be any one of the existing methods or future methods.

[0075] In another implementation, the PWM control device may also directly obtain the junction temperatures of the N power semiconductor devices.

[0076] It can be understood that the PWM control device may obtain the junction temperatures of the N power semiconductor devices in any other conventional method or any method to be developed in the future.

[0077] The power semiconductor device in the inverter circuit of the present application may include at least one of the following: IGBT, MOSFET, diode, etc. At least some of the N power semiconductor devices may include: IGBT and / or MOSFET.

[0078] Step 220: When the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than a first threshold, inject a common mode voltage into the modulation wave. The common mode voltage is used to reduce the on-duty cycle of K power semiconductor devices among the M power semiconductor devices, where K is an integer greater than 0 and less than or equal to M, and M is an integer greater than 0 and less than or equal to N.

[0079] The N power semiconductor devices correspond to the N first thresholds one by one, and the N first thresholds may be the same or different. For example, the first thresholds of the same type of power semiconductor devices may be the same, and the first thresholds of different types or models of power semiconductor devices may be different. The junction temperatures of the M power semiconductor devices are greater than the first threshold, which can be understood as the junction temperatures of the M power semiconductor devices are respectively greater than the first thresholds corresponding to the power semiconductor devices.

[0080] Since the current in the motor and inverter circuit depends on the input differential mode voltage, the common mode voltage has no contribution to the current, and the level of the common mode voltage can determine the conduction duty cycle of the power semiconductor devices of the inverter circuit. Therefore, the conduction duty cycle of the power semiconductor devices of the inverter circuit can be adjusted by adjusting the common mode voltage, thereby achieving adjustment of the loss of the power semiconductor devices of the inverter circuit.

[0081] Optionally, the common mode voltage may cause a change in the on-duty cycle of power semiconductor devices other than the M power semiconductor devices among the N power semiconductor devices while reducing the on-duty cycle of the K power semiconductor devices.

[0082] For example, the common-mode voltage is used to reduce the conduction duty cycle of the K power semiconductor devices and also to increase the conduction duty cycle of the P power semiconductor devices, the P power semiconductor devices being power semiconductor devices other than the M power semiconductor devices among the N power semiconductor devices, and P being an integer greater than 0. It can be understood that the common-mode voltage is used to adjust the conduction duty cycle of the K power semiconductor devices and the P power semiconductor devices, so that the P power semiconductor devices share part of the current that should be borne by the K power semiconductor devices, thereby reducing the loss of the K power semiconductor devices and lowering the junction temperature of the K power semiconductor devices.

[0083] For another example, the common-mode voltage is used to reduce the on-duty ratio of the K power semiconductor devices and also to increase the on-duty ratio of the P power semiconductor devices. In addition, the common-mode voltage is also used to reduce the on-duty ratio of the R power semiconductor devices, the junction temperature of the R power semiconductor devices does not exceed the first threshold, and the R power semiconductor devices belong to the N power semiconductor devices but do not belong to the K power semiconductor devices and the P power semiconductor devices. It can be understood that the common-mode voltage can change the on-duty ratio of one or more power semiconductor devices whose junction temperature does not exceed the first threshold while reducing the on-duty ratio of the K power semiconductor devices and increasing the on-duty ratio of the P power semiconductor devices.

[0084] Optionally, in some implementations, the PWM control device may also directly determine whether the on-duty cycle needs to be adjusted according to the losses of the N power semiconductor devices.

[0085] Optionally, when the inverter circuit adopts an I-type three-level topology structure or a T-type three-level topology structure, the amplitude of the common-mode voltage may be one-fourth of the DC input voltage of the inverter circuit. In this way, the losses of the N power semiconductor devices can be reasonably distributed.

[0086] In some implementations, before injecting the common-mode voltage into the modulated wave, the PWM control device may also determine that the modulation ratio of the inverter circuit is lower than a second threshold, or that the output power factor of the inverter circuit is lower than a third threshold, or that the output frequency of the inverter circuit is lower than a fourth threshold, that is, when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than the first threshold and the modulation ratio of the inverter circuit is lower than the second threshold, or when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than the first threshold and the output power factor of the inverter circuit is lower than the third threshold, or when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than the first threshold and the output frequency of the inverter circuit is lower than the fourth threshold, the common-mode voltage is injected into the modulated wave. That is, only when the modulation ratio of the inverter circuit, the output power factor of the inverter circuit or the output frequency of the inverter circuit is low, the PWM control device will inject the common-mode voltage into the modulated wave so as to adjust the conduction duty cycle of some power semiconductor devices in the inverter circuit. For example, when the motor is in a stalled condition or a low-frequency, high-torque condition, the PWM control device injects a common-mode voltage into the modulation wave, thereby preventing the common-mode voltage from affecting the system under normal conditions.

[0087] Step 230, issuing a control signal based on the modulated wave after the common mode voltage is injected, wherein the control signal is used to control the turning on or off of at least some of the N power semiconductor devices, for example, the control signal controls the turning on or off of the IGBT and / or MOSFET in the inverter circuit.

[0088] Sending a control signal according to the modulation wave after the common mode voltage is injected can change the conduction duty cycle of some power semiconductor devices among the N power semiconductor devices, thereby achieving reasonable distribution of the losses of the N power semiconductor devices.

[0089] In this way, the above technical solution can reasonably distribute the conduction duty cycle of the power semiconductor devices in the inverter circuit by injecting the common-mode voltage into the modulation wave, thereby making the loss distribution of the power semiconductor devices in the inverter circuit more reasonable, helping to reduce the probability of damage to the power semiconductor devices, thereby improving the safety of the system. In addition, since the conduction duty cycle of the power semiconductor devices in the inverter circuit can be distributed by injecting the common-mode voltage into the modulation wave, power semiconductor devices with a smaller current level can be used in the inverter circuit, which helps to reduce the cost of the inverter circuit.

[0090] The PWM control method of the present application is described below with reference to specific examples.

[0091] Example 1

[0092] Assume that the inverter circuit adopts Figure 3 The two-level topology shown in the figure. When the motor stalls at an angle of 90 degrees, the A phase current I a Maximum, the current of phase B and phase C is equal, and I b =I c =-1 / 2I a In this case, S1 and D4 of phase A carry the current of phase A, S2 and D1 of phase A do not pass the current, and the loss is close to zero.

[0093] Figure 4 It is a schematic diagram of the conduction duty cycle of S1 and D4.

[0094] When the motor is stalled, if the on-duty ratio is not adjusted, such as Figure 4 As shown in Figure (a), the conduction duty cycle of S1 and D4 is approximately 0.5.

[0095] If the PWM control device determines that the junction temperature of D4 is too high and the junction temperature of S1 has margin, the PWM control device can inject a positive common-mode voltage (for example, V dc / 4), such as Figure 4 As shown in Figure (b), the on-duty cycle of S1 increases and the on-duty cycle of D4 decreases.

[0096] If the PWM control device determines that the junction temperature of S1 is too high and the junction temperature of D4 has margin, the PWM control device can inject a negative common mode voltage (e.g., -Vdc / 4) into the three-phase modulation waves A, B, and C, such as Figure 4 As shown in Figure (c), the on-duty cycle of S1 decreases and the on-duty cycle of D4 increases.

[0097] In Example 1, for the three-phase two-level topology, the injected common-mode voltage only changes the on-duty cycle of S1 and D4, and does not use power semiconductor devices other than S1 and D4 to carry the current of phase A.

[0098] Figure 4 Only phase A is taken as an example for explanation. The conduction duty cycle adjustment of phases B and C is similar and will not be repeated here.

[0099] Figure 5 It is the simulation waveform of the common-mode voltage injected into the two-level inverter modulation wave. Figure 5 A schematic diagram is shown of injecting a common mode voltage into a two-level space vector pulse width modulation (SVPWM) modulation signal to change the conduction duty cycle of a power semiconductor device. Figure 5In Figure (a), from 0 to 0.02s, the three-phase modulation wave of the inverter is a conventional SVPWM modulation wave, which can be understood as the injected common-mode signal is zero at this time; at 0.02s, the common-mode voltage signal jumps from 0 to 0.3V, and the three-phase modulation wave moves up as a whole. Figure (b) is a schematic diagram of the comparison between the modulation wave of the A-phase bridge arm and the triangular carrier, and the comparison between the two generates the drive signal of the A-phase bridge arm; for the upper tube of the A-phase bridge arm, when the modulation wave Vca is greater than the triangular carrier Vcarr, the upper tube is turned on, and when the modulation wave Vca is less than the triangular carrier Vcarr, the upper tube is turned off. Figure (c) is the A-phase upper tube drive signal generated by the comparison of the modulation wave and the carrier in Figure (b). It can be seen that around 0.02s, the conduction duty cycle of the A-phase upper tube has changed significantly.

[0100] Example 2

[0101] Assume that the inverter circuit adopts Figure 6 The NPC three-level topology shown in the figure. If the output current of the inverter circuit is positive and the output voltage is also positive when the motor is stalled, the current in the inverter circuit is controlled by S1, S2 and D p1 bear.

[0102] Figure 7 S1, S2, D p1 , schematic diagram of the conduction duty cycle of D3 and D4.

[0103] When the motor is stalled, if the on-duty ratio is not adjusted, such as Figure 7 As shown in Figure (a), the on-duty ratio of S1 is relatively small, and the on-duty ratio of S2 is large. p1 The on-duty ratio is also large, and D3 and D4 do not pass current, so S2 and D p1 The loss will be greater.

[0104] If the PWM control device determines S2 and / or D p1 If the junction temperature is too high, the PWM control device can inject a positive common-mode voltage (for example, V dc / 4), such as Figure 7 As shown in Figure (b), D p1 The on-duty cycle of S1 decreases, the on-duty cycle of D p1 The duty ratio of S1 and S2 is changed to about 0.5, and S2 is still normally on. In this way, S1 can bear the D p1 of the current.

[0105] If the PWM control device determines S2 and / or D p1 If the junction temperature is too high, the PWM control device can also inject a negative common-mode voltage (for example, -V dc / 4), such as Figure 7 As shown in Figure (c), S1 does not pass current, Dp1 The on-duty ratio of S1 and S2 decreases, the on-duty ratio of D3 and D4 increases, and D p1 The on-duty ratios of S2, D3 and D4 all change to around 0.5. In this way, D3 and D4 can bear the load of D p1 1. Partial current of S2 and S1.

[0106] Figure 6 and Figure 7 Only one phase is taken as an example for explanation. If the inverter circuit includes more phases, the conduction duty cycle adjustment of other phases is similar and will not be repeated here.

[0107] Example 3

[0108] Assume that the inverter circuit adopts Figure 8 The T-type three-level topology shown in the figure. If the output current of the inverter circuit is positive and the output voltage is also positive when the motor is stalled, the current in the inverter circuit is borne by S1, S3 and D4.

[0109] Fig. 9 It is a schematic diagram of the conduction duty cycle of S1, S3, D2 and D4.

[0110] When the motor is stalled, if the on-duty ratio is not adjusted, such as Fig. 9 As shown in Figure (a), the on-time duty cycle of S1 is relatively small, and the on-time duty cycles of S3 and D4 are also large. D2 does not pass current, so the losses of S3 and D4 will be relatively large.

[0111] If the PWM control device determines that the junction temperature of S3 and / or D4 is too high, the PWM control device may inject a positive common-mode voltage (e.g., V dc / 4), such as Fig. 9 As shown in Figure (b), the on-duty ratio of S3 and D4 decreases, the on-duty ratio of S1 increases, the on-duty ratio of S1, S3 and D4 becomes close to 0.5, and D2 does not pass current. In this way, S1 can bear part of the current of S3 and D4.

[0112] If the PWM control device determines that the junction temperature of S3 and / or D4 is too high, the PWM control device may also inject a negative common mode voltage (e.g., -V dc / 4), such as Fig. 9 As shown in Figure (c), S1 does not pass current, the on-duty ratios of S3 and D4 decrease, the on-duty ratio of D2 increases, and the on-duty ratios of S3, D2, and D4 all change to around 0.5. In this way, D2 can bear part of the current of S1, S3, and D4.

[0113] Figure 8 and Fig. 9Only one phase is used as an example for explanation. If the inverter circuit includes more phases, the conduction duty cycle adjustment of other phases is similar and will not be described in detail here. Figures 2 to 9 , describes in detail the PWM control method provided by the present application, and will be combined with Fig.10 and Fig.11 , describes in detail the device embodiment of the present application. It can be understood that in order to realize the functions in the above embodiments, Fig.10 or Fig.11 The device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0114] Fig.10 and Fig.11 The following is a schematic diagram of the structure of possible devices provided by the embodiments of the present application. These devices can be used to implement the functions of the PWM control device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0115] like Fig.10 As shown, the device 900 includes an acquisition unit 910 and a processing unit 920 .

[0116] The acquisition unit 910 is used to acquire the junction temperature of N power semiconductor devices in the inverter circuit, where N is an integer greater than 1.

[0117] The processing unit 920 is used to inject a common-mode voltage into the modulation wave when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than a first threshold value, and the modulation wave is used to generate a signal for controlling the turning on or off of at least some of the N power semiconductor devices, and the common-mode voltage is used to reduce the conduction duty cycle of K power semiconductor devices among the M power semiconductor devices, where K is an integer greater than 0 and less than or equal to M, and M is an integer greater than 0 and less than or equal to N.

[0118] The processing unit 920 is further used to send a control signal according to the modulated wave after the common mode voltage is injected, and the control signal is used to control the opening or closing of at least part of the power semiconductor devices.

[0119] Optionally, the common-mode voltage is also used to increase a conduction duty cycle of P power semiconductor devices, where the P power semiconductor devices are power semiconductor devices in the N power semiconductor devices other than the M power semiconductor devices, and P is an integer greater than 0.

[0120] Optionally, the processing unit 920 is also used to: when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than the first threshold and the modulation ratio of the inverter circuit is lower than a second threshold, inject the common-mode voltage into the modulated wave; or, when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than the first threshold and the output power factor of the inverter circuit is lower than a third threshold, inject the common-mode voltage into the modulated wave; or, when the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than the first threshold and the output frequency of the inverter circuit is lower than a fourth threshold, inject the common-mode voltage into the modulated wave.

[0121] Optionally, the N power semiconductor devices correspond to N first thresholds one by one, and the junction temperature of each power semiconductor device in the M power semiconductor devices is greater than the first threshold corresponding to the power semiconductor device. In other words, the junction temperature of the M power semiconductor devices is greater than the first threshold, which can be understood as that the junction temperatures of the M power semiconductor devices are respectively greater than the first threshold corresponding to the power semiconductor device. The above-mentioned N first thresholds may be the same or different. For example, the first thresholds of power semiconductor devices of the same model may be the same, and the first thresholds of power semiconductor devices of different types or models may be different.

[0122] Optionally, the inverter circuit is a single-phase or multi-phase inverter circuit.

[0123] Optionally, the inverter circuit adopts a two-level topology structure or a multi-level topology structure.

[0124] Optionally, when the inverter circuit adopts an I-type three-level topology structure or a T-type three-level topology structure, the amplitude of the common-mode voltage is one quarter of a DC input voltage of the inverter circuit.

[0125] A more detailed description of the acquisition unit 910 and the processing unit 920 can be directly obtained by referring to the relevant description in the above method embodiment, and will not be repeated here.

[0126] like Fig.11 As shown, the device 1000 includes a processor 1010 and an interface circuit 1020. The processor 1010 and the interface circuit 1020 are coupled to each other. It can be understood that the interface circuit 1020 can be a transceiver or an input-output interface. Optionally, the device 1000 may also include a memory 1030 for storing instructions executed by the processor 1010 or storing input data required by the processor 1010 to execute instructions or storing data generated after the processor 1010 executes instructions.

[0127] When the apparatus 1000 is used to implement the method described above, the processor 1010 is used to implement the function of the processing unit 920 , and the interface circuit 1020 is used to implement the function of the acquisition unit 910 .

[0128] An embodiment of the present application also provides a motor controller, comprising any one of the above-mentioned PWM control devices.

[0129] An embodiment of the present application also provides a chip, which obtains instructions and executes the instructions to implement the above method.

[0130] Optionally, as an implementation manner, the chip includes a processor and a data interface, and the processor reads instructions stored in the memory through the data interface to execute the above method.

[0131] Optionally, as an implementation manner, the chip may further include a memory, in which instructions are stored, and the processor is used to execute the instructions stored in the memory. When the instructions are executed, the processor is used to execute the above method.

[0132] An embodiment of the present application also provides an electric drive system, comprising any one of the above-mentioned PWM control devices, or any one of the above-mentioned motor controllers, or any one of the above-mentioned chips.

[0133] An embodiment of the present application also provides a computer-readable storage medium, which stores instructions, and the instructions are used in the method in the above method embodiment.

[0134] The embodiment of the present application also provides a computer program product including instructions, wherein the instructions are used to implement the method in the above method embodiment.

[0135] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0136] The memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0137] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0138] It is understood that the various numbers involved in the embodiments of the present application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. The size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic.

[0139] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. It should be understood that the above is for illustration, and the examples above are only to help those skilled in the art understand the embodiments of the present application, rather than to limit the application embodiments to the specific numerical values ​​or specific scenarios illustrated. It is obvious that various equivalent modifications or changes can be made by those skilled in the art according to the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

[0140] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0141] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0142] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0143] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0144] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A PWM control method, characterized in that: The method comprises: Obtaining the junction temperature of N power semiconductor devices in the inverter circuit, where N is an integer greater than 1; When the junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than a first threshold, and the modulation ratio of the inverter circuit is lower than a second threshold, or the output power factor of the inverter circuit is lower than a third threshold, injecting a common-mode voltage into the modulation wave, the modulation wave is used to generate a signal for controlling the turning on or off of at least some of the N power semiconductor devices, and the common-mode voltage is used to reduce the conduction duty cycle of K power semiconductor devices among the M power semiconductor devices, where K is an integer greater than 0 and less than or equal to M, and M is an integer greater than 0 and less than or equal to N; The inverter circuit adopts a two-level topology structure or a multi-level topology structure. When the inverter circuit adopts an I-type three-level topology structure or a T-type three-level topology structure, the amplitude of the common-mode voltage is one quarter of the DC input voltage of the inverter circuit; A control signal is issued according to the modulated wave after the common mode voltage is injected, and the control signal is used to control the turning on or off of at least part of the power semiconductor devices.

2. The method according to claim 1, characterized in that The common mode voltage is also used to increase the conduction duty cycle of P power semiconductor devices, where the P power semiconductor devices are power semiconductor devices other than the M power semiconductor devices among the N power semiconductor devices, and P is an integer greater than 0.

3. The method according to claim 1 or 2, characterized in that: When the junction temperatures of M power semiconductor devices among the N power semiconductor devices are greater than the first threshold and the output frequency of the inverter circuit is lower than a fourth threshold, the common mode voltage is injected into the modulated wave.

4. The method according to claim 1 or 2, characterized in that: The N power semiconductor devices correspond one by one to the N first thresholds, and the junction temperature of each power semiconductor device in the M power semiconductor devices is greater than the first threshold corresponding to the power semiconductor device.

5. The method according to claim 1 or 2, characterized in that: The inverter circuit is a single-phase or multi-phase inverter circuit.

6. A PWM control device, characterized in that: The device comprises: An acquisition unit, used to acquire the junction temperature of N power semiconductor devices in the inverter circuit, where N is an integer greater than 1; a processing unit, configured to inject a common-mode voltage into a modulation wave when a junction temperature of M power semiconductor devices among the N power semiconductor devices is greater than a first threshold, and a modulation ratio of the inverter circuit is lower than a second threshold, or an output power factor of the inverter circuit is lower than a third threshold, wherein the modulation wave is used to generate a signal for controlling the turning on or off of at least some of the N power semiconductor devices, and the common-mode voltage is used to reduce a conduction duty cycle of K power semiconductor devices among the M power semiconductor devices, where K is an integer greater than 0 and less than or equal to M, and M is an integer greater than 0 and less than or equal to N; The inverter circuit adopts a two-level topology structure or a multi-level topology structure. When the inverter circuit adopts an I-type three-level topology structure or a T-type three-level topology structure, the amplitude of the common-mode voltage is one quarter of the DC input voltage of the inverter circuit; The processing unit is further used to send a control signal according to the modulated wave after the common mode voltage is injected, and the control signal is used to control the opening or closing of at least part of the power semiconductor devices.

7. The device according to claim 6, characterized in that The common mode voltage is also used to increase the conduction duty cycle of P power semiconductor devices, where the P power semiconductor devices are power semiconductor devices other than the M power semiconductor devices among the N power semiconductor devices, and P is an integer greater than 0.

8. The device according to claim 6 or 7, characterized in that The processing unit is specifically used for: When the junction temperatures of M power semiconductor devices among the N power semiconductor devices are greater than the first threshold and the output frequency of the inverter circuit is lower than a fourth threshold, the common mode voltage is injected into the modulated wave.

9. The device according to claim 6 or 7, characterized in that The N power semiconductor devices correspond one by one to the N first thresholds, and the junction temperature of each power semiconductor device in the M power semiconductor devices is greater than the first threshold corresponding to the power semiconductor device.

10. The device according to claim 6 or 7, characterized in that The inverter circuit is a single-phase or multi-phase inverter circuit.

11. A PWM control device, characterized in that: include: A processor, configured to execute computer instructions stored in a memory so that the device performs: a method as claimed in any one of claims 1 to 5.

12. A motor controller, characterized in that: The method comprises the PWM control device as claimed in any one of claims 6 to 10.

13. A chip, characterized in that: The chip comprises a processor connected to a memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the chip executes the method as claimed in any one of claims 1 to 5.

14. An electric drive system, characterized in that: It comprises the PWM control device as claimed in any one of claims 6 to 11, or comprises the motor controller as claimed in claim 12, or comprises the chip as claimed in claim 13.

15. A computer storage medium, characterized in that A computer program is stored thereon, and when the computer program is executed by a computer, the computer is caused to implement the method according to any one of claims 1 to 5.

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