Write voltage generator for non-volatile memory

Abstract

A write voltage generator for use in a non-volatile memory. The write voltage generator is connected to a magnetoresistive random access memory. During a write operation, the write voltage generator provides a write voltage. According to the write voltage, the storage state of a selected memory cell in a write path in the magnetoresistive random access memory can be changed accordingly. The write voltage generator includes: a temperature compensation circuit and a process corner compensation circuit. The temperature compensation circuit generates a transition voltage according to an ambient temperature, and the higher the ambient temperature, the lower the transition voltage. Furthermore, the process corner compensation circuit receives the transition voltage and generates the write voltage.

Description

Technical Field

[0001] The present invention relates to a write voltage generator, and in particular to a write voltage generator used in a non-volatile memory. Background Art

[0002] As we all know, non-volatile memory can continue to store data even when the power is turned off. There are many types of non-volatile memory. For example, magnetoresistive random access memory (MRAM memory) and resistive random access memory (RRAM memory or ReRAM memory) are both programmable-erasable non-volatile memory.

[0003] Please refer to Figure 1 , which is a schematic diagram of a conventional MRAM memory cell. The MRAM memory cell 110 includes a switch transistor Ms and a storage element 120, wherein the storage element 120 is also called a magnetic tunnel junction (MTJ).

[0004] The MRAM memory cell 110 has three terminals A, B, and S, wherein the terminal S is a control terminal. A first drain / source terminal of the switch transistor Ms is connected to the node C, a second drain / source terminal of the switch transistor Ms is connected to the terminal B, and a gate terminal of the switch transistor Ms is connected to the terminal S. The switch transistor Ms is an NMOS transistor.

[0005] The memory element 120 includes a stacked free layer 126, an isolation layer 124, and a pin layer 122. The pin layer 122 of the memory element 120 is connected to the node C, and the free layer 126 of the memory element 120 is connected to the terminal A.

[0006] Basically, when the fixed layer 122 and the free layer 126 have the same magnetization direction, the memory element 120 has a smaller impedance (e.g., 2.0K ohms), which can be regarded as the first storage state of the MRAM memory cell 110, also known as the low impedance state. When the fixed layer 122 and the free layer 126 have different magnetization directions, the memory element 120 has a larger impedance (e.g., 4.0K ohms), which can be regarded as the second storage state of the MRAM memory cell 110, also known as the high impedance state. Therefore, during a write operation, when different write voltages are provided to the memory element 120, the MRAM memory cell 110 can be controlled to be in the first storage state or the second storage state.

[0007] Of course, in Figure 1 In the MRAM memory cell 110 , the fixed layer 122 of the storage element 120 may also be connected to the terminal A, and the free layer 126 of the storage element 120 may be connected to the node C.

[0008] Please refer to Figure 2A and Figure 2B , which is a schematic diagram of bias voltages for the MRAM memory cell to be in the first storage state and the second storage state during the write operation. Basically, during the write operation, the MRAM memory cell 110 can be selectively controlled to be in the first storage state or the second storage state by using a write voltage generator to provide different write voltages to the MRAM memory cell 110.

[0009] like Figure 2A As shown, a first write voltage Vw1 is provided to terminal A, a ground voltage Vss is provided to terminal B, and a turn-on voltage (Von) is provided to terminal S to turn on the switch transistor Ms. The first write voltage Vw1 is greater than the ground voltage Vss, which is 0V.

[0010] When the switch transistor Ms is turned on and the voltage difference Vac across the storage element 120 reaches a first transition voltage, the MRAM memory cell 110 changes to a first storage state, ie, a low impedance state.

[0011] like Figure 2BAs shown, a second write voltage Vw2 is provided to terminal B, a ground voltage Vss is provided to terminal A, and a turn-on voltage (Von) is provided to terminal S to turn on the switch transistor Ms. The second write voltage Vw2 is greater than the ground voltage Vss, and the ground voltage Vss is 0V.

[0012] When the switch transistor Ms is turned on and the voltage difference Vca across the storage element 120 reaches the second transition voltage, the MRAM memory cell 110 changes to the second storage state, ie, the high impedance state.

[0013] Please refer to Figure 2C , which shows the relationship between the transition voltage and the impedance (Rmtj) of the storage element at different temperatures. At room temperature (e.g., 25°C), in order to change the MRAM memory cell 110 to the first storage state, the voltage difference (voltage difference) Vac received by the two ends of the storage element 120 must be greater than 0.5V to change the state. In other words, the first transition voltage for converting from the second storage state to the first storage state is 0.5V.

[0014] In addition, in order to change the MRAM memory cell 110 to the second storage state, the voltage difference Vac received by the two ends of the storage element 120 must be less than -0.4V (that is, Vca must be greater than 0.4V) before the state can be changed. In other words, the second transition voltage from the first storage state to the second storage state is -0.4V.

[0015] Furthermore, the lower the temperature, the higher the absolute value of the transition voltage of the memory element 120. Conversely, the higher the temperature, the lower the absolute value of the transition voltage of the memory element 120. For example, at -40°C, the first transition voltage is greater than 0.5V, and the second transition voltage is less than -0.4V. At 85°C, the first transition voltage is less than 0.5V, and the second transition voltage is greater than -0.4V.

[0016] In addition, by Figure 2C It can be seen that when the absolute value of the voltage difference received by the two ends of the storage element 120 is greater than the breakdown voltage (Vbk), the storage element 120 will be permanently damaged and the storage element 120 can no longer change the storage state. The breakdown voltage Vbk is 0.54V.

[0017] Since there is still a switch transistor Ms in the MRAM memory cell 110, and the switch transistor Ms can be regarded as a load. During the write operation, a voltage drop will be generated at the two ends of the switch transistor Ms. Therefore, during the write operation, the first write voltage Vw1 supplied by the write voltage generator (not shown) needs to be greater than the first transition voltage. Similarly, the second write voltage Vw2 supplied by the write voltage generator (not shown) must also be greater than the second transition voltage. Taking 25°C as an example, the first write voltage Vw1 needs to be greater than 0.5V, and the second write voltage Vw2 needs to be greater than 0.4V.

[0018] In addition, when multiple memory cells are combined into a memory cell array, the write path will include more loads. Figure 3A , which shows an MRAM memory composed of MRAM memory cells. The MRAM memory includes a memory cell array 300, a bit line multiplexer 310 and a source line multiplexer 320. The MRAM memory is a non-volatile memory.

[0019] The memory cell array 300 includes m×n MRAM memory cells c11-cmn, each of which has the same structure as Figure 1 , I will not go into details here.

[0020] The control terminals of the n memory cells c11-c1n in the first column are connected to the word line WL1, the first terminals of the n memory cells c11-c1n in the first column are connected to the corresponding bit lines BL1-BLn, and the second terminals of the n memory cells c11-c1n in the first column are connected to the corresponding source lines SL1-SLn. The control terminals of the n memory cells c21-c2n in the second column are connected to the word line WL2, the first terminals of the n memory cells c21-c21n in the second column are connected to the corresponding bit lines BL1-BLn, and the second terminals of the n memory cells c11-c1n in the second column are connected to the corresponding source lines SL1-SLn, and so on. The control terminals of the n memory cells cm1-cmn in the mth column are connected to the word line WLm, the first terminals of the n memory cells cm1-cmn in the mth column are connected to the corresponding bit lines BL1-BLn, and the second terminals of the n memory cells c11-c1n in the mth column are connected to the corresponding source lines SL1-SLn.

[0021] The bit line multiplexer 310 includes n selection transistors mb1-mbn. The first drain / source terminals of the n selection transistors mb1-mbn are connected to the first voltage receiving terminal T1, the second drain / source terminals of the n selection transistors mb1-mbn are connected to the corresponding bit lines BL1-BLn, and the gate terminals of the n selection transistors mb1-mbn receive corresponding bit line selection signals sb1-sbn.

[0022] The source line multiplexer 320 includes n selection transistors ms1-msn. The first drain / source terminals of the n selection transistors ms1-msn are connected to the corresponding source lines SL1-SLn, the second drain / source terminals of the n selection transistors ms1-msn are connected to the second voltage receiving terminal T2, and the gate terminals of the n selection transistors ms1-msn receive corresponding source line selecting signals ss1-ssn.

[0023] In addition, the bit line multiplexer 310 and the source line multiplexer 320 are not limited to Figure 3A More complex bit line multiplexers and source line multiplexers can also be designed using more transistors for use in MRAM memory.

[0024] During the write operation, only one of the n word lines WL1 to WL2 operates, while the others do not operate. Only one of the n bit line selection signals sb1 to sbn operates, while the others do not operate. Only one of the n source line selection signals ss1 to ssn operates, while the others do not operate.

[0025] Therefore, according to the activated word line, bit line selection signal and source line selection signal, a selected memory cell can be determined in the memory cell array 300. For example, when the word line WL1, the bit line selection signal sb1 and the source line selection signal ss1 are activated, the memory cell c11 is the selected memory cell. Furthermore, providing a specific voltage to the two voltage receiving terminals T1 and T2 can control the selected memory cell to be in the first storage state or the second storage state.

[0026] The following description is made by taking memory cell c11 as the selected memory cell. Figure 3B and Figure 3C , which is a schematic diagram of bias voltage for performing a write operation on a selected memory cell to achieve a first storage state and a second storage state.

[0027] like Figure 3BAs shown, a first write voltage Vw1 is provided to the first voltage receiving terminal T1, a ground voltage Vss is provided to the second voltage receiving terminal T2, and an on voltage (Von) is provided to the word line WL1 to activate the word line WL1. The first write voltage Vw1 is greater than the ground voltage Vss, and the ground voltage Vss is 0V.

[0028] When the bit line selection signal sb1 and the source line selection signal ss1 receive the on voltage (Von) and act, a write path is formed between the first voltage receiving terminal T1 and the second voltage receiving terminal T2. The write path includes: the bit line multiplexer 310, the bit line BL1, the selected memory cell c11, the source line SL1 and the source line multiplexer 320. When the voltage difference Vac across the storage element 120 in the selected memory cell c11 reaches the first transition voltage, the selected memory cell c11 changes to the first storage state, that is, the low impedance state.

[0029] like Figure 3C As shown, a ground voltage Vss is provided to the first voltage receiving terminal T1, a second write voltage Vw2 is provided to the second voltage receiving terminal T2, and an on voltage (Von) is provided to the word line WL1 to activate the word line WL1. The second write voltage Vw2 is greater than the ground voltage Vss, and the ground voltage Vss is 0V.

[0030] When the bit line selection signal sb1 and the source line selection signal ss1 receive the on voltage (Von) and operate, a write path is formed between the first voltage receiving terminal T1 and the second voltage receiving terminal T2. The write path includes: the bit line multiplexer 310, the bit line BL1, the selected memory cell c11, the source line SL1 and the source line multiplexer 320. When the voltage difference Vca across the storage element 120 in the selected memory cell c11 reaches the second transition voltage, the selected memory cell c11 changes to the second storage state, that is, the high impedance state.

[0031] As can be seen from the above description, the write path includes more loads, such as switch transistors mb1, Ms1, and ms1, in addition to the storage element 120. Therefore, the first write voltage Vw1 supplied by the write voltage generator (not shown) needs to be greater than the first transition voltage, and the second write voltage Vw2 supplied by the write voltage generator (not shown) also needs to be greater than the second transition voltage.

[0032] However, since the first transition voltage is very close to the breakdown voltage Vbk, if the first write voltage Vw1 is set too high, the voltage received by the two ends of the storage element 120 may be greater than the breakdown voltage Vbk and may be damaged. On the contrary, if the first write voltage Vw1 is set too low, the storage element 120 may fail to successfully switch to the first storage state.

[0033] Similarly, if the second programming voltage Vw2 is set too high, the voltage received by the two terminals of the memory element 120 may be greater than the breakdown voltage Vbk and may be damaged. Conversely, if the second programming voltage Vw2 is set too low, the memory element 120 may fail to successfully switch to the second storage state.

[0034] In addition, since the two transition voltages of the memory element 120 change with the ambient temperature, the resistance values ​​of the switch transistors mb1, Ms1, and ms1 in the write path change with the process corner. For example, when the switch transistor belongs to a "slow corner (Scorner)" transistor, its internal resistance is larger. When the switch transistor is classified as a "fast corner (F corner)" transistor, its internal resistance is smaller.

[0035] From the above description, it can be seen that it is very difficult to design a programming voltage generator that can generate an appropriate programming voltage according to the change of ambient temperature and the difference of process corners. Summary of the invention

[0036] The present invention relates to a write voltage generator coupled to a memory cell array. The write voltage generator provides a write voltage during a write action to change the storage state of a selected memory cell in a write path in the memory cell array. The write voltage generator includes: a temperature compensation circuit, the temperature compensation circuit generates a transition voltage according to an ambient temperature, wherein the higher the ambient temperature, the lower the transition voltage; and a process corner compensation circuit, including a current mirror, a storage element equivalent circuit and a write path equivalent circuit. The current mirror receives the transition voltage, the storage element equivalent circuit is connected between a first end of the current mirror and a ground end, a second end of the current mirror is connected to a first node, the write path equivalent circuit is connected between the first node and the ground end, and the write voltage is output from the first node.

[0037] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic diagram of a known MRAM memory cell;

[0039] Figure 2A and Figure 2B A schematic diagram of bias voltages for a MRAM memory cell to be in a first storage state and a second storage state during a write operation;

[0040] Figure 2CA schematic diagram of the relationship between the transition voltage and impedance of a storage element at different temperatures;

[0041] Figure 3A An MRAM memory composed of MRAM memory cells;

[0042] Figure 3B and Figure 3C A schematic diagram of bias voltages for performing a write operation on a selected memory cell to achieve a first storage state and a second storage state;

[0043] Figure 4 The present invention is applied to a write voltage generator of an MRAM memory;

[0044] Figure 5A and Figure 5B is a first example of a temperature compensation circuit and a graph showing the relationship between its transition voltage and temperature;

[0045] Figure 5C and Figure 5D is a second example of a temperature compensation circuit and a graph showing the relationship between its transition voltage and temperature;

[0046] Figure 5E and Fig. 5F is a third example of a temperature compensation circuit and a graph showing the relationship between its transition voltage and temperature;

[0047] Fig. 6A A first example of a process corner compensation circuit;

[0048] Figure 6B A second example of a process corner compensation circuit can provide a first write voltage;

[0049] Figure 6C A third example of a process corner compensation circuit can provide a first write voltage;

[0050] Fig.6D A fourth example of a process corner compensation circuit can provide a second write voltage; and

[0051] Fig. 6E As a fifth example of the process corner compensation circuit, a second programming voltage may be provided.

[0052]

Explanation of symbols

[0053] 110:MRAM memory cell

[0054] 120: Storage element

[0055] 122: Fixed layer

[0056] 124: Barrier layer

[0057] 126: Free Layer

[0058] 300: memory cell array

[0059] 310: Bit line multiplexer

[0060] 320: Source Line Multiplexer

[0061] 400: write voltage generator

[0062] 410, 410a, 410b, 410c: temperature compensation circuit

[0063] 420, 420a, 420b, 420c, 420d, 420e: process corner compensation circuit

[0064] 430:MRAM memory

[0065] 516, 532, 542, 552, 642: Operational amplifier

[0066] 522: first voltage generator

[0067] 524: Second voltage generator

[0068] 530: Lower voltage limiting circuit

[0069] 540: Buffer circuit

[0070] 550: Upper voltage limit circuit

[0071] 560:CTAT Circuit

[0072] 610a, 610b, 610c, 610d, 610e: current mirror

[0073] 620a, 620b, 620c, 620d, 620e: storage element equivalent circuit

[0074] 630a, 630b, 630c, 630d, 630e: write path equivalent circuit

[0075] 652: First reference storage element

[0076] 662: Reference bit line multiplexer

[0077] 664b, 664c, 664d, 664e: Reference memory cells

[0078] 665: Second reference storage element

[0079] 666: Reference Source Line Multiplexer DETAILED DESCRIPTION

[0080] Please refer to Figure 4, which shows a write voltage generator of the present invention applied to an MRAM memory. The write voltage generator 400 includes: a temperature compensation circuit 410 and a process corner compensation circuit 420. The write voltage generator 400 is connected to the MRAM memory 430, and the write voltage generator 400 can provide a write voltage Vw to the MRAM 430 during a write operation. The structure of the MRAM memory 430 is similar to Figure 3A The write voltage Vw may be a first write voltage (eg Figure 3B 4), is used to change the selected memory cell in the MRAM memory 430 from the second storage state to the first storage state. Alternatively, the write voltage Vw may be a second write voltage (such as Figure 3C Vw2 in ), is used to change the selected memory cell in the MRAM memory 430 from the first storage state to the second storage state.

[0081] According to an embodiment of the present invention, the temperature compensation circuit 410 generates a transition voltage Vts according to the ambient temperature, and the higher the ambient temperature, the lower the transition voltage Vts generated by the temperature compensation circuit 410. Furthermore, the process corner compensation circuit 420 receives the transition voltage Vts and generates a write voltage Vw. The detailed structures of the temperature compensation circuit 410 and the process corner compensation circuit 420 are described in detail below.

[0082] It can be seen from the storage element characteristics of the MRAM memory cell that when the ambient temperature is higher, the transition voltage of the storage element will decrease. When the ambient temperature is lower, the transition voltage of the storage element will increase. Therefore, the transition voltage generated by the temperature compensation circuit 410 needs to meet the above characteristics.

[0083] For example, the temperature compensation circuit 410 may be a negative temperature coefficient circuit (complementary to absolute temperature circuit, hereinafter referred to as CTAT circuit), which may generate a voltage V ctat As the transition voltage Vts. In other embodiments, the temperature compensation circuit 410 may include a CTAT circuit and an auxiliary circuit, so that the temperature compensation circuit 410 generates the transition voltage Vts.

[0084] Please refer to Figure 5A and Figure 5B , which shows a first example of a temperature compensation circuit and a relationship diagram between its transition voltage and temperature. The temperature compensation circuit 410a is implemented by a CTAT circuit.

[0085] The temperature compensation circuit 410a is composed of PMOS transistors M1-M3, PNP bipolar junction transistors (BJT) Q1, Q2, four resistors R1, R2 1 , R2 2 , R3 and an operational amplifier 516. The resistance value of the resistor R1 is r1, and the resistance value of the resistor R2 is 1 With R2 2 The resistance value of resistor R3 is r2, and the resistance value of resistor R3 is r3. Furthermore, PMOS transistors M1-M3 form a current mirror. In this example, PMOS transistors M1-M3 have the same aspect ratio (W / L). Among them, the gate terminals of PMOS transistors M1-M3 are connected to each other, the first drain / source terminals of PMOS transistors M1-M3 are connected to the supply voltage Vdd, and the second drain / source terminals of PMOS transistors M1-M3 can output currents of the same magnitude.

[0086] In addition, the output terminal of the operational amplifier 516 is connected to the gate terminals of the PMOS transistors M1 to M3, the second drain / source terminal of the PMOS transistor M1 is connected to the positive input terminal of the operational amplifier 516, the second drain / source terminal of the PMOS transistor M2 is connected to the negative input terminal of the operational amplifier 516, and the resistor R3 is connected between the second drain / source terminal of the PMOS transistor M3 and the ground terminal GND. The second drain / source terminal of the PMOS transistor M3 can generate a voltage V as the output terminal of the CTAT circuit. ctat , and the voltage V ctat is the transition voltage Vts (that is, V ctat =Vts).

[0087] Furthermore, the area of ​​the PNP bipolar transistor Q1 is N times the area of ​​the PNP bipolar transistor Q2. The base and collector of the PNP bipolar transistors Q1 and Q2 are connected to the ground terminal GND, so that the PNP bipolar transistors Q1 and Q2 form a diode connection. Furthermore, the negative input terminal of the operational amplifier 516 is connected to the emitter of the PNP bipolar transistor Q2, and a resistor R2 is connected between the negative input terminal of the operational amplifier 516 and the ground terminal GND. 1 A resistor R1 is connected between the positive input terminal of the operational amplifier 516 and the emitter of the PNP bipolar transistor Q1, and a resistor R2 is connected between the positive input terminal of the operational amplifier 516 and the ground terminal GND. 2 .

[0088] Basically, when the operational amplifier 516 has infinite gain, the negative input voltage V- With the positive input voltage V + will be equal. Therefore, r1×I1+V EB1 =V EB2 .

[0089] Since Q1 and Q2 form a diode connection and the area of ​​Q1 is N times the area of ​​Q2, and Then we can deduce V BE1 =V T ln(I1 / N·I s ) and V BE2 =V T ln(I1 / I s ). Among them, I s is the saturation current of Q2, V T is the thermal voltage.

[0090] Therefore, we can obtain I1 = V T ln(N) / r1,I2=V EB2 / r2,V ctat =Vts=(r3 / r2)V EB2 +ln(N)(r3 / r1)V T .

[0091] From the above voltage V ctat From the expression, we can see that the voltage V ctat (i.e., the transition voltage Vts) is equal to the base-emitter voltage V generated by the base-emitter voltage generator. BE2 Multiply by the first constant (r3 / r2) plus the thermal voltage V generated by the thermal voltage generator T Multiply by a second constant (ln(N)(r3 / r1)).

[0092] like Figure 5B As shown, due to V EB2 =I2×r2 has a negative temperature coefficient, and the base-emitter voltage V BE2 has a negative temperature coefficient, so the first constant (r3 / r2) is multiplied by V EB2 The characteristic curve I will decrease as the absolute temperature increases. In addition, the first constant (r3 / r2) can determine the slope of the characteristic curve I. Similarly, due to the thermal voltage V Thas a positive temperature coefficient, so the second constant (ln(N)(r3 / r1)) is multiplied by the thermal voltage V T The characteristic curve II will rise as the absolute temperature rises. In addition, the second constant (ln(N)(r3 / r1)) can determine the slope of the characteristic curve II. Furthermore, after properly adjusting the first constant and the second constant, the voltage V ctat characteristic curve III, and the voltage V ctat Decreases as the ambient temperature increases.

[0093] Basically, the present invention is not limited to Figure 5A The CTAT circuit of FIG. 4 is used as the temperature compensation circuit 410a. Those skilled in the art may also use CTAT circuits of other structures as the temperature compensation circuit.

[0094] Please refer to Figure 5C and Figure 5D , which shows a second example of a temperature compensation circuit and a graph showing the relationship between its transition voltage and temperature. The temperature compensation circuit 410b is implemented by another CTAT circuit.

[0095] The temperature compensation circuit 410b includes a first voltage generator 522 and a second voltage generator 524. The first voltage generator 522 generates a first voltage V1 with a negative temperature coefficient, and the second voltage generator 524 generates a second voltage V2 with a positive temperature coefficient. Furthermore, the first voltage V1 multiplied by the first constant c1 plus the second voltage V2 multiplied by the second constant c2 is the voltage V ctat That is, the output terminal of the temperature compensation circuit 410b can generate a voltage V ctat , and the voltage V ctat =c1×V1+c2×V2.

[0096] Taking the CTAT circuit as an example, the first voltage generator 522 can be regarded as a base-emitter voltage generator, and the first voltage V1 can be regarded as a base-emitter voltage of a bipolar transistor (eg, V EB2 ). The second voltage generator 524 can be regarded as a thermal voltage generator, and the second voltage V2 can be regarded as a thermal voltage V T .

[0097] like Figure 5D As shown, I is the characteristic curve of c1×V1, II is the characteristic curve of c2×V2, and III is the voltage V ctatSince the first voltage V1 has a negative temperature coefficient, the characteristic curve I of c1×V1 will decrease as the absolute temperature rises. In addition, the first constant c1 can determine the slope of the characteristic curve I. Similarly, since the second voltage V2 has a positive temperature coefficient, the characteristic curve II of c2×V2 will increase as the absolute temperature rises. In addition, the second constant c2 can determine the slope of the characteristic curve II. In other words, after properly adjusting the first constant c1 and the second constant c2, the voltage V ctat characteristic curve III, and the voltage V ctat Decreases as the ambient temperature increases.

[0098] Please refer to Figure 5E and Fig. 5F , which shows a third example of a temperature compensation circuit and a graph showing the relationship between its transition voltage and temperature. The temperature compensation circuit 410c includes a CTAT circuit 560, a buffering circuit 540, a lower voltage limiting circuit 530, and an upper voltage limiting circuit 550. The CTAT circuit 560 can be Figure 5A or Figure 5C The CTAT circuit shown will not be described in detail here.

[0099] The voltage output terminal of the CTAT circuit 560 is connected to the buffer circuit 540. The buffer circuit 540 includes an operational amplifier 542, the positive input terminal of the operational amplifier 542 is connected to the voltage output terminal of the CTAT circuit 542 to receive the voltage Vctat, the negative input terminal of the operational amplifier 542 is connected to the output terminal of the operational amplifier 542, and the output terminal of the operational amplifier 542 is connected to the node X.

[0100] The lower voltage limit circuit 530 includes an operational amplifier 532 and a PMOS transistor Mp1. The input terminal of the lower voltage limit circuit 530 receives the lower voltage V L The output terminal of the lower voltage limit circuit 530 is connected to the node X. The negative input terminal of the operational amplifier 532 receives a lower voltage V L , the positive input terminal of the operational amplifier 532 is connected to the node X. The first drain / source terminal of the PMOS transistor Mp1 receives the supply voltage Vdd, the gate terminal of the PMOS transistor Mp1 is connected to the output terminal of the operational amplifier 532, and the second drain / source terminal of the PMOS transistor Mp1 is connected to the node X.

[0101] The upper limit voltage limiting circuit 550 includes an operational amplifier 552 and an NMOS transistor Mn1. The input terminal of the upper limit voltage limiting circuit 550 receives the upper limit voltage V H The output terminal of the upper voltage limit circuit 550 is connected to the node X. The negative input terminal of the operational amplifier 552 receives an upper voltage V H , the positive input terminal of the operational amplifier 552 is connected to the node X. The first drain / source terminal of the NMOS transistor Mn1 is connected to the ground terminal GND, the gate terminal of the NMOS transistor Mn1 is connected to the output terminal of the operational amplifier 552, and the second drain / source terminal of the NMOS transistor Mn1 is connected to the node X. Among them, the upper limit voltage V H Greater than the lower limit voltage V L .

[0102] Depend on Fig. 5F It can be seen that the transition voltage Vts provided by the temperature compensation circuit 410c will be limited to the upper limit voltage V H With the lower limit voltage V L According to an embodiment of the present invention, the upper limit voltage V in the upper limit voltage limiting circuit 550 is H It can be set to be lower than the breakdown voltage Vbk of the storage element (eg, 0.53 V). Therefore, the voltage received by the storage element in the MRAM memory cell can be prevented from exceeding the breakdown voltage Vbk, thereby ensuring that the storage element in the MRAM memory cell will not be damaged.

[0103] In other embodiments, the temperature compensation circuit 410c may also use only one of the two voltage limiting circuits 530 and 550. For example, the temperature compensation circuit 410c only uses the upper voltage limiting circuit 550 to limit the transition voltage Vts from exceeding the breakdown voltage Vbk.

[0104] Please refer to Fig. 6A , which is a first example of a process corner compensation circuit. The process corner compensation circuit 420a includes a current mirror 610a, an equivalent circuit of a storage element 620a and an equivalent circuit of a write path 630a.

[0105] The current mirror 610a receives the transition voltage Vts or the voltage V output by the temperature compensation circuit. ctatThe current mirror 610a includes a first end and a second end. The storage element equivalent circuit 620a is connected between the first end and the ground end GND. Furthermore, the second end is connected to the node Y, and the write path equivalent circuit 630a is connected between the node Y and the ground end GND. The write voltage Vw is output from the node Y.

[0106] According to an embodiment of the present invention, the current mirror 610a receives the transition voltage Vts or the voltage V ctat , and the transition voltage Vts or voltage V ctat Therefore, the storage element equivalent circuit 620a is provided to the first terminal according to the transition voltage Vts or the voltage V ctat To generate input current Ix.

[0107] Furthermore, according to the input current Ix, the second end of the current mirror 610a generates a mirror current Iy and flows to the write path equivalent circuit 630a. Therefore, the mirror current Iy flows through the write path equivalent circuit 630a to generate a write voltage Vw, and the write voltage Vw is output from the node Y. Among them, the input current Ix is equal to the mirror current Iy.

[0108] According to an embodiment of the present invention, the process corner compensation circuit can provide different write voltages to the MRAM 430 during a write operation. For example, the process corner compensation circuit provides a first write voltage Vw1 to change the selected memory cell from the second storage state to the first storage state. Alternatively, the process corner compensation circuit provides a second write voltage Vw2 to change the selected memory cell from the first storage state to the second storage state. This is further described below.

[0109] Please refer to Figure 6B , which is a second example of a process corner compensation circuit, which can provide a first write voltage. The process corner compensation circuit 420b includes a current mirror 610b, a storage element equivalent circuit 620b and a write path equivalent circuit 630b.

[0110] The current mirror 610b receives the transition voltage Vts output by the temperature compensation circuit. The current mirror 610b includes an operational amplifier 642 and PMOS transistors Mp2-Mp5. The PMOS transistors Mp2-Mp5 have the same aspect ratio (W / L).

[0111] A negative input terminal of the operational amplifier 642 receives the transition voltage Vts, and a positive input terminal of the operational amplifier 642 is connected to a node Z, wherein the node Z is a first terminal of the current mirror 610 b.

[0112] The first drain / source terminals of the PMOS transistors Mp2 and Mp3 receive the supply voltage Vdd, and the gate terminals of the PMOS transistors Mp2 and Mp3 are connected to the output terminal of the operational amplifier 642. The gate terminals of the PMOS transistors Mp4 and Mp5 receive a bias voltage (bias voltage, Vb). The first drain / source terminal of the PMOS transistor Mp4 is connected to the second drain / source terminal of the PMOS transistor Mp2, and the second drain / source terminal of the PMOS transistor Mp4 is connected to the node Z. The first drain / source terminal of the PMOS transistor Mp5 is connected to the second drain / source terminal of the PMOS transistor Mp3, and the second drain / source terminal of the PMOS transistor Mp5 is connected to the node Y. Node Y is the second terminal of the current mirror 610b, and the first write voltage Vw1 is outputted from the node Y.

[0113] The storage element equivalent circuit 620b includes a first reference storage element 652. The structure of the first reference storage element 652 is the same as Figure 1 The storage element 120 in the embodiment of the present invention is not described in detail. Furthermore, the current mirror 610b provides the transition voltage Vts to the first terminal. Therefore, the first storage element 652 generates an input current Ix according to the transition voltage Vts, and the second terminal of the current mirror 610b can generate a mirror current Iy according to the input current Ix.

[0114] The write path equivalent circuit 630b includes: a reference bit line multiplexer 662, a reference bit line BLref, a reference memory cell 664b, a reference source line SLref and a reference source line multiplexer 666. Furthermore, the reference memory cell 664b includes a second reference storage element 665, a reference selection transistor Mref and a reference word line WLref, and the reference word line WLref can receive a turn-on voltage (Von). Basically, the structure of the write path equivalent circuit 630b is the same as Figure 3B The writing path of , its structure will not be described in detail.

[0115] Furthermore, according to the input current Ix, the second end of the current mirror 610b generates a mirror current Iy and flows to the write path equivalent circuit 630b. Therefore, the mirror current Iy flows through the write path equivalent circuit 630b to generate a first write voltage Vw1, and the first write voltage Vw1 is output from the node Y. Among them, the input current Ix is equal to the mirror current Iy.

[0116] According to the embodiment of the present invention, since the MRAM memory and the write voltage generator are fabricated at the same time, all transistors in the MRAM memory and the write voltage generator have the same process corners.

[0117] That is, the write path equivalent circuit 630b in the process corner compensation circuit 420b has the same circuit structure and resistance value as the write path in the memory cell array. Therefore, the first write voltage Vw1 output by the write voltage generator 400 can make the selected memory cell of the write path in the memory cell array change to the first storage state smoothly. That is, the storage element in the selected memory cell can receive the transition voltage Vts and change to the first storage state.

[0118] For example, when the first reference memory element 652 and the second reference memory element 665 are both in the second memory state, the process corner compensation circuit 420b can provide the first write voltage Vw1. Since the first reference memory element 652, the second reference memory element 665, and the memory element in the selected memory cell have almost equal resistance values, the selected memory cell in the memory cell array can be successfully changed from the second memory state to the first memory state.

[0119] Please refer to Figure 6C , which is a third example of a process corner compensation circuit, which can generate a first write voltage Vw1. The process corner compensation circuit 420c includes a current mirror 610c, a storage element equivalent circuit 620c and a write path equivalent circuit 630c. The structure of the current mirror 610c is the same as Figure 6B The current mirror 610b is not described in detail here.

[0120] The storage element equivalent circuit 620c includes: a first reference resistor R1ref, which is a variable resistor. The first reference resistor R1ref can be adjusted to a resistance value of the second storage state (e.g., 4K ohms). Similarly, the current mirror 610c provides the transition voltage Vts to the first terminal. Therefore, the first reference resistor R1ref generates an input current Ix, and the second terminal of the current mirror 610b can generate a mirrored current Iy according to the input current Ix.

[0121] The write path equivalent circuit 630c includes: a reference bit line multiplexer 662, a bit line equivalent resistor R BL , reference memory cell 664c, source line equivalent resistance R SL and a reference source line multiplexer 666. Furthermore, the reference memory cell 664c includes a second reference resistor R2ref, a reference selection transistor Mref and a reference word line WLref, and the reference word line WLref can receive a turn-on voltage (Von).

[0122] Compared to Figure 6B The write path equivalent circuit 630b, Figure 6C The write path equivalent circuit 630c is composed of a bit line equivalent resistance R BL The equivalent resistance R of the source lineSL The reference bit line BLref and the reference source line SLref are replaced by the second reference resistor R2ref. Furthermore, the second reference storage element 665 is replaced by the second reference resistor R2ref. Furthermore, the second reference resistor R2ref is a variable resistor. The second reference resistor R2ref can be adjusted to a resistance value of the second storage state (eg, 4K ohms).

[0123] Similarly, according to the input current Ix, the second end of the current mirror 610b generates a mirror current Iy and flows to the write path equivalent circuit 630c. Therefore, the mirror current Iy flows through the write path equivalent circuit 630c to generate a first write voltage Vw1, and the first write voltage Vw1 is output from the node Y. Among them, the input current Ix is equal to the mirror current Iy.

[0124] For example, when the first reference resistor R1ref and the second reference resistor R2ref are both 4K ohms (second memory state), the process corner compensation circuit 420c can provide the first write voltage Vw1. Since the first reference resistor R1ref and the second reference resistor R2ref and the memory element in the selected memory cell have almost equal resistance values, the selected memory cell in the memory cell array can be successfully changed from the second memory state to the first memory state.

[0125] Please refer to Fig.6D , which is a fourth example of a process corner compensation circuit, which can provide a second write voltage. The process corner compensation circuit 420d includes a current mirror 610d, a storage element equivalent circuit 620d and a write path equivalent circuit 630d. The structures of the current mirror 610d and the storage element equivalent circuit 620d are the same as Figure 6B The current mirror 610b and the storage element equivalent circuit 620b are not described in detail here.

[0126] The write path equivalent circuit 630d includes a reference bit line multiplexer 662, a reference bit line BLref, a reference memory cell 664d, a reference source line SLref, and a reference source line multiplexer 666. Furthermore, the reference memory cell 664d includes a second reference storage element 665, a reference selection transistor Mref, and a reference word line WLref, and the reference word line WLref can receive a turn-on voltage (Von).

[0127] In the write path equivalent circuit 630d, the reference source line multiplexer 666 is connected between the node Y and the reference source line SLref. The reference bit line multiplexer 662 is connected between the ground terminal GND and the reference bit line BLref. The reference selection transistor Mref is connected to the reference bit line BLref, the reference source line SLref and the reference word line WLref.

[0128] Similarly, according to the input current Ix, the second end of the current mirror 610d generates a mirror current Iy and flows to the write path equivalent circuit 630d. Therefore, the mirror current Iy flows through the write path equivalent circuit 630d to generate a second write voltage Vw2, and the second write voltage Vw2 is output from the node Y. Among them, the input current Ix is equal to the mirror current Iy.

[0129] According to an embodiment of the present invention, the write path equivalent circuit 630d in the process corner compensation circuit 420d has the same circuit structure and resistance value as the write path in the memory cell array. Therefore, the second write voltage Vw2 output by the write voltage generator 400 can smoothly change the selected memory cell of the write path in the memory cell array to the second storage state. That is, the storage element in the selected memory cell can receive the transition voltage Vts and change to the second storage state.

[0130] For example, when the first reference memory element 620d and the second reference memory element 665 are both in the first memory state, the process corner compensation circuit 420d can provide the second write voltage Vw2. Since the first reference memory element 620d, the second reference memory element 665, and the memory element in the selected memory cell have almost equal resistance values, the selected memory cell in the memory cell array can be successfully changed from the first memory state to the second memory state.

[0131] Please refer to Fig. 6E , which is a fifth example of a process corner compensation circuit, which can generate a second write voltage Vw2. The process corner compensation circuit 420e includes a current mirror 610e, a storage element equivalent circuit 620e and a write path equivalent circuit 630e. The structures of the current mirror 610e and the storage element equivalent circuit 620e are the same as Figure 6C The current mirror 610c and the storage element equivalent circuit 620c are not described in detail here.

[0132] The write path equivalent circuit 630e includes: a reference bit line multiplexer 662, a bit line equivalent resistor R BL , reference memory cell 664e, source line equivalent resistance R SL and a reference source line multiplexer 666. Furthermore, the reference memory cell 664e includes a second reference resistor R2ref, a reference selection transistor Mref and a reference word line WLref, and the reference word line WLref can receive a turn-on voltage (Von).

[0133] Compared to Fig.6D The write path equivalent circuit 630d, Fig. 6E The write path equivalent circuit 630e is composed of a bit line equivalent resistance R BL The equivalent resistance R of the source line SLThe reference bit line BLref and the reference source line SLref are replaced by the second reference resistor R2ref. Furthermore, the second reference storage element 665 is replaced by the second reference resistor R2ref. Furthermore, the second reference resistor R2ref is a variable resistor. The second reference resistor R2ref can be adjusted to a resistance value of the first storage state (eg, 2.0K ohms).

[0134] Similarly, according to the input current Ix, the second end of the current mirror 610e generates a mirror current Iy and flows to the write path equivalent circuit 630e. Therefore, the mirror current Iy flows through the write path equivalent circuit 630e to generate a second write voltage Vw2, and the second write voltage Vw2 is output from the node Y. Among them, the input current Ix is equal to the mirror current Iy.

[0135] For example, when the first reference resistor R1ref and the second reference resistor R2ref are both 2K ohms (first memory state), the process corner compensation circuit 420e can provide the second write voltage Vw2. Since the first reference resistor R1ref and the second reference resistor R2ref and the memory element in the selected memory cell have almost equal resistance values, the selected memory cell in the memory cell array can be successfully changed from the first memory state to the second memory state.

[0136] Furthermore, the above FIG. 6A to FIG. 6E The process corner compensation circuits 420a-420e may further include a voltage regulator. The input end of the voltage regulator is connected to the node Y to receive the write voltage Vw. The output end of the voltage regulator can generate the same write voltage Vw. The function of the voltage regulator is similar to that of a buffer circuit to enhance the driving strength of the write voltage generator.

[0137] According to an embodiment of the present invention, since the MRAM memory and the write voltage generator are manufactured at the same time, all transistors belong to the same process corner. In the present invention, the function of the current mirror 610a~610e is to provide a mirror current Iy to ensure that the second storage element in the write path equivalent circuit 630a~630e can receive the transition voltage Vts, and the write path equivalent circuit 630a~630e can generate the correct write voltage. Furthermore, since the structure of the write path equivalent circuit 630a~630e is almost the same as the write path in the MRAM memory. Therefore, when the MRAM memory receives the write voltage output by the write voltage generator 400, the storage element of the selected memory cell in the write path can receive the transition voltage Vts and successfully change the storage state.

[0138] Of course, using the technology disclosed in the present invention, a person skilled in the art can also make two write voltage generators and provide them to the MRAM memory, wherein the first write voltage generator generates a first write voltage and the second write voltage generator generates a second write voltage.

[0139] From the above embodiments, it can be seen that the write voltage generator of the present invention is applied to MRAM memory. Of course, the technology of the present invention can also be applied to other types of non-volatile memory. For example, the write voltage generator of the present invention is applied to RRAM memory or ReRAM memory.

[0140] As can be seen from the above description, the present invention proposes a write voltage generator for non-volatile memory. The write voltage generator includes a temperature compensation circuit and a process corner compensation circuit. The temperature compensation circuit can generate a transition voltage according to the change of the ambient temperature, and the process corner compensation circuit can generate a write voltage to the write path according to the process corner of the memory cell array. In this way, during the write operation, it can be ensured that the selected memory cell in the write path in the memory cell array can change the storage state.

[0141] In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A write voltage generator coupled to a memory cell array, the write voltage generator providing a write voltage during a write operation, the write voltage being used to change the storage state of a selected memory cell in a write path in the memory cell array, the write voltage generator comprising: A temperature compensation circuit, wherein the temperature compensation circuit generates a transition voltage according to the ambient temperature, wherein the higher the ambient temperature, the lower the transition voltage; as well as A process corner compensation circuit includes a current mirror, a storage element equivalent circuit and a write path equivalent circuit, wherein the current mirror receives the transition voltage, the storage element equivalent circuit is connected between the first end of the current mirror and the ground end, the second end of the current mirror is connected to a first node, the write path equivalent circuit is connected between the first node and the ground end, and the write voltage is output from the first node.

2. The write voltage generator as claimed in claim 1, wherein the temperature compensation circuit comprises a negative temperature coefficient circuit.

3. The write voltage generator as claimed in claim 2, wherein the temperature compensation circuit further comprises: a buffer circuit, wherein an input terminal of the buffer circuit is connected to the negative temperature coefficient circuit, and an output terminal of the buffer circuit is connected to the second node; as well as an upper limit voltage limiting circuit, wherein an input terminal of the upper limit voltage limiting circuit receives an upper limit voltage, and an output terminal of the upper limit voltage limiting circuit is connected to the second node; The transition voltage is outputted by the second node, and the transition voltage is limited to not exceed the upper limit voltage.

4. The write voltage generator as claimed in claim 2, wherein the temperature compensation circuit further comprises: a buffer circuit, wherein an input terminal of the buffer circuit is connected to the negative temperature coefficient circuit, and an output terminal of the buffer circuit is connected to the second node; as well as a lower limit voltage limiting circuit, wherein an input terminal of the lower limit voltage limiting circuit receives a lower limit voltage, and an output terminal of the lower limit voltage limiting circuit is connected to the second node; The transition voltage is outputted by the second node, and the transition voltage is limited to be not less than the lower limit voltage.

5. The write voltage generator as claimed in claim 2, wherein the temperature compensation circuit further comprises: A buffer circuit comprises a first operational amplifier, a positive input terminal of the first operational amplifier is connected to the negative temperature coefficient circuit, a negative input terminal of the first operational amplifier is connected to a second node, and an output terminal of the first operational amplifier is connected to the second node; A lower limit voltage limiting circuit comprises a first PMOS transistor and a second operational amplifier, wherein a negative input terminal of the second operational amplifier receives a lower limit voltage, a positive input terminal of the second operational amplifier is connected to the second node, an output terminal of the second operational amplifier is connected to a gate terminal of the first PMOS transistor, a first drain / source terminal of the first PMOS transistor receives a supply voltage, and a second drain / source terminal of the first PMOS transistor is connected to the second node; and An upper limit voltage limiting circuit comprises a first NMOS transistor and a third operational amplifier, wherein a negative input terminal of the third operational amplifier receives an upper limit voltage, a positive input terminal of the third operational amplifier is connected to the second node, an output terminal of the third operational amplifier is connected to a gate terminal of the first NMOS transistor, a first drain / source terminal of the first NMOS transistor is connected to the ground terminal, and a second drain / source terminal of the first NMOS transistor is connected to the second node; The transition voltage is outputted from the second node, and the transition voltage is limited between the upper limit voltage and the lower limit voltage.

6. The write voltage generator as claimed in claim 1, wherein the current mirror comprises: A first operational amplifier, wherein a negative input terminal of the first operational amplifier receives the transition voltage, and a positive input terminal of the first operational amplifier is connected to a second node, and the second node is the first end of the current mirror; a first PMOS transistor, a first drain / source terminal of the first PMOS transistor receiving a supply voltage, a gate terminal of the first PMOS transistor connected to an output terminal of the first operational amplifier; a second PMOS transistor, a first drain / source terminal of the second PMOS transistor receiving the supply voltage, a gate terminal of the second PMOS transistor connected to the output terminal of the first operational amplifier; a third PMOS transistor, a first drain / source terminal of the third PMOS transistor being connected to the second drain / source terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor receiving a bias voltage, and a second drain / source terminal of the third PMOS transistor being connected to the second node; and A fourth PMOS transistor, a first drain / source terminal of the fourth PMOS transistor is connected to the second drain / source terminal of the second PMOS transistor, a gate terminal of the fourth PMOS transistor receives the bias voltage, and a second drain / source terminal of the fourth PMOS transistor is connected to the first node.

7. The write voltage generator as claimed in claim 1, wherein the storage element equivalent circuit comprises: The first reference storage element is connected between the first terminal and the ground terminal.

8. A write voltage generator as described in claim 7, wherein in the write path equivalent circuit, the reference bit line multiplexer is connected between the second end of the current mirror and the first end of the reference bit line, the reference memory cell is connected between the second end of the reference bit line and the first end of the reference source line, and the reference source line multiplexer is connected between the second end of the reference source line and the ground end; or, in the write path equivalent circuit, the reference source line multiplexer is connected between the second end of the current mirror and the first end of the reference source line, the reference memory cell is connected between the second end of the reference source line and the first end of the reference bit line, and the reference bit line multiplexer is connected between the second end of the reference bit line and the ground end.

9. The write voltage generator as claimed in claim 8, wherein the reference memory cell comprises: A second reference storage element and a reference selection transistor are connected in series, wherein the first reference storage element and the second reference storage element have the same storage state.

10. The write voltage generator of claim 9, wherein a first resistance value of the first reference memory element is almost the same as a second resistance value of the second reference memory element, and the second resistance value is almost the same as a third resistance value of a selected memory element in the selected memory cell.

11. The write voltage generator as claimed in claim 1, wherein the storage element equivalent circuit comprises: A first reference resistor is a variable resistor.

12. A write voltage generator as described in claim 11, wherein in the write path equivalent circuit, the reference bit line multiplexer is connected between the second end of the current mirror and the first end of the bit line equivalent resistor, the reference memory cell is connected between the second end of the bit line equivalent resistor and the first end of the source line equivalent resistor, and the reference source line multiplexer is connected between the second end of the source line equivalent resistor and the ground end; or, in the write path equivalent circuit, the reference source line multiplexer is connected between the second end of the current mirror and the first end of the source line equivalent resistor, the reference memory cell is connected between the second end of the source line equivalent resistor and the first end of the bit line equivalent resistor, and the reference bit line multiplexer is connected between the second end of the bit line equivalent resistor and the ground end.

13. The write voltage generator as claimed in claim 12, wherein the reference memory cell comprises: The second reference resistor and the reference selection transistor are connected in series, and the second reference resistor is a variable resistor.

14. The write voltage generator of claim 13, wherein a first resistance value of the first reference resistor is almost the same as a second resistance value of the second reference resistor, and the second resistance value is almost the same as a third resistance value of a selected storage element in the selected memory cell. 15 . The write voltage generator as claimed in claim 1 , wherein the first node is further connected to an input terminal of a regulator, and an output terminal of the regulator outputs the write voltage. 16 . The write voltage generator as claimed in claim 1 , wherein the memory cell array is a memory cell array of a magnetoresistive random access memory or a memory cell array of a resistive random access memory.

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