Modified seeding scheme during program operations in memory sub-systems

Abstract

Embodiments of the present disclosure relate to modified seeding schemes during program operations in a memory sub-system. A processing device in a memory system initiates a program operation on a memory device, the program operation including a seeding phase. The processing device further causes a seed voltage to be applied to strings of memory cells in a data block of the memory device during the seeding phase of the program operation, and causes a positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase. Each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, the first plurality of word lines including a selected word line associated with the program operation.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically to modified inoculation protocols during programming operations in memory subsystems. Summary of the Invention

[0002] A memory device is described. The memory device includes: a memory array; and control logic operably coupled to the memory array to perform operations including: initiating a programming operation on the memory array, the programming operation including a seeding phase; applying a seeding voltage to a string of memory cells in a data block of the memory array during the seeding phase of the programming operation; and applying a positive voltage to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, the first plurality of word lines including a selected word line associated with the programming operation.

[0003] A method is described. The method includes: initiating a programming operation on a memory device, the programming operation including a seeding phase; applying a seeding voltage to a string of memory cells in a data block of the memory device during the seeding phase of the programming operation; and applying a positive voltage to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, the first plurality of word lines including selected word lines associated with the programming operation.

[0004] A memory device is described. The memory device includes: a first memory cell string in a first sub-block of a memory cell block, the first sub-block including selected sub-blocks, wherein the first memory cell string includes a first plurality of memory cells coupled to a plurality of word lines; and a second memory cell string in a second sub-block of the memory cell block, the second sub-block including unselected sub-blocks, wherein the second memory cell string includes a second plurality of memory cells coupled to the plurality of word lines coupled to the first memory cell string, wherein a first subset of the plurality of word lines is configured to receive a positive voltage signal during an inoculation phase of a programming operation performed on the selected sub-blocks, wherein each of the first subset of the plurality of word lines is coupled to a corresponding memory cell of a first subset of the second plurality of memory cells in the second string, the first subset of the plurality of word lines including selected word lines associated with the programming operation. Background Technology

[0005] A memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0006] This disclosure will be more fully understood from the specific embodiments given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 Examples of computing systems including a memory subsystem are shown according to some embodiments of the present disclosure.

[0008] Figure 2 This is a schematic diagram illustrating a string of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3 This is a timing diagram of the operation of a memory device during programming operations according to some embodiments of the present disclosure.

[0010] Figure 4 This is a timing diagram of the operation of a memory device during programming operations according to some embodiments of the present disclosure.

[0011] Figure 5 This is a diagram illustrating the channel potential of a string of memory cells during the inoculation phase of a programming operation according to some embodiments of the present disclosure.

[0012] Figure 6 This is a diagram illustrating the channel potential of a string of memory cells during the inoculation phase of a programming operation according to some embodiments of the present disclosure.

[0013] Figure 7 This is a flowchart illustrating an example method of implementing a modified inoculation protocol during programming operations in a memory subsystem according to some embodiments of this disclosure.

[0014] Figure 8 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0015] Various aspects of this disclosure relate to modified inoculation schemes during programming operations in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0016] The memory subsystem may include high-density non-volatile memory devices where data retention is required when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each containing one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane consists of a set of physical blocks. Each block contains a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Hereinafter, a data block refers to a cell of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. Each data block may contain several sub-blocks, each sub-block being defined by an associated set of pillars (e.g., vertical conductive traces) extending from a shared bit line. A memory page (also referred to herein as a “page”) stores one or more bits of binary data corresponding to data received from the host system. To achieve high density, strings of memory cells in non-volatile memory devices can be configured to comprise multiple memory cells comprising pillars that at least partially surround the channel material. The memory cells can be coupled to access lines, often referred to as "word lines," which are typically manufactured in the same manner as the memory cells to form a string array within the memory block. The compact nature of certain non-volatile memory devices, such as 3D flash NAND memory, means that word lines are shared by many memory cells within the memory block.

[0017] During a programming operation, a selected memory cell can be programmed by applying a programming voltage to the selected word line. Because word lines are shared by multiple memory cells, unselected memory cells may experience the same programming voltage as the selected memory cells. If not otherwise preprocessed, unselected memory cells may experience the effects of the programming voltage from the common word line. These programming voltage effects can include situations where charge is stored in unselected memory cells intended to hold stored data. This programming voltage effect is called "programming disturbance" or "program disturb." Programming disturbance can render the charge stored in unselected memory cells completely unreadable, or, although still clearly readable, allow the contents of the memory cell to be read as a different data value than the intended data value stored before the programming voltage was applied.

[0018] The presence of residual electrons (e.g., electrons trapped or otherwise retained within the polysilicon channel of the charge storage structure after an earlier operation (e.g., a previous programming operation)) can lead to programming interference effects. At the end of a programming verification operation, for example, the pass voltage (Vpass) applied to unprogrammed word lines slopes down, and word lines with high threshold voltages on the source side will be cut off before word lines with lower threshold voltages. Therefore, electrons will be trapped inside the polysilicon channel at word lines with lower threshold voltages (i.e., between cut-off word lines) and become residual electrons. Since the polysilicon channels (i.e., columnar channel regions) in some non-volatile memory devices are floating channels that may not be connected to a block ground body, there is typically no path for residual electrons in the channel region to discharge toward the source other than through the source of the memory string. Programming operations typically include a seeding phase, in which a seed voltage (e.g., 2 volts) is applied to the string, and a ground voltage (e.g., 0 volts) is applied to all word lines intersecting the string, including selected word lines. Using a ground voltage during the seeding phase keeps the source-side word line open, and residual electrons remain trapped on the source side of the selected word line at the end of the seeding phase. These residual electrons can cause programming interference in several ways. For example, when the pass voltage or programming voltage ramps up in subsequent programming operations, the selected word line can be subjected to hot electron (hot e) interference, where a large voltage difference between the gate and source causes residual electrons to be injected from the drain depletion region into the floating gate. Additionally, this voltage difference can generate an electrostatic field of sufficient magnitude to alter the charge on the selected word line and cause the contents of the memory cell to be unintentionally programmed or incorrectly read. Furthermore, the electrostatic field can generate localized electron-hole pairs in the channel region, resulting in even more electrons that can be injected into the selected word line.

[0019] The present disclosure addresses the above and other shortcomings by implementing a modified seeding scheme during programming operations in the memory subsystem. In one embodiment, the memory subsystem initiates a programming operation on the memory device such that a seeding voltage is applied to a string of memory cells in a data block of the memory device during the seeding phase of the programming operation, and a positive voltage is applied to a first plurality of word lines of the data block during the seeding phase. Each of the first plurality of word lines is coupled to a corresponding memory cell of the first plurality of memory cells in the string, and the first plurality of word lines include selected word lines associated with the programming operation. This positive voltage reduces the electron potential barrier at those memory cells coupled to the corresponding word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and to the drain side of the string. Additionally, the memory subsystem may apply at least one of a negative voltage or a ground voltage to other word lines of the string during the seeding phase to actively push residual electrons from the source side to the drain side. As a result, most (if not all) of the residual electrons can be cleared from the channel of the string during the seeding phase, so that when a high programming voltage is subsequently applied to the selected word line, the residual electrons are absent and not injected into the selected word line. Therefore, programming interference effects can be significantly reduced, thereby improving the programming performance of the memory subsystem.

[0020] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., included in a vehicle, industrial equipment or networked business device), or such computing device including memory and processing device.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0024] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0025] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can perform bit storage based on changes in volume resistance by combining a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, in which non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), triple-level cell (TLC), and quadruple-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] Although non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-type memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-type RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0033] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, cache storage operations, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes a raw memory device 130 having control logic (e.g., local controller 135) on a die and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, memory device 130 may represent a single die having some control logic embodied thereon (e.g., local media controller 135). In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0036] In one embodiment, memory device 130 includes a memory device programming management component 113 that can monitor, control, and / or manage data access operations (e.g., programming operations) performed on a non-volatile memory device (e.g., memory device 130) of memory subsystem 110. For example, a programming operation may include multiple phases, such as a seeding phase, a pass voltage ramp-up phase, a programming voltage ramp-up phase, and a programming recovery phase. The programming management component 113 is responsible for applying (or indicating which voltages are applied) specific voltages to memory device 130 during the programming operation. The seeding phase typically involves an overall increase in the channel voltage of suppression strings (i.e., strings of memory cells not programmed onto) in memory device 130 to attempt to counteract programming interference generated by the use of high-voltage programming pulses. The seeding voltage applied to the strings (e.g., bit lines) couples the source, drain, and channel of the strings at a higher voltage level, thereby better suppressing programming interference. Because a relatively high voltage is applied during the programming voltage ramp-up phase, the programming recovery phase allows the device to recover from a high-voltage mode. Generally, during the programming recovery phase, all signals ramp down to some lower voltage level. In one embodiment, the programming management component 113 causes word line drivers to apply a seeding voltage to a string of memory cells in a data block of the memory device 130 during the seeding phase of a programming operation, and causes a positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase. Each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, and the first plurality of word lines include selected word lines associated with the programming operation. This positive voltage reduces the electron potential barrier at those memory cells coupled to the corresponding word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and to the drain side of the string. Additionally, the programming management component 113 can cause at least one of a negative voltage or a ground voltage to be applied to other word lines of the string during the seeding phase to actively push residual electrons from the source side to the drain side. Further details regarding the operation of the programming management component 113 are described below.

[0037] In some embodiments, the memory subsystem controller 115 includes at least a portion of the programming management component 113. For example, the memory subsystem controller 115 may include a processor 117 (e.g., a processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the programming management component 113 is part of the host system 110, application programming, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the programming management component 113 and is configured to perform the functionality described herein. In such embodiments, the programming management component 113 may be implemented using hardware or firmware stored on the memory device 130, which is executed by control logic (e.g., the programming management component 113) to perform operations related to the modified vaccination protocol described herein.

[0038] Figure 2 This is a schematic diagram illustrating a string 200 of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure. In one embodiment, string 200 represents a portion of memory device 130. String 200 includes a plurality of memory cells 212 (i.e., charge storage devices), for example, up to 32 memory cells (or more) in some embodiments. String 200 includes a source-side select transistor, referred to as a source-select gate 220 (SGS) (typically an n-channel transistor), coupled between the memory cells 212 and a common source 226 at one end of string 200. The common source 226 may comprise, for example, a co-doped semiconductor material and / or other conductive material. At the other end of string 200, a drain-side select transistor, referred to as a drain-select gate 230 (SGD) (typically an n-channel transistor), and a gate-induced drain leakage (GIDL) generator 240 (GG) (typically an n-channel transistor) are coupled between one of the memory cells 212 and a data line 234, which is generally referred to in the art as a "bit line". The common source 226 can be coupled to a reference voltage (e.g., ground voltage or simply "ground" [Gnd]) or a voltage source (e.g., a charge pump circuit or power supply, which may be selectively configured to a specific voltage suitable for optimized programming operation).

[0039] Each memory cell 212 may include, for example, a floating gate transistor or a charge trapping transistor, and may include a single-layer memory cell or a multi-layer memory cell. The floating gate may be referred to as charge storage structure 235. The memory cell 212, source-select gate 220, drain-select gate 230, and GIDL generator 240 may be controlled by signals on their respective control gates 250.

[0040] Control signals can be applied or applied in the direction of the programming management component 113, for example, applied to a select line (not shown) to select a string, or applied to an access line (not shown) to select a memory cell 212. In some cases, control gates may form portions of a select line (for selecting a device) or an access line (for a cell). Drain select gate 230 receives a voltage that allows drain select gate 230 to select or deselect string 200. In one embodiment, each corresponding control gate 250 is connected to a separate word line (i.e., an access line) so that each device or memory cell can be controlled individually. String 200 may be one of a plurality of memory cell strings in a block of memory cells in memory device 130. For example, when a plurality of memory cell strings exist, each memory cell 212 in string 200 may be connected to a corresponding shared word line, and a corresponding memory cell in each of the plurality of strings may also be connected to the corresponding shared word line. Therefore, if a selected memory cell in one of the multiple strings is being programmed, the corresponding unselected memory cells 212 in string 200 connected to the same word line as the selected cell can experience the same programming voltage, potentially causing programming interference. Thus, in one embodiment, the programming management component 113 causes the word line driver to apply a seeding voltage to bit line 234 during the seeding phase of the programming operation, and causes a positive voltage to be applied during the seeding phase to specific control gates 250 of the means and / or cells 212 in string 200. Additionally, the memory subsystem can cause at least one of a negative voltage or a ground voltage to be applied during the seeding phase to other control gates 250 of the means and / or cells 212 in string 200 to actively push residual electrons from the source side to the drain side. As a result, most (if not all) of the residual electrons can be cleared from the string channel during the seeding phase, such that when a high programming voltage is subsequently applied to the selected word line, residual electrons are absent and not injected into the selected word line.

[0041] Figure 3This is a timing diagram 300 for operation of a memory device during programming operations according to some embodiments of the present disclosure. During programming operations performed on a non-volatile memory device (e.g., memory device 130), certain phases may be encountered, including a seeding phase 310, a pass voltage ramp phase 320, a programming voltage ramp phase 330, and a programming recovery phase 340. The seeding phase 310 typically involves an overall increase in the channel voltage of the suppression string in memory device 130 to attempt to counteract programming interference generated by the use of a high-voltage programming pulse. During the pass voltage ramp phase 320, a pass voltage (Vpass) is applied to the word line of memory device 130 to further increase the channel voltage of the associated channel. During the programming voltage ramp phase 330, a programming voltage is applied to a selected word line (e.g., WLn) of memory device 130 to program a certain charge level to the selected memory cell on the word line representing the desired value. Because a relatively high voltage is applied during the programming voltage ramp phase 330, the programming recovery phase 340 allows the device to recover from a high-voltage mode.

[0042] Timing diagram 300 illustrates various stages of programming operation 300 according to one embodiment. In this embodiment, different signals are applied to various means in the memory device 130 during each of the stages shown. During the seeding stage 310, programming management component 113 causes a signal 301 having a seed voltage (e.g., 3 volts) to bit line 234 of string 200. In one embodiment, programming management component 113 sends a signal to word line driver (or some other component) instructing the driver to apply signal 301 to bit line 234. Signal 301 may be maintained at the seed voltage throughout the pass voltage ramp stage 320 and programming voltage ramp stage 330. During programming recovery stage 340, signal 301 returns to ground voltage (e.g., 0V). During seeding stage 310, programming management component 113 further causes a signal 302 to be applied to drain-select gate 230. Signal 302 (e.g., 7V) activates drain-select gate 230 (e.g., "turns it on"), thereby allowing the seed voltage to flow from bit line 234 through drain-select gate 230 to various data word lines connected to string 200. In one embodiment, the data word lines include one or more word lines connected to the remaining memory cells 212 of string 200. These cells 212 are typically used to store data, such as data from host system 120. Signal 302 returns to ground voltage during the pass voltage ramp phase 320, the programming voltage ramp phase 330, and the programming recovery phase 340.

[0043] In one embodiment, the programming management component 113 may enable a positive voltage to be applied to specific word lines of the string 200 during the seeding phase 310, wherein a positive voltage may be seen at the control gate 250 of the corresponding memory cell 212. The positive voltage reduces the electron barrier at those specific word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and to the drain (i.e., bit line 234). Additionally, the programming management component 113 may enable a negative voltage to be applied to other word lines of the string 200 during the seeding phase 310 to actively push residual electrons from the source side to the drain side.

[0044] As shown in timing diagram 300, programming management component 113 enables a signal 303 with a positive voltage (e.g., 1V) to be applied to the selected word line (i.e., the properly programmed word line (WLn)) and any word lines above the selected word line in the string (i.e., those word lines located between WLn and drain-select gate 230). This positive voltage ensures that the channel potential is primarily determined by the seed voltage (e.g., 3V). This higher channel potential produces a larger drain-induced barrier reduction (DIBL) effect on adjacent source-side word lines (i.e., the next word line down the string (WLn-1 and WLn-2), allowing more residual electrons to flow to the drain side. During the transfer voltage ramp-up phase 320, signal 303 increases to a higher voltage (e.g., 10V), and during the programming voltage ramp-up phase 330, signal 303 increases to an even higher voltage (e.g., 20V). Signal 303 returns to ground voltage during programming recovery phase 340. Furthermore, the programming management component 113 allows a signal 304 with a positive voltage (e.g., 2V) to be applied to adjacent source-side word lines (i.e., WLn-1 and WLn-2). This positive voltage also reduces the electron barrier in these word lines. During the transfer voltage ramp-up phase 320 and the programming voltage ramp-up phase 330, the signal 304 increases to a higher voltage (e.g., 10V). The signal 304 returns to ground voltage during the programming recovery phase 340. In one embodiment, the programming management component 113 allows different voltages to be applied to WLn-1 and WLn-2. For example, a higher voltage may be applied to WLn-1 and a lower voltage may be applied to WLn-2 because WLn-1 receives more threshold voltage reduction due to the DIBL effect than WLn-2. In another embodiment, the same voltage may also be applied to WLn-1, WLn-2, ​​and WLn-3.

[0045] In one embodiment, the programming management component 113 may cause a signal 305 having a negative voltage (e.g., -1V) to be applied to the remaining data word lines (i.e., WLn-3 and below). The negative voltage generates even lower channel potentials on these word lines, which can actively push any residual electrons trapped there toward the drain. During the pass voltage ramp-up phase 320 and the programming voltage ramp-up phase 330, the signal 305 is increased to a higher voltage (e.g., 10V). The signal 305 returns to ground voltage during the programming recovery phase 340. In one embodiment, the programming management component 113 causes a signal 306 having a ground voltage (i.e., 0V) to be applied to the source-select gate 220 throughout the seeding phase 310, the pass voltage ramp-up phase 320, the programming voltage ramp-up phase 330, and the programming recovery phase 340. It should be understood that the specific voltage levels described herein are merely examples, and different voltage levels may be used in other embodiments.

[0046] Figure 4 This is a timing diagram 400 for operation of a memory device during programming operations according to some embodiments of the present disclosure. During programming operations performed on a non-volatile memory device (e.g., memory device 130), certain phases may be encountered, including a seeding phase 410, a pass voltage ramp phase 420, a programming voltage ramp phase 430, and a programming recovery phase 440. The seeding phase 410 typically involves an overall increase in the channel voltage of the suppression string in memory device 130 to attempt to counteract programming interference generated by the use of a high-voltage programming pulse. During the pass voltage ramp phase 420, a pass voltage (Vpass) is applied to the word line of memory device 130 to increase the channel voltage of the associated channel. During the programming voltage ramp phase 430, a programming voltage is applied to a selected word line (e.g., WLn) of memory device 130 to program a certain charge level to the selected memory cell on the word line representing the desired value. Because a relatively high voltage is applied during the programming voltage ramp phase 430, the programming recovery phase 440 allows the device to recover from a high-voltage mode.

[0047] Timing diagram 400 illustrates various stages of programming operation 400 according to one embodiment. In this embodiment, different signals are applied to various means in the memory device 130 during each of the stages shown. During the seeding stage 410, programming management component 113 applies a signal 401 having a seed voltage (e.g., 3 volts) to bit line 234 of string 200. Signal 401 may be maintained at the seed voltage throughout the pass voltage ramp stage 420 and programming voltage ramp stage 430. During programming recovery stage 440, signal 401 returns to ground voltage (e.g., 0V). During seeding stage 410, programming management component 113 further applies a signal 402 to drain select gate 230. Signal 402 (e.g., 7V) activates drain select gate 230 (e.g., "turns on"), thereby allowing the seed voltage to flow from bit line 234 through drain select gate 230 to various data word lines connected to string 200. In one embodiment, the data word lines include one or more word lines connected to the remaining memory cells 212 of the string 200. These cells 212 are typically used to store data, such as data from the host system 120. The signal 402 returns to ground voltage during the pass voltage ramp-up phase 420, the programming voltage ramp-up phase 430, and the programming recovery phase 440.

[0048] In one embodiment, the programming management component 113 may allow a positive voltage to be applied to specific word lines of the string 200 during the seeding phase 410, wherein a positive voltage may be seen at the control gate 250 of the corresponding memory cell 212. The positive voltage reduces the electron barrier at those specific word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and to the drain (i.e., bit line 234). Additionally, the programming management component 113 may allow a negative voltage to be applied to other word lines of the string 200 during the seeding phase 410 to actively push residual electrons from the source side to the drain side.

[0049] As shown in timing diagram 400, programming management component 113 enables a signal 403 with a positive voltage (e.g., 1V) to be applied to the selected word line (i.e., the properly programmed word line (WLn)) and any word lines above the selected word line in the string (i.e., those word lines located between WLn and drain select gate 230). This positive voltage ensures that the channel potential is primarily determined by the seed voltage (e.g., 3V). This higher channel potential produces a larger drain-induced barrier reduction (DIBL) effect on adjacent source-side word lines (i.e., the next word line down the string (WLn-1 and WLn-2), allowing more residual electrons to flow to the drain side. During the transfer voltage ramp-up phase 420, signal 403 increases to a higher voltage (e.g., 10V), and during the programming voltage ramp-up phase 430, signal 403 increases to an even higher voltage (e.g., 20V). Signal 403 returns to ground voltage during programming recovery phase 440. Furthermore, the programming management component 113 allows a signal 404 with a positive voltage (e.g., 5V) to be applied to adjacent source-side word lines (i.e., WLn-1 and WLn-2). This positive voltage ensures that the memory cells 212 to which these word lines are attached are fully activated, thereby allowing the seeding voltage applied to the bit lines to propagate WLn-1 and WLn-2 to the source side. During the propagation voltage ramp-up phase 420 and the programming voltage ramp-up phase 430, signal 404 increases to a higher voltage (e.g., 10V). Signal 404 returns to ground voltage during the programming recovery phase 440. Additionally, the programming management component 113 allows a signal 405 with a positive voltage (e.g., 2V) to be applied to the next source-side word line (i.e., WLn-3). This positive voltage avoids a sharp change in channel potential between WLn-2 and WLn-4. This sharp change would generate a large electric field, leading to increased local electron generation, which would exacerbate programming interference problems for the selected word line WLn. The intermediate voltage of signal 405 causes a smoother change in channel potential. During the transfer voltage ramp-up phase 420 and the programming voltage ramp-up phase 430, signal 404 increases to a higher voltage (e.g., 10V). Signal 404 returns to ground voltage during the programming recovery phase 440. In one embodiment, the programming management component 113 may allow different voltages to be applied to WLn-1 and WLn-2. For example, a higher voltage may be applied to WLn-1 and a lower voltage may be applied to WLn-2 because WLn-1 receives more threshold voltage reduction due to the DIBL effect than WLn-2. In another embodiment, the same voltage may also be applied to WLn-1, WLn-2, ​​and WLn-3.

[0050] In one embodiment, the programming management component 113 may cause a signal 406 having a ground voltage (e.g., 0V) to be applied to the remaining data word lines (i.e., WLn-4 and below). The ground voltage generates a low channel potential on these word lines, which can actively push any residual electrons trapped there toward the drain. During the pass voltage ramp-up phase 420 and the programming voltage ramp-up phase 430, the signal 406 is increased to a higher voltage (e.g., 10V). The signal 406 returns to the ground voltage during the programming recovery phase 440. In one embodiment, the programming management component 113 causes a signal 407 having a ground voltage (i.e., 0V) to be applied to the source select gate 220 throughout the seeding phase 410, the pass voltage ramp-up phase 420, the programming voltage ramp-up phase 430, and the programming recovery phase 440.

[0051] Figure 5 This is a diagram illustrating the channel potential 500 of a string of memory cells during the inoculation phase of a programming operation according to some embodiments of the present disclosure. In one embodiment, string 200 corresponds to... Figure 2 The string 200 shown, and the vaccination protocol used corresponds to Figure 3 The timing diagram 300 shown is illustrated. As described above, string 200 includes a GIDL generator (GG) device, a drain-select gate (SGD) device, a plurality of memory cells (each connected to a separate word line (WL)), and a source-select gate (SGS) device. In one embodiment, one or more of the memory cells are connected to a dummy word line (DWL) and are generally not used for storing data. At least one of the memory cells in string 200 may be connected to a selected word line (i.e., a properly programmed word line (WLn)), and each of the remaining memory cells on the source side of the selected word line may be connected to a word line referred to as a data word line (WLn-1, WLn-2, ​​..., WLn-17). In one embodiment, one or more memory cells may be connected to a word line (e.g., WLn+1) on the drain side of a selected word line, which may be a dummy word line or a data word line. Depending on the embodiment, any number of data word lines may be present. In one embodiment, string 200 represents an unselected sub-block of a data block of memory cells in memory device 130. As described above, a data block may include additional sub-blocks with additional memory cell strings. For example, string 550 may represent a selected sub-block of the same data block and may similarly include multiple memory cells and / or other devices coupled to the same word lines as the corresponding memory cells and / or other devices of string 200.

[0052] In one embodiment, each device in string 200 has an associated threshold voltage (Vt), which represents the voltage at which each device switches from an "off" state to an "on" state, or vice versa. For example, a memory cell connected to WLn+1 and the selected word line WLn may have a threshold voltage of -2V, a memory cell connected to WLn-1 and WLn-2 may have a threshold voltage of 5V, a memory cell connected to WLn-3 through WLn-15 may have a threshold voltage of -1V, and a memory cell connected to WLn-16 and WLn-17 may have a threshold voltage of 5V. In one embodiment, the channel potential 500 of string 200 represents the difference between the voltage applied at the control gate of each device (i.e., the gate voltage (Vg)) and a representative threshold voltage. In one embodiment, a first representative threshold voltage exists on the drain side of the selected word line (WLn), and a second representative threshold voltage exists on the source side of the selected word line (WLn). Each representative threshold voltage can be the highest threshold voltage on the drain side and the source side, respectively. Therefore, in the illustrated embodiment, the first representative threshold voltage on the drain side can be -2V associated with the memory devices connected to WLn+1 and WLn, and the second representative threshold voltage on the source side can be 5V associated with the memory devices connected to WLn-1, WLn-2, ​​WLn-16, and WLn-17. Since WLn-1 has the highest threshold voltage on the source side of the selected word line, the highest number of source-side residual electrons are captured here. This represents the worst-case scenario in terms of programming interference effects, and therefore the corresponding threshold voltage can be used as the representative threshold voltage.

[0053] As mentioned above Figure 3 As described, in one embodiment, the programming management component 113 allows different voltage signals to be applied to the gate terminals of different devices during the seeding phase of the programming operation. These voltage signals may be referred to as corresponding gate voltages (Vg). Figure 5As shown, in one embodiment, the programming management component 113 can apply a positive voltage to a specific word line of the string 200 during the seeding phase 410, where the positive voltage can be seen at the control gate 250 of the corresponding memory cell 212. For example, the programming management component 113 can apply a first positive voltage (e.g., 1V) to the selected word line (i.e., WLn) and any word line above the selected word line in the string (e.g., WLn+1), and can apply a second positive voltage (e.g., 2V) to a plurality of data word lines (e.g., WLn-1 and WLn-2) adjacent to the selected word line on the source side. These positive voltages can reduce the electron barrier at the corresponding memory cell, thereby allowing any residual electrons 520 trapped on the source side to flow across the barrier and to the drain (i.e., bit line 234). Furthermore, the programming management component 113 can apply negative voltages to other word lines of the string 200 during the seeding phase 310. For example, the programming management component 113 can apply a negative voltage (e.g., -1V) to word lines WLn-3 to WLn-17. This negative voltage can actively push residual electrons 520 from the source side to the drain side.

[0054] As a result, the channel potential 500 on the drain side of the selected word line (WLn) is 3V (i.e., 1V gate voltage minus -2V first representative threshold voltage), and the channel potential 500 on the source side of the selected word line (WLn) is -6V (i.e., -1V gate voltage minus 5V second representative threshold voltage). Therefore, the difference in channel potential 500 from the drain side to the source side is -9V. It should be noted that if a ground voltage (0V) is applied to the word line, then the drain-side channel potential will be 2V, the source-side channel potential will be -5V, and the difference will only be -7V. Therefore, applying a positive voltage to a specific word line and applying a negative voltage to other word lines will increase the potential gradient between the drain and source sides of the selected word line (WLn). Because the source side of the selected word line (WLn) has a low channel potential, the residual electrons 520 trapped on the source side tend to flow to the drain side during the seeding phase, and flow across the reduced barriers at WLn-1 and WLn-2, ​​where they can be cleared via bit line 234. In the worst-case mode, the electron barriers on WLn-1 and WLn-2 as seen by the residual electrons 520 are 5V in the seeding scheme and can be reduced to less than 2V using the techniques described herein. This indicates that more than 60% of the residual electrons can be cleared during the seeding phase, and therefore, programming interference from hot electron injection can also be expected to be reduced by about 60% during the programming voltage ramp-up phase.

[0055] Figure 6 This is a diagram illustrating the channel potential 600 of a string of memory cells during the inoculation phase of a programming operation according to some embodiments of the present disclosure. In one embodiment, string 200 corresponds to... Figure 2The string 200 shown, and the vaccination protocol used corresponds to Figure 4 The timing diagram 400 is shown. As described above, string 200 includes a GIDL generator (GG) device, a drain-select gate (SGD) device, a plurality of memory cells (each connected to a separate word line (WL)), and a source-select gate (SGS) device. In one embodiment, one or more of the memory cells are connected to a dummy word line (DWL) and are generally not used to store data. At least one of the memory cells in string 200 may be connected to a selected word line (i.e., a properly programmed word line (WLn)), and each of the remaining memory cells on the source side of the selected word line may be connected to a word line referred to as a data word line (WLn-1, WLn-2, ​​..., WLn-17). In one embodiment, one or more memory cells may be connected to a word line (e.g., WLn+1) on the drain side of a selected word line, which may be a dummy word line or a data word line. Depending on the embodiment, any number of data word lines may be present. In one embodiment, string 200 represents an unselected sub-block of a data block of memory cells in memory device 130. As described above, a data block may include additional sub-blocks with additional memory cell strings. For example, string 650 may represent a selected sub-block of the same data block and may similarly include multiple memory cells and / or other devices coupled to the same word lines as the corresponding memory cells and / or other devices of string 200.

[0056] In one embodiment, each device in string 200 has an associated threshold voltage (Vt), which represents the voltage at which each device switches from an "off" state to an "on" state, or vice versa. For example, a memory cell connected to WLn+1 and a selected word line WLn may have a threshold voltage of -2V, a memory cell connected to WLn-1 and WLn-2 may have a threshold voltage of 5V, a memory cell connected to WLn-3 through WLn-15 may have a threshold voltage of -1V, and a memory cell connected to WLn-16 and WLn-17 may have a threshold voltage of 5V. In one embodiment, the channel potential 600 of string 200 represents the difference between the voltage applied at the control gate of each device (i.e., the gate voltage (Vg)) and a representative threshold voltage. In one embodiment, a first representative threshold voltage exists on the drain side of the selected word line (WLn), and a second representative threshold voltage exists on the source side of the selected word line (WLn). Each representative threshold voltage can be the highest threshold voltage on the drain side and the source side, respectively. Therefore, in the illustrated embodiment, the first representative threshold voltage on the drain side can be -2V associated with the memory devices connected to WLn+1 and WLn, and the second representative threshold voltage on the source side can be 5V associated with the memory devices connected to WLn-1, WLn-2, ​​WLn-16, and WLn-17.

[0057] As mentioned above Figure 4 As described, in one embodiment, the programming management component 113 allows different voltage signals to be applied to the gate terminals of different devices during the seeding phase of the programming operation. These voltage signals may be referred to as corresponding gate voltages (Vg). Figure 6 As shown, in one embodiment, the programming management component 113 can apply a positive voltage to a specific word line of the string 200 during the seeding phase 410, wherein the positive voltage can be seen at the control gate 250 of the corresponding memory cell 212. For example, the programming management component 113 can apply a first positive voltage (e.g., 1V) to the selected word line (i.e., WLn) and any word line above the selected word line in the string (e.g., WLn+1); can apply a second positive voltage (e.g., 5V) to a plurality of data word lines (e.g., WLn-1 and WLn-2) adjacent to the selected word line on the source side; and can apply a third positive voltage (e.g., 2V) to at least one additional word line (e.g., WLn-3). These positive voltages can reduce the electron barrier at the corresponding memory cell, thereby allowing any residual electrons 620 trapped on the source side to flow across the barrier and to the drain (i.e., bit line 234). Furthermore, the programming management component 113 can cause a ground voltage to be applied to other word lines of the string 200 during the inoculation phase 410. For example, the programming management component 113 can cause a ground voltage (e.g., 0V) to be applied to word lines WLn-4 through WLn-17.

[0058] As a result, the channel potential 600 on the drain side of the selected word line (WLn) is 3V (i.e., 1V gate voltage minus -2V first representative threshold voltage), and the channel potential 600 on the source side of the selected word line (WLn) is -5V (i.e., 0V gate voltage minus 5V second representative threshold voltage). Therefore, the difference from the drain side to the source side in the channel potential 600 is -8V. Applying a positive voltage to a specific word line and applying a ground voltage to other word lines increases the potential gradient between the drain side and the source side of the selected word line (WLn). Because the source side of the selected word line (WLn) has a lower channel potential, the residual electrons 620 trapped on the source side tend to flow to the drain side during the seeding phase and flow through the reduced barrier at WLn-1 and WLn-2, ​​where they can be cleared via bit line 234.

[0059] Figure 7This is a flowchart illustrating an example method of implementing a modified inoculation protocol during programming operations in a memory subsystem according to some embodiments of this disclosure. Method 700 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 700 is performed by… Figure 1 The programming management component 113 executes. Although shown in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0060] At operation 705, a programming operation is initiated. For example, processing logic (e.g., processor 117 or local media controller 135) may initiate a programming operation on a memory device (e.g., memory device 130). In one embodiment, the programming operation includes a seeding phase, a pass voltage ramp phase, a programming voltage ramp phase, and a programming recovery phase. In some embodiments, each of these phases may be repeated multiple times in a loop during a single programming operation. The seeding phase typically involves an overall increase in the channel voltage of the suppression string in memory device 130 to attempt to counteract programming interference caused by the use of high-voltage programming pulses. During the pass voltage ramp phase, a pass voltage (Vpass) is applied to the word line of memory device 130 to raise the channel voltage of the associated channel. During the programming voltage ramp phase, a programming voltage is applied to a selected word line (e.g., WLn) of memory device 130 to program a certain charge level to the selected memory cell on the word line representing the desired value. Because a relatively high voltage is applied during programming voltage ramp phase 330, the programming recovery phase allows the device to recover from the high-voltage mode.

[0061] At operation 710, a seeding voltage is applied to the string of memory cells. For example, processing logic may cause the seeding voltage to be applied to the string of memory cells in a data block of the memory device during the seeding phase of a programming operation. During seeding phases 310 / 410, programming management component 113 causes a signal 301 / 401 having a seeding voltage (e.g., 3 volts) to bit line 234 of string 200. Signal 301 / 401 may be maintained at the seeding voltage throughout the pass voltage ramp phases 320 / 420 and programming voltage ramp phases 330 / 430. In one embodiment, the seeding voltage is higher than the seeding voltage used in the seeding phase of the programming operation in order to increase the channel potential of string 200.

[0062] At operation 715, a positive voltage is applied to a specific word line. For example, processing logic may cause a positive voltage to be applied to a first plurality of word lines of a data block during the inoculation phase, each of which is coupled to a corresponding memory cell of a first plurality of memory cells in a string, including selected word lines associated with programming operations. In one embodiment, programming management component 113 may cause a positive voltage to be applied to a specific word line of string 200 during inoculation phases 310 / 410, where a positive voltage may be seen at the control gate 250 of the corresponding memory cell 212. The positive voltage reduces the electron barrier at those specific word lines, thereby allowing any residual electrons trapped on the source side to flow across the barrier and to the drain (i.e., bit line 234).

[0063] In one embodiment, the programming management component 113 may apply a first positive voltage (e.g., 1V) to a selected word line (i.e., WLn) and may apply a second positive voltage to one or more first word lines (e.g., WLn-1 and WLn-2) adjacent to the selected word line (i.e., WLn), wherein the one or more first word lines adjacent to the selected word line are coupled to one or more of a first plurality of memory cells on the source side of a first memory cell in a memory cell string. Generally, the second positive voltage is greater than the first positive voltage. For example, in the embodiment shown in timing diagram 300, the second positive voltage is 2V, and in the embodiment shown in timing diagram 400, the second positive voltage is 5V. Programming management component 113 may optionally apply a third positive voltage to one or more second word lines (e.g., WLn-3) adjacent to one or more first word lines (e.g., WLn-1 and WLn-2), wherein the one or more second word lines adjacent to the one or more first word lines are coupled to one or more of a first plurality of memory cells on the source side of a memory cell coupled to the one or more first word lines. Generally, the third positive voltage is greater than the first positive voltage and less than the second positive voltage. For example, in the embodiment shown in timing diagram 400, the third positive voltage is 2V.

[0064] At operation 720, a negative voltage or a ground voltage is applied to the other word lines. For example, the processing logic may cause at least one of the negative voltage or a ground voltage to be applied to a second plurality of word lines of a data block during the seeding phase, each of the second plurality of word lines being coupled to a corresponding memory cell of a second plurality of memory cells in a string, wherein the second plurality of memory cells are adjacent to a first plurality of memory cells on the source side of the memory cell string. For example, in the embodiment shown in timing diagram 300, programming management component 113 applies a negative voltage (e.g., -1V) to WLn-3 to WLn-17, and in the embodiment shown in timing diagram 400, programming management component 113 applies a ground voltage (i.e., 0V) to WLn-4 to WLn-17. This negative voltage may actively push residual electrons from the source side to the drain side.

[0065] In one embodiment, the programming management component 113 may cause positive and / or negative voltages to be applied to the word lines of a data block only during certain seeding phases of a programming operation. For example, a programming operation may include multiple seeding phases, multiple pass voltage ramping phases, and multiple programming voltage ramping phases, which are repeated sequentially. In one embodiment, positive and / or negative voltages are applied to a first plurality of word lines only during a subset of the plurality of seeding phases, the subset occurring after a threshold number of the plurality of programming voltage ramping phases have occurred. For example, if the threshold is four, then the positive and / or negative voltages will not be applied during the first four seeding phases, but will be applied in any seeding phase after that. In another embodiment, if the total number of seeding phases to be performed is known in advance, then the programming management component 113 may cause positive and / or negative voltages to be applied only during the last few seeding phases (e.g., during the last five seeding phases). In the first number of seeding phases, a ground voltage may be applied instead of positive and / or negative voltages.

[0066] Figure 8 An example machine of computer system 800 is shown, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 800 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or the computer system, can be used to perform the operation of the controller (e.g., execute an operating system to perform operations corresponding to...). Figure 1(Operation of the programming management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, corporate intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0067] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any of the aforementioned machines capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0068] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818 that communicates with each other via a bus 830.

[0069] Processing device 802 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. Computer system 800 may further include a network interface device 808 for communication via network 820.

[0070] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium, such as a non-transitory computer-readable medium) storing one or more sets of instructions 826 or software embodying any one or more of the methods or functions described herein. The instructions 826 may also reside wholly or at least partially within main memory 804 and / or processing device 802 during execution by computer system 800, which also constitute machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or main memory 804 may correspond to... Figure 1 The memory subsystem 110.

[0071] In one embodiment, instruction 826 includes instructions for implementing and Figure 1 The programming management component 113 corresponds to the functional instructions. Although the machine-readable storage medium 824 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0072] Some parts of the previously described descriptions have already been presented regarding the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent set of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0073] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0074] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0075] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0076] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0077] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, this specification and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: a memory array; and control logic coupled with the memory array to perform operations including: initiating a program operation on the memory array, the program operation comprising a seed phase; causing a seed voltage to be applied to strings of memory cells in a data block of the memory array during the seed phase of the program operation; causing a positive voltage to be applied to a first plurality of word lines of the data block during the seed phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, the first plurality of word lines comprising a selected word line associated with the program operation, wherein the selected word line is coupled to a first memory cell of the first plurality of memory cells, wherein causing the positive voltage to be applied to the first plurality of word lines of the data block comprises: causing a first positive voltage to be applied to the selected word line, a second positive voltage to be applied to one or more first word lines adjacent to the selected word line, and a third positive voltage to be applied to one or more second word lines adjacent to the one or more first word lines, wherein the third positive voltage is greater than the first positive voltage and less than the second positive voltage, wherein the one or more first word lines adjacent to the selected word line are coupled to one or more of the first plurality of memory cells on a source side of the first memory cell in the string of memory cells, and wherein the one or more second word lines adjacent to the one or more first word lines are coupled to one or more of the first plurality of memory cells on a source side of the memory cells coupled to the one or more first word lines; and causing a ground voltage to be applied to a second plurality of word lines of the data block during the seed phase.

2. The memory device of claim 1, wherein the control logic is to perform further operations including: causing the positive voltage to be applied to one or more word lines coupled to one or more of the first plurality of memory cells on a source side of the first memory cell in the string of memory cells.

3. The memory device of claim 1, wherein the control logic is to perform further operations including: causing a negative voltage to be applied to a third plurality of word lines of the data block during the seed phase, wherein each of the third plurality of word lines is coupled to a corresponding memory cell of a third plurality of memory cells in the string, wherein the third plurality of memory cells are adjacent to the first plurality of memory cells on a source side of the string of memory cells.

4. The memory device of claim 1, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string, wherein the second plurality of memory cells are adjacent to the first plurality of memory cells on a source side of the string of memory cells.

5. The memory device of claim 1, wherein the program operation comprises a plurality of seed phases, a plurality of pass voltage ramp phases, and a plurality of program voltage ramp phases, and wherein the positive voltage is applied to the first plurality of word lines only during a subset of the plurality of seed phases, the subset occurring after a threshold number of the plurality of program voltage ramp phases occur.

6. A method comprising: initiating a program operation on a memory device, the program operation comprising a seed phase; causing a seed voltage to be applied to a string of memory cells in a data block of the memory device during the seed phase of the program operation; causing a positive voltage to be applied to a first plurality of word lines of the data block during the seed phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, the first plurality of word lines comprising a selected word line associated with the program operation, wherein the selected word line is coupled to a first memory cell of the first plurality of memory cells, wherein causing the positive voltage to be applied to the first plurality of word lines of the data block comprises: causing a first positive voltage to be applied to the selected word line, a second positive voltage to be applied to one or more first word lines adjacent to the selected word line, and a third positive voltage to be applied to one or more second word lines adjacent to the one or more first word lines, wherein the third positive voltage is greater than the first positive voltage and less than the second positive voltage, wherein the one or more first word lines adjacent to the selected word line are coupled to one or more of the first plurality of memory cells on a source side of the first memory cell in the string of memory cells, and wherein the one or more second word lines adjacent to the one or more first word lines are coupled to one or more of the first plurality of memory cells on a source side of the memory cells coupled to the one or more first word lines; and causing a ground voltage to be applied to a second plurality of word lines of the data block during the seed phase.

7. The method of claim 6, the method further comprising: causing the positive voltage to be applied to one or more word lines coupled to one or more of the first plurality of memory cells on a source side of the first memory cell in the string of memory cells.

8. The method of claim 6, further comprising: causing a negative voltage to be applied to a third plurality of word lines of the data block during the seed phase, wherein each of the third plurality of word lines is coupled to a corresponding memory cell of a third plurality of memory cells in the string, wherein the third plurality of memory cells are adjacent to the first plurality of memory cells on a source side of the string of memory cells.

9. The method of claim 6, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string, wherein the second plurality of memory cells are adjacent to the first plurality of memory cells on a source side of the string of memory cells.

10. The method of claim 6, wherein the program operation comprises a plurality of seed phases, a plurality of pass voltage ramp phases, and a plurality of program voltage ramp phases, and wherein the positive voltage is only applied to the first plurality of word lines during a subset of the plurality of seed phases, the subset occurring after a threshold number of the plurality of program voltage ramp phases occur.

11. A memory device comprising: a first string of memory cells in a first sub-block of a block of memory cells, the first sub-block comprising a selected sub-block, wherein the first string of memory cells comprises a first plurality of memory cells coupled to a plurality of word lines; and a second string of memory cells in a second sub-block of the block of memory cells, the second sub-block comprising an unselected sub-block, wherein the second string of memory cells comprises a second plurality of memory cells coupled to the plurality of word lines coupled to the first string of memory cells, wherein a first subset of the plurality of word lines is configured to receive a positive voltage signal during a seed phase of a program operation performed on the selected sub-block, wherein each of the first subset of the plurality of word lines is coupled to a corresponding memory cell of a first subset of the second plurality of memory cells in the second string of memory cells, the first subset of the plurality of word lines comprising a selected word line associated with the program operation, wherein the selected word line is coupled to a first memory cell of the second plurality of memory cells, wherein: the selected word line is configured to receive a first positive voltage, one or more first word lines adjacent to the selected word line are configured to receive a second positive voltage, and one or more second word lines adjacent to the one or more first word lines are configured to receive a third positive voltage, wherein the third positive voltage is greater than the first positive voltage and less than the second positive voltage, wherein the one or more first word lines adjacent to the selected word line are coupled to one or more of the second plurality of memory cells on a source side of the first memory cell in the second string of memory cells, and wherein the one or more second word lines adjacent to the one or more first word lines are coupled to one or more of the second plurality of memory cells on a source side of the first memory cell in the second string of memory cells coupled to the one or more first word lines; wherein a second subset of the plurality of word lines of a block of data is configured to receive a ground voltage during the seed phase.

12. The memory device of claim 11, wherein one or more word lines adjacent to the selected word line are configured to receive the positive voltage, wherein the one or more word lines adjacent to the selected word line are coupled to one or more of the second plurality of memory cells on a source side of the first memory cell in the second string of memory cells.

13. The memory device of claim 11, wherein a third subset of the plurality of word lines of the block of data is configured to receive a negative voltage during the seeding phase, wherein each of the third subset of the plurality of word lines is coupled to a corresponding memory cell of a third subset of a third plurality of memory cells in the second string of memory cells, wherein the third subset of the third plurality of memory cells is adjacent to the first subset of the second plurality of memory cells on a source side of the second string of memory cells.

14. The memory device of claim 11, wherein each of the second subset of the plurality of word lines is coupled to a corresponding memory cell of a second subset of the second plurality of memory cells in the second string of memory cells, wherein the second subset of the second plurality of memory cells is adjacent to the first subset of the second plurality of memory cells on a source side of the second string of memory cells.

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