Hybrid flip-chip packaging structure and method of manufacturing the same

Abstract

The application discloses a hybrid embedded packaging structure and a manufacturing method thereof. The structure comprises a substrate, the substrate is provided with a first insulating layer, a conductive copper column, a buried core cavity and a first circuit layer; a first electronic device is arranged inside the buried core cavity, and a terminal surface faces a bottom surface of the substrate; a second electronic device is arranged on a back surface of the first electronic device, and a terminal surface faces a top surface of the substrate; a second insulating layer covers and fills the buried core cavity and an upper layer of the substrate, and partially exposes the first circuit layer and partially exposes the back surface of the first electronic device or the second electronic device; a second circuit layer is electrically connected with the conductive copper column and the terminal of the first electronic device; a wire is electrically connected with the first circuit layer and the terminal of the second electronic device; and a protective cover is arranged on the top surface of the substrate. The packaging structure and the manufacturing method thereof combine embedded packaging and WB packaging, and selectively perform embedded packaging or WB packaging on electronic devices and other components in the packaging, so that the packaging volume is reduced, the production cost is lowered, and the processing period is shortened.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a hybrid embedded packaging structure and its fabrication method. Technical Background

[0002] With the development and advancement of electronic technology, electronic products are evolving towards smaller, thinner, and lighter designs. Meanwhile, the functional requirements of electronic products are becoming increasingly powerful, driving the development of highly integrated and miniaturized packaging structures. Embedded packaging for electronic components has emerged as a result, gradually replacing wire bond (WB) packaging. However, for electronic devices with fewer I / Os, WB packaging offers advantages in cost and processing cycle compared to creating an RDL (redistribution layer) after embedded packaging. Furthermore, the special applications of some devices are difficult to achieve through embedded packaging. For example, devices involving light emission or reception, such as LEDs and photodiodes, suffer from reduced light emission and reception after traditional embedded packaging. Therefore, WB packaging will continue to play an important role in the short term.

[0003] In existing technologies, the traditional WB (Wire Bonding) packaging method involves mounting electronic components onto the surface of a substrate, then performing wire bonding to electrically connect the electronic components to the substrate, and finally injection molding the package. The drawback of this method is that both mounting the electronic components onto the substrate surface and the wire bonding process increase the package size, failing to meet the demands of high-density integration and miniaturization.

[0004] Traditional embedded packaging methods for electronic devices involve mounting electronic components onto a polymer frame or core material within a pre-defined cavity, encapsulating it with plastic material, and then creating an RDL (redistribution layer). The disadvantages of this method are: for electronic devices with a small number of I / Os, embedding the package before creating the RDL results in higher costs and longer processing cycles compared to web packaging; furthermore, due to the specific applications of some devices, it is difficult to achieve this through embedded packaging. For example, for devices involving light emission or reception, such as LEDs and photodiodes, traditional embedded packaging methods negatively impact both light emission and reception.

[0005] Application content

[0006] This application aims to at least partially address one of the technical problems in the related art. To this end, this application proposes a hybrid embedded packaging structure and its fabrication method. By combining embedded packaging and WB packaging, the hybrid embedded packaging achieves high integration and miniaturization while meeting the special packaging requirements of special devices. The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims. The technical solution is as follows:

[0007] In a first aspect, embodiments of this application provide a method for fabricating a hybrid embedded packaging structure, characterized by comprising the following steps:

[0008] Fabricating a substrate, the substrate comprising a first insulating layer, a conductive copper pillar penetrating the first insulating layer, a buried core cavity formed on the first insulating layer, and a first circuit layer electrically connected to the conductive copper pillar;

[0009] A support member is provided at the bottom of the substrate, the support member being used to pre-fix electronic device assemblies;

[0010] The electronic device assembly is pre-fixed inside the support member corresponding to the embedded core cavity. The electronic device assembly includes a first electronic device and a second electronic device. The second electronic device is disposed on the back of the first electronic device, and the terminal surface of the first electronic device faces the support member, while the terminal surface of the second electronic device faces away from the first electronic device.

[0011] The electronic device assembly is encapsulated, exposing a portion of the first circuit layer and the terminals of the second electronic device to form a second insulating layer;

[0012] Remove the support member;

[0013] A second circuit layer is formed on the bottom of the substrate;

[0014] The terminals of the second electronic device are connected to the first circuit layer by wire bonding.

[0015] The hybrid embedded packaging structure fabrication method according to the first aspect of this application has at least the following beneficial effects: First, the hybrid embedded packaging structure fabrication method proposed in this application combines embedded packaging with WB packaging, selectively embedding or WB packaging (wire bonding) of electronic devices and other components, which can reduce production costs and shorten the processing cycle; Second, sensing and photosensitive devices (LEDs, PDs, etc.) can be integrated inside the substrate, and the sensing and photosensitive devices can be exposed, reducing the package size without affecting the transmission / reception of signals by the sensing and photosensitive devices; Third, the second electronic device to be WB is fixed on the back of the embedded first electronic device, and then wire bonding is used to electrically connect the WB second electronic device to the substrate.

[0016] Optionally, in some embodiments of this application, a solder resist layer is formed on the bottom of the substrate and at least a portion of the surface of the second circuit layer; and a surface treatment layer is formed on the surfaces of the first circuit layer and the second circuit layer.

[0017] Optionally, in some embodiments of this application, a protective cover is also applied to the top surface of the substrate.

[0018] Optionally, in some embodiments of this application, the specific steps for fabricating the substrate include:

[0019] Prepare a carrier plate, which, from bottom to top, comprises a core layer, a first metal layer, a second metal layer, an etch barrier layer, and a first metal seed layer;

[0020] A first photoresist layer is fabricated on the surface of the first metal seed layer, and the first photoresist layer is provided with a conductive copper pillar window and a sacrificial copper pillar window.

[0021] Conductive copper pillars and sacrificial copper pillars are respectively fabricated at the locations of the openings in the conductive copper pillars and the openings in the sacrificial copper pillars;

[0022] Remove the first photoresist layer;

[0023] A laminated insulating layer is used to cover the copper pillars. The insulating layer is then thinned to expose the ends of the conducting copper pillars and the sacrificial copper pillars, forming the first insulating layer.

[0024] A second metal seed layer is created on the surface of the exposed copper pillar;

[0025] A photoresist material is applied to the surface of the second metal seed layer, and the photoresist material is exposed and developed to create a first circuit layer pattern, forming a second photoresist layer.

[0026] Electroplating is performed on the circuit to remove the second photoresist layer and the exposed second metal seed layer, forming the first circuit layer.

[0027] Separate the first metal layer and the second metal layer;

[0028] Remove the second metal layer, the etch barrier layer, and the first metal seed layer;

[0029] Photoresist material is applied to both sides, and the photoresist material is exposed and developed to cover the first circuit layer and the conductive copper pillar, exposing the sacrificial copper pillar.

[0030] The sacrificial copper pillar is removed to form the embedded core cavity.

[0031] Optionally, the first electronic device and the second electronic device are connected by an adhesive material.

[0032] Optionally, the terminal block of the second electronic device is also provided with a sensor.

[0033] Optionally, the specific steps of encapsulating the electronic device assembly and exposing a portion of the first circuit layer 503 and the terminals of the second electronic device to form a second insulating layer are as follows:

[0034] Use insulating materials to encapsulate electronic devices;

[0035] The insulating material is processed to expose a portion of the first circuit layer, the terminals of the second electronic device, and the sensor, forming a second insulating layer.

[0036] Optionally, the insulating material used in the second insulating layer is a photosensitive insulating material. By exposing and developing the photosensitive insulating material, a portion of the first circuit layer, the terminals of the second electronic device, and the sensor are exposed to form the second insulating layer.

[0037] Optionally, the specific steps for fabricating the second circuit layer on the bottom of the substrate are as follows:

[0038] A third metal seed layer is formed on the bottom surface of the substrate;

[0039] Photoresist material is applied to both sides by means of film lamination or coating;

[0040] The photoresist material is exposed and developed, the top surface is completely masked, and the bottom surface is used to create the second circuit layer pattern, forming the fifth and sixth photoresist layers.

[0041] Electroplating second line;

[0042] Remove the fifth and sixth photoresist layers;

[0043] The metal seed layer is etched to remove the exposed third metal seed layer, forming the second circuit layer.

[0044] Optionally, the first insulating layer is pure resin or an organic insulating material containing resin and glass fiber.

[0045] Secondly, embodiments of this application provide a method for fabricating a hybrid embedded packaging structure, characterized by comprising the following steps:

[0046] Fabricating a substrate, the substrate comprising a first insulating layer, a conductive copper pillar penetrating the first insulating layer, a buried core cavity formed on the first insulating layer, and a first circuit layer electrically connected to the conductive copper pillar;

[0047] A support member is provided at the bottom of the substrate;

[0048] A first electronic device is pre-fixed inside the support corresponding to the embedded core cavity, with the terminal surface of the first electronic device facing the support.

[0049] The first electronic device is packaged, exposing a portion of the first circuit layer and the back surface of the first electronic device to form a second insulating layer, wherein the second insulating layer forms at least two openings on the back surface of the first electronic device;

[0050] Remove the support member;

[0051] A second circuit layer is formed on the bottom of the substrate;

[0052] A second electronic device is disposed at the opening in the second insulating layer on the back of the first electronic device, with the terminal surface of the second electronic device facing away from the first electronic device;

[0053] The terminals of the second electronic device are connected to the first circuit layer by wire bonding.

[0054] Optionally, in some embodiments of this application, a solder resist layer is formed on the bottom of the substrate and at least a portion of the surface of the second circuit layer; and a surface treatment layer is formed on the surfaces of the first circuit layer and the second circuit layer.

[0055] Optionally, in some embodiments of this application, a protective cover is also applied to the top surface of the substrate.

[0056] The hybrid embedded packaging structure fabrication method according to the second aspect of this application has at least the following beneficial effects: First, the hybrid embedded packaging structure fabrication method proposed in this application combines embedded packaging with WB packaging, selectively embedding or WB packaging (wire bonding) of electronic devices and other components, which can reduce production costs and shorten the processing cycle; Second, sensing and photosensitive devices (LEDs, PDs, etc.) can be integrated inside the substrate, and the sensing and photosensitive devices can be exposed, reducing the package size without affecting the transmission / reception of signals by the sensing and photosensitive devices; Third, the second electronic device to be WB is fixed on the back of the embedded first electronic device, and then wire bonding is used to electrically connect the WB second electronic device to the substrate; Fourth, multiple second electronic devices to be WB can be set as needed, and the types of each electronic component can be arbitrarily combined, and can be the same or different, making the design very flexible.

[0057] Thirdly, embodiments of this application provide a hybrid embedded packaging structure, characterized in that it includes:

[0058] The substrate 500 includes a first insulating layer, a conductive copper pillar penetrating the first insulating layer, a buried core cavity formed on the first insulating layer, and a first circuit layer electrically connected to the conductive copper pillar.

[0059] A first electronic device is disposed inside the embedded core cavity, and the terminal surface of the first electronic device faces the bottom surface of the substrate;

[0060] The second electronic device is disposed on the back side of the first electronic device, and the terminal surface of the second electronic device faces the top surface of the substrate;

[0061] The second insulating layer covers and fills the upper layer of the buried core cavity and the substrate, and exposes a portion of the first circuit layer and a portion of the second electronic device or the back of a portion of the first electronic device.

[0062] A second circuit layer is disposed on the bottom surface of the substrate, and the second circuit layer is electrically connected to the conductive copper pillar and the terminal of the first electronic device.

[0063] The wire electrically connects the first circuit layer and the terminals of the second electronic device.

[0064] The hybrid embedded packaging structure according to the third aspect of this application has at least the following beneficial effects: First, the hybrid embedded packaging structure manufacturing method proposed in this application combines embedded packaging with WB packaging, selectively embedding or WB packaging (wire bonding) of electronic devices and other components, which can reduce production costs and shorten the processing cycle; Second, sensing and photosensitive devices (LEDs, PDs, etc.) can be integrated inside the substrate, and the sensing and photosensitive devices can be exposed, reducing the package size without affecting the transmission / reception of signals by the sensing and photosensitive devices; Third, the second electronic device to be WB is fixed on the back of the embedded first electronic device, and then wire bonding is used to electrically connect the WB second electronic device to the substrate; Fourth, multiple second electronic devices to be WB can be set as needed, and the types of each electronic component can be arbitrarily combined, and can be the same or different, making the design very flexible.

[0065] Optionally, the second electronic device is provided, and the second insulating layer covers and fills the buried core cavity and the upper layer of the substrate, exposing a portion of the first circuit layer and the terminals of the second electronic device.

[0066] Optionally, the terminal face of the second electronic device is further provided with a sensor, and the second insulating layer covers and fills the buried core cavity and the upper layer of the substrate, exposing a portion of the first circuit layer, the terminals of the second electronic device, and the sensor.

[0067] Optionally, at least two second electronic devices are provided, the second insulating layer covers and fills the upper layer of the buried core cavity and the substrate, and exposes a portion of the first circuit layer and the back side of a portion of the first electronic device, and the second insulating layer forms at least two openings on the back side of the first electronic device, with each second electronic device disposed in a corresponding opening.

[0068] Optionally, when at least two second electronic devices are provided, the at least two second electronic devices may use the same electronic components or different electronic components.

[0069] Optionally, the second electronic device is disposed on the back side of the first electronic device 601 by means of an adhesive material.

[0070] Optionally, it may also include a solder resist layer, which at least partially covers the second circuit layer.

[0071] Optionally, a protective cover is also included, which is disposed on the top surface of the substrate.

[0072] Optionally, the protective cover is a light-transmitting cover.

[0073] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0074] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0075] Figure 1 This is a flowchart of the steps in the method for fabricating a hybrid embedded packaging structure provided in the first embodiment of this application;

[0076] Figures 2 to 17 This is a cross-sectional view corresponding to the steps of the packaging substrate fabrication method provided in the first embodiment of this application;

[0077] Figure 18 This is a flowchart of the steps in the method for fabricating a hybrid embedded packaging structure provided in the second embodiment of this application;

[0078] Figures 19 to 25 This is a cross-sectional view corresponding to the steps of the packaging substrate fabrication method provided in the second embodiment of this application;

[0079] Figure 26 This is a cross-sectional view of the packaging substrate provided in the first embodiment of this application;

[0080] Figure 27 This is a cross-sectional view of the packaging substrate provided in the second embodiment of this application. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. Therefore, they do not have substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives achieved by this application, should still fall within the scope of the technical content disclosed in this application.

[0082] This section will describe in detail the specific embodiments of this application. Preferred embodiments of this application are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of this application, but they should not be construed as limiting the scope of protection of this application.

[0083] In the description of the application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. If the description mentions "first" or "second," it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order of the technical features indicated.

[0084] Reference Figure 1 An embodiment of this application provides a method for fabricating a hybrid embedded packaging structure, comprising the following steps:

[0085] S100, fabricating a substrate 500, the substrate including a first insulating layer 502, a conductive copper pillar 501 penetrating the first insulating layer 502, a buried core cavity 504 formed in the first insulating layer 502, and a first circuit layer 503 electrically connected to the conductive copper pillar 501; specifically, as shown... Figure 2-11 As shown,

[0086] Further reference Figure 2 A carrier plate 100 is prepared, which includes, from bottom to top, a core layer 101, a first metal layer 102, a second metal layer 103, an etch barrier layer 104, and a first metal seed layer 105. In some embodiments, the first metal layer 102 and the second metal layer 103 can be made of copper, and the two are physically bonded together and can be separated. After the first and second metal layers 102 and 103 are separated, when etching the second metal layer 103, the etch barrier layer 104 can protect the circuits and copper pillars of the substrate and prevent over-etching. The etch barrier layer 104 can be made of nickel. The first metal seed layer 105 can be made of copper with a thickness of 1-3 μm, serving as the conductive basis for subsequent electroplating.

[0087] Further reference Figure 3 A first photoresist layer 201 is fabricated on the surface of the first metal seed layer 105. The first photoresist layer 201 is provided with a conductive copper pillar window 202 and a sacrificial copper pillar window 203. Specifically, a photoresist material is applied to the surface of the first metal seed layer 105. The photoresist material can be applied by film lamination or coating. The photoresist material is exposed and developed to create a copper pillar pattern and form the first photoresist layer 201. The first photoresist layer 201 includes the conductive copper pillar window 202 and the sacrificial copper pillar window 203. The copper pillar is not limited to a cylinder and can be a cube, cuboid, etc.

[0088] Further reference Figure 4 Copper pillar electroplating is performed, and conductive copper pillars 501 and sacrificial copper pillars 302 are fabricated at the positions of conductive copper pillar opening 202 and sacrificial copper pillar opening 203, respectively. The thickness of copper pillars 501 and 302 is defined according to actual needs and is usually lower than the thickness of the first photoresist layer 201.

[0089] Further reference Figure 5 The first photoresist layer can be removed by stripping; the laminated insulating layer covering the copper pillars can also be removed by stripping; the insulating layer can be thinned by plasma etching or grinding to expose the ends of the conductive copper pillars 501 and the sacrificial copper pillars 302, forming the first insulating layer 502.

[0090] Further reference Figure 6 A second metal seed layer 401 is fabricated on the surface of the exposed copper pillar. In some embodiments, copper plating or ion sputtering can be selected. The second metal seed layer 401 can be Cu or Ti+Cu.

[0091] Further reference Figure 7 A photoresist material is applied to the surface of the second metal seed layer. In some embodiments, a film or coating method can be selected. The photoresist material is exposed and developed to create a first circuit layer pattern and form the second photoresist layer 402.

[0092] Further reference Figure 8 The circuit is electroplated, and the thickness is defined according to actual needs. It is usually lower than the thickness of the second photoresist layer 402. The second photoresist layer 402 and the exposed second metal seed layer 401 are removed to form the first circuit layer 503. In some embodiments, the second photoresist layer can be removed by stripping, and the exposed second metal seed layer can be removed by etching.

[0093] Further reference Figure 9 Separate the first metal layer 102 and the second metal layer 103; remove the second metal layer 103, the etch barrier layer 104 and the first metal seed layer 105; in some embodiments, the removal of the first metal layer on the separation surface is usually done by etching, the removal of the etch barrier layer is usually done by etching with a specific chemical solution, preferably using a nickel etching solution, and the removal of the first metal seed layer is usually done by etching.

[0094] Further reference Figure 10 Photoresist material is applied to both sides, and can be applied by film or coating. The photoresist material is exposed and developed to cover the first circuit layer and the conductive copper pillar 501, exposing the sacrificial copper pillar 302, forming the third photoresist layer 404 and the fourth photoresist layer 405.

[0095] Further reference Figure 11 The sacrificial copper pillar 302 is removed to form a buried core cavity 504, resulting in a substrate 500 containing a conductive copper pillar 501, a first insulating layer 502, a first circuit layer 503, and a buried core cavity 504. In some embodiments, the sacrificial copper pillar is etched, and the first and fourth photoresist layers can be removed by stripping.

[0096] S200, see appendix Figure 12 A support member 505 is provided at the bottom of the substrate 500. The support member 505 is used to pre-fix electronic device assemblies. In some embodiments, the support member 505 may be made of tape, and the adhesive side of the tape helps to pre-fix the electronic devices.

[0097] S300, an electronic component assembly is pre-fixed inside the support member 505 corresponding to the embedded core cavity 504. The electronic component assembly includes a first electronic component 601 and a second electronic component 602. The second electronic component 602 is disposed on the back of the first electronic component 601, and the terminal surface of the first electronic component 601 faces the support member, while the terminal surface of the second electronic component faces away from the first electronic component 601. In some embodiments, the first electronic component 601 and the second electronic component 602 can be bonded together by an adhesive material 603. The bonding of the electronic components can be done by bonding the first electronic component 601, the adhesive material 603, and the second electronic component 602 in sequence, or by directly bonding the first electronic component 601, the adhesive material 603, and the second electronic component 602 together as a whole. That is, the first electronic component 601, the adhesive material, and the second electronic component 602 are bonded together as a whole beforehand, and then the whole is attached to the tape 505.

[0098] S400, see appendix Figure 13 The electronic device components are encapsulated, exposing a portion of the first circuit layer 503 and the terminals of the second electronic device to form a second insulating layer 701. In some embodiments, a photosensitive insulating material can be used to encapsulate the chip, and then the photosensitive insulating material is exposed and developed to expose a portion of the first circuit layer and the terminals of the second electronic device to form the second insulating layer 701. Alternatively, ordinary non-photosensitive insulating materials can be used for encapsulation by vacuum pressing, lamination, and coating, and then the insulating material can be removed by laser etching, plasma etching, or other methods to form a window. Alternatively, encapsulation can be performed by partial injection molding to form a window that exposes a portion of the terminals.

[0099] S500, see appendix Figure 14 Remove the support member 505; in some embodiments, after removing the support member 505, a third metal seed layer 702 is first fabricated on the bottom surface of the base 500 to prepare for the fabrication of the second circuit layer. The third metal seed layer 702 can be made by copper plating or ion sputtering. The third metal seed layer can be Cu or Ti+Cu.

[0100] S600, see appendix Figure 15 , 16 And 17, a second circuit layer 705 and a solder mask layer 706 are fabricated on the bottom of the substrate 500. The specific steps are as follows:

[0101] Photoresist material can be applied to both sides by either lamination or coating.

[0102] The photoresist material is exposed and developed, the top surface is completely masked, and the bottom surface is patterned with the second circuit layer to form the fifth photoresist layer 703 and the sixth photoresist layer 704.

[0103] The thickness of the second line electroplating is defined according to actual needs and is usually lower than the thickness of the sixth photoresist layer.

[0104] To remove the fifth and sixth photoresist layers, a stripping method can usually be chosen.

[0105] The metal seed layer is etched to remove the exposed third metal seed layer and form the second circuit layer 705.

[0106] A 706 solder mask layer is applied to the bottom surface. The application of the solder mask layer can be customized as needed.

[0107] S700 has a surface treatment layer 707 formed by processing the surfaces of the first circuit layer 503 and the second circuit layer 705. The surface treatment layer can be anti-oxidation, nickel-palladium-gold plating, tin plating, silver plating, etc. When processing the surface, it is usually necessary to shield the windowed area of ​​the chip area.

[0108] S800, see attached document Figure 18 The second electronic device is connected to the first circuit layer 503 by wire bonding, which can be done by gold wire bonding, copper wire bonding, etc.

[0109] S900, apply a protective cover. After wire bonding, apply a protective cover 708 to the top surface. In some embodiments, a transparent glass material can be selected. When the second electronic device has a sensor or is a light-emitting device such as an LED, the operation of the sensor, LED, etc. will not be affected while the protective encapsulation is performed.

[0110] The hybrid embedded packaging structure fabrication method of the first aspect of this application combines embedded packaging with wire bonding (WB) packaging, selectively performing either embedded packaging or WB packaging (wire bonding) on ​​the packaged chip or other components. For chips with a large number of I / Os, WB packaging is more difficult and costly, so embedded packaging can be chosen; for chips with a small number of I / Os, embedded packaging has a longer processing cycle and is more costly, so WB can be chosen; for special applications of special devices, such as LEDs and photodiodes designed to emit or receive light, WB can be chosen, exposing the device to achieve photoelectric sensing. Meanwhile, the WB packaging structure in this application involves fixing the chip or other electronic component to be WB-bonded to the back of the embedded chip or other electronic component, and then electrically connecting the WB chip or other electronic component to the substrate via wire bonding. Compared with the traditional method of mounting WB devices on the substrate surface and then wire bonding, this structure reduces the package size, meeting the development needs of high-density integration and miniaturization of packages.

[0111] In some embodiments, the terminal block of the second electronic device 602 is further provided with a sensor 6022, and the sensor needs to be exposed after the electronic device assembly is packaged.

[0112] In some embodiments, the first insulating layer may be made of pure resin or an organic insulating material containing resin and glass fiber.

[0113] Reference Figure 17 Another embodiment of this application provides a method for fabricating a hybrid embedded packaging structure, the first two steps of which are the same as in the first embodiment, specifically including the following steps:

[0114] S100b, fabricating a substrate 500, the substrate includes a first insulating layer 502, a conductive copper pillar 501 penetrating the first insulating layer 502, a buried core cavity 504 formed on the first insulating layer 502, and a first circuit layer 503 electrically connected to the conductive copper pillar 501.

[0115] S200b, a support member 505 is provided at the bottom of the substrate 500;

[0116] S300b, further reference Figure 19 The first electronic device 601 is pre-fixed inside the support 505 corresponding to the embedded core cavity 504, and the terminal surface 6011 of the first electronic device 601 faces the support.

[0117] S400b, further reference Figure 20 The first electronic device 601 is encapsulated, exposing a portion of the first circuit layer 503 and the back side of the first electronic device to form a second insulating layer. The second insulating layer forms at least two windows on the back side of the first electronic device. In this embodiment, a photosensitive insulating material is specifically used to encapsulate the chip. The photosensitive insulating material is exposed and developed to expose a portion of the first circuit layer and the back side of a portion of the first electronic device, forming a second insulating layer 701. The second insulating layer forms two windows on the back side of the first electronic device, namely windows 902 and 903. It should be noted that the number of windows is not limited to two; it can be multiple, defined according to actual needs. This embodiment uses two windows as an example. Alternatively, ordinary non-photosensitive insulating materials can be used for encapsulation through vacuum pressing, lamination, and coating, followed by removal of the insulating material using laser etching, plasma etching, or other methods to form windows. Alternatively, partial injection molding can be used for encapsulation to form windows exposing partial terminals.

[0118] S500b, further reference Figure 21 Remove the support 505 and fabricate a third metal seed layer 702 on the bottom surface of the substrate. The method can be copper plating or ion sputtering. The third metal seed layer can be Cu or Ti+Cu.

[0119] S600b, further reference Figure 22 , 23 And 24, a second circuit layer 705 and a solder mask layer 706 are fabricated on the bottom of the substrate 500, specifically as follows:

[0120] Photoresist material is applied to both sides, and can be applied by lamination or coating.

[0121] The photoresist material is exposed and developed, the top surface is completely masked, and the bottom surface is patterned with the second circuit layer to form the fifth photoresist layer 703 and the sixth photoresist layer 704.

[0122] The thickness of the second line electroplating is defined according to actual needs and is usually lower than the thickness of the sixth photoresist layer.

[0123] To remove the fifth and sixth photoresist layers, a stripping method can usually be chosen.

[0124] The metal seed layer is etched to remove the exposed third metal seed layer and form the second circuit layer 705.

[0125] A 706 solder resist layer is applied to the bottom surface;

[0126] S700b, the first circuit layer 503 and the second circuit layer 705 are processed to form a surface treatment layer, that is, selective surface treatment is performed on both sides to form a surface treatment layer 707. The surface treatment layer 707 can be selected from anti-oxidation, nickel palladium gold, tin plating, silver plating, etc. When the surface is processed, it is usually necessary to shield the window position of the chip area.

[0127] S800b, further reference Figure 25 A second electronic device 602 is disposed at an opening in the second insulating layer on the back of the first electronic device, with the terminal face of the second electronic device facing away from the first electronic device 601. Specifically, an adhesive material 603 is applied to each opening in the second insulating layer on the back of the first electronic device, and a second electronic device 602 is attached thereto. Each second electronic device 602 can be the same or different electronic devices depending on the actual situation. In this embodiment, two different electronic devices are disposed, one being an LED chip and the other being a photodiode PD. The back faces of the two different second electronic devices are tightly bonded to the back face of the first electronic device through the adhesive material.

[0128] S900b, wire bonding, connects the terminals of the second electronic device to the first circuit layer 503;

[0129] S1000b, apply protective cover 708.

[0130] Reference Figure 26 One embodiment of this application provides a hybrid embedded packaging structure, including:

[0131] The substrate includes a first insulating layer 502, a conductive copper pillar 501 penetrating the first insulating layer 502, a buried core cavity 504 formed on the first insulating layer 502, and a first circuit layer 503 electrically connected to the conductive copper pillar 501.

[0132] The first electronic device 601 is disposed inside the buried core cavity 504, and the terminal surface of the first electronic device 601 faces the bottom surface of the substrate.

[0133] The second electronic device is disposed on the back side of the first electronic device, and the terminal surface of the second electronic device is also disposed thereon.

[0134] The second electronic device 602 is disposed on the back side of the first electronic device 601, and the terminal surface of the second electronic device faces the top surface of the substrate.

[0135] The second insulating layer 503 covers the upper layer of the buried core cavity 504 and the substrate, and exposes a portion of the first circuit layer 503 and a portion of the second electronic device 602 or the back of the portion of the first electronic device.

[0136] The second circuit layer 705 is disposed on the bottom surface of the substrate 500. The second circuit layer 705 is electrically connected to the conductive copper pillar 501 and the terminal 6011 of the first electronic device 601.

[0137] A wire electrically connects the first circuit layer 503 to the terminal 6021 of the second electronic device 602.

[0138] According to the hybrid embedded packaging structure of the embodiments of this application, the embedded packaging and WB packaging are combined. By selectively embedding or WB packaging (wire bonding) of electronic devices and other components, production costs can be reduced and processing cycles can be shortened. Sensing and photosensitive devices (LEDs, PDs, etc.) can be integrated inside the substrate, while the sensing and photosensitive devices can be exposed, reducing the package size without affecting the transmission / reception of signals by the sensing and photosensitive devices. The second electronic device to be WB is fixed on the back of the embedded first electronic device, and then wire bonding is used to electrically connect the WB second electronic device to the substrate.

[0139] In some embodiments, the second electronic device 602 is provided with a second insulating layer 503 covering the upper layer of the buried core cavity 504 and the substrate, and exposing a portion of the first circuit layer 503 and the terminals of the second electronic device 602.

[0140] In some embodiments, the terminal face of the second electronic device 602 is further provided with a sensor, and the second insulating layer 503 covers the upper layer of the buried core cavity 504 and the substrate, and exposes a portion of the first circuit layer 503 as well as the terminals and sensor of the second electronic device 602.

[0141] In some embodiments, a second metal seed layer 401 and a third metal seed layer 702 are also included. The second metal seed layer 401 is disposed between the conductive copper pillar 501 and the first circuit layer 503, and the third metal seed layer 702 is disposed between the conductive copper pillar 501 and the second circuit layer 705.

[0142] In some embodiments, further references Figure 27 At least two second electronic devices 602 are provided. A second insulating layer 503 covers the upper layer of the buried core cavity 504 and the substrate, exposing a portion of the first circuit layer 503 and the back side of a portion of the first electronic device 601. The second insulating layer 503 forms at least two windows on the back side of the first electronic device 601, and each second electronic device 602 is disposed within a corresponding window. Multiple second electronic devices to be used for WB can be provided, and the types of each electronic component can be arbitrarily combined, either the same or different, making the design very flexible.

[0143] In some embodiments, when at least two second electronic devices 602 are provided, the at least two second electronic devices 602 may use the same electronic components or different electronic components.

[0144] In some embodiments, the second electronic device is disposed on the back side of the first electronic device 601 by means of an adhesive material.

[0145] In some embodiments, a solder mask layer 706 is also included, which at least partially covers the second circuit layer 705;

[0146] In some embodiments, a protective cover 708 is also included, disposed on the top surface of the substrate 500, to further protect the package; in order not to affect the operation of electronic devices such as LEDs and PDs, the protective cover may also be a light-transmitting cover, such as a glass light-transmitting cover or a plastic light-transmitting cover.

[0147] The above is a detailed description of the preferred embodiments of this application. However, this application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A method for fabricating a hybrid embedded encapsulation structure, characterized in that, Includes the following steps: Fabricating a substrate, the substrate comprising a first insulating layer, a conductive copper pillar penetrating the first insulating layer, a buried core cavity formed on the first insulating layer, and a first circuit layer electrically connected to the conductive copper pillar; A support member is provided at the bottom of the substrate, the support member being used to pre-fix electronic device assemblies; The electronic device assembly is pre-fixed inside the support member corresponding to the embedded core cavity. The electronic device assembly includes a first electronic device and a second electronic device. The second electronic device is disposed on the back of the first electronic device, and the terminal surface of the first electronic device faces the support member, while the terminal surface of the second electronic device faces away from the first electronic device. The electronic device assembly is encapsulated, exposing a portion of the first circuit layer and the terminals of the second electronic device to form a second insulating layer; Remove the support member; A second circuit layer is formed on the bottom of the substrate; Wire bonding is performed to connect the terminals of the second electronic device to the first circuit layer; The specific steps for fabricating the substrate include: Prepare a carrier plate, which, from bottom to top, comprises a core layer, a first metal layer, a second metal layer, an etch barrier layer, and a first metal seed layer; A first photoresist layer is fabricated on the surface of the first metal seed layer, and the first photoresist layer is provided with a conductive copper pillar window and a sacrificial copper pillar window. Conductive copper pillars and sacrificial copper pillars are respectively fabricated at the locations of the openings in the conductive copper pillars and the openings in the sacrificial copper pillars; Remove the first photoresist layer; A laminated insulating layer is used to cover the copper pillars. The insulating layer is then thinned to expose the ends of the conducting copper pillars and the sacrificial copper pillars, forming the first insulating layer. A second metal seed layer is created on the surface of the exposed copper pillar; A photoresist material is applied to the surface of the second metal seed layer, and the photoresist material is exposed and developed to create a first circuit layer pattern, forming a second photoresist layer. Electroplating is performed to remove the second photoresist layer and the exposed second metal seed layer, forming the first circuit layer. Separate the first metal layer and the second metal layer; Remove the second metal layer, the etch barrier layer, and the first metal seed layer; Photoresist material is applied to both sides, and the photoresist material is exposed and developed to cover the first circuit layer and the conductive copper pillar, exposing the sacrificial copper pillar. The sacrificial copper pillar is removed to form the embedded core cavity.

2. The method for fabricating a hybrid embedded encapsulation structure according to claim 1, characterized in that, After the second circuit layer is fabricated, the following steps are also included: A solder resist layer is formed on the bottom of the substrate and on at least a portion of the surface of the second circuit layer; A surface treatment layer is formed by processing the surfaces of the first circuit layer and the second circuit layer.

3. The method for fabricating a hybrid embedded packaging structure according to claim 1, characterized in that, It also includes applying a protective cover to the top surface of the substrate.

4. The method for fabricating a hybrid embedded encapsulation structure according to any one of claims 1-3, characterized in that, The first electronic device and the second electronic device are connected by an adhesive material.

5. The method for fabricating a hybrid embedded encapsulation structure according to any one of claims 1-3, characterized in that, The terminal block of the second electronic device is also equipped with a sensor.

6. The method for fabricating a hybrid embedded packaging structure according to claim 5, characterized in that, The specific steps for encapsulating the electronic device assembly and exposing a portion of the first circuit layer and the terminals of the second electronic device to form a second insulating layer are as follows: Use insulating materials to encapsulate electronic devices; The insulating material is processed to expose a portion of the first circuit layer, the terminals of the second electronic device, and the sensor, forming a second insulating layer.

7. The method for fabricating a hybrid embedded packaging structure according to claim 6, characterized in that, The second insulating layer uses a photosensitive insulating material. By exposing and developing the photosensitive insulating material, a portion of the first circuit layer, the terminals of the second electronic device, and the sensor are exposed to form the second insulating layer.

8. The method for fabricating a hybrid embedded encapsulation structure according to any one of claims 1-3, characterized in that, The specific steps for fabricating the second circuit layer on the bottom of the substrate are as follows: A third metal seed layer is formed on the bottom surface of the substrate; Photoresist material is applied to both sides by means of film lamination or coating; The photoresist material is exposed and developed, the top surface is completely masked, and the bottom surface is used to create the second circuit layer pattern, forming the fifth and sixth photoresist layers. Electroplating second line; Remove the fifth and sixth photoresist layers; The metal seed layer is etched to remove the exposed third metal seed layer, forming the second circuit layer.

9. The method for fabricating a hybrid embedded packaging structure according to claim 1, characterized in that, The first insulating layer is pure resin or an organic insulating material containing resin and glass fiber.

10. A method for fabricating a hybrid embedded encapsulation structure, characterized in that, Includes the following steps: Fabricating a substrate, the substrate comprising a first insulating layer, a conductive copper pillar penetrating the first insulating layer, a buried core cavity formed on the first insulating layer, and a first circuit layer electrically connected to the conductive copper pillar; A support member is provided at the bottom of the substrate; A first electronic device is pre-fixed inside the support corresponding to the embedded core cavity, with the terminal surface of the first electronic device facing the support. The first electronic device is packaged, exposing a portion of the first circuit layer and the back surface of the first electronic device to form a second insulating layer, wherein the second insulating layer forms at least two openings on the back surface of the first electronic device; Remove the support member; A second circuit layer is formed on the bottom of the substrate; A second electronic device is disposed at the opening in the second insulating layer on the back of the first electronic device, with the terminal surface of the second electronic device facing away from the first electronic device; The terminals of the second electronic device are connected to the first circuit layer by wire bonding.

11. A hybrid embedded packaging structure, characterized in that, include: The substrate includes a first insulating layer, a conductive copper pillar penetrating the first insulating layer, a buried core cavity formed on the first insulating layer, and a first circuit layer electrically connected to the conductive copper pillar. A first electronic device is disposed inside the embedded core cavity, and the terminal surface of the first electronic device faces the bottom surface of the substrate; The second electronic device is disposed on the back side of the first electronic device, and the terminal surface of the second electronic device faces the top surface of the substrate; The second insulating layer covers and fills the upper layer of the buried core cavity and the substrate, and exposes a portion of the first circuit layer and a portion of the second electronic device or the back of a portion of the first electronic device. A second circuit layer is disposed on the bottom surface of the substrate, and the second circuit layer is electrically connected to the conductive copper pillar and the terminal of the first electronic device. A wire electrically connects the first circuit layer and the terminals of the second electronic device; The second electronic device is provided in at least two, the second insulating layer covers and fills the buried core cavity and the upper layer of the substrate, and exposes a portion of the first circuit layer and the back of a portion of the first electronic device, and the second insulating layer forms at least two openings on the back of the first electronic device, with each second electronic device disposed in a corresponding opening.

12. The hybrid embedded packaging structure according to claim 11, characterized in that, The second electronic device is provided, and the second insulating layer covers and fills the buried core cavity and the upper layer of the substrate, and exposes a portion of the first circuit layer and the terminals of the second electronic device.

13. The hybrid embedded packaging structure according to claim 12, characterized in that, The terminal face of the second electronic device is also provided with a sensor. The second insulating layer covers and fills the buried core cavity and the upper layer of the substrate, and exposes part of the first circuit layer, the terminals of the second electronic device, and the sensor.

14. The hybrid embedded packaging structure according to claim 11, characterized in that, When at least two second electronic devices are provided, the at least two second electronic devices may use the same electronic components or different electronic components.

15. The hybrid embedded packaging structure according to claim 11, characterized in that, The second electronic device is disposed on the back of the first electronic device by means of an adhesive material.

16. The hybrid embedded packaging structure according to claim 11, characterized in that, It also includes a solder resist layer, which at least partially covers the second circuit layer.

17. The hybrid embedded packaging structure according to claim 11, characterized in that, It also includes a protective cover disposed on the top surface of the substrate.

18. The hybrid embedded packaging structure according to claim 17, characterized in that, The protective cover is a light-transmitting cover.

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