Microelectronic device including transfer word line structure and related electronic system and method

Abstract

The present application relates to a microelectronic device including a transfer wordline structure and to related electronic systems and methods. The microelectronic device includes: a first column of semiconductor material; a second column of the semiconductor material, the second column of the semiconductor material is adjacent to the first column of the semiconductor material; an active wordline, the active wordline extending between the first column and the second column; and a transfer wordline, the transfer wordline extending on a side of the second column opposite to the active wordline, the transfer wordline extending into an isolation region within the semiconductor material, the isolation region including a lower portion and an upper portion, the upper portion having a substantially circular cross-sectional shape and a lateral dimension larger than the lower portion. Related microelectronic devices, electronic systems and methods are also described.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. patent application serial number 16 / 899,339, filed on June 11, 2020, entitled “MICROELECTRONIC DEVICES INCLUDING PASSING WORD LINESTRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS.” Technical Field

[0003] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More specifically, the present disclosure relates to methods of forming microelectronic devices, and to related microelectronic devices and electronic systems. Background Art

[0004] Conventional volatile memory cells such as dynamic random access memory (DRAM) cells may include a memory storage element and a transistor. The memory storage element may, for example, include a capacitor (e.g., sometimes referred to as a "cell capacitor" or "storage capacitor") configured to store a logic state (e.g., a binary value of "0" or "1") defined by the charge stored in the capacitor. The transistor may be referred to as an "access transistor" in the art. The transistor conventionally includes a channel region between a pair of source / drain regions and further includes a gate configured to electrically connect the source / drain regions to each other through the channel region. The channel region conventionally includes a semiconductor material such as silicon.

[0005] To charge, discharge, read, or recharge the capacitor, the transistor can be selectively turned to an "on" state, where current flows between the source and drain regions through the channel region of the transistor. t ) applied to the gate induces an inversion layer in the channel region, thereby causing current to flow between the drain region and the source region. The transistor can be selectively turned to an "off" state, in which the flow of current essentially stops.

[0006] In the off state, it is expected that the capacitor associated with the transistor maintains the stored charge through the transistor without change (e.g., leakage thereof). However, conventional volatile memory cells may exhibit discharge of current over time and loss in the stored charge. Therefore, even in the "off" state where the source and drain regions of the associated transistor are electrically isolated (e.g., when there is no inversion layer in the channel region) and the memory cell is not selected (e.g., not selected), current may leak from the capacitor through the transistor. This off-state current is referred to in the art as subthreshold leakage current. Undesirable charge leakage from the capacitor requires that the capacitor be constantly refreshed (e.g., recharged) to maintain the logical state of the memory cell. However, refreshing the charge on the capacitor increases the power consumption of the microelectronic device associated with the memory cell.

[0007] In addition to maintaining a low refresh rate, it is desirable to reduce the amount that unselected memory cells are disturbed when a voltage is applied to a pass word line (e.g., a word line that is not electrically coupled to an unselected memory cell, but is located near (e.g., adjacent) to an unselected memory cell. In some cases, applying a voltage to a word line adjacent to an unselected memory cell can cause current to leak or capacitors associated with the unselected memory cell to change through the drain of the unselected memory cell. The leakage can increase the required refresh rate of the unselected memory cell and affect the performance of the microelectronic device. Summary of the invention

[0008] Embodiments disclosed herein relate to a microelectronic device comprising: a first column of semiconductor material; a second column of the semiconductor material, the second column of the semiconductor material being adjacent to the first column of the semiconductor material; an active word line, the active word line extending between the first column and the second column; and a transfer word line, the transfer word line extending on a side of the second column opposite to the active word line, the transfer word line extending into an isolation region within the semiconductor material, the isolation region comprising a lower portion and an upper portion, the upper portion having a substantially circular cross-sectional shape and a lateral dimension larger than the lower portion.

[0009] According to another embodiment, a microelectronic device includes: a first column of semiconductor material; a second column of semiconductor material, the second column of semiconductor material is adjacent to the first column of semiconductor material, and the lateral dimension of the second column is smaller than the lateral dimension of the first column; a first electrode structure, the first electrode structure is between the first column and each second column in the second column; and a second electrode structure, the second electrode structure is on a side of the second column opposite to the first electrode structure.

[0010] Additional embodiments include a method of forming a microelectronic device, the method comprising forming an isolation structure in a semiconductor material. Forming the isolation structure comprises: forming a first opening pattern in the material; forming a second opening pattern in the material laterally offset from the first opening pattern; transferring the first opening pattern and the second opening pattern to a base material; and filling the openings in the base material with an insulating material. The method further comprises: removing a portion of the insulating material to form an opening above the isolation structure; forming a dielectric material within the opening; and forming a conductive material adjacent to the dielectric material.

[0011] Still other embodiments relate to an electronic system comprising an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device and comprising at least one microelectronic device. The at least one microelectronic device comprises an embedded access device, the embedded access device comprising: a first electrode, the first electrode between a first pillar of semiconductor material and a second pillar of the semiconductor material; and an oxide material, the oxide material between the first electrode and each of the first pillar and the second pillar. The at least one microelectronic device further comprises a transfer word line structure, the transfer word line structure adjacent to the second pillar, the transfer word line structure comprising: a second electrode, the second electrode adjacent to the second pillar; and another oxide material, the another oxide material between the second electrode and the second pillar. The at least one microelectronic device further comprises an isolation structure, the isolation structure being located directly below the transfer word line structure and comprising a widened portion, the widened portion having a lateral dimension greater than a lateral dimension of the transfer word line structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A to Figure 1Z is a simplified cross-sectional view showing a method of forming a microelectronic device according to an embodiment of the present disclosure ( Figure 1A , Figure 1C , Figure 1E , Figure 1G to Figure 1L , Figure 1N , Figure 1P to Figure 1R , Figure 1U , Figure 1V as well as Figure 1X to Figure 1Z ) and top view ( Figure 1B , Figure 1D , Figure 1F , Figure 1M , Fig.1O , Figure 1S , Figure 1T and Figure 1W );

[0013] Figure 2is a simplified cross-sectional view of a microelectronic device according to an embodiment of the present disclosure;

[0014] Figure 3 is a block diagram of an electronic system according to an embodiment of the present disclosure; and

[0015] Figure 4 is a block diagram of a processor-based system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The illustrations contained herein are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or integrated circuit thereof, but are merely idealized representations used to describe the embodiments herein. Elements and features common between the figures may retain the same numerical designations, except as follows: To facilitate the following description, the figure number begins with the number of the figure that introduces or most fully describes the element.

[0017] The following description provides specific details, such as material type, material thickness and processing conditions, in order to provide a comprehensive description of the embodiments described herein. However, it will be appreciated by those skilled in the art that the embodiments disclosed herein may be practiced without adopting these specific details. In fact, the embodiments may be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. In addition, the description provided herein does not form a complete processing flow for manufacturing microelectronic devices (e.g., semiconductor devices, memory devices such as DRAM memory devices), equipment or electronic systems or complete microelectronic devices, equipment or electronic systems. The structures described below do not form complete microelectronic devices, equipment or electronic systems. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Other actions of forming complete microelectronic devices, equipment or electronic systems by the structures may be performed by conventional techniques.

[0018] The materials described herein may be formed by conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Alternatively, the material may be grown in situ. Depending on the specific material to be formed, one of ordinary skill in the art may select a technique for depositing or growing the material. Unless the context indicates otherwise, removal of material may be accomplished by any suitable technique including, but not limited to, etching, grinding planarization (e.g., chemical-mechanical planarization), or other known methods.

[0019] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates one or more of the structure and device to operate in a predetermined manner.

[0020] As used herein, the terms "longitudinal", "vertical", "lateral", and "horizontal" are referenced to a principal plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) in or on which one or more structures and / or features are formed and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the principal plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the principal plane of the substrate. The principal plane of a substrate is defined by a surface of the substrate having a relatively larger area than other surfaces of the substrate.

[0021] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses the extent to which one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a certain degree of variance (e.g., variance within an acceptable tolerance). For example, depending on a particular parameter, property, or condition being substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, at least 99.9% met, or even 100.0% met.

[0022] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and a certain degree of difference relative to the numerical value that will be understood by those of ordinary skill in the art as being within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​that are within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0% of the numerical value, within the range of 97.5% to 102.5% of the numerical value, within the range of 99.0% to 101.0% of the numerical value, within the range of 99.5% to 100.5% of the numerical value, or within the range of 99.9% to 100.1% of the numerical value.

[0023] As used herein, for ease of description, spatially relative terms such as "under", "below", "lower", "bottom", "above", "upper", "top", "front", "back", "left", "right", etc. may be used to describe the relationship of one element or feature to another or more elements or features as shown in the accompanying drawings. Unless otherwise specified, spatially relative terms are intended to cover different orientations in addition to the orientation of the materials depicted in the accompanying drawings. For example, if the materials in the accompanying drawings are inverted, the elements described as being "under" or "below" or "below" or "bottom" of other elements or features will be oriented as being "above" or "top" of the other elements or features. Therefore, depending on the context in which the term is used, the term "under" can cover both the above and below orientations, which will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.), and the spatially relative descriptors used herein may be interpreted accordingly.

[0024] As used herein, features (e.g., regions, materials, structures, devices) described as being "adjacent" to each other means and includes features of the disclosed one (or more) identities that are positioned closest to each other (e.g., closest). Additional features (e.g., additional regions, additional materials, additional structures, additional devices) that do not match the disclosed one (or more) identities of the "adjacent" features may be positioned between the "adjacent" features. In other words, the "adjacent" features may be positioned directly adjacent to each other, such that no other features intervene between the "adjacent" features; or the "adjacent" features may be positioned indirectly adjacent to each other, such that at least one feature having an identity other than the identity associated with at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other means and includes features of the disclosed one (or more) identities that are positioned closest to each other (e.g., closest vertically). Furthermore, features described as being "horizontally adjacent" to each other means and includes features of the disclosed one (or more) identities that are positioned closest to each other (e.g., closest vertically).

[0025] As used herein, the term "memory device" means and includes a microelectronic device that exhibits memory functionality but is not necessarily limited to memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application specific integrated circuits (ASICs) (e.g., systems on a chip (SoC)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that incorporate memory.

[0026] As used herein, "conductive material" means and includes conductive materials such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based alloys , Fe-based alloys, Ni-based alloys, Fe-Ni-based alloys, Co-Ni-based alloys, Fe-Co-based alloys, Co-Ni-Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)). In addition, the “conductive structure” means and includes a structure formed of a conductive material and including a conductive material.

[0027] As used herein, "insulating material" means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )) and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y )). The formula herein includes one or more of "x", "y" and "z" (e.g., SiO x 、AlO x , HfO x 、NbO x 、TiO x 、SiN y 、SiO x Ny 、SiO x C z N y ) represents a material with an average ratio of "x" atoms of another element, "y" atoms of another element, and "z" atoms of yet another element (if any) for each atom of an element (e.g., Si, Al, Hf, Nb, Ti). Since the formula represents a relative atomic ratio rather than a strict chemical structure, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y" and "z" (if any) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds whose elemental composition cannot be represented by a ratio of well-defined natural numbers and violates the law of definite ratios. In addition, "insulating structure" means and includes a structure formed by and including an insulating material.

[0028] According to embodiments described herein, a microelectronic device includes an active wordline structure and a transfer wordline structure, which may be recessed within a semiconductor material. The active wordline structure may include a portion of a memory cell, the memory cell including the active wordline structure, an access device (e.g., a transistor), and a storage structure (e.g., a capacitor) coupled to the access device via the active wordline structure. The transfer wordline structure may be positioned adjacent to the active wordline structure. In some embodiments, the transfer wordline structure may be coupled to another storage structure at a location distal to the memory cell coupled to the active wordline structure. The transfer wordline structure may be formed over and at least partially within an isolation structure including an insulating material, the insulating material being configured to reduce leakage of charge (e.g., current) and form a storage structure of the memory cell coupled to the active wordline structure during application of a voltage to the transfer wordline structure.

[0029] In some embodiments, a microelectronic device includes pillars of semiconductor material between adjacent transfer word line structures, the pillars extending from a base portion of the semiconductor material. An active word line structure may be positioned between adjacent transfer word line structures. In some embodiments, a dimension (e.g., diameter, width, thickness) of a pillar adjacent to a transfer word line structure may be smaller than a corresponding dimension of a pillar not positioned adjacent to a transfer word line structure (e.g., a pillar positioned adjacent only to an active word line structure). A dielectric material (e.g., a gate dielectric) of the transfer word line structure may be positioned adjacent to an insulating material, and the transfer word line structure may include a dielectric material having an effective thickness greater than a thickness of a corresponding dielectric material of the active word line structure. The greater effective thickness of the dielectric material of the transfer word line structure may reduce leakage of charge from an unselected storage structure adjacent to a transfer word line structure to which a voltage is applied. Reduction in charge leakage from the storage structure may improve performance of the microelectronic device, such as by increasing the amount of time between refresh operations of memory cells associated with the storage structure.

[0030] Figure 1A to Figure 1Z are simplified partial cross-sectional and top plan views illustrating an embodiment of a method of forming a microelectronic device according to an embodiment of the present disclosure. Figure 1A is through Figure 1B A simplified cross-sectional view of the microelectronic device 100 taken along the section line AA, Figure 1B yes Figure 1A FIG. 1 is a top view of the microelectronic device 100 .

[0031] refer to Figure 1A and Figure 1B The microelectronic device 100 may include a substrate material 102, a first oxide material 104 vertically (e.g., in the Z direction) covering the substrate material 102, a first nitride material 106 vertically covering the first oxide material 104, a first carbon-containing material 108 vertically covering the first nitride material 106, a first dielectric antireflective coating (DARC) material 110 vertically covering the first carbon-containing material 108, and a first photoresist material 113 vertically covering the first DARC material 110.

[0032] The first photoresist material 113 can be patterned to include openings 115 therein through which portions of the first DARC material 110 are exposed. In some embodiments, the openings 115 are formed in the array region 105 of the microelectronic device 100 and are not formed in the peripheral region 107 of the microelectronic device 100. The array region 105 can include an area of ​​the microelectronic device 100 that includes active circuitry and memory cells (e.g., a memory cell array). Although Figure 1BOnly six openings 115 are shown in the array region 105, but it should be understood that the microelectronic device 100 may include many more openings 115 (eg, thousands of openings 115), and only six openings 115 are shown for ease of understanding of the present disclosure.

[0033] The opening 115 may have a substantially elliptical shape, a rectangular shape, or other shapes. In some embodiments, the opening 115 has an elliptical shape.

[0034] The base material 102 may include a semiconductor substrate, a base semiconductor material on a supporting substrate, a metal electrode, or a semiconductor substrate having one or more materials, one or more structures, or one or more regions formed thereon. The base material 102 may be a conventional silicon substrate or other bulk substrates including semiconductor materials. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-semiconductor ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates or silicon-on-glass ("SOG") substrates, epitaxial silicon layers on a base semiconductor basis, or other semiconductor or optoelectronic materials, such as silicon germanium (Si 1-x Ge x , where x is a mole fraction, for example, between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. In addition, when "substrate" or "base material" is referenced in the following description, materials, regions, or junctions may have been formed in the base semiconductor structure or foundation using previous process stages. Base material 102 may include one or more materials associated with integrated circuit system manufacturing. Such materials may include, for example, one or more of refractory metals, barrier materials, diffusion materials, insulator materials. Base material 102 may include, for example, a complementary metal oxide semiconductor (CMOS) structure or other semiconductor structure. Different portions of base material 102 may be electrically isolated from each other by one or more dielectric materials.

[0035] The first oxide material 104 may be formed of and include one or more dielectric materials, for example, one or more of the following: silicon dioxide (SiO2), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), and another insulating material. The first oxide material 104 may be formed by thermal oxidation of the substrate material 102, deposition (e.g., deposition with, for example, tetraethyl orthosilicate (TEOS)), or another method. In some embodiments, the first oxide material 104 includes silicon dioxide.

[0036] The first nitride material 106 may be formed of or include one or more of the following: silicon nitride (Si3N4), silicon oxynitride (SiOx N y ) or another material. In some embodiments, the first nitride material 106 includes silicon nitride.

[0037] The first carbon-containing material 108 may be formed of and include a carbon-containing mask material. In some embodiments, the first carbon-containing material 108 includes amorphous hydrogenated carbon (also referred to as "amorphous carbon"). In some embodiments, the first carbon-containing material 108 includes a spin-on carbon (SOC) material.

[0038] The first DARC material 110 may be formed of and include a silicon oxynitride material, such as Si x O y N z , wherein x is between about 10 and about 60, y is between about 20 and about 50, and z is between about 10 and about 20. However, the present disclosure is not limited thereto, and the first DARC material 110 may include other suitable DARC materials known in the art. The first DARC material 110 may be formulated and configured to substantially prevent reflection of electromagnetic radiation (e.g., a light source) during exposure of a photoresist material (e.g., the first photoresist material 113) during patterning of the photoresist material.

[0039] The first photoresist material 113 can be formed by and include: a 193 nanometer (nm) photoresist material, a 248nm photoresist material, or a photoresist material that is sensitive to radiation of different wavelengths. The first photoresist material 113 can be a positive or negative photoresist material, a photopolymerized photoresist material, a photodecomposed photoresist material, or a photocrosslinked photoresist material. Photoresist materials, such as positive and negative resists, are known in the art and are therefore not described in detail herein. As described above, an opening 115 can be formed in the first photoresist material 113 in the array region 105.

[0040] Figure 1D yes Figure 1C A top view of the microelectronic device 100, Figure 1C is through Figure 1D A cross-sectional view of the microelectronic device 100 taken along the section line CC of FIG. Figure 1C After the opening 115 is formed in the first photoresist material 113, the opening 115 may be transferred to the first DARC material 110, and then the first photoresist material 113 may be removed. Figure 1A ). After removing the first photoresist material 113, a second carbon-containing material 114 may be formed over the first DARC material 110 and a second DARC material 116 may be formed over the second carbon-containing material 114. Figure 1C, the second carbon-containing material 114 may fill the opening 115 in the first DARC material 110 ( Figure 1A ).

[0041] The second carbon-containing material 114 may be formed from one or more of and include one or more of the materials described above with reference to the first carbon-containing material 108, and the second DARC material 116 may be formed from one or more of and include one or more of the materials described above with reference to the first DARC material 110. In some embodiments, the second carbon-containing material 114 includes the same material composition as the first carbon-containing material 108. In some embodiments, the second DARC material 116 includes the same material composition as the first DARC material 110.

[0042] A second photoresist material 118 may be formed over the second DARC material 116. The second photoresist material 118 may include one or more of the materials described above with reference to the first photoresist material 113. In some embodiments, the second photoresist material 118 includes the same material composition as the first photoresist material 113.

[0043] The opening 120 may be formed in the second photoresist material 118 to expose a portion of the second DARC material 116. The opening 120 may be formed in the array region 105 and may not be formed in the peripheral region 107. In some embodiments, the opening 120 extends from the opening 115 ( Figure 1B ) lateral offset (e.g., in the X direction and in the Y direction).

[0044] Reference now Figure 1E and Figure 1F , the opening 120 in the second photoresist material 118 can be transferred to the second DARC material 116, and the second photoresist material 118 can be removed (e.g., stripped) from the second DARC material 116. After the opening 120 is formed in the second DARC material 116, the opening 120 can be transferred to the second carbon-containing material 114. For example, the opening 120 can be formed in the second carbon-containing material 114 by exposing the second carbon-containing material 114 to a plasma etch containing one or more of HBr, Cl2, carbon tetrafluoride (CF4), or another material.

[0045] Continue to refer Figure 1E , after the opening 120 is formed in the second carbonaceous material 114 ( Figure 1C), the pattern of openings 120 can be transferred from the second carbon-containing material 114 to the first DARC material 110, and the second carbon-containing material 114 can be removed. Thus, the first DARC material 110 can include openings 115 and openings 120, and the openings 120 can be laterally offset from the openings 115 (e.g., in the X direction and the Y direction), such as Figure 1F As shown, Figure 1F yes Figure 1E FIG. 1 is a top view of the microelectronic device 100. Figure 1E , the openings 115 may be aligned with other openings 115 in a lateral direction (e.g., in each of the X and Z directions) and may be laterally offset from each of the openings 120 (e.g., in each of the X and Y directions). Similarly, the openings 120 may be aligned with other openings 120 in a lateral direction (e.g., in each of the X and Z directions) and may be laterally offset from each of the openings 115 (e.g., in each of the X and Y directions). One or more openings 115 may be laterally inserted (e.g., in the X direction, in the Y direction) between adjacent openings in the openings 120, and one or more openings 120 may be laterally inserted (e.g., in the X direction, in the Y direction) between adjacent openings in the openings 115.

[0046] although Figure 1E and Figure 1F Specific spacing between adjacent openings 115, 120 is shown, but the disclosure is not limited thereto. It should be understood that the spacing between openings 115, 120 can be different (eg, greater) than the spacing shown, but for ease of understanding of the description, the openings 115, 120 are shown at specific spacings.

[0047] Figure 1G Shown with Figure 1E The cross-sectional view of the microelectronic device 100 shown is the same as the cross-sectional view. Figure 1G , the first DARC material 110 ( Figure 1E ) can be transferred to the first oxide material 104. For example, the openings 115, 120 can be formed by the first carbon-containing material 108 ( Figure 1E ) is formed. In some embodiments, after the openings are formed in the first carbon-containing material 108, the first DARC material 110 is removed. The openings 115, 120 may be formed by the first nitride material 106 ( Figure 1E ) is transferred, and then transferred to the first oxide material 104, such as Figure 1G Reference Figure 1G , portions of the base material 102 may be exposed through the openings 115 , 120 in the first oxide material 104 .

[0048] refer to Figure 1H , which shows Figure 1G The same cross section shown, the substrate material 102 may be patterned with the openings 115, 120 in the first oxide material 104 to extend the openings 115, 120 into the substrate material 102. By way of non-limiting example, the openings 115, 120 may be transferred to the substrate material 102 by exposing the substrate material 102 to a wet etchant, such as one or more of potassium hydroxide (KOH), sodium hydroxide (NaOH), tetramethylammonium hydroxide (TMAH), or another material. In some embodiments, the substrate material 102 is anisotropically etched to form the openings 115, 120 therein.

[0049] The depth D1 of the openings 115, 120 in the substrate material 102 may be in a range of about 100 nm to about 180 nm, such as about 100 nm to about 120 nm, about 120 nm to about 140 nm, about 140 nm to about 160 nm, or about 160 nm to about 180 nm. However, the present disclosure is not limited thereto, and the depth D1 may be different from those described above.

[0050] After forming the openings 115, 120 in the base material 102, a first liner material 122 can be formed over the microelectronic device 100. In some embodiments, the first liner material 122 is substantially conformally formed over the microelectronic device 100. The first liner material 122 can be formed of and include a nitride material such as silicon nitride, a metal nitride (e.g., titanium nitride, tungsten nitride, tantalum nitride, aluminum nitride), an oxynitride material, a silicon carbonitride material, or another material. In some embodiments, the first liner material 122 includes silicon nitride. In some embodiments, the first liner material 122 includes a first nitride material 106 ( Figure 1A ) have the same material composition.

[0051] Continue to refer Figure 1H, lateral extensions (e.g., in the X direction, in the Y direction) of the first liner material 122 can be removed from the microelectronic device 100 (e.g., from the first oxide material 104 and from the substrate material 102 within the openings 115, 120). By way of non-limiting example, the first liner material 122 can be exposed to a dry etchant such as one or more of the following: sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), oxygen (O2), difluorocarbene (CF2), CF4, trifluoromethane (CHF3) (also known as trifluoromethane (fluoroform)), difluoromethane (CH2F2), fluoromethane (CH3F) (also known as fluoromethane (fluormethane)), hexafluoromethane (C2F6), perfluoropropane (C3F8), octafluorocyclobutane (C4F8), octafluorocyclopentene (C5F8), and another material to remove the lateral extensions of the first liner material 122.

[0052] Reference now Fig. 1I , which shows the Figure 1H The same cross-section, isotropic openings 124 (also referred to as "pockets") can be formed in the substrate material 102. The dimension D2 (e.g., diameter) of the isotropic openings 124 can be in the range of about 10 nm to about 40 nm, such as about 10 nm to about 20 nm, about 20 nm to about 30 nm, or about 30 nm to about 40 nm. In some embodiments, the dimension D2 is about 30 nm to about 40 nm, such as about 35 nm to about 40 nm. In some embodiments, the dimension D2 is about 40 nm.

[0053] The depth D3 of the isotropic opening 124 from the surface of the substrate material may be in the range of about 10 nm to about 40 nm, as described above with reference to dimension D2.

[0054] The isotropic opening 124 may be formed through the openings 115, 120 by isotropically etching the substrate material 102. By way of non-limiting example, the substrate material 102 may be exposed to one or more of nitric acid, hydrochloric acid, and acetic acid.

[0055] After forming the isotropic opening 124, the first liner material 122 may be removed from the surfaces of the first oxide material 104 and the base material 102. Figure 1H In some embodiments, the first liner material 122 is exposed to a wet etchant, such as one or both of nitric acid and phosphoric acid (H 3 PO 4 ).

[0056] refer to Figure 1J , which shows the Fig. 1IIn some embodiments, the second liner material 126 is substantially conformally formed over the microelectronic device 100 and over the surface of the opening 124 including the isotropic opening 115, 120. The second liner material 126 may include one or more of the materials described above with reference to the first liner material 122. In some embodiments, the second liner material 126 includes silicon nitride. In some embodiments, the second liner material 126 includes the same material composition as the material composition of the first liner material 122.

[0057] After forming the second liner material 126, the laterally extending (e.g., in the X direction, in the Y direction) portions of the second liner material 126 may be removed, as described above with reference to the first liner material 122. For example, the laterally extending portions of the second liner material 126 may be removed from the laterally extending surface of the first oxide material 104 and the lower portion of the isotropic opening 124. The laterally extending portions of the second liner material 126 may be removed by exposing the microelectronic device 100 to a dry etchant such as one or more of SF6, NF3, O2, CF2, CF4, CHF3, CH2F2, CH3F, C2F6, C3F8, C4F8, and C5F8.

[0058] Removing the lateral extension of the second liner material 126 may expose the base material 102 at the lower portion of the isotropic opening 124. Figure 1J , the substrate material 102 at the lower portion of the isotropic opening 124 can be exposed to one or more materials to remove the substrate material 102 and form the vertical extension 128 of the openings 115, 120. By way of non-limiting example, the substrate material 102 can be exposed to a dry etchant, the dry etchant containing one or more of the following: SF6, one or more fluorocarbons (e.g., carbon tetrafluoride (CF4), difluorocarbene (CF2), trifluoromethane (CHF3) (also known as trifluoromethane (fluoroform)), difluoromethane (CH2F2), fluoromethane (CH3F) (also known as fluoromethane (fluormethane)), hexafluoromethane (C2F6), perfluoropropane (C3F8), octafluorocyclobutane (C4F8) and octafluorocyclopentene (C5F8)) to form the vertical extension 128.

[0059] The depth D4 of the substrate material 102 removed below the isotropic opening 124 can be in a range of about 10 nm to about 25 nm, such as about 10 nm to about 15 nm, about 15 nm to about 20 nm, or about 20 nm to about 25 nm. However, the present disclosure is not limited thereto, and the depth D4 can be different from those described.

[0060] Figure 1K Shown with Figure 1J A cross section of the same microelectronic device 100. Figure 1K , the second liner material 126 can be removed from the openings 115, 120 and the protective material 130 can be formed over the exposed surface of the substrate material 102. In some embodiments, the second liner material 126 is removed by exposing the second liner material 126 to a wet etchant including, for example, one or both of nitric acid and phosphoric acid (H3PO4), as described above with reference to the removal of the first liner material 122 ( Fig. 1I ) described.

[0061] The protective material 130 may be formed by epitaxial growth from the base material 102. By way of non-limiting example, in some embodiments, the base material 102 includes silicon and the protective material 130 includes polysilicon grown from exposed portions of the base material 102. The protective material 130 may not be formed on (e.g., grown on) the exposed portions of the first oxide material 104.

[0062] refer to Figure 1L and Figure 1M , can be at openings 115, 120 ( Figure 1K ) and the insulating material may substantially fill the openings 115, 120 to form an isolation structure 135 (also referred to herein as an "insulating structure") extending into the base material 102. After forming the insulating material 132, the microelectronic device 100 may be exposed to a chemical mechanical planarization (CMP) process to remove the insulating material 132 from portions outside the openings 115, 120. Figure 1L is through Figure 1M The section line LL is taken Figure 1M FIG. 1 is a cross-sectional view of a microelectronic device 100 .

[0063] The insulating material 132 may be formed of a spin-on dielectric (SOD) material and include a spin-on dielectric material, for example, one or more of silicon dioxide, polyimide, polynorbornene, benzocyclobutene, polytetrafluoroethylene (PTFE), hydrogen silsesquioxane (HSQ), BSG, PSG, BPSG, or another material. In some embodiments, the insulating material 132 is formed by applying the spin-on dielectric material and exposing the spin-on dielectric material to a curing condition (e.g., exposing the spin-on dielectric material to a suitable temperature (e.g., such as a rapid thermal annealing (RTA) process)) to densify the spin-on dielectric material and form the insulating material 132. In some embodiments, densifying the spin-on dielectric material may convert the protective material 130 into an oxide (e.g., silicon dioxide), which may form a portion of the insulating material 132. In other embodiments, the insulating material 132 includes aluminum oxide.

[0064] The isolation structure 135 may include a shallow trench isolation (STI) structure including: a first portion 134 extending from the surface of the substrate material 102 to a second portion 136 vertically located (e.g., in the Z direction) below the first portion 134; and a third portion 138 vertically located (e.g., in the Z direction) below the second portion 136. The second portion 136 may include an arcuate portion including, for example, a curved surface in each of the XZ plane and the YZ plane, and the second portion may also be referred to as a "pocket region" of the isolation structure 135. The cross-sectional shape of the second portion 136 in the XZ plane may be substantially circular, substantially elliptical, substantially oval, or other shapes. In other embodiments, the cross-sectional shape of the second portion 136 in the XZ plane is substantially circular. In some embodiments, the cross-sectional shape of the second portion 136 in the YZ plane is substantially the same as the cross-sectional shape of the second portion 136 in the XY plane. In some embodiments, the size of the second portion 136 in the XZ plane may be different from the size of the second portion 136 in the YZ plane.

[0065] In some embodiments, the second portion 136 includes a laterally extending pocket that extends further in the X-direction and the Y-direction than the first portion 134 or the third portion 138 of the isolation structure 135. In some embodiments, the sidewalls of the first portion 134 and the sidewalls of the third portion 138 may be tapered. For example, the cross-sectional area of ​​the upper portion of the first portion 134 is larger than the cross-sectional area of ​​the lower portion of the first portion 134. Similarly, the cross-sectional area of ​​the upper portion of the third portion 138 is larger than the cross-sectional area of ​​the lower portion of the third portion 138.

[0066] Fig.1O yes Figure 1N A top view of the microelectronic device 100, Figure 1N is through Fig.1O A simplified cross-sectional view of the microelectronic device 100 is taken along the section line NN. Figure 1N ,because Figure 1N The cross section of FIG. 1 is taken through the XZ plane, so it should be understood that the spacing between adjacent isolation structures 135 may be different from Figure 1L The interval shown in the cross section.

[0067] refer to Figure 1N, a second nitride material 140 can be vertically formed above the first oxide material 104 (for example, in the Z direction), a third carbon-containing material 142 can be vertically formed above the second nitride material 140, a third DARC material 144 can be vertically formed above the third carbon-containing material 142, a second oxide material 146 can be vertically formed above the third DARC material 144, a polysilicon material 148 can be vertically formed above the second oxide material 146, a fourth carbon-containing material 150 can be vertically formed above the polysilicon material 148, and a fourth DARC material 152 can be vertically formed above the fourth carbon-containing material 150.

[0068] The second nitride material 140 may be formed of and include one or more of the following: Figure 1A In some embodiments, the second nitride material 140 includes silicon nitride.

[0069] The third carbonaceous material 142 and the fourth carbonaceous material 150 may each be individually formed of and include one or more of the following: Figure 1A ). In some embodiments, the third carbon-containing material 142 and the fourth carbon-containing material 150 each include amorphous carbon. In some embodiments, the third carbon-containing material 142 includes the same material composition as the fourth carbon-containing material 150.

[0070] The third DARC material 144 and the fourth DARC material 152 may each be individually formed of and include one or more of the following: Figure 1A ). In some embodiments, the third DARC material 144 and the fourth DARC material 152 each include silicon oxynitride. In some embodiments, the third DARC material 144 includes the same material composition as the fourth DARC material 152.

[0071] The second oxide material 146 may be formed of and include one or more of the following: the materials described above with reference to the first oxide material 104. In some embodiments, the second oxide material 146 includes silicon dioxide. In some embodiments, the second oxide material 146 includes the same material composition as the material composition of the first oxide material 104.

[0072] Continue to refer Figure 1N and Fig.1O, a third photoresist material 154 may be vertically formed and patterned above the fourth DARC material 152 (eg, in the Z direction). The third photoresist material 154 may be formed of and include one or more of the following: Figure 1A ) described in the specification.

[0073] refer to Fig.1O , the third photoresist material 154 can be patterned into lines 156, each of which can be separated from one or more adjacent lines 156 by intervals 158. The lines 156 of the third photoresist material 154 can extend at a certain angle relative to the X-axis and the Y-axis. For example, the lines 156 can extend at an angle in the range of about 30° to about 60° relative to the X-axis. However, the present disclosure is not limited thereto, and the lines 156 can extend at an angle different from the angle described above relative to the X-axis.

[0074] Reference now Figure 1P , the third photoresist material 154 ( Figure 1P , Fig.1O ) of line 156( Fig.1O ) is exposed to a pitch multiplication process to form a pattern of lines 160 of the fourth carbon-containing material 150. By way of non-limiting example, spacers may be formed on the sidewalls of the lines 156 of the third photoresist material 154 and the third photoresist material 154 may be removed (e.g., stripped) from the surface of the fourth carbon-containing material 150. The spacers may be used as a mask to pattern the pattern of the spacers and transfer it to the fourth carbon-containing material 150, such as Figure 1P What is shown.

[0075] refer to Figure 1Q , the fourth carbonaceous material 150( Figure 1P ) of line 160( Figure 1P ) may be exposed to another pitch multiplication process to form lines 164 of third oxide material 162. For example, spacers including third oxide material 162 may be formed on sidewalls of lines 160 of fourth carbon-containing material 150 and lines 160 of fourth carbon-containing material 150 may be selectively removed relative to lines 164 of third oxide material 162. After forming lines 164 of third oxide material 162, fourth photoresist material 166 may be formed over peripheral region 107 of microelectronic device 100 and lines 164 of third oxide material 162 may remain exposed in array region 105.

[0076] refer to Figure 1R and Figure 1S , the third oxide material 162 ( Figure 1Q ) of line 164( Figure 1Q) is transferred to the polysilicon material 148 to form lines 168 of the polysilicon material 148. Figure 1S yes Figure 1R A top view of the microelectronic device 100, Figure 1R Demonstrated through Figure 1S RR of FIG. 1 shows a cross section of microelectronic device 100. Lines 168 of polysilicon material 148 may be formed, for example, by exposing polysilicon material 148 to one or more dry etchants, such as one or more of Cl2, HBr, O2, CF4, C2F6, carbon tetrafluoride (CCl4), or another material.

[0077] Figure 1T In the case of polysilicon material 148 ( Figure 1R , Figure 1S ) of line 168( Figure 1R , Figure 1S ) is transferred to the first oxide material 104 after the pattern is transferred to the first oxide material 104. Figure 1U is through Figure 1T A simplified cross-sectional view of the array region 105 taken along the section line UU and Figure 1V is through Figure 1T A simplified cross-sectional view of the array area taken along the section line VV of FIG. Figure 1S to Figure 1U Only a portion of the array area 105 is shown. Figure 1T The cross section and Figure 1F and Figure 1M The cross sections shown are identical.

[0078] The polysilicon material 148 ( Figure 1R , Figure 1S ) of line 168( Figure 1R , Figure 1S ) may include forming lines 170 extending between isolation structures 135 of the first oxide material 104. The insulating material 132 and the first oxide material 104 may be removed from the area between adjacent lines 170 of the first oxide material 104 to expose the base material 102. By way of non-limiting example, the pattern of lines 168 may be transferred to the second oxide material 146 and then the polysilicon material 148 may be removed. Thereafter, as is known in the art, the pattern may be transferred from the second oxide material 146 to the second nitride material 140. The pattern may then be transferred from the second nitride material 140 to the first oxide material 104. For example, the pattern of the second nitride material 140 may be used as a mask when patterning the first oxide material 104. Methods of transferring patterns are known in the art and are not described in detail herein.

[0079] Figure 1W In removing the first oxide material 104 ( Figure 1T ) and removing adjacent lines 170 of first oxide material 104 ( Figure 1T ) to form trenches 190 in the substrate material 102. For example, about 250 nm to about 300 nm of substrate material 102 may be removed between adjacent lines 170. It should be understood that the lower portion of the trench 190 may be defined by the substrate material 102, but for ease of understanding the description, this is not shown. Figure 1W The substrate material 102 is shown beneath the groove 190 in the view of FIG. Figure 1X is through Figure 1W 1 is a simplified cross-sectional view of the array region 105 taken along the section line XX of FIG. Removing the first oxide material 104 may expose a portion of the base material 102 and the isolation structure 135 .

[0080] Reference now Figure 1Y , the microelectronic device 100 may be exposed to various manufacturing actions to form Figure 1Y A microelectronic device 100 is provided. Figure 1Y The cross-sectional view shows the Figure 1X The cross-section of the microelectronic device 100 shown is the same as the cross-section. For example, the isolation structure 135 ( Figure 1X ) may be patterned to form a transfer word line structure 172 and the base material 102 between adjacent isolation structures 135 may be patterned to form an active word line structure 174.

[0081] This can be accomplished by, for example, removing the isolation structure 135 ( Figure 1X ) and removing portions of the base material 102 between adjacent isolation structures 135 to form transfer word line structures 172 and active word line structures 174. In some embodiments, the insulating material 132 is removed at a faster rate than the base material 102. In some such embodiments, the depth of the transfer word line structure 172 can be greater than the depth of the active word line structure 174. In some embodiments, at least a portion of the second portion 136 of the isolation structure 135 is removed.

[0082] In some embodiments, the depth of the transfer word line structure 172 is greater than the depth D5 of the active word line structure 174. The depth D5 of the active word line structure 174 may be in a range of about 40 nm to about 90 nm, such as about 40 nm to about 50 nm, about 50 nm to about 70 nm, or about 70 nm to about 90 nm. The depth D6 of the transfer word line structure 172 extending below the lower portion of the active word line structure 174 may be in a range of about 5 nm to about 35 nm, such as about 5 nm to about 15 nm, about 15 nm to about 25 nm, or about 25 nm to about 35 nm. However, the present disclosure is not limited thereto, and the depths D5, D6 may be different from those described.

[0083] Removing portions of the base material 102 between adjacent isolation structures 135 during the formation of the transfer word line structures 172 and the active word line structures 174 may include forming pillars extending from the base material 102. For example, the pillars may include a first pillar 175 between the active word line structures 174 and a second pillar 177 positioned adjacent to the transfer word line structures 172 (e.g., between the transfer word line structures 172 and the active word line structures 174).

[0084] The first pillar 175 and the second pillar 177 may each individually include a material composition that is the same as the material composition of the substrate material 102. In some embodiments, at least a portion of the first pillar 175 and the second pillar 177 include one or more dopants. By way of non-limiting example, the first pillar 175 may include a source region of a transistor and the second pillar 177 may include a drain region of the transistor. The first pillar 175 may be doped with at least one N-type dopant (e.g., arsenic ions, phosphorus ions, antimony ions) and the second pillar 177 may be doped with at least one P-type dopant (e.g., boron ions).

[0085] The height H of the first pillar 175 and the second pillar 177 may be in a range of about 100 nm to about 150 nm, such as about 100 nm to about 125 nm, or about 125 nm to about 150 nm. However, the disclosure is not limited thereto, and the heights may be different from those described.

[0086] In some embodiments, the sidewalls of the first and second pillars 175, 177 are tapered (e.g., angled). In some such embodiments, the widths of the first and second pillars 175, 177 may be the upper portions of the respective first and second pillars 175, 177 rather than the lower portions thereof. For example, the width W1 of the upper portions of the first and second pillars 175, 177 may be in a range of about 10 nm to about 15 nm, such as about 10 nm to about 12.5 nm, or about 12.5 nm to about 20 nm. The width W2 of the lower portions of the first and second pillars 175, 177 may be in a range of about 12.5 nm to about 17.5 nm, such as about 12.5 nm to about 15.0 nm, or about 15.0 nm to about 17.5 nm. However, the present disclosure is not limited thereto, and the widths W1, W2 may be different from those described.

[0087] Continue to refer Figure 1Y After removing portions of the base material 102 and forming the first pillar 175 and the second pillar 177 , a dielectric material 176 (eg, gate oxide material, gate dielectric material) may be formed over a surface of the base material 102 .

[0088] The dielectric material 176 may be formed of and include one or more of silicon dioxide, silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material (e.g., silicon nitride (Si3N4)), an oxynitride (e.g., silicon oxynitride, another gate dielectric material, a dielectric carbon nitride material (e.g., silicon carbonitride (SiCN))), a dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiOCN)), or a combination thereof. In some embodiments, the dielectric material 176 includes silicon dioxide.

[0089] In some embodiments, dielectric material 176 is formed by epitaxial growth from exposed surfaces of substrate material 102 and insulating material 132. In some such embodiments, epitaxially grown dielectric material 176 may be exposed to oxygen to form an oxide (e.g., silicon dioxide). In other embodiments, dielectric material 176 is formed by deposition (e.g., one or more of ALD, PVD, CVD, LPCVD, PECVD). Although Figure 1Y The dielectric material 176 is shown extending laterally (eg, in the X direction, in the Y direction) between the first electrode material 178 and the insulating material 132 of the second portion 136 , but the disclosure is not limited thereto. In other embodiments, the dielectric material 172 may terminate within the insulating material 132 .

[0090] After forming the dielectric material 176, a first electrode material (eg, a first gate electrode material) 178 may be formed over the dielectric material 176. The first electrode material 178 may be formed of and include a conductive material. In some embodiments, the first electrode material 178 includes titanium nitride.

[0091] A second electrode material 180 may be formed over the first gate electrode material 178 and adjacent to the dielectric material 176. The second electrode material 180 may be formed of and include a conductive material. For example, the second electrode material 180 may be formed of and include one or more of the materials described above with reference to the first electrode material 178. In some embodiments, the second electrode material 180 includes polysilicon.

[0092] A first electrode material 178 and a second electrode material 180 of each of the transfer word line structure 172 and the active word line structure 174 may be formed vertically (e.g., in the Z direction) below upper portions of the first pillar 175 and the second pillar 177. Since the first electrode material 178 and the second electrode material 180 of the active word line structure 174 are formed below upper portions of the first pillar 175 and the second pillar 177, the active word line structure 174 may be referred to herein as an “embedded access device” (RAD).

[0093] Continue to refer Figure 1Y , a transfer word line structure 172 may be formed over and at least partially within an isolation structure 185 including at least some of the second portion 136 and the third portion 138 of the insulating material 132. By comparison, an active word line structure 174 may not be formed directly over or within the isolation structure 185.

[0094] In some embodiments, the second portion 136 of the isolation structure 185 can extend laterally (e.g., in the X direction, in the Y direction) below the active word line structure 174. In other words, in some such embodiments, at least a portion of the insulating material 132 of the isolation structure 185 (e.g., the second portion 136) can extend laterally directly below the active word line structure 174.

[0095] As discussed above, second portion 136 of isolation structure 185 can be substantially circular, substantially elliptical, substantially oval, or other shapes. In some embodiments, second portion 136 can include a portion that extends further laterally (e.g., in the X direction, in the Y direction) than other portions of isolation structure 185.

[0096] Reference now Figure 1ZInsulating material 182 may be formed over second electrode material 180 in the region between first pillar 175 and second pillar 177 and over microelectronic device 100 (e.g., over first pillar 175 and second pillar 177). Insulating material 182 may be formed of and include one or more dielectric materials. In some embodiments, insulating material 182 includes a material composition different from a material composition of dielectric material 176. In some embodiments, insulating material 182 includes silicon nitride.

[0097] An opening may be formed in insulating material 182 over second pillar 177 and filled with conductive material 184 , which may include a conductive contact in electrical communication with storage structure 186 (eg, a memory storage structure such as a capacitor).

[0098] An opening may be formed in insulating material 182 directly above first pillar 175 and may be filled with conductive material 188. Conductive material 188 may be in electrical communication with a conductive access line such as a digit line or a bit line.

[0099] Forming the passing word line structure 172 within the isolation structure 185 can facilitate improved performance of the microelectronic device 100. For example, the second portion 136 of the isolation structure 185 can include a laterally extending (e.g., in the X direction, in the Y direction) portion that reduces so-called passing word line disturbances of memory cells associated with the storage structure 186 when an adjacent passing word line structure 172 is exposed to a voltage (e.g., to access a memory cell to which the passing word line is operably coupled). In some embodiments, the passing word line disturbance can be approximately 15% less than a passing word line disturbance of a conventional microelectronic device without significantly affecting drain current.

[0100] although Figure 1A to Figure 1Z The microelectronic device 100 has been described and illustrated as being formed to have a particular structure, but the present disclosure is not limited thereto. Figure 2 is a simplified cross-sectional view of a microelectronic device 200 according to an embodiment of the present disclosure. The microelectronic device 200 may be substantially similar to Figure 1Z The microelectronic device 200 may include a second pillar 277 having a size narrower than that of the second pillar 177 of the microelectronic device 100. The size of the first pillar 175 is substantially the same as that of the first pillar 175 of the microelectronic device 100.

[0101] The microelectronic device 200 may be Figure 1Z The microelectronic device 100 is formed in substantially the same manner, except that the Figure 1E and Figure 1FThe microelectronic device 100 is exposed to a trimming process to thin the first DARC material 110 between the opening 115 and the opening 120. In other words, the microelectronic device 100 may be processed Figure 1E and Figure 1F The microelectronic device 100 can be manufactured in the same manner as described above with reference to Figure 1G to Figure 1Z The same manner as described above is followed to form the microelectronic device 200. Figure 2 , the openings 115, 120 are formed to have larger lateral dimensions so that portions of the insulating material 132 may remain during the formation of the transfer word line structure 172. For example, the dielectric material 176 of the transfer word line structure 172 may be formed adjacent to (e.g., laterally adjacent to) portions of the insulating material 132 and the insulating material 132 may be positioned between the base material 102 and the dielectric material 176. The insulating material 132 extending along the dielectric material 176 may effectively increase the thickness of the dielectric material 176 of the transfer word line structure 172.

[0102] The microelectronic device 200 can exhibit a reduction in gate induced drain leakage (GIDL) compared to conventional microelectronic devices that do not include the insulating material 132 extending along the dielectric material 176. It is believed that when a voltage is applied to the active word line structure 174, the combination of the insulating material 132 and the dielectric material 176 can reduce the amount of leakage from the memory structure 186 through the second pillar 277 during access to the memory structure 186, without substantially affecting the current through the second pillar 277.

[0103] Therefore, according to an embodiment of the present disclosure, a microelectronic device includes: a first column of semiconductor material; a second column of the semiconductor material, the second column of the semiconductor material is adjacent to the first column of the semiconductor material; an active word line, the active word line extending between the first column and the second column; and a transfer word line, the transfer word line extending on a side of the second column opposite to the active word line, the transfer word line extending into an isolation region within the semiconductor material, the isolation region including a lower portion and an upper portion, the upper portion having a substantially circular cross-sectional shape and a lateral dimension larger than that of the lower portion.

[0104] Therefore, according to another embodiment of the present disclosure, a microelectronic device includes: a first column of semiconductor material; a second column of semiconductor material, the second column of semiconductor material is adjacent to the first column of semiconductor material, and the lateral dimension of the second column is smaller than the lateral dimension of the first column; a first electrode structure, the first electrode structure is between the first column and each second column in the second column; and a second electrode structure, the second electrode structure is on a side of the second column opposite to the first electrode structure.

[0105] Therefore, according to another embodiment of the present disclosure, a method of forming a microelectronic device includes forming an isolation structure in a semiconductor material. Forming the isolation structure includes: forming a first opening pattern in the material; forming a second opening pattern in the material laterally offset from the first opening pattern; transferring the first opening pattern and the second opening pattern to a base material; and filling the opening in the base material with an insulating material. The method further includes: removing a portion of the insulating material to form an opening above the isolation structure; forming a dielectric material within the opening; and forming a conductive material adjacent to the dielectric material.

[0106] A microelectronic device including a microelectronic device (e.g., microelectronic device 100, 200) according to an embodiment of the present disclosure may be used in an embodiment of an electronic system of the present disclosure, wherein the microelectronic device includes a transfer wordline structure 172 including an isolation structure 185 and / or includes a dielectric material of an effective thickness (e.g., dielectric material 176 adjacent to insulating material 132). For example, Figure 3 303 is a block diagram of an electronic system 303 according to an embodiment of the present disclosure. The electronic system 303 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or Tablet computers), electronic books, navigation devices, etc. The electronic system 303 includes at least one memory device 305. The memory device 305 may include, for example, a microelectronic device structure previously described herein or previously referenced. Figure 1A to Figure 1Z and Figure 2 Embodiments of a microelectronic device (eg, microelectronic devices 100 , 200 ) are described that include a transfer wordline structure 172 .

[0107] The electronic system 303 may further include at least one electronic signal processor device 307 (commonly referred to as a "microprocessor"). The electronic signal processor device 307 may optionally include a microelectronic device or microelectronic device structure previously described herein (e.g., as previously described in reference Figure 1A to Figure 1Z and Figure 2The electronic system 303 may further include one or more input devices 309 for inputting information into the electronic system 303 by a user, such as a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 303 may further include one or more output devices 311 for outputting information (e.g., visual output or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 309 and the output device 311 may include a single touch screen device, which can be used to input information to the electronic system 303 and to output visual information to the user. The input device 309 and the output device 311 can be in electrical communication with one or more of the memory device 305 and the electronic signal processor device 307.

[0108] refer to Figure 4 , depicting a processor-based system 400. The processor-based system 400 may include various microelectronic devices and microelectronic device structures (e.g., microelectronic devices and microelectronic device structures including one or more of the microelectronic devices 100, 200) fabricated according to embodiments of the present disclosure. The processor-based system 400 may be any of a variety of types such as a computer, a pager, a cellular phone, a personal organizer, a control circuit, or other electronic device. The processor-based system 400 may include one or more processors 402 such as a microprocessor for controlling system functions and processing of requests in the processor-based system 400. The processor 402 and other subcomponents of the processor-based system 400 may include microelectronic devices and microelectronic device structures (e.g., microelectronic devices and microelectronic device structures including one or more of the microelectronic devices 100, 200) fabricated according to embodiments of the present disclosure.

[0109] The processor-based system 400 may include a power source 404 in operable communication with the processor 402. For example, if the processor-based system 400 is a portable system, the power source 404 may include one or more of a fuel cell unit, a power harvesting device, a permanent battery, a replaceable battery, and a rechargeable battery. The power source 404 may also include an AC adapter; thus, the processor-based system 400 may be plugged into, for example, a wall outlet. The power source 404 may also include a DC adapter, so that the processor-based system 400 may be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0110] Depending on the functions performed by the processor-based system 400, various other devices can be coupled to the processor 402. For example, a user interface 406 can be coupled to the processor 402. The user interface 406 can include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touch screens, voice recognition systems, microphones, or combinations thereof. A display 408 can also be coupled to the processor 402. The display 408 can include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or a combination thereof. In addition, an RF subsystem / baseband processor 410 can also be coupled to the processor 402. The RF subsystem / baseband processor 410 can include an antenna coupled to an RF receiver and an RF transmitter (not shown). A communication port 412 or more than one communication port 412 can also be coupled to the processor 402. The communication port 412 may be adapted to couple to one or more peripheral devices 414, such as a modem, printer, computer, scanner, or camera, or to a network, such as a local area network, a remote local area network, an intranet, or the Internet.

[0111] The processor 402 can control the processor-based system 400 by implementing software programs stored in the memory. The software programs may include, for example, an operating system, database software, drawing software, word processing software, media editing software, or media playback software. The memory is operably coupled to the processor 402 to store various programs and facilitate the execution of various programs. For example, the processor 402 can be coupled to a system memory 416, which may include one or more of the following: spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. The system memory 416 may include volatile memory, non-volatile memory, or a combination thereof. The system memory 416 is typically large so that it can store dynamically loaded applications and data. In some embodiments, the system memory 416 may include a semiconductor device, such as a microelectronic device and a microelectronic device structure (e.g., microelectronic device 100, 200) described above, or a combination thereof.

[0112] The processor 402 may also be coupled to a non-volatile memory 418, which does not imply that the system memory 416 is necessarily volatile. The non-volatile memory 418 may include one or more of: STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with the system memory 416. The size of the non-volatile memory 418 is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. In addition, the non-volatile memory 418 may include high-capacity memory, such as disk drive memory, for example, a hybrid drive including resistive memory or other types of non-volatile solid-state memory. The non-volatile memory 418 may include a microelectronic device, such as the microelectronic device and microelectronic device structure described above (e.g., microelectronic device 100, 200) or a combination thereof.

[0113] Therefore, according to an embodiment of the present disclosure, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes an embedded access device, the embedded access device including: a first electrode, the first electrode between a first column of semiconductor material and a second column of the semiconductor material; and an oxide material, the oxide material between the first electrode and each of the first column and the second column. The at least one microelectronic device further includes a transfer word line structure, the transfer word line structure is adjacent to the second column, the transfer word line structure includes: a second electrode, the second electrode is adjacent to the second column; and another oxide material, the another oxide material is between the second electrode and the second column. The at least one microelectronic device further includes an isolation structure, the isolation structure is located directly below the transfer word line structure and includes a widened portion, the lateral dimension of the widened portion is larger than the lateral dimension of the transfer word line structure.

[0114] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0115] Embodiment 1: A microelectronic device comprising: a first column of semiconductor material; a second column of the semiconductor material, the second column of the semiconductor material being adjacent to the first column of the semiconductor material; an active word line, the active word line extending between the first column and the second column; and a transfer word line, the transfer word line extending on a side of the second column opposite to the active word line, the transfer word line extending into an isolation region within the semiconductor material, the isolation region comprising a lower portion and an upper portion, the upper portion having a substantially circular cross-sectional shape and a lateral dimension larger than that of the lower portion.

[0116] Embodiment 2: The microelectronic device of Embodiment 1, further comprising an additional active word line adjacent to the active word line.

[0117] Embodiment 3: The microelectronic device of Embodiment 1 or Embodiment 2, further comprising an additional passing word line, the active word line, and the additional active word line between the passing word line and the additional passing word line.

[0118] Embodiment 4: The microelectronic device of any one of embodiments 1 to 3, further comprising a memory element electrically coupled to the second pillar.

[0119] Embodiment 5: The microelectronic device of any one of embodiments 1 to 4, further comprising a dielectric material between: the active word line and the first pillar; and the passing word line and the second pillar.

[0120] Embodiment 6: The microelectronic device of Embodiment 5, further comprising an insulating material extending from the isolation region and along the dielectric material between the passing word line and the second pillar.

[0121] Embodiment 7: The microelectronic device of Embodiment 5 or Embodiment 6, wherein the dielectric material comprises a different material composition than the isolation region.

[0122] Embodiment 8: The microelectronic device of any one of embodiments 1 to 7, wherein a diameter of the upper portion is in a range of about 10 nanometers (nm) to about 40 nm.

[0123] Embodiment 9: The microelectronic device of any one of embodiments 1 to 8, wherein the upper portion of the isolation region extends laterally further than the passing word line.

[0124] Embodiment 10: The microelectronic device of any one of embodiments 1 to 9, wherein the isolation region comprises silicon dioxide.

[0125] Embodiment 11: The microelectronic device of any one of embodiments 1 to 9, wherein the isolation region comprises aluminum oxide.

[0126] Embodiment 12: The microelectronic device of any one of Embodiments 1 to 11, wherein a distance between opposite sidewalls of the second pillar is smaller than a distance between opposite sidewalls of the first pillar.

[0127] Embodiment 13: A microelectronic device, comprising: a first column of semiconductor material; a second column of semiconductor material, the second column of semiconductor material being adjacent to the first column of semiconductor material, the second column having a lateral dimension smaller than a lateral dimension of the first column; a first electrode structure, the first electrode structure being between the first column and each second column in the second column; and a second electrode structure, the second electrode structure being on a side of the second column opposite to the first electrode structure.

[0128] Embodiment 14: According to the microelectronic device described in embodiment 13, it further includes an insulating material, which is between the first electrode structure and the first column and between the second electrode structure and the second column, and the thickness of the insulating material between the second electrode structure and the second column is greater than the thickness of the insulating material between the first electrode structure and the first column.

[0129] Embodiment 15: The microelectronic device according to embodiment 13 or embodiment 14 further comprises an isolation structure, wherein the isolation structure is located directly below the second electrode structure, and the isolation structure comprises a substantially circular cross-sectional shape, and its lateral dimension is larger than the lateral dimension of the second electrode structure.

[0130] Embodiment 16: The microelectronic device of Embodiment 15, wherein at least a portion of the isolation structure extends under the first electrode structure.

[0131] Embodiment 17: The microelectronic device of any one of Embodiments 13 to 16, wherein a height of the first electrode structure is different from a height of the second electrode structure.

[0132] Embodiment 18: A method for forming a microelectronic device, the method comprising: forming an isolation structure in a semiconductor material, forming the isolation structure comprising: forming a first opening pattern in the material; forming a second opening pattern in the material that is laterally offset from the first opening pattern; transferring the first opening pattern and the second opening pattern to a substrate material; and filling the openings in the substrate material with an insulating material; removing a portion of the insulating material to form an opening above the isolation structure; forming a dielectric material within the opening; and forming a conductive material adjacent to the dielectric material.

[0133] Embodiment 19: The method of Embodiment 18, wherein transferring the first opening pattern and the second opening pattern to a base material comprises isotropically removing a portion of the base material.

[0134] Embodiment 20: The method according to Embodiment 18 or Embodiment 19, further comprising removing portions of the semiconductor material between the isolation structures while forming the openings above the isolation structures.

[0135] Embodiment 21: The method of any one of Embodiments 18 to 20, wherein removing portions of the semiconductor material comprises forming pillars of the semiconductor material between the isolation structures.

[0136] Embodiment 22: The method of any one of Embodiments 18 to 21, further comprising forming additional conductive material within the semiconductor material between the isolation structures.

[0137] Embodiment 23: The method of any one of embodiments 18 to 22, further comprising forming pillars of the semiconductor material between the conductive material of the openings, at least some of the pillars having lateral dimensions different from lateral dimensions of at least another of the pillars.

[0138] Embodiment 24: The method of any one of Embodiments 18 to 24, wherein forming a dielectric material within the opening comprises forming the dielectric material adjacent to a vertically extending portion of the insulating material.

[0139] Embodiment 25: An electronic system, comprising: an input device; an output device; a processor device, the processor device being operably coupled to the input device and the output device; and a memory device, the memory device being operably coupled to the processor device and comprising at least one microelectronic device, the at least one microelectronic device comprising: an embedded access device, the embedded access device comprising: a first electrode, the first electrode being between a first column of semiconductor material and a second column of the semiconductor material; and an oxide material, the oxide material being between the first electrode and each of the first column and the second column; a transfer word line structure, the transfer word line structure being adjacent to the second column, the transfer word line structure comprising: a second electrode, the second electrode being adjacent to the second column; and another oxide material, the another oxide material being between the second electrode and the second column; and an isolation structure, the isolation structure being located directly below the transfer word line structure and comprising a widened portion, the lateral dimension of the widened portion being greater than the lateral dimension of the transfer word line structure.

[0140] Although certain illustrative embodiments have been described in conjunction with the accompanying drawings, it will be recognized and appreciated by those skilled in the art that the embodiments covered by the present disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications, including legal equivalents, may be made to the embodiments described herein without departing from the scope of the embodiments covered by the present disclosure (such as the embodiments claimed hereinafter). Additionally, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the present disclosure.

Claims

1. A microelectronic device comprising: The first column of semiconductor materials; a second column of the semiconductor material, the second column of the semiconductor material being adjacent to the first column of the semiconductor material; an active word line extending between the first pillar and the second pillar; as well as A transfer word line extends on a side of the second pillar opposite the active word line, the transfer word line extending into an isolation region within the semiconductor material, the isolation region including a lower portion and an upper portion, the upper portion having a substantially circular cross-sectional shape and a larger lateral dimension than the lower portion.

2. The microelectronic device of claim 1, further comprising an additional active word line adjacent to the active word line.

3. The microelectronic device of claim 2, further comprising an additional passing word line, the active word line, and the additional active word line between the passing word line and the additional passing word line.

4. The microelectronic device of claim 1, further comprising a memory element electrically coupled to the second pillar.

5. The microelectronic device of claim 1 , further comprising a dielectric material between: the active word line and the first pillar; and The transfer word line and the second pillar.

6. The microelectronic device of claim 5, further comprising an insulating material extending from the isolation region and along the dielectric material between the passing word line and the second pillar.

7. The microelectronic device of claim 5, wherein the dielectric material comprises a different material composition than the isolation region.

8. The microelectronic device of any one of claims 1 to 7, wherein a diameter of the upper portion is in a range of about 10 nanometers (nm) to about 40 nm.

9. The microelectronic device of any one of claims 1 to 7, wherein the upper portion of the isolation region extends laterally further than the passing word line.

10. A microelectronic device as claimed in any one of claims 1 to 7, wherein the isolation region comprises silicon dioxide.

11. A microelectronic device as claimed in any one of claims 1 to 7, wherein the isolation region comprises aluminum oxide.

12. The microelectronic device of any one of claims 1 to 7, wherein a distance between opposing sidewalls of the second pillar is smaller than a distance between opposing sidewalls of the first pillar.

13. A microelectronic device comprising: The first column of semiconductor materials; a second column of semiconductor material, the second column of semiconductor material being adjacent to the first column of semiconductor material, the second column having a lateral dimension that is smaller than a lateral dimension of the first column; a first electrode structure between the first pillar and each of the second pillars; a second electrode structure on a side of the second column opposite the first electrode structure; as well as An insulating material is provided between the first electrode structure and the first column and between the second electrode structure and the second column, wherein a thickness of the insulating material between the second electrode structure and the second column is greater than a thickness of the insulating material between the first electrode structure and the first column.

14. The microelectronic device of claim 13, further comprising an isolation structure located directly below the second electrode structure, the isolation structure comprising a substantially circular cross-sectional shape having a lateral dimension greater than a lateral dimension of the second electrode structure.

15. The microelectronic device of claim 14, wherein at least a portion of the isolation structure extends under the first electrode structure.

16. The microelectronic device of any one of claims 13 to 15, wherein a height of the first electrode structure is different from a height of the second electrode structure.

17. A method of forming a microelectronic device, the method comprising: An isolation structure is formed in a semiconductor material, wherein forming the isolation structure comprises: forming a first pattern of openings in a material; forming a second pattern of openings in the material laterally offset from the first pattern of openings; transferring the first opening pattern and the second opening pattern to a base material; and filling the opening in the base material with an insulating material; removing portions of the insulating material to form openings over the isolation structures and removing portions of the semiconductor material between the isolation structures to form: a first column of semiconductor material; and a second column of the semiconductor material adjacent to the first column of the semiconductor material, the second column having a smaller lateral dimension than the first column; forming a conductive material adjacent to the dielectric material to form: a first electrode structure between the first pillar and each of the second pillars; and A second electrode structure, wherein the second electrode structure is located on a side of the second column opposite to the first electrode structure, the insulating material is located between the first electrode structure and the first column and between the second electrode structure and the second column, and the insulating material between the second electrode structure and the second column has a greater thickness than the insulating material between the first electrode structure and the first column. 18 . The method of claim 17 , wherein transferring the first opening pattern and the second opening pattern to a base material comprises isotropically removing a portion of the base material.

19. The method of claim 17, wherein removing a portion of the insulating material and removing portions of the semiconductor material between the isolation structures comprises removing the portions of the semiconductor material simultaneously with removing the portion of the insulating material.

20. The method of claim 19, wherein removing portions of the semiconductor material comprises forming the first and second pillars of the semiconductor material between the isolation structures.

21. The method of any one of claims 17 to 20, further comprising forming additional conductive material within the semiconductor material between the isolation structures.

22. The method of claim 17, wherein removing a portion of the insulating material comprises leaving a portion of the insulating material on a portion of the second pillar.

23. An electronic system comprising: Input device; Output device; a processor device operatively coupled to the input device and the output device; as well as a memory device operatively coupled to the processor device and comprising at least one microelectronic device, the at least one microelectronic device comprising: An embedded access device, the embedded access device comprising: a first electrode between a first column of semiconductor material and a second column of semiconductor material; and an oxide material between the first electrode and each of the first pillar and the second pillar; a transfer word line structure, the transfer word line structure being adjacent to the second pillar, the transfer word line structure comprising: a second electrode adjacent to the second pillar; and another oxide material, the another oxide material being between the second electrode and the second pillar; and An isolation structure is located directly below the passing wordline structure and includes a widened portion including a substantially circular vertical cross-sectional shape and having a lateral dimension greater than a lateral dimension of the passing wordline structure.

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