Semiconductor devices and their manufacturing methods

Abstract

This disclosure relates to semiconductor devices and methods of manufacturing the same. A semiconductor device includes: a gate structure, a double-diffused region, a source region, a drain region, a first gate spacer, and a second gate spacer. The gate structure is located on a semiconductor substrate. The double-diffused region is located in the semiconductor substrate and extends laterally beyond a first side of the gate structure. The source region is located in the semiconductor substrate and is adjacent to a second side of the gate structure, the second side being opposite to the first side. The drain region is located in the double-diffused region in the semiconductor substrate and has the same conductivity type as the double-diffused region. The first gate spacer is located on the first side of the gate structure. The second gate spacer extends upward from the double-diffused region along the outermost wall of the first gate spacer and terminates before reaching the top surface of the gate structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from shrinking semiconductor process nodes (e.g., reducing process nodes to less than 20nm). As semiconductor devices shrink, new technologies are needed to maintain the performance of electronic components from one generation to the next. For example, for various high-power applications, low on-resistance and high breakdown voltage of transistors are desirable.

[0003] With the development of semiconductor technology, metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely used in today's integrated circuits. MOSFETs are voltage-controlled devices. When a control voltage is applied to the gate of the MOSFET and the control voltage is greater than the MOSFET's threshold voltage, a conductive channel is established between the drain and source of the MOSFET. As a result, current flows between the drain and source of the MOSFET. On the other hand, when the control voltage is less than the MOSFET's threshold voltage, the MOSFET is turned off accordingly.

[0004] Based on the difference in conductivity type, MOSFETs can be divided into two main categories: n-channel MOSFETs and p-channel MOSFETs. On the other hand, based on structural differences, MOSFETs can be further divided into three subcategories: planar MOSFETs, laterally diffused MOSFETs (LDMOS), and vertically diffused MOSFETs. Summary of the Invention

[0005] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a gate structure located on a semiconductor substrate; a double-diffused region located in the semiconductor substrate and extending laterally beyond a first side of the gate structure; a source region located in the semiconductor substrate and adjacent to a second side of the gate structure, the second side being opposite to the first side; a drain region located in the double-diffused region in the semiconductor substrate and having the same conductivity type as the double-diffused region; a first gate spacer located on the first side of the gate structure; and a second gate spacer extending upward from the double-diffused region along the outermost wall of the first gate spacer and terminating before reaching the top surface of the gate structure, wherein the second gate spacer has an outermost end surface aligned with the boundary of the drain region.

[0006] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a double-diffused region located in the semiconductor substrate; a gate structure overlapping at least a portion of the double-diffused region; a drain region located in the double-diffused region and having the same conductivity type as the double-diffused region; a first gate spacer located adjacent to the gate structure and above the double-diffused region; a drain silicide layer extending laterally along the top surface of the drain region from the outermost end surface of the first gate spacer; and a second gate spacer located above the first gate spacer and having an outermost end aligned with the boundary of the drain region.

[0007] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a body region having a first conductivity type and a doped region having a second conductivity type in a semiconductor substrate; forming a gate structure over a portion of the body region and over a portion of the doped region; forming a first gate spacer on a first side and a second side of the gate structure, respectively; sequentially depositing a second spacer layer and a third spacer layer over the gate structure; patterning the third spacer layer into third gate spacers located on the first side and the second side of the gate structure, respectively; removing the first third gate spacer from the first side of the gate structure, leaving a second third gate spacer on the second side of the gate structure; patterning the second spacer layer into a second gate spacer using the second third gate spacer as an etch mask; and after patterning the second spacer layer, forming a source region having the second conductivity type in the body region and a drain region having the second conductivity type in the doped region. Attached Figure Description

[0008] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A and Figure 1B A block diagram of a method for forming a semiconductor device according to some embodiments is shown.

[0010] Figures 2 to 20 Methods for manufacturing semiconductor devices at different stages are illustrated according to some embodiments.

[0011] Figure 21 and Figure 22Methods for manufacturing semiconductor devices at different stages are illustrated according to some embodiments.

[0012] Figure 23A and Figure 23B A block diagram of a method for forming a semiconductor device according to some embodiments is shown.

[0013] Figure 24 A method for manufacturing a semiconductor device in stages, according to some embodiments, is illustrated.

[0014] Figures 25 to 28 Methods for manufacturing semiconductor devices at different stages are illustrated according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit this disclosure. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or characters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, spatially related terms (such as "below," "below," "lower than," "above," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0017] As used herein, “about,” “approximately,” “approximately,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “about,” “approximately,” “approximately,” or “substantially” can be inferred unless explicitly stated otherwise.

[0018] Laterally diffused (LD) MOS transistors have advantages. For example, LDMOS transistors can deliver more current per unit area because their asymmetric structure provides a short channel between the drain and source. However, some problems with LDMOS transistors have been recognized, as described below. Due to the large field oxide (FOX) structure between the source and drain regions of the LDMOS transistor, LDMOS transistors formed using FOX will result in excessively large device size and excessively high specific on-resistance (R). sp On the other hand, if the LDMOS transistor is formed without FOX, non-self-aligned implantation is used to form the source / drain regions of the LDMOS transistor, and a resist protection layer (RPO) is used to define the desired silicide region in the drain region of the LDMOS transistor. However, non-self-aligned implantation may produce undoped regions in the polysilicon gate of the LDMOS transistor because the photolithography used in non-self-aligned implantation may suffer from misalignment, and the RPO may produce non-silicide regions in the polysilicon gate because the RPO may be formed above the top surface of the polysilicon gate. Furthermore, due to the minimum length limitation of the RPO, the drift region of the LDMOS transistor may not be scaled down proportionally.

[0019] This disclosure will be described in a specific context with reference to embodiments, using an improved process flow to fabricate LDMOS transistors to address the aforementioned problems caused by FOX and RPO. However, embodiments of this disclosure can also be applied to various metal-oxide-semiconductor transistors. Various embodiments will now be described in detail with reference to the accompanying drawings.

[0020] Now for reference Figure 1A and Figure 1B An exemplary method M1 for manufacturing a semiconductor device according to some embodiments is illustrated, wherein the manufacturing includes a self-aligned implantation process for manufacturing the semiconductor device. Method M1 includes relevant portions of the overall manufacturing process. It should be understood that... Figure 1A and Figure 1B Additional operations are provided before, during, and after the operations shown, and some operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchangeable. Method M1 includes the fabrication of semiconductor device 100. However, the fabrication of semiconductor device 100 is merely an example illustrating a self-aligned implantation process for fabricating semiconductor device 100 according to some embodiments of this disclosure.

[0021] It should be noted that, for the purpose of better understanding the disclosed embodiments, simplifications have been implemented. Figure 1A and Figure 1BFurthermore, the semiconductor device 100 can be configured as a system-on-a-chip (SoC) device having various PMOS and NMOS transistors fabricated to operate at different voltage levels. The PMOS and NMOS transistors can provide low-voltage functions, including logic / memory devices and input / output devices, as well as high-voltage functions, including power management devices. For example, transistors providing low-voltage functions may have an operating (or drain) voltage of approximately 1.1V in standard CMOS technology, or approximately 1.8 / 2.5 / 3.3V for specialized (input / output) transistors in standard CMOS technology. Furthermore, transistors providing medium / high-voltage functions may have an operating (or drain) voltage of approximately 5V or greater (e.g., approximately 20-35V). It should be understood that... Figures 2-21 The semiconductor device 100 may also include resistors, capacitors, inductors, diodes, and other suitable microelectronic devices that can be implemented in the integrated circuit.

[0022] Figures 2 to 20 Methods for fabricating a semiconductor device 100 at different stages are illustrated according to some embodiments. Method M1 begins at block S10, in which an isolation structure 142 is formed in a semiconductor substrate 110, such as... Figure 2 As shown. Semiconductor substrate 110 may include a semiconductor wafer, such as a silicon wafer. Alternatively, semiconductor substrate 110 may include other elemental semiconductors, such as germanium. Semiconductor substrate 110 may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or other suitable materials. Furthermore, semiconductor substrate 110 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenide, and gallium indium phosphide, or other suitable materials. In some embodiments, semiconductor substrate 110 includes an epitaxial layer (epi layer) covering the bulk semiconductor. Additionally, semiconductor substrate 110 may include a semiconductor-on-insulator (SOI) structure. For example, semiconductor substrate 110 may include a buried oxide (BOX) layer formed by a process such as oxygen implantation isolation (SIMOX). In various embodiments, semiconductor substrate 110 may include a buried layer, such as an n-type buried layer (NBL), a p-type buried layer (PBL), and / or a buried dielectric layer including a buried oxide (BOX) layer. In some embodiments, shown as an n-type MOS, semiconductor substrate 110 includes a p-type silicon substrate (p substrate). For example, a p-type impurity (e.g., boron) is doped into the semiconductor substrate 110 to form a p-substrate. To form a complementary MOS, an n-type buried layer, i.e., a deep n-well (DNW), can be implanted deep beneath the active region of the p-substrate 110. In some embodiments, arsenic or phosphorus ions are implanted to form the DNW. In some other embodiments, the DNW is formed by selective diffusion. The DNW is used to electrically isolate the p-substrate.

[0023] exist Figure 2 In this process, isolation structures 142 (e.g., shallow trench isolation (STI)) or localized oxides (LOCOS) (or field oxides, FOX) of silicon including isolation regions can be formed in the semiconductor substrate 110 to define and electrically isolate various active regions, thereby preventing leakage current from flowing between adjacent active regions. As an example, the formation of STI features may include dry etching trenches in the substrate and filling the trenches with an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials). The filled trenches may have a multilayer structure, such as a thermal oxide liner filled with silicon nitride or silicon oxide. In some other embodiments, the STI structure can be created using a process sequence such as the following: growing a pad oxide, forming a low-pressure chemical vapor deposition (LPCVD) nitride layer, patterning the STI openings using photoresist and a mask, etching trenches in the substrate, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trenches with CVD oxide, planarizing the CVD oxide using a chemical mechanical polishing (CMP) process, and removing the silicon nitride using a nitride stripping process. In some embodiments where the CVD oxide of the STI region 142 is formed using a flowable CVD, an annealing process can be performed to solidify the deposited oxide.

[0024] return Figure 1A Method M1 then proceeds to block S11, where a gate dielectric layer is formed on the semiconductor substrate. (See reference...) Figure 3 In some embodiments of block S11, a gate dielectric layer 162' is formed on the semiconductor substrate 110. The gate dielectric layer 162' may include a silicon oxide layer. Alternatively, the gate dielectric layer 162' may include a high-k dielectric material. The high-k material may be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, hafnium oxide, other suitable materials, or combinations thereof. Alternatively, the gate dielectric layer 162' may include oxide and / or nitride materials. For example, the gate dielectric layer 162' may include silicon oxide, silicon nitride, silicon oxynitride, SiCN, or SiC. x O y N z Other suitable materials, or combinations thereof. For example, the gate dielectric layer 162' may include silicon oxide. In some embodiments, the gate dielectric layer 162' may have a multilayer structure, such as a layer of silicon oxide and another layer of high-k material. The gate dielectric layer 162' may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxide, other suitable processes, or combinations thereof.

[0025] return Figure 1A Method M1 then proceeds to block S12, where a conductive layer is formed over the gate dielectric layer. (See reference...) Figure 4 In some embodiments of block S12, a conductive layer 164' is formed over the gate dielectric layer 162'. The conductive layer 164' may comprise polycrystalline silicon (interchangeably referred to as polysilicon). Alternatively, the conductive layer 164' may comprise a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof. The conductive layer 164' may be formed by CVD, PVD, electroplating, and other suitable processes. The conductive layer 164' may have a multilayer structure and may be formed in a multi-step process using a combination of different processes.

[0026] return Figure 1A Method M1 then proceeds to block S13, where a conductive layer is patterned to form a gate electrode. (See reference...) Figure 5 In some embodiments of block S13, patterning Figure 4 A conductive layer 164' is formed on the gate dielectric layer 162' to form a gate electrode 164. In some embodiments, in Figure 4 In this process, a patterned mask layer (not shown) is formed on the conductive layer 164'. The patterned mask layer can be formed by a series of operations, including deposition, photolithographic patterning, and etching processes. The photolithographic patterning process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), and / or other suitable processes. The etching process may include dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching). Then, one or more etching processes are performed using the patterned mask as an etching mask to form the gate electrode 164 on the gate dielectric layer 162', and the patterned mask layer is removed after etching.

[0027] return Figure 1A Method M1 then proceeds to block S14, where n-type doped regions and p-type doped regions are formed in the semiconductor substrate. (See reference...) Figure 6 In some embodiments of block S14, an n-type double-diffused (NDD) doped region 152 is formed in the semiconductor substrate 110 and near the top surface 112 of the semiconductor substrate 110. In this context, a "double-diffused" doped region is a doped region that undergoes a double-implantation process with dopants of the same conductivity type during the fabrication of an LDMOS transistor. For example, in Figure 6 In the steps shown, region 152 is implanted with an n-type dopant, and then... Figure 17In the steps shown, a portion of region 152 will be implanted with n-type dopant again, and therefore this region is referred to as a double-diffused doped region (e.g., a double-diffused drain region in this embodiment). It should be noted that the double-diffused doping distribution will... Figure 17 Formed in the steps shown, rather than in Figure 6 The double-diffused region is formed in the steps shown, and the term “double-diffused region” used in this step is used only to distinguish it from the body region of an LDMOS transistor.

[0028] In some embodiments, the NDD region 152 is formed by ion implantation, diffusion techniques, or other suitable techniques. For example, ion implantation using an n-type dopant (e.g., arsenic or phosphorus) can be performed to form the NDD region 152 in the semiconductor substrate 110 using a first patterned mask layer (e.g., a first patterned photoresist mask) and a portion of the gate electrode 164 as an implantation mask, through the gate dielectric layer 162'. Figure 6 In this process, due to the implantation tilt angle used for ion implantation to form the NDD region 152, the NDD region 152 has a portion located below the gate electrode 164. For example, a first mask layer (e.g., a patterned photoresist mask) is formed to cover the left portion of the gate electrode 164 and a region of the semiconductor substrate 110 near the left portion of the gate electrode 164, while exposing the right portion of the gate electrode 164 and another region of the semiconductor substrate 110 near the right portion of the gate electrode 164. In some embodiments, the first mask layer can be formed by a photolithography process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), and / or other suitable processes. An implantation process is then performed to implant n-type dopant at a tilt angle (as shown by arrow A1) using the first mask layer and the gate electrode 164 as an implantation mask, thereby forming the NDD region 152 in the semiconductor substrate 110 and extending directly below the gate electrode 164 due to the tilt angle. The first mask layer is then removed after the NDD region 152 is formed. In some embodiments, the dopant concentration of the NDD region 152 is, for example, but not limited to, about 10 ppm. 16 To about 10 18 The concentrations of other dopant components are within the range specified in this disclosure. In some embodiments, the isolation structure 142 has a depth D1. In some embodiments, the NDD region 152 has a depth D4 that is less than the depth D1 of the isolation structure 142. By way of example, and not limitation, the ratio of the depth D4 of the NDD region 152 to the depth D1 of the STI 142 is in the range of about 0.2 to about 1. In some other embodiments, the depth D4 of the NDD region 152 may be greater than the depth D1 of the isolation structure 142.

[0029] Then, a p-type doped region (interchangeably referred to as a p-body region) 156 is formed in the semiconductor substrate 110 and near the top surface 112 of the semiconductor substrate 110. Specifically, the p-body region 156 is formed between the NDD region 152 and the isolation structure 142. In some embodiments, the p-body region 156 is formed by ion implantation, diffusion techniques, or other suitable techniques. For example, ion implantation using a p-type dopant (e.g., boron) can be performed to form the p-body region 156 in the semiconductor substrate 110 through the gate dielectric layer 162' using a second patterned mask layer (e.g., a second patterned photoresist mask) and the left side of the gate electrode 164 as the implantation mask. Figure 6 In this process, due to the implantation tilt angle used for ion implantation to form the p-body region 156, the p-body region 156 has a portion located below the gate electrode 164. For example, a second mask layer is formed to cover the right-side portion of the gate electrode 164 and the NDD region 152, while exposing the left-side portion of the gate electrode 164 and a region of the semiconductor substrate 110 near the left-side portion of the gate electrode 164. In some embodiments, the second mask layer can be formed by a photolithographic patterning process. The photolithographic patterning process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), and / or other suitable processes. An implantation process is then performed to implant p-type dopant at a tilt angle (as shown by arrow A2) using the second mask layer and the gate electrode 164 as an implantation mask, thereby forming the p-body region 156 in the semiconductor substrate 110 and extending directly below the gate electrode 164 due to the tilt angle. The second mask layer is then removed after the p-body region 156 is formed. Ion implantation using p-type dopants (e.g., boron and / or boron difluoride (BF2)) can be performed to form p-body regions 156 in the semiconductor substrate 110. In some embodiments, the dopant concentration of each of the p-body regions 156 may be approximately 10⁻⁶ per cubic centimeter. 17 To about 10 19 The dopant concentrations are within the range of the NDD region 152, and other dopant concentrations are within the range of this disclosure. In some embodiments, the dopant concentration of the p-body region 156 may be greater than the dopant concentration of the NDD region 152. Although the embodiments discussed above include forming the p-body region 156 after forming the NDD region 152, in some other embodiments, the p-body region 156 may be formed before forming the NDD region 152.

[0030] In some embodiments, the depth D5 of the p-body region 156 is less than the depth D1 of the isolation structure 142 and greater than the depth D4 of the NDD region 152. In some other embodiments, the depth D5 of the p-body region 156 may be less than the depth D4 of the NDD region 152. In some other embodiments, the depth D5 of the p-body region 156 may be greater than the depth D1 of the isolation structure 142.

[0031] It should be understood that Figure 1A and Figure 1B The sequence of operations / processes shown may be interchangeable. In some embodiments, the NDD region 152 may be formed before the formation of the gate dielectric layer 162' and after the formation of the isolation structure 142. For example, the NDD region 152 may be formed by ion implantation, diffusion techniques, or other suitable techniques using a patterned photoresist layer. A photoresist layer is coated on the semiconductor substrate 110, and then the coated photoresist layer is patterned in a photolithography process or other suitable process using a photomask. An exemplary photolithography process may include process steps of photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development, and hard baking. The patterned photoresist layer exposes a region of the semiconductor substrate 110. Subsequently, ion implantation using an n-type dopant (e.g., arsenic or phosphorus) may be performed to form the NDD region 152 in the semiconductor substrate 110 using the patterned photoresist layer as an implantation mask.

[0032] In some embodiments, the P-body region 156 is formed before the formation of the gate dielectric layer 162' and after the formation of the isolation structure 142. For example, the P-body region 156 can be formed by ion implantation, diffusion techniques, or other suitable techniques using a patterned photoresist layer. The photoresist layer defining the NDD region 152 is stripped by ashing, and then another photoresist layer is coated on the semiconductor substrate 110. Next, another photomask having the pattern of the P-body region 156 is used to pattern the photoresist layer in a photolithography process or other suitable process. An exemplary photolithography process may include process steps such as photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development, and hard baking.

[0033] return Figure 1A Method M1 then proceeds to block S15, in which a first spacer layer is deposited over the gate electrode and the gate dielectric layer. (See reference...) Figure 7 In some embodiments of block S15, the first spacer layer 170' is blanket-deposited on Figure 6The structure shown is above (i.e., above the NDD region 152, the p-body region 156, the gate dielectric layer 162', the gate electrode 164, and the isolation feature 142). In some embodiments, the first spacer layer 170' may include silicon oxide, silicon nitride, silicon oxynitride, SiCN, or SiC. x O y N z Other suitable materials or combinations thereof. For example, the first spacer layer 170' may be a dielectric material such as silicon nitride. In some embodiments, the first spacer layer 170' comprises a material different from that of the gate dielectric layer 162'. In some embodiments, the first spacer layer 170' may have a multilayer structure. The first spacer layer 170' may be formed using deposition methods such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), subatmospheric chemical vapor deposition (SACVD), etc.

[0034] return Figure 1A Method M1 then proceeds to block S16, where the first spacer layer is etched to form the first gate spacer. (See reference...) Figure 8 In some embodiments of block S16, a first gate spacer 170 is formed on the opposite side of the gate electrode 164. More specifically, an isotropic etching process P1 is performed to remove the horizontal portion of the first spacer layer 170'. The remaining vertical portion of the first spacer layer 170' forms the first gate spacer 170. The first gate spacer 170 has a height H2 measured from the top surface of the semiconductor substrate 110, and the gate electrode 164 has a height H1 measured from the top surface of the semiconductor substrate 110. In some embodiments, due to the property that the isotropic etching process selectively etches the material of the first gate spacer 170 at a faster etch rate than etching the polysilicon gate 164, the height H2 of the first gate spacer 170 may be lower than the height H1 of the gate electrode 164. The height H2 of the first gate spacer 170 depends on the process conditions of the isotropic etching process P1 (e.g., etch duration, etc.). Furthermore, each of the first gate spacers 170 has a vertical portion 170v and a lateral portion 170l. The vertical portion 170v extends vertically along the vertical sidewall of the gate electrode 164, and the lateral portion 170l extends laterally from the outermost sidewall of the vertical portion 170v by a short length L1. The length L1 of the lateral portion 170l also depends on the process conditions of the isotropic etching process P1 (e.g., etching duration, etc.). In some embodiments, the first spacer layer 170' is etched using, for example but not limited to, phosphoric acid (H3PO4).

[0035] return Figure 1AMethod M1 then proceeds to block S17, where a blanket gate dielectric layer is etched to form a patterned gate dielectric layer. (See reference...) Figure 9 In some embodiments of block S17, such as Figure 8 The blanket gate dielectric layer 162' shown is patterned to form a gate dielectric layer 162 remaining beneath the gate electrode 164 and the first gate spacer 170. More specifically, another etching process P2 is performed to pattern the gate dielectric layer 162 using the gate electrode 164 and the gate spacer 170 as an etch mask. By way of example, and not limitation, in some cases where the gate dielectric layer 162 is silicon oxide, liquid hydrogen fluoride (HF) or gaseous HF can be used as an etchant to pattern the gate dielectric layer 162. The gate dielectric layer 162 and the gate electrode 164 are combined to form a gate structure 160 having a vertical axis of symmetry A. Figure 9 As shown, the gate structure 160 covers a portion of the NDD region 152 and the p-body region 156.

[0036] return Figure 1A Method M1 then proceeds to block S18, where a second spacer layer is deposited on the semiconductor substrate. (See reference...) Figure 10 In some embodiments of block S18, the second spacer layer 180' is blanket-deposited on, for example... Figure 9 The structure shown is over the NDD region 152, p-body region 156, gate dielectric layer 162, gate electrode 164, first gate spacer 170, and STI region 142. In some embodiments, the second spacer layer 180' may include silicon oxide, silicon nitride, silicon oxynitride, SiCN, or SiC. x O y N z Other suitable materials or combinations thereof. For example, the second spacer layer 180' may be a dielectric material such as silicon oxide. In some embodiments, the second spacer layer 180' may include a material different from that of the first gate spacer 170. In some embodiments, the material of the second spacer layer 180' may be the same as that of the gate dielectric layer 162 (e.g., silicon oxide). In some embodiments, the second spacer layer 180' may have a multilayer structure. The second spacer layer 180' may be formed using deposition methods such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), subatmospheric chemical vapor deposition (SACVD), etc.

[0037] return Figure 1A Method M1 then proceeds to block S19, where a third spacer layer is deposited on top of the second spacer layer. (See reference...) Figure 11In some embodiments of block S19, the third spacer layer 182' is blanket-deposited over the second spacer layer 180'. In some embodiments, the third spacer layer 182' may include silicon oxide, silicon nitride, silicon oxynitride, SiCN, or SiC. x O y N z Other suitable materials or combinations thereof. For example, the third spacer layer 182' may be a dielectric material such as silicon nitride. In some embodiments, the third spacer layer 182' may include a material different from that of the second spacer layer 180'. In some embodiments, the material of the third spacer layer 182' may be the same as that of the first gate spacer 170. In some specific embodiments, the first gate spacer 170 and the third spacer layer 182' are formed of silicon nitride, and the second spacer layer 180' is formed of silicon oxide.

[0038] In some embodiments, the third spacer layer 182' may have a multilayer structure. In some embodiments, the thickness T1 of the second spacer layer 180' may be less than the thickness T2 of the third spacer layer 182'. For example, the thickness T1 of the second spacer layer 180' may be in the range from about 10 nm to about 50 nm, and the thickness T2 of the third spacer layer 182' may be in the range from about 50 nm to about 300 nm, and other thickness ranges are within the scope of this disclosure. In some embodiments, if the thickness T1 of the second spacer layer 180' is less than about 10 nm, the second spacer layer 180', the polysilicon gate 164, the first gate spacer 170, and the semiconductor substrate 110 may be etched in the following etching process P3 (e.g., ...). Figure 12 The second spacer 182 may be damaged (as shown in the image) and this could reduce yield. If the thickness T1 is greater than about 50 nm, the top surface of the second spacer 180' may be undesirably flat, such that when the third spacer etching process P3 is completed, the lateral width of the third spacer 182 may not be usable for subsequent self-aligned implantation processes P7 (as shown in the image). Figure 17The implantation mask is shown. In some embodiments, if the thickness T2 of the third spacer layer 182' is less than about 50 nm, the lateral width of the third spacer 182 may not be usable as a mask for the self-aligned implantation process P7 when the third spacer etching process P3 is completed. If the thickness T2 is greater than about 300 nm, the process time of the etching process P3 may increase, and the second spacer layer 180', polysilicon 164, first gate spacer 170, and semiconductor substrate 110 may be further damaged, and the yield may be reduced. In other words, the ratio of thickness T2 to thickness T1 is in the range of about 1 to about 30, and other thickness ranges are within the scope of this disclosure. In some embodiments, if the ratio of thickness T2 to thickness T1 is less than about 1, the lateral width of the third spacer 182 may not be usable as a mask for the self-aligned implantation process P7 when the third spacer etching process P3 is completed. If the ratio of thickness T2 to thickness T1 is greater than approximately 30, the process time of etching process P3 may increase and may further damage the second spacer layer 180', polysilicon 164, first gate spacer 170, and semiconductor substrate 110, and thus may reduce yield. The thickness T1 of the second spacer layer 180' and the thickness T2 of the third spacer layer 182' are determined based on the subsequently formed drain region (e.g., as shown in the image). Figure 18 The drain region 174 shown) and the silicide region formed on the drain region (e.g., as shown) Figure 20 The desired location of the silicide region 220 shown is selected. In other words, the thickness T1 of the second spacer layer 180' and the thickness T2 of the third spacer layer 182' are selected to achieve the desired drift region length (e.g., as shown). Figure 18 The drift region length S1 is shown. In other words, if the thicknesses T1 and T2 are excessively smaller than the selected range, the drift region length may be undesirably short, and thus result in a lower device breakdown voltage; if the thicknesses T1 and T2 are excessively larger than the selected range, the drift region length may be undesirably long, and thus result in poor resistance. In some embodiments, the third spacer layer 182' may be formed using a deposition method such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), subatmospheric chemical vapor deposition (SACVD), etc.

[0039] return Figure 1B Method M1 then proceeds to block S20, where a third spacer layer is etched to form a third gate spacer over the second spacer layer. (See reference...) Figure 12In some embodiments of block S20, an anisotropic etching process P3 is performed to remove the horizontal portion of the third spacer layer 182'. The etching operation P3 etches the third spacer layer 182' at a faster etch rate than it etches the second spacer layer 180'. By way of example, and not limitation, the ratio of the etch rate of the third spacer layer 182' to the etch rate of the second spacer layer 180' can be greater than about 2. If the ratio of the etch rate of the third spacer layer 182' to the etch rate of the second spacer layer 180' is less than about 2, the etch operation P3 will significantly deplete the second spacer layer 180', and therefore the second spacer layer 180', polysilicon 164, first gate spacer 170, and semiconductor substrate 110 may be damaged, and thus yield may be reduced. In some embodiments, the ratio of the etch rate of the third spacer layer 182' to the etch rate of the second spacer layer 180' can be greater than about 10. In some embodiments, phosphoric acid (H3PO4) is used, for example, to etch the third spacer layer 182'.

[0040] return Figure 1B Method M1 then proceeds to block S21, in which a first mask layer is formed, wherein the first mask layer covers the portion of the gate structure, the first gate spacer, the third gate spacer, and the second spacer layer located on one side of the axis of symmetry of the gate structure, and exposes the other portion of the gate structure, the first gate spacer, the third gate spacer, and the second spacer layer located on the other side of the axis of symmetry of the gate structure. (See reference...) Figure 13 In some embodiments of block S21, the mask layer 190 is formed on the semiconductor substrate 110 and then patterned to form individual mask portions to cover, for example, Figure 13 The portion of the gate structure 160, the first gate spacer 170, the third gate spacer 182, and the second spacer layer 180' shown are located to the right of the axis of symmetry A of the gate structure 160, and are exposed as shown. Figure 13 The gate structure 160, the first gate spacer 170, the third gate spacer 182, and the second spacer layer 180' shown are located on the left side of the axis of symmetry A of the gate structure.

[0041] In some embodiments, the mask layer 190 may be formed by a photolithographic patterning process. The photolithographic patterning process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking) and / or other suitable processes.

[0042] return Figure 1B Method M1 then proceeds to block S22, where the third gate spacer exposed by the first mask layer is removed. (See reference...) Figure 14In some embodiments of block S22, one or more etching processes are performed to remove the third gate spacer 182 located on the second spacer layer 180 using mask layer 190 as an etching mask. For example, etching process P4 is performed to remove the third gate spacer 182 exposed by mask layer 190. Etching process P4 is a selective etching process that uses an etchant to etch the nitride spacer 182 at a faster etch rate than etching oxide spacer layer 180'. For example, etching process P4 etches the nitride spacer 182 at a rate approximately twice that of etching process P4 etches the oxide spacer layer 180'. If the etching rate of etching process P4 on the nitride spacer 182 is less than approximately twice the etching rate of etching process P4 on the oxide spacer layer 180', then etching process P4 may excessively consume the second spacer layer 180', and thus the second spacer layer 180', polysilicon 164, first gate spacer 170, and semiconductor substrate 110 may be damaged, potentially reducing yield. In this way, after removing the nitride spacer 182 from the left side of the axis of symmetry A of the gate structure 160, the oxide spacer layer 180' remains substantially intact. For example, the etchant used in etching process P4 includes phosphoric acid (H3PO4).

[0043] return Figure 1B Method M1 then proceeds to block S23, where the first mask layer is removed. (See reference...) Figure 15 In some embodiments of block S23, the mask layer 190 is removed after the third gate spacer 182 and dielectric layer 180 exposed by the mask layer have been etched. For example, if the mask layer 190 is photoresist, it is stripped by ashing.

[0044] return Figure 1B Method M1 then proceeds to block S24, in which the portion of the second spacer layer not covered by the third gate spacer 182 is removed to form a second gate spacer sandwiched between the first gate spacer and the third gate spacer. (See reference...) Figure 16In some embodiments of block S24, an etching operation P6 is performed to remove the portion of the second spacer layer 180' located to the left of the axis of symmetry A of the gate structure 160 using the third gate spacer 182 as an etching mask, and to remove the horizontal portion of the second spacer layer 180' located to the right of the axis of symmetry A of the gate structure 160, so as to form the second gate spacer 180 on only one side of the gate structure 160 (e.g., only on the right side of the gate structure 160). The etching operation P6 is a selective etching process that etches the oxide spacer layer 180' at a faster rate than it etches the nitride spacer 170, the polysilicon gate 164, and the third gate spacer 182. For example, the etching rate of the oxide spacer layer 180' by the etching operation P6 is approximately ten times greater than the etching rate of the nitride spacer 170, the polysilicon gate 164, and the nitride spacer 182. If the etching rate of etching operation P6 on the oxide spacer layer 180' is less than approximately ten times the etching rate of etching operation P6 on the nitride spacer 170, polysilicon gate 164, and nitride spacer 182, then etching operation P6 may excessively consume the nitride spacer 182 located to the right of the polysilicon gate 164 and the nitride spacer 170 located to the left of the polysilicon gate 170. Therefore, the excessively consumed nitride spacers 170 and 182 may not be usable for subsequent self-aligned implantation processes P7 (e.g., ...). Figure 17 The injection mask (shown) adversely affects the desired drift region length. In this way, after removing a portion of the second spacer layer 180', the nitride spacers 170 and 182 and the polysilicon gate 164 remain substantially intact.

[0045] exist Figure 16In this embodiment, the sidewall of the resulting second gate spacer 180 has a notched corner, and the third gate spacer 182 is embedded in the notched corner of the second gate spacer 180. In some embodiments, the outermost sidewall of the third gate spacer 182 is connected to the outermost end surface of the second gate spacer 180. The third gate spacer 182 is perpendicularly separated from the substrate 110 by the second gate spacer 180 and laterally separated from the gate electrode 164 by the second gate spacer 180 and the first gate spacer 170. The second gate spacer 180 and the third gate spacer 182 can be used in combination as silicide barrier layers during a subsequent self-aligned silicide (self-aligned silicide) process, which will be discussed in more detail below. The second gate spacer 180 and the third gate spacer 182 cover the device region intentionally excluded from the silicide process. This protects the region beneath the second gate spacer 180 and the third gate spacer 182 from subsequent silicide formation. NDD region 152 provides a resistive path, which acts as a voltage drop in the channel region, and thus the semiconductor device 100 has an improved blocking voltage capability.

[0046] The second gate spacer 180 can be defined by applying, for example, anisotropic etching that partially removes the second spacer layer 180' exposed by the third gate spacer 182. Therefore, the third gate spacer 182 can serve as an etch mask during etch operation P6. Thus, the width W1 of the remaining portion of the second spacer layer 180' (i.e., the second gate spacer 180) can be controlled by the thickness of the third gate spacer 182, which in turn controls the drift region within the NDD region 152 (i.e., the region in the NDD region 152 other than the subsequently formed drain region), thereby helping to reduce the drift region length.

[0047] Etching operation P6 etches the second spacer layer 180' at a faster etch rate than it etches the third gate spacer 182. By way of example, and not limitation, the ratio of the etch rate of the second spacer layer 180' to the etch rate of the third gate spacer 182 can be greater than about 10. If the ratio of the etch rate of the second spacer layer 180' to the etch rate of the third gate spacer layer 182' is less than about 10, then etching operation P6 will significantly consume the third gate spacer 182, and therefore the third gate spacer 182 may not be usable as an etch mask during etching operation P6, which in turn adversely affects the desired drift region length. In some embodiments, the ratio of the etch rate of the second spacer layer 180' to the etch rate of the third gate spacer 182 can be greater than about 10. In some embodiments, where silicon oxide is used as the oxide spacer layer 180', the second spacer layer 180' is etched using, for example, liquid hydrogen fluoride (HF) or gaseous HF. In some embodiments where the gate dielectric layer 162 is silicon oxide, the left end of the gate dielectric layer 162 can be recessed by an etchant used in the etching process P6, as indicated by the dashed line DL.

[0048] return Figure 1B Method M1 then proceeds to block S25, where the N-type source and drain regions are formed in the NDD or p-body region. (See reference...) Figure 17 In some embodiments of block S25, a self-aligned implantation process P7 is performed to dope N-type dopant into the p-body region 156 and the NDD region 152, thus forming an N-type source region 172 in the p-body region 156 and an N-type drain region 174 in the NDD region 152. Furthermore, the self-aligned implantation process P7 also dopes N-type dopant into the polysilicon gate 164. Because, as in... Figure 16In the preceding etching process P6 shown, the oxide spacer 180 has been removed from the top surface of the polysilicon gate 164, thus allowing implantation of the polysilicon gate 164 across its entire top surface, which in turn reduces the undoped area in the polysilicon gate 164. Prior to performing the self-aligned implantation process P7, a mask layer 194 is formed on the semiconductor substrate 110 and then patterned to form separate mask portions covering the portion of the p-body region 156 adjacent to the isolation structure 142, thereby defining the target location of the N-type source region 172. The mask layer 194 is removed after the formation of the N-type source region 172 and the N-type drain region 174. For example, ion implantation can be performed using spacers 170, 180, and 182 and the patterned mask layer 194 as an implantation mask to implant an n-type dopant (e.g., arsenic or phosphorus) at a vertical angle, thereby forming the N-type drain region 174 in the NDD region 152. Because the ions of the n-type dopant are guided at a vertical angle (i.e., perpendicular to the top surface of the substrate 110), the resulting N-type source region 172 has a left boundary substantially aligned with the patterned mask layer 194 and a right boundary substantially aligned with the left nitride spacer 170, and the N-type drain region 174 has a left boundary substantially aligned with the outermost surface of the oxide spacer 180 and the outermost end of the right nitride spacer 182. Therefore, in implantation process P7, the left boundary of the N-type drain region 174 is self-aligned with the outermost surface of the oxide spacer 180, and the right boundary of the N-type source region 172 is self-aligned with the outermost surface of the left nitride spacer 170. Thus, in this context, implantation process P7 is referred to as a self-aligned implantation process.

[0049] More specifically, the second gate spacer 180 and the third gate spacer 182 can serve as implantation barrier layers during a self-aligned implantation process P7 with a vertical implantation angle, and thus the N-type drain region 174 is self-aligned with the outermost walls of the second gate spacer 180 and the third gate spacer 182. Therefore, the outermost surface of the second gate spacer 180 is connected to the boundary between the N-type drain region 174 and the NDD region, and thus the second gate spacer 180 and the third gate spacer 182 may not overlap with the N-type drain region 174. However, in some embodiments, due to unintentional thermal diffusion occurring in subsequent steps of the front-end (FEOL) and back-end (BEOL) processes, the N-type drain region 174 may extend laterally beyond the outermost surface of the second gate spacer 180.

[0050] In some embodiments, the N-type drain region 174 is spaced apart from the channel region 110c in the substrate 110 by a distance S1 (interchangeably referred to as the drift region length). The drift region length S1 depends on the width W1 of the second gate spacer 180 and the third gate spacer 182. Therefore, the drift region can be proportionally reduced by controlling the width W1 of the second gate spacer 180 and the third gate spacer 182, which depends on the thickness of the second spacer layer 180' and the third spacer layer 182', such as... Figure 11 As shown. Therefore, the drift region length S1 can be controlled by the thickness of the second spacer layer 180' and the third spacer layer 182'. For example, the drift region length S1 can be in the range of about 0.05 μm to about 0.5 μm, and other drift region length ranges are within the scope of this disclosure. In some embodiments, if the drift region length S1 is less than about 0.05 μm, it may result in an excessively low device breakdown voltage, and if the drift region length S1 is greater than about 0.5 μm, it may result in excessively high resistance.

[0051] In some embodiments, the mask layer 194 may be formed by a photolithographic patterning process. The photolithographic patterning process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking) and / or other suitable processes.

[0052] N-type source region 172 and N-type drain region 174 are N+ regions (interchangeably referred to as heavily doped N-type regions) with an n-type impurity concentration greater than that of NDD region 152 and P-body region 156. In some embodiments, N-type source region 172 and N-type drain region 174 include n-type dopants, such as P or As. A rapid thermal annealing (RTA) process can be performed after self-aligned implantation process P7 to activate the dopants implanted in polysilicon gate 164 and N-type source / drain regions 172 and 174.

[0053] like Figure 17 As shown, the depth D8 of the N-type drain region 174 can be less than the depth D4 of the NDD region 152 and / or the depth D1 of the isolation structure 142. For example, the depth D8 of the N-type drain region 174 can be in the range of about 0.1 μm to about 0.5 μm, and other depth ranges are within the scope of this disclosure. In some embodiments, the depth D8 of the N-type drain region 174 can be greater than the depth D4 of the NDD region 152 and / or the depth D1 of the isolation structure 142. Figure 17In this embodiment, the depth D9 of the N-type source region 172 may be less than the depth D5 of the p-body region 156 and / or the depth D1 of the isolation structure 142. For example, the depth D9 of the N-type drain region 174 may be in the range of about 0.1 μm to about 0.5 μm, and other depth ranges are within the scope of this disclosure. In some embodiments, the depth D9 of the N-type source region 172 may be greater than the depth D5 of the p-body region 156 and / or the depth D1 of the isolation structure 142. In some embodiments, the depth D9 of the N-type source region 172 is comparable to the depth D8 of the N-type drain region 174 because they are formed using the same implantation process P7.

[0054] In some embodiments, the dopant concentration of each of the N-type source region 172 and the N-type drain region 174 can be approximately 10⁻⁶ per cubic centimeter. 20 To about 10 21 Between, and other dopant concentrations within the range of this disclosure. For example Figure 17 As shown, the lateral distance between the N-type drain region 174 and the gate structure 160 is greater than the lateral distance between the N-type source region 172 and the gate structure 160, and therefore the LDMOS transistor has source / drain regions 172 and 174 that are asymmetrical relative to the gate structure 160. Furthermore, the width W3 of the drain region 174 is greater than the width W4 of the source region 172. By way of example, and not limitation, the ratio of the width W3 of the drain region 174 to the width W4 of the source region 172 is greater than 2, and other ratios are within the scope of this disclosure.

[0055] return Figure 1B Method M1 then proceeds to block S26, where a P-type body contact region is formed in the p-body region. (See reference...) Figure 18 In some embodiments of block S26, for example, if Figure 17 The mask layer 194 shown is photoresist, which is removed by ashing. Then, mask layer 192 is formed on semiconductor substrate 110 and patterned to cover N-type source and drain regions 172 and 174, as well as the N-doped polysilicon gate 164. Then, implantation process P8 is performed to implant p-type dopant into p-body region 156 using mask layer 192 as an implantation mask, thereby forming P-type body contact region 176 in p-body region 156. Mask layer 192 is removed after the formation of P-type body contact region 176. In some embodiments where mask layer 192 is photoresist, mask layer 192 is removed by ashing after the formation of P-type body contact region 176 is completed.

[0056] In some embodiments, the mask layer 192 may be formed by a photolithographic patterning process. The photolithographic patterning process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking) and / or other suitable processes.

[0057] The p-type body contact region 176 can be a P+ or heavily doped region with a p-type impurity concentration greater than that of the p-body region 156. In some embodiments, the p-type body contact region 176 includes a p-type dopant, such as boron or boron difluoride (BF2). The p-type body contact region 176 can be formed by methods such as ion implantation or diffusion. A rapid thermal annealing (RTA) process can be performed after the implantation process P8 to activate the implanted dopant. Figure 18 As shown, a P-type body contact region 176 is formed within the p-type body region 156 and between the N-type source region 172 and the isolation structure 142. In the depicted embodiment, the P-type body contact region 176 is formed after the formation of the second spacer 180 and the third gate spacer 182. In some other embodiments, the P-type body contact region 176 may be formed before the formation of the N-type source region 172 and the N-type drain region 174.

[0058] In some embodiments, the depth D10 of the P-type body contact region 176 may be less than the depth D5 of the P-type body region 156 and, for example, Figure 3 The isolation structure 142 shown has a depth D1. In some other embodiments, the depth D10 of the P-type body contact region 176 may be greater than or less than the depth D9 of the N-type source region 172. In some embodiments, the depth D10 of the P-type body contact region 176 may be comparable to the depth D9 of the N-type source region 172. For example, the depth D10 of the P-type body contact region 176 may range from about 0.1 μm to about 0.5 μm, and other depth ranges are within the scope of this disclosure. In some embodiments, the dopant concentration of each of the P-type body contact regions 176 may be about 10 μm per cubic centimeter. 20 To about 10 21 The concentrations of other dopants are within the range specified in this disclosure.

[0059] return Figure 1B Method M1 then proceeds to block S27, where metal alloy layers are formed on the gate structure, the N-type source / drain region, and the P-type source / drain region, respectively. (See reference...) Figure 19In some embodiments of block S27, the metal alloy layer 220 can be formed using a self-aligned silicide (self-aligned silicide) process. In an exemplary self-aligned silicide process, a metal material (e.g., cobalt, nickel, or other suitable metal) is formed on a substrate, then the temperature is raised for annealing, causing a reaction between the metal material and the underlying silicon / polysilicon to form the silicide layer 220, and any unreacted metal is etched away. The silicide material is self-aligned with the N-type source region 172 and N-type drain region 174, the P-type body contact region 176, and / or the gate electrode 164 to reduce contact resistance.

[0060] exist Figure 19 In this configuration, one of the metal alloy layers 220 contacts the entire top surface of the N-type drain region 174 within the NDD region 152, as well as the outermost surface of the second gate spacer 180. Other regions of the NDD region 152, intentionally excluded from the silicide process, are covered by the second gate spacer 180 and the third gate spacer 182. This protects the NDD region 152 beneath the second gate spacer 180 and the third gate spacer 182 from silicide formation. One of the metal alloy layers 220 contacts the entire top surface of the gate electrode 164 to reduce gate resistance. One of the metal alloy layers 220 makes full contact with the top surface of the N-type source region 172 and the top surface of the P-type body contact region 176, and thus extends across the interface between the N-type source region 172 and the P-type body contact region 176.

[0061] return Figure 1B Method M1 then proceeds to block S28, where contacts are formed on the metal alloy layer. (See reference) Figure 20 In some embodiments of block S28, in Figure 19 An interlayer dielectric (ILD) layer 196 is formed on top of the structure. In some embodiments, the ILD layer 196 comprises a material having a low dielectric constant (e.g., less than about 3.9). For example, the ILD layer 196 may comprise silicon oxide. In some embodiments, the dielectric layer comprises silicon dioxide, silicon nitride, silicon oxynitride, polyimide, spin-coated glass (SOG), fluorine-doped silicate glass (FSG), carbon-doped silicon oxide, etc. The ILD layer 196 can be formed using techniques including spin coating, CVD, or other suitable processes. These include: (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (his-benzocyclobutene), SiLK (Dow Chemical Company, Midland, Michigan), polyimide, and / or other suitable materials.

[0062] Then, a plurality of contacts 242, 244, and 246 are formed in the ILD layer 196 to contact the corresponding metal alloy layer 220 (i.e., silicide layer 220). For example, a plurality of openings are formed in the ILD layer 196, and then conductive material is deposited in the openings. Excess portions of the conductive material outside the openings are removed by using a CMP process, leaving portions in the openings to serve as contacts 242, 244, and 246. Contacts 242, 244, and 246 may be made of tungsten, aluminum, copper, or other suitable materials. In some embodiments, contact 242 is electrically connected to gate structure 160 via a metal alloy layer 220 on top of gate structure 160, contact 244 is connected to P-type body contact region 176 and N-type source region 172 via a metal alloy layer 220 spanning across P-type body contact region 176 and N-type source region 172, and contact 246 is connected to N-type drain region 174 via a metal alloy layer 220 on top of N-type drain region 174. In the depicted embodiment, P-type body contact region 176 and N-type source region 172 share the same contact 244. In some other embodiments, P-type body contact region 176 and N-type source region 172 may be separate from each other and electrically connected to separate contacts.

[0063] refer to Figure 21 and Figure 22 . Figure 21 and Figure 22 Methods for manufacturing a semiconductor device 200 at different stages according to some embodiments are shown. The operations for forming the semiconductor device 200 are substantially the same as those for forming the semiconductor device 100 described above, and therefore will not be repeated here for clarity. Figure 21 and Figure 22 The ratio of LDMOS fabricated using method M1 is shown. Figure 19 and Figure 20 A more practical silhouette.

[0064] Figure 21 Some alternative embodiments of the present disclosure are shown in relation to Figure 19 The corresponding stage of semiconductor device 200. For example... Figure 21As shown, the top of the third gate spacer 282 and the top of the second gate spacer 280 can be lower than the top surface of the gate electrode 264. Furthermore, due to the nature of etching processes P3 and P6, the top of the third gate spacer 282 can be lower than the top of the second gate spacer 280. Additionally, due to the nature of etching process P6 which etches the oxide material, the gate dielectric layer 262 has a left end that is set back from the outermost end of the left first spacer 270. However, because the right end of the gate dielectric layer 262 is covered and therefore protected by the photoresist mask 190, the right end of the gate dielectric layer 262 can still be connected to the outermost end of the right first spacer 270.

[0065] Figure 22 Some alternative embodiments of the present disclosure are shown in relation to Figure 20 The corresponding stage of semiconductor device 200. For example... Figure 22 As shown, one of the metal alloy layers 220 contacts the entire top surface of the N-type drain region 174 within the NDD 152 and the outermost surface of the second gate spacer 280. Regions of the NDD region 152 intentionally excluded from the silicide process are covered by the second gate spacer 280 and the third gate spacer 282. This protects the NDD region 152 beneath the second and third gate spacers 280 from silicide formation. Therefore, the NDD region 152 provides a resistive path that acts as a voltage drop in the channel region, and thus the semiconductor device 200 has improved blocking voltage capability. One of the metal alloy layers 220 contacts the entire top surface of the gate electrode 264 to reduce the gate resistance. One of the metal alloy layers 220 spans the N-type source region 172 and the P-type body contact region 176.

[0066] Now for reference Figure 23A and Figure 23B , Figure 23A and Figure 23B An exemplary method M2 for manufacturing a semiconductor device according to some embodiments is shown, wherein the manufacturing includes a self-aligned implantation and silicide process for the semiconductor device. Figure 24 An LDMOS transistor fabricated using method M2 is shown. Method M2 encompasses the relevant parts of the overall fabrication process. It should be understood that, in Figure 23A and Figure 23B Additional operations may be provided before, during, and after the operations shown, and some operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchangeable. Method M2 includes the fabrication of semiconductor device 400. However, the fabrication of semiconductor device 400 is merely an example used to describe a self-aligned process for semiconductor device 400 according to some embodiments of the present invention.

[0067] refer to Figure 24 At block S40, an isolation structure 142 (e.g., shallow trench isolation (STI) or localized oxidation of silicon (LOCOS) (or field oxide, FOX) including isolation features) can be formed in the semiconductor substrate 110 to define and electrically isolate various active regions, thereby preventing leakage current from flowing between adjacent active regions.

[0068] At block S41, a gate dielectric layer is formed over the semiconductor substrate 110. At block S42, a conductive layer is formed over the gate dielectric layer. In some embodiments, the conductive layer may comprise polycrystalline silicon (interchangeably referred to as polycrystalline silicon). At block S43, the conductive layer is patterned to form a gate electrode 464 on the gate dielectric layer. At block S44, a p-type double-diffused doped (PDD) region 452 and an n-type doped region 456 (interchangeably referred to as an n-body region) are formed in the semiconductor substrate 110 and near the top surface 112 of the semiconductor substrate 110. At block S45, a first spacer layer is blanket-deposited over the PDD region 452, the n-body region 456, the gate dielectric layer, the gate electrode 464, and the isolation feature 142. At block S46, the first spacer layer is etched to form a first gate spacer 170. At block S47, a gate dielectric layer is patterned to form a gate dielectric layer 462 below the gate electrode 464, and the gate dielectric layer 462 and the gate electrode 464 are defined as a gate structure 460.

[0069] At block S48, a second spacer layer is blanket-deposited over the PDD region 452, the n-body region 456, the gate dielectric layer 462, the gate electrode 464, the first gate spacer 170, and the isolation feature 142. At block S49, a third spacer layer is blanket-deposited over the second spacer layer. At block S50, an etching operation is performed to remove the horizontal portion of the third spacer layer.

[0070] At block S51, a first mask layer is formed on the semiconductor substrate 110 and then patterned to form separate mask portions to cover the gate structure 460, the first gate spacer 170, the third gate spacer 482, and the second spacer layer located on the semiconductor substrate 110. Figure 24 The portion to the right of the symmetry axis A of the gate structure 160 shown, and exposing the gate structure 460, the first gate spacer 170, the third gate spacer 482, and the second spacer layer located at... Figure 24 The other part to the left of the axis of symmetry A of the gate structure 160 shown. At block S52, one or more etching processes are performed to remove the third gate spacer 482 on the second spacer layer using the first mask layer as an etching mask.

[0071] At block S53, the first mask layer is removed after etching the third gate spacer 482. At block S54, an etching operation is performed to remove the portion of the second spacer layer located to the left of the axis of symmetry A of the gate structure 460 using the third gate spacer 482 as an etching mask, and to remove the horizontal portion of the second spacer layer located to the right of the axis of symmetry A of the gate structure 460, thereby forming the second gate spacer 480 only on one side of the gate structure 460 (e.g., only on the right side of the gate structure 460). At block S55, P-type source and drain regions 474 and 472 are formed in the PDD region 452 and the n-body region 456 by a self-aligned process. At block S56, an N-type body contact region 476 is formed in the n-body region 456.

[0072] At block S57, the metal alloy layer 220 can be self-aligned to form on various features (e.g., P-type source and drain regions 472 and 474, N-type body contact region 476, and / or gate electrode 464) to reduce contact resistance. At block S58, an interlayer dielectric (ILD) layer 196 is formed over the semiconductor substrate 110, and a plurality of contacts 242, 244, and 246 are formed in the ILD layer 196 to contact the respective metal alloy layers 220 (i.e., silicide layers 220). For example, contact 242 is connected to the gate structure 460, contact 244 is connected to the N-type body contact region 476 and the P-type source and drain regions 472, and contact 246 is connected to the P-type source / drain region 474 (i.e., the drain region of the semiconductor device 400).

[0073] Figures 25-28 Exemplary cross-sectional views of various stages in the manufacture of a semiconductor device 600 according to some embodiments of the present disclosure are shown. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 25-28 Additional operations are provided before, during, and after the process shown, and some of these operations can replace or eliminate those described below. The order of operations / processes can be interchangeable. In the following embodiments, [the following examples may employ...] Figures 2-20 The same or similar configurations, materials, processes and / or operations may be described, and detailed explanations may be omitted.

[0074] In the formation of such Figure 11 Following the structure shown, an anisotropic etching process P9 is performed to remove the horizontal portion of the third spacer layer 182'. Figure 25The resulting structure is shown. Etching operation P9 etches the third spacer layer 182' at a faster etch rate than it etches the second spacer layer 180'. For example, the ratio of the etch rate of the third spacer layer 182' to the etch rate of the second spacer layer 180' can be greater than about 2. If the ratio of the etch rate of the third spacer layer 182' to the etch rate of the second spacer layer 180' by etching operation P9 is less than about 2, then etching operation P9 will significantly consume the second spacer layer 180', and therefore the second spacer layer 180', the polysilicon gate 164, the first gate spacer 170, and the semiconductor substrate 110 may be damaged, and thus the yield may be reduced. In some embodiments, the ratio of the etch rate of the third spacer layer 182' to the etch rate of the second spacer layer 180' can be greater than about 10. In some embodiments, phosphoric acid (H3PO4) is used, for example, to etch the third spacer layer 182'.

[0075] like Figure 25 As shown, the remaining vertical portion of the third spacer layer 182' serves as the third gate spacer 682. The third gate spacer 682 has a height H4 measured from the top surface of the second spacer layer 180'. In some embodiments, the height H4 of the third gate spacer 682 may be substantially the same as or equivalent to the height H1 of the gate electrode 164. The height H4 of the third gate spacer 682 depends on the process conditions of the anisotropic etching process P9 (e.g., etching duration, etc.). For example, the etching duration of the etching process P9 can be controlled such that the resulting third gate spacer 682 has a top position substantially flush with the topmost position of the second spacer layer 180'.

[0076] After that, as Figure 26 As shown, a planarization process P10, such as chemical mechanical polishing (CMP), is performed to remove excess third gate spacer 682 and second spacer layer 180' above gate electrode 164, thereby exposing the top surface of gate electrode 164. In some embodiments, the planarization process stops when gate electrode 164 is exposed, and gate electrode 164 can be used as an etch stop layer during planarization. Therefore, the second spacer layer 180' may not overlap with the top surface of gate electrode 164. In some embodiments, after the planarization process, the top surface of the second spacer layer 180' may be flush with the top surface of gate electrode 164.

[0077] It should be noted that the above Figure 26 The etching process shown is P9 and Figure 27 The sequence of planarization process P10 shown is merely an example and is not intended to limit this disclosure. In some other embodiments, planarization process P10 may be performed before etching process P9.

[0078] Then, as Figure 27 As shown, a mask layer 690 is formed on a semiconductor substrate 110 and then patterned to form separate mask portions covering the portions of the gate structure 160, the first gate spacer 170, the third gate spacer 682, and the second spacer layer 180' located to the right of the axis of symmetry A of the gate structure 160, and exposing the other portion of the gate structure 160, the first gate spacer 170, the third gate spacer 682, and the second spacer layer 180' located to the left of the axis of symmetry A of the gate structure 160.

[0079] like Figure 27 As shown, the mask layer 690 is in contact with the top surface of the gate structure 160 because, as Figure 27 In the CMP process P10 shown, the top surface of the gate structure 160 is not covered by the second spacer layer 180'. In some embodiments, the mask layer 690 can be formed by a photolithographic patterning process. The photolithographic patterning process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking) and / or other suitable processes.

[0080] After that, as Figure 28 As shown, an etching process P4 is performed to remove the third gate spacer 682 exposed by the mask layer 690. Etching process P4 is a selective etching process that uses an etchant to etch the nitride spacer 682 at a faster etch rate than it etches the oxide spacer layer 180'. In this way, after the nitride spacer 682 is removed from the left side of the axis of symmetry A of the gate structure 160, the oxide spacer layer 180' remains substantially intact. For example, the etchant used in etching process P4 includes phosphoric acid (H3PO4).

[0081] After that, as Figures 15-20 The process steps shown continue to complete the fabrication of the LDMOS transistor.

[0082] As can be seen from the foregoing embodiments, this disclosure provides advantages in manufacturing semiconductor devices. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein. One advantage is that the field oxide (FOX) can be omitted in the NDD / PDD region of the LDMOS transistor, which in turn reduces the device size and specific on-state resistance (Rsp). Another advantage is that the undoped and / or non-silicide regions in the polysilicon gate can be reduced. Yet another advantage is that the drift region length can be precisely controlled by the oxide spacer thickness and the nitride spacer thickness, which in turn helps to proportionally reduce the drift region length. Furthermore, the trade-offs between the drain-source breakdown voltage (BVDSS), specific on-state resistance (Rsp), and switching speed of the LDMOS transistor can be improved, and a superior factor of quality (FOM) can be obtained.

[0083] In some embodiments, a semiconductor device includes: a gate structure, a double-diffused region, a source region, a drain region, a first gate spacer, and a second gate spacer. The gate structure is situated on a semiconductor substrate. The double-diffused region is situated in the semiconductor substrate and extends laterally beyond a first side of the gate structure. The source region is situated in the semiconductor substrate and is adjacent to a second side of the gate structure, the second side being opposite to the first side. The drain region is situated in the double-diffused region in the semiconductor substrate and has the same conductivity type as the double-diffused region. The first gate spacer is situated on the first side of the gate structure. The second gate spacer extends upward from the double-diffused region along the outermost wall of the first gate spacer and terminates before reaching the top surface of the gate structure. The second gate spacer has an outermost end surface substantially aligned with the boundary of the drain region.

[0084] In some embodiments, a semiconductor device includes: a semiconductor substrate, a double-diffused region, a gate structure, a drain region, a first gate spacer, a drain silicide layer, and a second gate spacer. The double-diffused region is located in the semiconductor substrate. The gate structure overlaps with at least a portion of the double-diffused region. The drain region is located in the double-diffused region and has the same conductivity type as the double-diffused region. The first gate spacer is located adjacent to the gate structure and above the double-diffused region. The drain silicide layer extends laterally along the top surface of the drain region from the outermost surface of the first gate spacer. The second gate spacer is located above the first gate spacer and has an outermost end substantially aligned with the boundary of the drain region.

[0085] In some embodiments, a method for manufacturing a semiconductor device includes: forming a body region having a first conductivity type and a doped region having a second conductivity type in a semiconductor substrate; forming a gate structure over at least a portion of the body region and a portion of the doped region, and forming a first gate spacer on a first side and a second side of the gate structure, respectively; sequentially depositing a second spacer layer and a third spacer layer over the gate structure; patterning the third spacer layer into third gate spacers located on the first side and the second side of the gate structure, respectively; removing the first third gate spacer from the first side of the gate structure, leaving a second third gate spacer on the second side of the gate structure; patterning the second spacer layer into second gate spacers using the second third gate spacer as an etch mask; and after patterning the second spacer layer, forming a source region having a second conductivity type in the body region and a drain region having a second conductivity type in the doped region.

[0086] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or realizing the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0087] Example 1. A semiconductor device comprising: a gate structure situated on a semiconductor substrate; a double-diffused region situated in the semiconductor substrate and extending laterally beyond a first side of the gate structure; a source region situated in the semiconductor substrate and adjacent to a second side of the gate structure, the second side being opposite to the first side; a drain region situated in the double-diffused region in the semiconductor substrate and having the same conductivity type as the double-diffused region; a first gate spacer situated on the first side of the gate structure; and a second gate spacer extending upward along the outermost wall of the first gate spacer from the double-diffused region and terminating before reaching a top surface of the gate structure, wherein the second gate spacer has an outermost end surface aligned with the boundary of the drain region.

[0088] Example 2. The semiconductor device according to Example 1 further includes: a silicide layer located above the drain region and in contact with the outermost surface of the second gate spacer.

[0089] Example 3. The semiconductor device according to Example 1 further includes: a silicide layer that contacts the entire top surface of the gate structure.

[0090] Example 4. The semiconductor device according to Example 3, wherein the second gate spacer is spaced apart from the silicide layer on the gate structure.

[0091] Example 5. The semiconductor device according to Example 1 further includes: a third gate spacer, the third gate spacer being located above the second gate spacer.

[0092] Example 6. The semiconductor device according to Example 5, wherein the third gate spacer is formed of silicon nitride and the second gate spacer is formed of silicon oxide.

[0093] Example 7. The semiconductor device according to Example 1 further includes: a fourth gate spacer located on a second side of the gate structure, wherein the first gate spacer and the fourth gate spacer are symmetrical with respect to the gate structure, and the fourth gate spacer has an outermost end surface aligned with the boundary of the source region.

[0094] Example 8. The semiconductor device according to Example 7 further includes: an interlayer dielectric (ILD) layer in contact with the fourth gate spacer, the ILD layer being at least partially spaced apart from the first gate spacer by the second gate spacer.

[0095] Example 9. The semiconductor device according to Example 7, wherein the gate structure has a gate dielectric layer having a first end surface that retracts from the outermost end surface of the fourth gate spacer.

[0096] Example 10. The semiconductor device according to Example 9, wherein the gate dielectric layer has a second end surface in contact with the second gate spacer.

[0097] Example 11. The semiconductor device according to Example 7 further includes: a silicide layer located above the source region and having an end surface in contact with the outermost end surface of the fourth gate spacer.

[0098] Example 12. A semiconductor device comprising: a semiconductor substrate; a double-diffused region located in the semiconductor substrate; a gate structure overlapping at least a portion of the double-diffused region; a drain region located in the double-diffused region and having the same conductivity type as the double-diffused region; a first gate spacer located adjacent to the gate structure and above the double-diffused region; a drain silicide layer extending laterally along a top surface of the drain region from the outermost end surface of the first gate spacer; and a second gate spacer located above the first gate spacer and having an outermost end aligned with a boundary of the drain region.

[0099] Example 13. The semiconductor device according to Example 12, wherein the first gate spacer is formed of silicon oxide and the second gate spacer is formed of silicon nitride.

[0100] Example 14. The semiconductor device according to Example 12 further includes: a third gate spacer located between the gate structure and the first gate spacer.

[0101] Example 15. The semiconductor device according to Example 14, wherein the third gate spacer is formed of the same material as the second gate spacer.

[0102] Example 16. The semiconductor device according to Example 12, wherein the topmost position of the first gate spacer is lower than the topmost position of the gate structure.

[0103] Example 17. The semiconductor device according to Example 12, wherein the topmost position of the second gate spacer is lower than the topmost position of the gate structure.

[0104] Example 18. A method of manufacturing a semiconductor device, comprising: forming a body region having a first conductivity type and a doped region having a second conductivity type in a semiconductor substrate; forming a gate structure over a portion of the body region and over a portion of the doped region; forming a first gate spacer on a first side and a second side of the gate structure, respectively; sequentially depositing a second spacer layer and a third spacer layer over the gate structure; patterning the third spacer layer into third gate spacers located on the first side and the second side of the gate structure, respectively; removing the first third gate spacer from the first side of the gate structure, leaving a second third gate spacer on the second side of the gate structure; patterning the second spacer layer into a second gate spacer using the second third gate spacer as an etch mask; and after patterning the second spacer layer, forming a source region having the second conductivity type in the body region and a drain region having the second conductivity type in the doped region.

[0105] Example 19. The method according to Example 18, wherein patterning the second spacer layer into the second gate spacer is performed such that the second gate spacer does not cover the top surface of the gate structure.

[0106] Example 20. The method according to Example 18 further includes: forming a silicide layer over the drain region and in contact with the outermost surface of the second gate spacer.

Claims

1. A semiconductor device, comprising: A gate structure, wherein the gate structure is located on a semiconductor substrate; A double-diffused region, wherein the double-diffused region is located in the semiconductor substrate and extends laterally beyond the first side of the gate structure; A source region, the source region being located in the semiconductor substrate and adjacent to a second side of the gate structure, the second side being opposite to the first side; Drain region, the drain region being located in the double-diffusion region in the semiconductor substrate and having the same conductivity type as the double-diffusion region; A first gate spacer is located on a first side of the gate structure; as well as A second gate spacer extends upward from the double-diffusion region along the outermost wall of the first gate spacer and terminates before reaching the top surface of the gate structure, wherein the second gate spacer has an outermost end surface aligned with the boundary of the drain region. The first gate spacer is in contact with the lower region of the first side of the gate structure, and the second gate spacer is in contact with the upper region of the first side of the gate structure.

2. The semiconductor device according to claim 1, further comprising: A silicide layer is located above the drain region and contacts the outermost surface of the second gate spacer.

3. The semiconductor device according to claim 1, further comprising: A silicide layer that contacts the entire top surface of the gate structure.

4. The semiconductor device according to claim 3, wherein, The second gate spacer is spaced apart from the silicide layer on the gate structure.

5. The semiconductor device according to claim 1, further comprising: A third gate spacer is located above the second gate spacer.

6. The semiconductor device according to claim 5, wherein, The third gate spacer is formed of silicon nitride, and the second gate spacer is formed of silicon oxide.

7. The semiconductor device according to claim 1, further comprising: A fourth gate spacer is located on the second side of the gate structure, wherein the first gate spacer and the fourth gate spacer are symmetrical with respect to the gate structure, and the fourth gate spacer has an outermost end surface aligned with the boundary of the source region.

8. The semiconductor device according to claim 7, further comprising: An interlayer dielectric (ILD) layer is in contact with the fourth gate spacer, and the ILD layer is at least partially spaced apart by the second gate spacer from the first gate spacer.

9. The semiconductor device according to claim 7, wherein, The gate structure has a gate dielectric layer having a first end surface that retracts from the outermost end surface of the fourth gate spacer.

10. The semiconductor device according to claim 9, wherein, The gate dielectric layer has a second end surface that contacts the second gate spacer.

11. The semiconductor device according to claim 7, further comprising: A silicide layer is located above the source region and has an end surface that contacts the outermost end surface of the fourth gate spacer.

12. A semiconductor device, comprising: Semiconductor substrate; A double-diffused region, wherein the double-diffused region is located in the semiconductor substrate; A gate structure that overlaps with at least a portion of the double-diffusion region; Drain region, the drain region being located in the double diffusion region and having the same conductivity type as the double diffusion region; A first gate spacer is located next to the gate structure and above the double diffusion region; A drain silicide layer, the drain silicide layer extending laterally along the top surface of the drain region from the outermost end surface of the first gate spacer; A second gate spacer is located above the first gate spacer and has an outermost end aligned with the boundary of the drain region; as well as A third gate spacer is located between the gate structure and the first gate spacer. The drain silicide layer is in contact with the first gate spacer and spaced apart from the second gate spacer.

13. The semiconductor device according to claim 12, wherein, The first gate spacer is formed of silicon oxide, and the second gate spacer is formed of silicon nitride.

14. The semiconductor device according to claim 12, wherein, The third gate spacer is formed of the same material as the second gate spacer.

15. The semiconductor device according to claim 12, wherein, The topmost position of the first gate spacer is lower than the topmost position of the gate structure.

16. The semiconductor device according to claim 12, wherein, The topmost position of the second gate spacer is lower than the topmost position of the gate structure.

17. A method for manufacturing a semiconductor device, comprising: A bulk region having a first conductivity type and a doped region having a second conductivity type are formed in a semiconductor substrate; A gate structure is formed over a portion of the body region and over a portion of the doped region, and first gate spacers are formed on a first side and a second side of the gate structure, respectively. A second spacer layer and a third spacer layer are sequentially deposited on the gate structure; The third spacer layer is patterned into third gate spacers located on the first side and the second side of the gate structure, respectively; The first third gate spacer is removed from the first side of the gate structure, while the second third gate spacer is left on the second side of the gate structure; By using the second third gate spacer as an etching mask, the second spacer layer is patterned into the second gate spacer; as well as After patterning the second spacer layer, a source region having the second conductivity type is formed in the body region, and a drain region having the second conductivity type is formed in the doped region. The first gate spacer contacts the lower region of the second side of the gate structure, and the second gate spacer contacts the upper region of the second side of the gate structure.

18. The method according to claim 17, wherein, Patterning the second spacer layer into the second gate spacer is performed such that the second gate spacer does not cover the top surface of the gate structure.

19. The method of claim 17, further comprising: A silicide layer is formed over the drain region and in contact with the outermost surface of the second gate spacer.

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