Memory device and method of forming a memory device

Abstract

The present disclosure relates to a memory device and a method of forming a memory device. A memory device may be provided, comprising: first, second and third electrodes, first and second mask elements, and a switching layer. The first mask element may be arranged over a portion of the first electrode and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of the second mask element and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode along a first side surface of the first mask element, a first side surface of the second electrode, and a first side surface of the second mask element.

Description

Technical Field

[0001] The present disclosure generally relates to memory devices and methods of forming memory devices. Background Art

[0002] Non-volatile memory cells are often used in consumer electronics such as smart phones and tablet computers. One type of non-volatile memory cell is a resistive memory cell that typically uses a switching layer sandwiched between two electrodes. The switching layer is typically insulating. However, when a set voltage difference is applied between the electrodes, a conductive filament may be formed in the switching layer and the switching layer thereby becomes conductive via the conductive filament. The switching layer may be insulated again by applying a reset voltage difference to the electrodes to disconnect the conductive filament. A typical resistive memory cell may be switchable between states based on the resistance of the switching layer. When the switching layer is insulating, the switching layer has a high resistance, and the resistive memory cell may be referred to as being in a high resistance state (HRS). The resistance of the switching layer in this state may be referred to as the HRS resistance of the cell. When the switching layer is turned on, the switching layer has a low resistance, and the resistive memory cell may be referred to as being in a low resistance state (LRS). The resistance of the switching layer in this state may be referred to as the LRS resistance of the cell.

[0003] Some resistive memory cells are switchable between only two states. Although multiple memory cells can be combined to provide a memory device switchable between more than two states, many of such current memory devices are large and costly to manufacture. It would therefore be desirable to provide an improved memory device that is not only switchable between more than two states, but is also more compact and less costly to manufacture than currently available memory devices. Summary of the invention

[0004] According to various non-limiting embodiments, a memory device may be provided, comprising: a first electrode; a first mask element disposed over a portion of the first electrode and laterally offset from the first electrode; a second electrode disposed over the first mask element; a second mask element disposed over the second electrode; a third electrode disposed over a portion of the second mask element and laterally offset from the second mask element; and a switching layer disposed between the first electrode and the third electrode along a first side surface of the first mask element, a first side surface of the second electrode, and a first side surface of the second mask element.

[0005] According to various non-limiting embodiments, a method of manufacturing a memory device may be provided. The method may include: forming a first electrode; forming a first mask element over a portion of the first electrode, wherein the first mask element is laterally offset from the first electrode; forming a second electrode over the first mask element; forming a second mask element over the second electrode; forming a third electrode over a portion of the second mask element, wherein the third electrode is laterally offset from the second mask element; and forming a switching layer between the first electrode and the third electrode along a first side surface of the first mask element, a first side surface of the second electrode, and a first side surface of the second mask element. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, the same reference numerals generally refer to the same parts throughout the different views. In addition, the drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. Non-limiting embodiments of the present invention will now be described with reference only to the following drawings, in which:

[0007] Figure 1 shows simplified cross-sectional views of memory devices according to various non-limiting embodiments;

[0008] Figures 2A to 2E Examples of various non-limiting embodiments are shown. Figure 1 A simplified cross-sectional view of a method for a memory device;

[0009] Figures 3A to 3C An example is shown in use Figure 1 A simplified cross-sectional view of a memory device;

[0010] Figure 4 An example is shown when the memory device is in use. Figure 1 A diagram of different states of a memory device;

[0011] Figure 5 shows a simplified cross-sectional view of a memory device according to an alternative non-limiting embodiment;

[0012] Figure 6 shows a simplified cross-sectional view of a memory device according to an alternative non-limiting embodiment;

[0013] Figure 7 shows a simplified cross-sectional view of a memory device according to an alternative non-limiting embodiment; and

[0014] Figure 8 A simplified cross-sectional view of a memory device according to an alternative non-limiting embodiment is shown. DETAILED DESCRIPTION

[0015] The present embodiments generally relate to semiconductor devices. More specifically, some embodiments relate to memory devices. For example, some embodiments may relate to non-volatile memory devices, such as resistive random access memory (RRAM) devices in a non-limiting example. The memory devices can be used in several applications, such as, but not limited to, neuromorphic computing applications and multi-bit applications.

[0016] The various aspects of the present invention and its features, advantages and details are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of known materials, manufacturing tools, processing techniques, etc. are omitted so as not to unnecessarily obscure the details of the present invention. However, it should be understood that while indicating aspects of the present invention, detailed descriptions and specific examples are provided only for illustration and not for limitation. Through this disclosure, various substitutions, modifications, additions and / or arrangements within the spirit and / or scope of the following inventive concepts will be apparent to those skilled in the art.

[0017] As used throughout the specification and claims herein, approximate language may be applied to modify any quantitative representation, which may be permissibly changed without causing a change in the basic function associated therewith. Therefore, the value modified by terms such as "approximately", "about" or a plurality of terms is not limited to the specified exact value. In some cases, the approximate language may correspond to the accuracy of the instrument used to measure the value. In addition, the direction is modified by one or more terms, such as "substantially" meaning that the direction will be applied within the normal tolerance of the semiconductor industry. For example, "substantially parallel" means extending to a great extent in the same direction within the normal tolerance of the semiconductor industry, and "substantially vertical" means being at an angle of 90 degrees plus or minus the normal tolerance of the semiconductor industry.

[0018] The terms used herein are only for describing specific examples and are not intended to limit the present invention. As used herein, the singular forms "one", "an" and "said" are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "include" (and any form of including, such as "include" and "include"), "have" (and any form of having, such as "have" and "have"), "include" (and any form of including, such as "include" and "include") and "contain" (and any form of containing, such as "contain" and "contain") are all open linking verbs. As a result, the method or device of "include", "have", "include" or "contain" one or more steps or elements has these one or more steps or elements, but is not limited to having only these one or more steps or elements. Similarly, the steps of the method or elements of the device of "include", "have", "include" or "contain" one or more features have these one or more features, but are not limited to having only these one or more features. In addition, the device or structure configured in a certain way is configured at least in this way, but can also be configured in an unlisted way.

[0019] As used herein, when used to refer to two physical elements, the term "connected" means a direct connection between the two physical elements. However, the term "coupled" can mean a direct connection or a connection through one or more intermediate elements.

[0020] As used herein, the terms "may" and "may be" indicate the possibility of occurring within a set of circumstances; possessing a specified attribute, characteristic, or function; and / or qualifying another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Thus, while taking into account that the modified term may sometimes not be appropriate, competent enough, or suitable in certain circumstances, the use of "may" and "may be" indicates that the modified term is clearly appropriate, competent enough, or suitable for the indicated ability, function, or use. For example, in some circumstances, an event or capability can be expected, while in other circumstances, the event or capability cannot occur - a distinction captured by the terms "may" and "may be".

[0021] Figure 1 A simplified cross-sectional view of a memory device 100 is shown according to various non-limiting embodiments. The memory device 100 may be a RRAM device and may have a 1R structure.

[0022] like Figure 1 As shown, the memory device 100 may include a base layer 102. The base layer 102 may include an insulating material such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, or a combination thereof. For example, the base layer 102 may be an interlayer dielectric (ILD) layer.

[0023] The memory device 100 may further include a first electrode 104 at least partially disposed within the substrate layer 102. In addition, the memory device 100 may include a first mask element 106, a second electrode 108, a second mask element 110, and a third electrode 112. The first mask element 106 may be disposed over the first electrode 104 and the substrate layer 102; the second electrode 108 may be disposed over the first mask element 106; the second mask element 110 may be disposed over the second electrode 108; and the third electrode 112 may be disposed over the second mask element 110.

[0024] refer to Figure 1 , the first electrode 104 and the first mask element 106 can be laterally offset from each other. Similarly, the third electrode 112 and the second mask element 110 can be laterally offset from each other. As used herein, "lateral offset" refers to partial but not complete overlap of two elements. For example, the first mask element 106 can be arranged above a portion of the first electrode 104, and the first electrode 104 can be arranged below a portion of the first mask element 106. In other words, the first mask element 106 can partially (and not completely) overlap with the first electrode 104, and the first electrode 104 can partially (and not completely) overlap with the first mask element 106. Similarly, the third electrode 112 can be arranged above a portion of the second mask element 110, and the second mask element 110 can be arranged below a portion of the third electrode 112. In other words, the third electrode 112 can partially (and not completely) overlap with the second mask element 110, and the second mask element 110 can partially (and not completely) overlap with the third electrode 112. Specifically, as Figure 1 As shown, the bottom surface 106b of the first mask element 106 may partially overlap with and optionally directly contact the first electrode 104. Similarly, the top surface 110t of the second mask element 110 may partially overlap with and optionally directly contact the third electrode 112.

[0025] In addition, if Figure 1 As shown, the second electrode 108 may be adjacent to (or in other words, may be in direct contact with) the first mask element 106, and the second mask element 110 may be adjacent to the second electrode 108. The first mask element 106, the second electrode 108, and the second mask element 110 may each include a first side surface 106s1, 108s1, 110s1 and a second side surface 106s2, 108s2, 110s2 facing in a direction opposite to the first side surface 106s1, 108s1, 110s1. Figure 1As shown, the first mask element 106, the second electrode 108, and the first side surfaces 106s1, 108s1, 110s1 of the second mask element 110 may be substantially vertically aligned. 106 , the length L of the second electrode 108 108 and the length L of the second mask element 110 110 Therefore, the second side surfaces 106s2, 108s2, 110s2 of the first mask element 106, the second electrode 108 and the second mask element 110 may also be substantially vertically aligned.

[0026] In addition, if Figure 1 As shown, the thickness T of the second mask element 110 110 It may be greater than the thickness T of the first mask element 106 106 In various non-limiting embodiments, the thickness T of the second mask element 110 is 110 The thickness T of the first mask element 106 may be 106 In addition, the thickness T of the second mask element 110 is at least twice as large as that of 110 For example, the thickness T of the first mask element 106 may be less than or equal to 50 nm. 106 The thickness T of the second mask element 110 may be in the range of from about 5 nm to about 10 nm. 110 The thickness T of the second mask element 110 may be in the range of about 10 nm to about 20 nm. 110 Alternatively, it may be approximately equal to the thickness T of the first mask element 106 106 Each of the first mask element 106 and the second mask element 110 may be referred to as a hard mask and may include an insulating mask material such as, but not limited to, various oxides and nitrides, such as silicon oxide (SiO x ), tantalum oxide (TaO x ), aluminum oxide (AlO x ), silicon nitride (Si3N4) or a combination thereof.

[0027] refer to Figure 1 , the memory device 100 may include a switching layer 114 disposed between the first electrode 104 and the third electrode 112 above the substrate layer 102. Specifically, the switching layer 114 may be arranged to extend substantially flatly between the top surface 104t of the first electrode 104 and the bottom surface 112b of the third electrode 112 along substantially vertically aligned first side surfaces 106s1, 108s1, 110s1 of the first mask element 106, the second electrode 108, and the second mask element 110. Figure 1As shown, the switching layer 114 may also extend horizontally on the top surface 104t of the first electrode 104 away from the first mask element 106. Thus, the first mask element 106 may overlap a portion of the top surface 104t of the first electrode 104, and the switching layer 114 may overlap the entire remaining portion of the top surface 104t of the first electrode 104. The switching layer 114 may be formed to have a uniform thickness T 114 The switching layer 114 has a thickness T 114 For example, the thickness T of the switching layer 114 may be less than 5 nm. 114 It may be in the range from about 3 nm to about 5 nm.

[0028] refer to Figure 1 , the memory device 100 may further include a further switching layer 116 arranged on the base layer 102. The further switching layer 116 may be arranged to extend substantially flat along the substantially vertically aligned second side surfaces 106s2, 108s2, 110s2 of the first mask element 106, the second electrode 108, and the second mask element 110. The further switching layer 116 may also extend horizontally on the base layer 102 away from the first mask element 106. The further switching layer 116 may similarly be a layer having a uniform thickness T 116 The thickness T of the switching layer 116 is 116 It can be approximately equal to the thickness T of the switching layer 114 114 , and may be less than or equal to 5 nm. For example, the thickness T of the further switching layer 116 is 116 It may be in the range from about 3 nm to about 5 nm. In the memory device 100, the further switching layer 116 may be optional (although the manufacturing process of the memory device 100 may be less complicated if the further switching layer 116 is included in the device 100).

[0029] like Figure 1 As shown, the first electrode 104 and the second electrode 108 and the first portion 1141 of the switching layer 114 (between the first electrode 104 and the second electrode 108) may form a first memory cell 100a; and the second electrode 108 and the third electrode 112 and the second portion 1142 of the switching layer 114 (between the second electrode 108 and the third electrode 112) may form a second memory cell 110b. In other words, the memory device 100 may include a first memory cell 100a including the first electrode 104 and the second electrode 108 and a second memory cell 100b including the second electrode 108 and the third electrode 112, wherein the second memory cell 100b may be arranged above the first memory cell 100a.

[0030] The first memory cell 110a and the second memory cell 110b may be memory cells of different types, and the first electrode 104 and the third electrode 112 may include different materials. Specifically, the first memory cell 110a may be an oxide-based memory cell, and the second memory cell 110b may be a conductive bridge memory cell. Therefore, the HRS resistance of the second memory cell 100b may be higher than the HRS resistance of the first memory cell 100a. Each memory cell 100a, 100b may be an RRAM cell. For example, the first memory cell 100a may be an oxide-based resistance random access memory (OxRAM) cell, and the second memory cell 100b may be a conductive bridge random access memory (CBRAM) cell.

[0031] As used herein, "oxide-based memory cell" means that the memory cell is switchable between states based on the formation and rupture of a conductive filament, which may include oxygen ion-related defects (e.g., oxygen vacancies). In an oxide-based memory cell, one of the electrodes (the "oxygen scavenging electrode") may be oxidizable to form a layer of oxygen ion-related defects. When a set voltage difference is applied between the electrodes, these oxygen ion-related defects may migrate to the other electrode (the "inert" electrode). The oxide-based memory cell may alternatively be referred to as a cationic filament memory cell or a valence change memory (VCM) cell.

[0032] As used herein, "conductive bridge memory cell" means that the memory cell is switchable between states based on the formation and rupture of a conductive filament, which may include metal atoms or molecules. When a set voltage difference is applied between the electrodes, the metal atoms or molecules may be formed by oxidation of one of the electrodes (the "active electrode") and may migrate to the other electrode (the "inert" electrode). The conductive bridge memory cell may alternatively be referred to as a cationic filament memory cell or an electrochemical metallization (ECM) cell.

[0033] In the memory device 100, the second electrode 108 may include an inert electrode of both the first memory cell 100a and the second memory cell 100b. In addition, the first electrode 104 may include an oxygen scavenging electrode of the first memory cell 100a, and the third electrode 112 may include an active electrode of the second memory cell 100b. The second electrode 108 may include the same material throughout, and may include an inert electrode material, such as but not limited to platinum (Pt), ruthenium (Ru), gold (Au), alloys thereof, or combinations thereof. The first electrode 104 may include an oxygen scavenging material, such as but not limited to titanium (Ti), tantalum (Ta), aluminum (Al), alloys thereof, or combinations thereof. The third electrode 112 may include a metal material, such as but not limited to silver (Ag), copper (Cu), nickel (Ni), alloys thereof, or combinations thereof. The switching layer 114 may include the same material throughout. In other words, the first portion 1141 and the second portion 1142 of the switching layer 114 may include the same material. Another switching layer 116 may similarly include the same material throughout, and may include the same material as the switching layer 114. Specifically, the switching layer 114 and the further switching layer 116 may include a switching material such as, but not limited to, a dielectric material. For example, the switching layer 114 and the further switching layer 116 may include magnesium oxide (MgO), tantalum oxide (TaO2), hafnium oxide (HfO2), titanium oxide (TiO2), aluminum oxide (AlO2), silicon dioxide (SiO2), or a combination thereof.

[0034] In addition, the memory device 100 may include a connector 118 and a contact 120. The connector 118 may electrically connect the contact 120 to the third electrode 112, specifically, the connector 118 may be arranged between the contact 120 and the third electrode 112 and may abut the contact 120 and the third electrode 112. The memory device 100 may also include an insulating layer 122 arranged on the base layer 102. Each of the first and second mask elements 106, 110, the second and third electrodes 108, 112, the switching layer 114, the further switching layer 116, the connector 118 and the contact 120 may be at least partially arranged within the insulating layer 122. The connector 118 and the contact 120 may include a conductive material, such as but not limited to aluminum, copper, tungsten, alloys thereof, or combinations thereof. For example, the contact 118 may include a conductive line, such as but not limited to a bit line of the memory device 100, and the connector 120 may include a conductive via. The insulating layer 122 may include an insulating material, such as but not limited to silicon oxide, silicon dioxide, silicon nitride, or a combination thereof. For example, the insulating layer 122 may be an interlayer dielectric (ILD) layer.

[0035] Figures 2A to 2E 1 shows a simplified cross-sectional view illustrating a method of forming a memory device 100 according to various non-limiting embodiments. Figures 2A to 2E Some reference numerals are omitted.

[0036] refer to Figure 2A , the method may include providing a base layer 102 and forming a first electrode 104 at least partially within the base layer 102. The first electrode 104 may be formed by depositing an oxygen scavenging material on a surface where the memory device 100 will be formed and then selectively etching the oxygen scavenging material using, for example, a photoresist mask. The base layer 102 may be provided by depositing an insulating material over the first electrode 104 and planarizing the insulating material using, for example, a chemical mechanical planarization (CMP) process.

[0037] refer to Figure 2B The method may further include forming a first mask element 106 over the first electrode 104 and the base layer 102, forming a second electrode 108 over the first mask element 106, and forming a second mask element 110 over the second electrode 108. The first mask element 106, the second electrode 108, and the second mask element 110 may be formed by depositing a first mask material over the base layer 102, depositing an inert electrode material over the first mask material, depositing a second mask material over the inert electrode material, and thereafter selectively etching the first mask material, the inert electrode material, and the second mask material. The remaining first mask material, the inert electrode material, and the second mask material may form the first mask element 106, the second electrode 108, and the second mask element 110, respectively.

[0038] refer to Figure 2C and 2D The method may further include forming a switching layer 114, a further switching layer 116, and a first portion 1221 of the insulating layer 122. Figure 2C As shown, the method may include depositing a thin liner of switching material 202 over the base layer 102 and the second mask element 110 and along the first and second side surfaces 106s1, 108s1, 110s1, 106s2, 108s2, 110s2 of the first mask element 106, the second electrode 108, and the second mask element 110. The method may further include depositing an insulating material 204 over the switching material 202. Figure 2D As shown, the method may further include removing portions of the switching material 202 and portions of the insulating material 204 located above the second mask element 110 to form a switching layer 114, a further switching layer 116 and a first portion 1221 of the insulating layer 122 (which may be an ILD layer as described above).

[0039] refer to Figure 2E, the method may include forming a third electrode 112, a connector 118, and a contact 120, and second and third portions 1222, 1223 of the insulating layer 122. The third electrode 112 may be formed by depositing an active electrode material over a first portion 1221 of the insulating layer 122 and selectively etching the active electrode material. An insulating material may then be deposited over the third electrode 112 to form a second portion 1222 of the insulating layer 122. The connector 118 and the contact 120 may then be formed using any process known to those skilled in the art, such as, but not limited to, a back-end of line (BEOL) process. For example, the second portion 1222 of the insulating layer 122 may be etched to form an opening, and the opening may be filled with a conductive material to form the connector 118. The third portion 1223 of the insulating layer 122 may then be formed by depositing an insulating material over the second portion 1222 of the insulating layer 122, and the contact 120 may be formed by etching the third portion 1223 of the insulating layer 122 to form an opening and depositing a conductive material into the opening.

[0040] The order described above regarding the method is intended to be exemplary only, and the method is not limited to the order specifically described above unless specifically stated otherwise.

[0041] Figures 3A to 3C A simplified cross-sectional view of a memory device 100 is shown illustrating the memory device 100 in use. Again, for clarity of illustration, FIG. 3A to FIG. 3C Some reference numerals are omitted. Figure 4 2 shows a diagram illustrating different states of the memory device 100 when the memory device 100 is in use. Figure 4 As shown, each state can be represented in the form of "XY", where each of "X" and "Y" can be 0 or 1, and where "X" indicates the state of the first memory cell 100a, and "Y" indicates the state of the second memory cell 100b located above the first memory cell 100a.

[0042] Initially, the switching layer 114 can be entirely insulating, and the memory device 100 can be referred to as being in a "00" state, or in other words, a home state.

[0043] refer to Figure 3A and Figure 4 , a first write voltage difference (V 01 ) to perform a first write operation 402 on the memory device 100. Figure 3AAs shown, this can form a conductive filament 302 between the second electrode 108 and the third electrode 112. The conductive filament 302 can be formed and confined within the second portion 1142 of the switching layer 114. As a result, the memory device 100 can be written to a "01" state, wherein the first memory cell 100a can still be in the HRS ("0") state, and the second memory cell 100b can be set to the LRS ("1") state. Therefore, the total resistance of the memory device 100 can depend on the HRS resistance of the first memory cell 100a.

[0044] refer to Figure 3B and Figure 4 , a second write voltage difference (V 11 ) to perform a second write operation 404 on the memory device 100. Figure 3B As shown, this can form a conductive filament 302 between the second electrode 108 and the third electrode 112, and can also form a conductive filament 304 between the first electrode 104 and the second electrode 108. The conductive filament 302 can be formed and confined within the second portion 1142 of the insulating layer 114; and the conductive filament 304 can be formed and confined within the first portion 1141 of the switching layer 114. In other words, the memory device 100 can be written to the "11" state, wherein the first memory cell 100a and the second memory cell 100b can be set to the LRS ("1") state.

[0045] refer to Figure 3C and Figure 4 , a third write voltage difference (V 10 ) to perform a third write operation 406 on the memory device 100. Figure 3C As shown, this can form a conductive filament 304 between the first electrode 104 and the second electrode 108. The conductive filament 304 can be formed and confined within the first portion 1141 of the switching layer 114. In other words, the memory device 100 can be written to a "10" state, wherein the first memory cell 100a can be set to an LRS ("1") state, and the second memory cell 100b can remain in an HRS ("0") state. Therefore, the total resistance of the memory device 100 can depend on the HRS resistance of the second memory cell 100a.

[0046] To read the memory device 100, a read voltage difference (Vread) can be applied between the first electrode 104 and the third electrode 112, and a current through the memory device 100 can be determined. The current can indicate the state of the memory device 100.

[0047] The first, second and third write voltage differences (V01 、V 10 、V 11 ) can be related to the first, second, third and fourth threshold voltages VTH1 100 、VTH2 100 、VTH3 100 、VTH4 100 The third and fourth threshold voltages VTH3 100 、VTH4 100 The polarity of the first and second threshold voltages VTH1 100 、VTH2 100 For example, the third and fourth threshold voltages VTH3 100 、VTH4 100 Can be negative (where VTH4 100 The magnitude is greater than VTH3 100 The value of |VTH4 100 |>|VTH3 100 |, or in other words, VTH4 100 VTH3 100 more negative); and the first and second threshold voltages VTH1 100 、VTH2 100 Can be positive (where VTH2 100 The value is greater than VTH1 100 The value of |VTH2 100 |>|VTH1 100 |, or in other words, VTH2 100 VTH1 100 correct).

[0048] Specifically, the first write voltage difference (V 01 ) may be negative and lower than the fourth threshold voltage VTH4 100 lower (in other words, more negative); the third write voltage difference (V 10 ) may be positive and greater than the second threshold voltage VTH2 100 ; and the second write voltage difference (V 11 ) can be positive and at a first threshold voltage VTH1 100 The second threshold voltage VTH2 100 between, or may be negative and at the third threshold voltage VTH3 100 The fourth threshold voltage VTH4 100 In other words, V 01 <VTH4 100 ; V 10 >VTH2 100 ;VTH1 100 <V11 <VTH2 100 or VTH4 100 <V 11 <VTH3 100 .

[0049] One of the states "01" or "10" may be an overall "on" state for the memory device 100, while the other state "11" or "01" may be an overall "off" state for the memory device 100. Specifically, the state associated with a lower overall resistance may be an overall "on" state, and the state associated with a higher overall resistance may be an overall "off" state.

[0050] As described above, the total resistance of the memory device 100 may depend on the HRS resistance of the first memory cell 100a (oxide-based memory cell) in the "01" state and on the HRS resistance of the second memory cell 100b (conductive-based memory cell) in the "10" state. Since the second memory cell 100b may have a higher HRS resistance than the first memory cell 100a, the memory device 100 may have a lower total resistance in the "01" state and a higher overall resistance in the "10" state. Therefore, for the memory device 100, the "01" state may be the overall "on" state, and the "10" state may be the overall "off" state. The on / off ratio of the memory device 100 may be determined as the ratio of the higher total resistance in the overall "off" state to the lower total resistance in the overall "on" state. In an exemplary non-limiting embodiment, the on / off ratio of the memory device 100 may be in the range from about 100 to about 10,000.

[0051] Although the memory device 100 is described above as being switchable between three states "01", "11", "10", the memory device 100 can be switchable between more than three states by adjusting the write voltage difference between the first electrode 104 and the third electrode 112 accordingly. By increasing the thickness T of the second mask element 110 (located between the electrodes 108, 112 of the conductive bridge memory cell) 110 The thickness T of the first mask element 106 (located between the electrodes 104, 108 of the oxide-based memory cell) is configured to be greater than the thickness T 106, the HRS resistance of the conductive bridge memory cell can be increased, and the difference between the HRS resistances of the memory cells 100a and 100b can be increased. Therefore, the on / off ratio of the memory device 100 can be increased. In the case of a higher on / off ratio, the gap between the higher total resistance and the lower total resistance of the memory device 100 may be larger, and thus the memory device 100 may be switchable between a larger number of different states (each state being associated with a different total resistance) within this gap. In addition, as described above, the switching layer 114 can be formed by depositing a thin liner of the switching material 202. Thus, the thickness T of the switching layer 114 is 114 It may not be limited by photolithography. Therefore, the conductive filaments 302, 304 may be formed in a thinner switching layer 114 and may be better confined. This in turn may help reduce the randomness of the formation of the conductive filaments 302, 304 and the variability of the resistance of the switching layer 114 and the memory device 100, especially when the first or second memory cell 100a, 100b is in HRS. Therefore, the cycle-to-cycle and device-to-device variability of the memory device 100 may be reduced. In addition, by better confining the conductive filaments 302, 304, the size of the conductive filaments 302, 304 may be better controlled (and thereby, the resistance of the first portion 1141 or the second portion 1142 of the switching layer 114 may be better controlled). This can allow the memory device 100 to be switchable between more states that can be clearly distinguished from each other. Therefore, the storage capacity of the memory device 100 may be increased.

[0052] Figure 5 A memory device 500 is shown in accordance with an alternative non-limiting embodiment. Memory device 500 is similar to memory device 100, and thus, common features are labeled with the same reference numerals and need not be discussed.

[0053] Similar to the memory device 100, the first memory cell 100a and the second memory cell 100b in the memory device 500 may be different types of memory cells, and the first electrode 104 and the third electrode 112 may include different materials. However, in the memory device 500, the first memory cell 100a may be a conductive bridge memory cell, and the second memory cell 100b may be an oxide-based memory cell. Therefore, the HRS resistance of the first memory cell 100a may be greater than the HRS resistance of the second memory cell 100b. In addition, the thickness T of the first mask element 106 (located between the electrodes 104, 108 of the conductive bridge memory cell) may be greater than the thickness T of the second mask element 106. 106 The thickness T of the second mask element 110 (located between the electrodes 108, 112 of the oxide-based memory cell) may be greater than 110 In various non-limiting embodiments, the thickness T of the first mask element 106 is106 The thickness T of the second mask element 110 may be 110 In addition, the thickness T of the first mask element 106 is at least twice as large as 106 For example, the thickness T of the first mask element 106 may be less than or equal to 50 nm. 106 The thickness T of the second mask element 110 may be in the range from about 10 nm to about 20 nm. 110 The thickness T of the first and second mask elements 106, 110 may be in the range of about 5 nm to about 10 nm. 106 , T 110 Can alternatively be approximately equal.

[0054] When in use, the memory device 500 may operate in a similar manner to the memory device 100. Specifically, when the first, second, and third write voltage differences V are applied between the first electrode 104 and the third electrode 112 of the memory device 500, respectively. 01 、V 11 、V 10 , the memory device 500 can be switched between states "01", "11", and "10". These write voltage differences (V 01 、V 11 、V 10 ) can also be related to the first, second, third and fourth threshold voltages VTH1 500 、VTH2 500 、VTH3 500 、VTH4 500 The third and fourth threshold voltages VTH3 500 、VTH4 500 The polarity of the first and second threshold voltages VTH1 can be similarly 500 、VTH2 500 For example, the third and fourth threshold voltages VTH3 500 、VTH4 500 Can be negative (where VTH4 500 VTH3 500 more negative); and the first and second threshold voltages VTH1 500 、VTH2 500 Can be positive (where VTH2 500 VTH1 500 In addition, the threshold voltage VTH1 for device 500 500 –VTH4 500 may be different from the threshold voltage VTH1 used for device 100 100 –VTH4 100 .

[0055] Specifically, for the memory device 500, the first write voltage difference (V 01 ) can be positive and greater than the second threshold voltage VTH2 500 ; The third write voltage difference (V 10 ) may be negative and lower than the fourth threshold voltage VTH4 500 (In other words, the fourth threshold voltage VTH4 500 more negative); and a second write voltage difference (V 11 ) can be positive and at a first threshold voltage VTH1 500 The second threshold voltage VTH2 500 between, or can be negative and at the threshold voltage VTH3 500 The fourth threshold voltage VTH4 500 In other words, V 01 >VTH2 500 ; V 10 <VTH4 500 ;VTH1 500 <V 11 <VTH2 500 or VTH4 500 <V 11 <VTH3 500 .

[0056] In the "01" state, the total resistance of the memory device 500 may similarly depend on the HRS resistance of the first memory cell 100a, and in the "10" state, the total resistance of the memory device 500 may similarly depend on the HRS resistance of the second memory cell 100b. However, the HRS resistance of the first memory cell 100a may alternatively be greater than the HRS resistance of the second memory cell 100b compared to the memory device 100. Thus, the memory device 500 may have a lower total resistance in the "10" state and a higher total resistance in the "01" state. Therefore, for the memory device 500, the "01" state may be a total "off" state, and the "10" state may be a total "on" state.

[0057] As described above, in the memory devices 100, 500, the first memory cell 100a and the second memory cell 100b may be different types of memory cells, wherein the first electrode 104 and the third electrode 112 may include different materials. However, the first memory cell 100a and the second memory cell 100b may alternatively be the same type of memory cells including a conductive bridge memory cell or an oxide-based memory cell, and the first electrode 104 and the third electrode 112 may include the same material.

[0058] In this alternative non-limiting embodiment, when first, second and third write voltage differences V are applied between the first electrode 104 and the third electrode 112 of the memory device, respectively. 01 、V 11 、V 10 When the memory device is similarly switchable between states "01", "11", and "10", the first, second, and third write voltage differences (V 01 、V 11 、V 10 ) can also be related to the first, second, third and fourth threshold voltages VTH1 EQ 、VTH2 EQ 、VTH3 EQ 、VTH4 EQ Similarly, the third and fourth threshold voltages VTH3 EQ 、VTH4 EQ The polarity of the first and second threshold voltages VTH1 EQ 、VTH2 EQ For example, the third and fourth threshold voltages VTH3 EQ 、VTH4 EQ Can be negative (where VTH4 EQ VTH3 EQ more negative); and the first and second threshold voltages VTH1 EQ 、VTH2 EQ Can be positive (where VTH2 EQ VTH1 EQ In addition, the threshold voltage VTH1 used for the memory device EQ –VTH4 EQ may be different from the threshold voltage VTH1 used for the memory devices 100, 500 100 –VTH4 100 and VTH1 500 –VTH4 500 .

[0059] Specifically, the first write voltage difference (V 01 ) can be positive and lower than the first threshold voltage VTH1 EQ , or may be negative and lower than the fourth threshold voltage VTH4 EQ (In other words, the fourth threshold voltage VTH4 EQ The second write voltage difference (V 10 ) can be positive and greater than the second threshold voltage VTH2 EQ , or may be negative and greater than the third threshold voltage VTH3 EQ (In other words, it is not as good as the third threshold voltage VTH3 EQNegative). The third write voltage difference (V 11 ) can be positive and at a first threshold voltage VTH1 EQ The second threshold voltage VTH2 EQ or may be negative and at the third threshold voltage VTH3 EQ The fourth threshold voltage VTH4 EQ In other words, 0 <V 01 <VTH1 EQ or V 01 <VTH4 EQ ; V 10 >VTH2 EQ or VTH3 EQ <V 10 <0; VTH1 EQ <V 11 <VTH2 EQ or VTH4 EQ <V 11 <VTH3 EQ .

[0060] Since the first and second memory cells 100a, 100b may be of the same type, if the thickness T of the first and second mask elements 106, 110 is 106 , T 110 If the HRS resistance of the memory cells 100a and 100b is approximately equal, then the HRS resistance of the memory cells 100a and 100b may also be approximately equal. In this case, the memory device may have approximately the same total resistance in the "10" state and the "01" state. Therefore, either of the "10" and "01" states may be an overall "on" state, while the other may be an overall "off" state.

[0061] Alternatively, the thickness T of the first and second mask elements 106, 108 may be 106 , T 110 In this case, when the first, second and third write voltage differences V are applied between the first electrode 104 and the third electrode 112 of the memory device, respectively, 01 、V 11 、V 10 When the memory device is switched between the states "01", "11", and "10", the first, second, and third write voltage differences V 01 、V 11 、V 10 It can also be used in the same way as above for thickness T 106 , T 110 The first to fourth threshold voltages VTH1 are approximately equal in a similar manner. UNEQ 、VTH2 UNEQ 、VTH3UNEQ 、VTH4 UNEQ However, at VTH1 UNEQ and VTH3 UNEQ can be approximately equal to VTH1 EQ and VTH3 EQ At the same time, VTH2 UNEQ Can be compared to VTH2 EQ higher (in other words, more correct), and VTH4 UNEQ Can be compared with VTH4 EQ As stated above, the state (“01” or “10”) with the lower total resistance of the memory device can be the overall “on” state, while the other state (“01” or “10”) can be the overall “off” state. Therefore, if the thickness T of the first mask element 106 is 106 Greater than the thickness T of the second mask element 110 110 , the HRS resistance of the first memory cell 100a may be greater than the HRS resistance of the second memory cell 100b, and thus, the "01" state may be a total "off" state, and the "10" state may be a total "on" state. On the other hand, if the thickness T of the second mask element 110 is 110 Greater than the first mask element T 106 Thickness T 106 , the HRS resistance of the second memory cell 100b can be greater than the HRS resistance of the first memory cell 100a, and thus, the "01" state can be the overall "on" state, and the "10" state can be the overall "off" state.

[0062] Figure 6 A memory device 600 is shown in accordance with an alternative non-limiting embodiment. Memory device 600 is similar to memory device 100, and thus common features are labeled with the same reference numerals and need not be discussed.

[0063] Compared with the memory device 100, the memory device 600 may further include a third memory cell 600a and a fourth memory cell 600b. Specifically, the third memory cell 600a may include a fourth electrode 604 at least partially arranged in the base layer 102, and the fourth memory cell 600b may include a fifth electrode 612 at least partially arranged in the insulating layer 122. Figure 6As shown, the first mask element 106 may be disposed over a portion of the fourth electrode 604 and laterally offset from the fourth electrode 604, and the fifth electrode 612 may be disposed over a portion of the second mask element 110 and laterally offset from the second mask element 110. Specifically, a bottom surface 106 b of the first mask element 106 may partially overlap with and optionally directly contact the fourth electrode 604, and a top surface 110 t of the second mask element 110 may partially overlap with and optionally directly contact the fifth electrode 612.

[0064] The further switching layer 116 may be arranged between the fourth electrode 604 and the fifth electrode 612. Specifically, the further switching layer 116 may extend substantially flatly between the top surface 604t of the fourth electrode 604 and the bottom surface 612b of the fifth electrode 612 along the substantially vertically aligned second side surfaces 106s2, 108s2, 110s2 of the first mask element 106, the second electrode 108 and the second mask element 110. The further switching layer 116 may also extend horizontally on the top surface 604t of the fourth electrode 604 away from the first mask element 106. Thereby, the first mask element 106 may overlap a portion of the top surface 604t of the fourth electrode 604, and the further switching layer 116 may overlap the entire remaining portion of the top surface 604t of the fourth electrode 604. The third memory cell 600a may further include a first portion 1161 of a further switching layer 116 between the fourth electrode 604 and the second electrode 108, and the fourth memory cell 600b may further include a second portion 1162 of a further switching layer 116 between the fifth electrode 612 and the second electrode 108.

[0065] The fourth electrode 604 may be laterally spaced apart from the first electrode 104, or in other words, a portion of the substrate layer 102 (including the insulating material) may be disposed between the first electrode 104 and the fourth electrode 604. Similarly, the fifth electrode 612 may be laterally spaced apart from the third electrode 112, or in other words, a portion of the insulating layer 122 (including the insulating material) may be disposed between the third electrode 112 and the fifth electrode 612. Thus, the fourth electrode 604 and the first electrode 104 may be electrically isolated from each other, and the fifth electrode 612 and the third electrode 112 may be electrically isolated from each other. In other words, the first and second memory cells 100a, 100b may be electrically isolated from the third and fourth memory cells 600a, 600b.

[0066] The memory device 600 may include a further connector 618 and a further contact 620 at least partially arranged within the insulating layer 122. The further connector 618 may electrically connect the further contact 620 to the fifth electrode 612. Specifically, the further connector 618 may be arranged between the further contact 620 and the fifth electrode 612 and may abut the further contact 620 and the fifth electrode 612. The further connector 618 and the further contact 620 may include a conductive material, such as but not limited to aluminum, copper, tungsten, alloys thereof, or combinations thereof. For example, the further contact 620 may include a further conductive line, such as but not limited to a further bit line of the memory device 600, and the further connector 618 may include a conductive via.

[0067] Similar to the first memory cell 100a, the third memory cell 600a may be an oxide-based memory cell, and similar to the second memory cell 100b, the fourth memory cell 600b may be a conductive bridge memory cell. The fourth electrode 604 may include an oxygen scavenging electrode of the third memory cell 600a. Specifically, the fourth electrode 604 may include an oxygen scavenging material such as, but not limited to, titanium (Ti), tantalum (Ta), aluminum (Al), an alloy thereof, or a combination thereof. The fifth electrode 612 may include an active electrode of the fourth memory cell 600b. Specifically, the fifth electrode 612 may include a metal material such as, but not limited to, silver (Ag), copper (Cu), nickel (Ni), an alloy thereof, or a combination thereof. As described above, the further switching layer 116 may include the same material. In other words, the first portion 1161 of the further switching layer 116 and the second portion 1162 of the further switching layer 116 may include the same material.

[0068] The first and second memory cells 100a, 100b may form a first memory cell of the memory device 600, and the third and fourth memory cells 600a, 600b may form a second memory cell of the memory device 600. The first memory cell may be operated in a similar manner to the memory device 100. Specifically, when a first, second, and third write voltage difference V is applied between the first electrode 104 and the third electrode 104, respectively, 01 、V 11 、V 10 , the first memory cell may be switchable between states "01", "11", "10". The second memory cell may also be operated in a similar manner to the memory device 100, except that the write voltage difference may be applied between the fourth electrode 604 and the fifth electrode 612 instead. Specifically, when the first, second and third write voltage differences V are applied between the fourth electrode 604 and the fifth electrode 612, respectively. 01 、V 11 、V 10When the fourth and fifth electrodes 604 and 612 are further provided, the memory device 600 can be similarly compact but with a larger storage capacity compared to the memory device 100.

[0069] Figure 7 A memory device 700 is shown in accordance with an alternative non-limiting embodiment. Memory device 700 is similar to memory device 600, and thus common features are labeled with the same reference numerals and need not be discussed.

[0070] The memory device 700 may similarly include a first memory unit including first and second memory cells 100a, 100b and a second memory unit including third and fourth memory cells 600b, 600b. However, the first and third memory cells 100a, 600a may alternatively be conductive bridge memory cells, and the second and fourth memory cells 100b, 600b may alternatively be oxide-based memory cells. Furthermore, the thickness T of the second mask element 110 may be greater than or equal to 0.03mm. 110 It may be smaller than the thickness T of the first mask element 106 106 The thickness T of the first and second mask elements 106, 110 is 106 , T 110 The thickness T of the mask elements 106 and 110 in the memory device 500 may be approximately equal to 106 , T 110 In use, each of the first and second memory cells of the memory device 700 may be operated in a similar manner as the memory device 500 described above. Specifically, the first, second, and third write voltage differences V may be applied between the first electrode 104 and the third electrode 112 for the first memory cell and between the fourth electrode 604 and the fifth electrode 612 for the second memory cell. 01 、V 11 、V 10 , so that the first and second memory cells can be switchable between the "01", "11", "10" states independently of each other. Therefore, compared with the memory device 500, by further providing the fourth and fifth electrodes 604, 612, the memory device 700 can be similarly compact but have a larger storage capacity.

[0071] The thickness T of the first and second mask elements 106, 110 in the memory devices 600, 700 is 106 , T 110May alternatively be approximately equal. In addition, the memory cells 100a, 100b in the first memory unit may alternatively be of the same type (oxide-based memory cells or conductive bridge memory cells), and similarly, the memory cells 600a, 600b in the second memory unit may alternatively be of the same type (oxide-based memory cells or conductive bridge memory cells). In this alternative non-limiting embodiment, the memory cells 100a, 100b, 600a, 600b in different memory cells may be of the same type or of different types. In addition, each memory cell may operate in a manner similar to that described above with respect to a memory device having first and second memory cells 100a, 100b of the same type.

[0072] Figure 8 A memory device 800 is shown in accordance with an alternative non-limiting embodiment. Memory device 800 is similar to memory device 100, and thus common features are labeled with the same reference numerals and need not be discussed.

[0073] Compared to the memory device 100, the second electrode 108 of the memory device 800 may alternatively include a first electrode layer 1081 and a second electrode layer 1082 disposed over the first electrode layer 1081. The first electrode layer 1081 and the second electrode layer 1082 may include different materials.

[0074] like Figure 8 As shown, the first memory cell 100a may include the first electrode 104, the first electrode layer 1081, and the first portion 1141 of the switching layer 114, and the second memory cell 100b may include the third electrode 112, the second electrode layer 1082, and the second portion 1142 of the switching layer 114. The first electrode layer 1081 may include an inert electrode of the first memory cell 100a, and the second electrode layer 1082 may include an inert electrode of the second memory cell 100b, wherein the first electrode layer 1081 and the second electrode layer 1082 may include different inert electrode materials. The inert electrode material may include platinum (Pt), ruthenium (Ru), gold (Au), alloys thereof, or combinations thereof, or any other inert electrode material known to those skilled in the art.

[0075] Alternatively, the first electrode 104 and the third electrode 112 may comprise inert electrodes of the first memory cell 100a and the second memory cell 100b, respectively; while the first electrode layer 1081 may comprise an oxygen scavenging electrode of the first memory cell 100a, and the second electrode layer 1082 may comprise an active electrode of the second memory cell 100b. The first electrode 104 and the third electrode 112 may comprise the same or different inert electrode materials. The first electrode layer 1081 may comprise an oxygen scavenging material, such as but not limited to titanium (Ti), tantalum (Ta), aluminum (Al), alloys thereof, or combinations thereof, and the second electrode layer 1082 may comprise a metal material, such as but not limited to silver (Ag), copper (Cu), nickel (Ni), alloys thereof, or combinations thereof.

[0076] In the memory devices 500-700 and memory devices having the same type of memory cells 100a, 100b / 600a, 600b as described above, the second electrode 108 may similarly include first and second electrode layers 1081, 1082 including different materials. For example, in the memory device 500, the second electrode 108 may include a first electrode layer 1081 and a second electrode layer 1082. The first electrode layer 1081 may include an active electrode of the first memory cell 100a, the second electrode layer 1082 may include an oxygen scavenging electrode of the second memory cell 100b, and the first electrode 104 and the third electrode 112 may include inert electrodes of the first memory cell 100a and the second memory cell 100b, respectively.

[0077] The present invention may be embodied in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the foregoing embodiments are considered to be illustrative in all respects, rather than limiting the present invention described herein. Therefore, the scope of the present invention is indicated by the appended claims rather than the foregoing description, and all changes within the meaning and scope of the equivalents of the claims are intended to be included therein.

Claims

1. A memory device, include: a first electrode; a first mask element disposed over a portion of the first electrode and partially overlapping and laterally offset from the first electrode; a second electrode disposed over the first mask element; a second mask element disposed over the second electrode; a third electrode disposed over a portion of the second mask element and partially overlapping and laterally offset from the second mask element; a switching layer arranged between the first electrode and the third electrode along a first side surface of the first mask element, a first side surface of the second electrode, and a first side surface of the second mask element; a further switching layer arranged along a second side surface of the first mask element, a second side surface of the second electrode and a second side surface of the second mask element; a fourth electrode, wherein the first masking element is arranged over and partially overlaps and is laterally offset from a portion of the fourth electrode; and a fifth electrode arranged over a portion of the second mask element and partially overlapping and laterally offset from the second mask element, Therein, the further switching layer is arranged between the fourth electrode and the fifth electrode.

2. The memory device according to claim 1, in, The switching layer comprises: a first portion located between the first electrode and the second electrode; and a second portion located between the second electrode and the third electrode; Wherein, the first part and the second part comprise the same material.

3. The memory device according to claim 1, in, The second electrode adjoins the first mask element, and the second mask element adjoins the second electrode.

4. The memory device according to claim 1, in, The second electrode comprises an inert electrode.

5. The memory device according to claim 1, in, The first electrode and the third electrode include different materials.

6. The memory device according to claim 1, in, The first electrode and the third electrode include the same material.

7. The memory device according to claim 1, in, The thickness of the second mask element is greater than the thickness of the first mask element.

8. The memory device according to claim 1, in, The thickness of the first mask element is greater than the thickness of the second mask element.

9. The memory device according to claim 1, in, The thickness of the first mask element is approximately equal to the thickness of the second mask element.

10. The memory device according to claim 1, in, The memory device includes a first memory cell including the first electrode and the second electrode, and a second memory cell including the third electrode and the second electrode.

11. The memory device according to claim 10, in, The first memory cell is an oxide-based memory cell and the second memory cell is a conductive bridge memory cell.

12. The memory device according to claim 10, in, The first memory cell is a conductive bridge memory cell and the second memory cell is an oxide based memory cell.

13. The memory device according to claim 10, in, The first memory cell and the second memory cell are the same type of memory cell including one of a conductive bridge memory cell and an oxide based memory cell.

14. The memory device according to claim 10, in, The second electrode comprises: a first electrode layer; and a second electrode layer disposed on the first electrode layer; wherein the first memory cell includes the first electrode and the first electrode layer of the second electrode, and the second memory cell includes the third electrode and the second electrode layer of the second electrode; and The first electrode layer and the second electrode layer include different materials.

15. The memory device according to claim 14, in, The first electrode layer comprises an oxygen scavenging electrode of the first memory cell, and the second electrode layer comprises an active electrode of the second memory cell.

16. The memory device according to claim 1, in, The second side surfaces of the first mask element, the second electrode and the second mask element face opposite directions to the first side surfaces of the first mask element, the second electrode and the second mask element, respectively.

17. A method for manufacturing a memory device, the method include: forming a first electrode; forming a first mask element over a portion of the first electrode, wherein the first mask element partially overlaps and is laterally offset from the first electrode; forming a second electrode over the first mask element; forming a second mask element over the second electrode; forming a third electrode over a portion of the second mask element, wherein the third electrode partially overlaps and is laterally offset from the second mask element; forming a fourth electrode, wherein the first masking element is disposed over and partially overlaps and is laterally offset from a portion of the fourth electrode; forming a fifth electrode over a portion of the second mask element, wherein the fifth electrode partially overlaps and is laterally offset from the second mask element; forming a switching layer between the first electrode and the third electrode along a first side surface of the first mask element, a first side surface of the second electrode, and a first side surface of the second mask element; and A further switching layer is formed between the fourth electrode and the fifth electrode along the second side surface of the first mask element, the second side surface of the second electrode and the second side surface of the second mask element.

18. The method according to claim 17, in, Forming the switching layer comprises: depositing a switching material over the second mask element; and A portion of the switching material over the second mask element is removed.

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