A synchronous rectification control circuit

Abstract

The present invention discloses a synchronous rectification control circuit, which is applied to an active clamp flyback converter, and transmits the falling edge of the clamp switch tube drive signal to the secondary side, and converts it into an enable control signal to control the shutdown of the synchronous rectifier tube. As a specific implementation method, based on the prior art, it also includes a switch tube Q3, an isolation transformer T2, a resistor R2, a capacitor C3 and a resistor R3; one end of the resistor R2 inputs the working voltage, and the other end is connected to one end of the switch tube Q3 and one end of the capacitor C3, the control end of the switch tube Q3 inputs a signal synchronized with the clamp tube drive signal, the other end of the switch tube Q3 is simultaneously connected to one end of the resistor R3, one end of the primary side of the isolation transformer T2 and the primary side ground, the other end of the capacitor C3 is simultaneously connected to the other end of the resistor R3 and the other end of the primary side of the isolation transformer T2, one end of the secondary side of the isolation transformer T2 is connected to the enable signal pin of the synchronous rectification control chip, and the same-name end of the secondary side of the isolation transformer T2 is connected to the secondary side ground. The present invention can ensure that the synchronous rectifier tube is turned off in advance before the main tube is turned on.

Description

Technical Field

[0001] The invention relates to the field of switching converters, and in particular to synchronous rectification control of active clamp flyback switching converters. Background Art

[0002] Active Clamp Flyback (ACF) converter is a kind of flyback converter. It has the advantages of zero voltage switch (ZVS) of the main switch tube, lossless absorption of leakage inductance, small voltage spike of the main switch tube, high efficiency, etc., and its application is becoming more and more extensive. The circuit schematic diagram of the existing conventional active clamp flyback converter is as follows: Figure 1 , Figure 1 In the figure, Q1 is the main switch tube (hereinafter referred to as the main tube), Q2 is the clamp switch tube (hereinafter referred to as the clamp tube), Cc is the clamp capacitor; Ds1 is the body diode of the main switch tube Q1, and Ds2 is the body diode of the clamp switch tube Q2. Figure 1 Taking the schematic diagram shown as an example, when using the trailing edge non-complementary control timing, its working principle is as follows.

[0003] The so-called trailing edge non-complementary control timing means that the clamping tube is turned on a short time before the main tube is turned on (dead time), and the on-time of the clamping tube is not complementary to the on-time of the main tube. on_c (The short period of time here t on_c After the clamp tube is turned off, a dead time t d , and then open the supervisor; and after the supervisor is shut down, after a long time t delay Then the clamping tube is turned on again, and the cycle repeats. Assuming the switching period is Ts, and the duty cycle of the main tube is D, then (1-D·T s ) = t delay +t on_c +t d .by Figure 1 Taking the active clamp flyback converter shown in FIG. 1 as an example, when the circuit operates in continuous mode (CCM), the timing control and main waveforms of the trailing edge non-complementary control mode are as follows: Figure 2 As shown, Figure 2 In the figure, GTL is the driving signal of the main tube Q1, GTH is the driving signal of the clamp tube Q2, Vds1 is the drain-source voltage of the main tube Q1, and Vds2 is the drain-source voltage of the clamp tube Q2; Vc is the voltage across the clamp capacitor Cc, and its direction is Figure 1The top of the schematic diagram is positive and the bottom is negative; Im is the current flowing through the transformer excitation inductance Lm (or called excitation current), Ids1 is the current flowing through the drain of the main pipe Q1; Ids2 is the current flowing through the drain of the clamping tube Q2, and Ids2 is also equal to the current flowing through the clamping capacitor Cc; Ip is the current flowing through the primary winding of the transformer, and is also the current flowing through the leakage inductance Lk; Id is the current flowing through the secondary rectifier diode, and Vd is the reverse voltage of the secondary rectifier diode.

[0004] In switching converters, synchronous rectification technology is often used to reduce the loss of rectifier tubes and improve the efficiency of the converter. Figure 3 The schematic diagram of an active clamp flyback converter using synchronous rectification on the secondary side is shown. Figure 3 In the figure, SR1 is the secondary side synchronous rectification N-MOS tube, and the body diode inside SR1 is omitted here; Vgs_SR is the driving signal of the synchronous rectification N-MOS tube SR1. Figure 3 The synchronous rectification control circuit includes: a synchronous rectification control chip U1, a capacitor C10, a resistor Rd and a resistor Rg; the synchronous rectification control chip U1 includes a power supply pin VCC, a detection pin VD, a drive signal pin GATE and a bootstrap pin VS, the power supply pin VCC is used to power the synchronous rectification IC, the detection pin VD is used to detect the drain-source voltage change of the synchronous rectification N-MOS tube SR1, the drive signal pin GATE is used to output the drive signal, and the bootstrap pin VS is used to realize the voltage bootstrap between the drive signal pin GATE and the bootstrap pin VS; the capacitor C10 is a decoupling capacitor of the synchronous rectification control chip U1 , the resistor Rg is the driving resistor of the synchronous rectifier N-MOS tube SR1; the connection relationship of the synchronous rectification control circuit is: the power supply pin VCC is used to input the power supply voltage VCC, the power supply pin VCC is also connected to one end of the capacitor C10, the other end of the capacitor C10 is connected to the secondary ground signal Vo-, the detection pin VD is connected to one end of the resistor Rd, the other end of the resistor Rd is connected to the drain of the synchronous rectifier N-MOS tube SR1, the drive signal pin GATE is connected to one end of the resistor Rg, the other end of the resistor Rg is connected to the gate of the synchronous rectifier N-MOS tube SR1, and the bootstrap pin VS is connected to the source of the synchronous rectifier N-MOS tube SR1.

[0005] Typically, the control mode of the synchronous rectification control chip U1 is to detect the drain-source voltage Vds_SR of the synchronous rectification N-MOS tube SR1. When Vds_SR is less than the turn-on threshold Vds_on, the drive signal Vgs_SR of the synchronous rectification N-MOS tube SR1 is set to a high level, and SR1 is turned on; when Vds_SR is greater than the turn-off threshold Vds_off, the drive signal Vgs_SR of the synchronous rectification N-MOS tube SR1 is set to a low level, and SR1 is turned off. However, when the circuit works in CCM mode, if the current Ids_SR of the secondary synchronous rectifier N-MOS tube SR1 has not dropped below the shutdown threshold of the control IC when the primary main tube Q1 is turned on, the primary and secondary N-MOS will be in common; or, when the primary main tube Q1 is turned on, the voltage across its Vds drops, and the voltage across the primary winding of the transformer and the voltage across the secondary winding both increase, causing the drain-source voltage Vds_SR of the secondary synchronous rectifier N-MOS tube SR1 to be forced to rise. When Vds_SR is greater than the shutdown threshold, the IC will be turned off. When Vds_off, the driving signal Vgs_SR of the synchronous rectifier N-MOS tube SR1 is set to a low level, and SR1 is turned off; it can be seen that the generation of the synchronous rectifier N-MOS tube shutdown signal is achieved by the voltage increase at both ends of the transformer winding. However, due to the transmission delay of the transformer and the signal transmission delay of other circuits such as the synchronous rectifier control chip U1, this delay will inevitably cause the shutdown of the synchronous rectifier N-MOS tube SR1 to be delayed, resulting in the simultaneous conduction (i.e., common) of the primary and secondary N-MOS, such as Figure 4 As shown; once the primary and secondary N-MOS tubes are in common, the current or voltage of the primary and secondary N-MOS tubes will increase sharply and fail.

[0006] It should be noted that the information disclosed in this background technology section is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as acknowledging or suggesting in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0007] In view of this, the technical problem to be solved by the present invention is to provide a synchronous rectification control method, which is applied to an active clamp flyback converter and can ensure that the synchronous rectification drive is turned off in advance before the primary main circuit is turned on.

[0008] The inventive concept of the present application is to transmit the falling edge of the clamp switch tube drive signal to the secondary side and convert it into an enable control signal for controlling the shutdown of the secondary side synchronous rectification N-MOS tube.

[0009] Based on the above inventive concept, the first technical solution provided by the present invention is as follows:

[0010] A synchronous rectification control circuit is applied to an active clamp flyback converter, wherein the synchronous rectification control circuit at least comprises a synchronous rectification control chip U1; wherein:

[0011] The synchronous rectification control circuit also includes a switch tube Q3, an isolation transformer T2, a resistor R2, a capacitor C3 and a resistor R3. The synchronous rectification control chip U1 includes an enable signal pin SYN. ​​The switch tube Q3 is the same type of switch tube as the clamp tube in the active clamp flyback converter. One end of the resistor R2 is used to input the working voltage VDD, and the other end of the resistor R2 is simultaneously connected to one end of the switch tube Q3 and one end of the capacitor C3. The control end of the switch tube Q3 is used to input a control signal synchronized with the clamp tube drive signal in the active clamp flyback converter. The other end of the switch tube Q3 is simultaneously connected to one end of the resistor R3, one end of the primary side of the isolation transformer T2 and the primary side ground GND. The other end of the capacitor C3 is simultaneously connected to the other end of the resistor R3 and the other end of the primary side of the isolation transformer T2. One end of the secondary side of the isolation transformer T2 is connected to the enable signal pin SYN, and the secondary side of the isolation transformer T2 is connected to the secondary side ground signal Vo-.

[0012] The same-name end and the opposite-name end of the isolation transformer T2 are configured as follows: when one end of the primary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end, one end of the secondary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end; when one end of the primary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end, one end of the secondary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end.

[0013] Preferably, the applied active clamp flyback converter adopts trailing edge non-complementary control timing and operates in CCM mode.

[0014] Preferably, when the clamping tube in the active clamping flyback converter is an N-MOS tube, the switch tube Q3 is an N-MOS tube, the gate of the N-MOS tube is the control end of the switch tube Q3, the drain of the N-MOS tube is one end of the switch tube Q3, and the source of the N-MOS tube is the other end of the switch tube Q3; or when the clamping tube in the active clamping flyback converter is an N-MOS tube, the switch tube Q3 is an NPN transistor, the base of the NPN transistor is the control end of the switch tube Q3, the collector of the NPN transistor is one end of the switch tube Q3, and the emitter of the NPN transistor is the other end of the switch tube Q3.

[0015] Furthermore, the synchronous rectification control circuit further includes a diode D3, wherein the anode of the diode D3 is connected to the primary opposite-name terminal of the isolation transformer T2, and the cathode of the diode D3 is connected to the primary same-name terminal of the isolation transformer T2.

[0016] Furthermore, the synchronous rectification control circuit further includes a capacitor C2, and the capacitor C2 is connected across the primary winding of the isolation transformer T2.

[0017] Furthermore, the synchronous rectification control circuit further includes a capacitor C1, and the capacitor C1 is connected across the secondary winding of the isolation transformer T2.

[0018] Furthermore, the synchronous rectification control circuit further includes a resistor R1, and the resistor R1 is connected across two ends of the secondary winding of the isolation transformer T2.

[0019] Furthermore, the synchronous rectification control circuit further includes a diode D1 and a diode D2. The diode D1 and the diode D2 are connected in reverse parallel and then connected across the secondary winding of the isolation transformer T2.

[0020] Based on the above inventive concept, the second technical solution provided by the present invention is as follows:

[0021] A synchronous rectification control circuit is applied to an active clamp flyback converter, wherein the synchronous rectification control circuit at least comprises a synchronous rectification control chip U1; wherein:

[0022] The synchronous rectification control circuit also includes an RS trigger U2, a switch tube Q4, a resistor R1 and an isolation transformer T2. The synchronous rectification control chip U1 includes an enable signal pin SYN. ​​The switch tube Q4 and the clamp tube in the active clamp flyback converter are different types of switch tubes. The S pin of the trigger U2 and the control end of the switch tube Q4 are both used to input a signal synchronized with the clamp tube drive signal in the active clamp flyback converter. The R pin of the trigger U2 is used to input a signal synchronized with the main tube drive signal in the active clamp flyback converter. The Q pin of the trigger U2 is connected to one end of the switch tube Q4, and the other end of the switch tube Q4 is connected to one end of the resistor R1 and one end of the primary side of the isolation transformer T2. The other end of the resistor R1 is connected to the other end of the primary side of the isolation transformer T2 and the primary side ground GND. One end of the secondary side of the isolation transformer T2 is connected to the enable signal pin SYN pin, and the other end of the secondary side of the isolation transformer T2 is connected to the secondary side ground signal Vo-.

[0023] The same-name end and the opposite-name end of the isolation transformer T2 are configured as follows: when one end of the primary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end, one end of the secondary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end; when one end of the primary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end, one end of the secondary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end.

[0024] Preferably, the applied active clamp flyback converter adopts trailing edge non-complementary control timing and operates in CCM mode.

[0025] Preferably, when the clamping tube in the active clamping flyback converter is an N-MOS tube, the switch tube Q4 is a P-MOS tube, the gate of the P-MOS tube is the control end of the switch tube Q4, the source of the P-MOS tube is one end of the switch tube Q4, and the drain of the P-MOS tube is the other end of the switch tube Q4; or when the clamping tube in the active clamping flyback converter is an N-MOS tube, the switch tube Q4 is a PNP transistor, the base of the PNP transistor is the control end of the switch tube Q4, the emitter of the PNP transistor is one end of the switch tube Q4, and the collector of the PNP transistor is the other end of the switch tube Q4.

[0026] Based on the above inventive concept, the third technical solution provided by the present invention is as follows:

[0027] A synchronous rectification control circuit is applied to an active clamp flyback converter, wherein the synchronous rectification control circuit at least comprises a synchronous rectification control chip U1; wherein:

[0028] The synchronous rectification control circuit also includes an RS trigger U2, a switch tube Q4, a resistor R1, a switch tube Q3 and an isolation transformer T2. The synchronous rectification control chip U1 includes an enable signal pin SYN. ​​The switch tube Q4 and the clamp tube in the active clamp flyback converter are switch tubes of different types. The switch tube Q3 and the clamp tube in the active clamp flyback converter are switch tubes of the same type. The S pin of the trigger U2 and the control end of the switch tube Q4 are both used to input a signal synchronized with the clamp tube drive signal in the active clamp flyback converter. The R pin of the trigger U2 is used to input a signal synchronized with the active clamp flyback converter. The signal for synchronizing the driving signal in the source clamp flyback converter, the Q pin of the trigger U2 is connected to one end of the switch tube Q4, the other end of the switch tube Q4 is connected to one end of the resistor R1 and the control end of the switch tube Q3, the other end of the resistor R1 is connected to the primary ground GND, one end of the switch tube Q3 is connected to the primary ground GND, the other end of the switch tube Q3 is connected to one end of the primary side of the isolation transformer T2, the other end of the primary side of the isolation transformer T2 is used to input the working voltage VDD, one end of the secondary side of the isolation transformer T2 is connected to the enable signal pin SYN pin, and the other end of the secondary side of the isolation transformer T2 is connected to the secondary ground signal Vo-;

[0029] The same-name end and the opposite-name end of the isolation transformer T2 are configured as follows: when one end of the primary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end, one end of the secondary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end; when one end of the primary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end, one end of the secondary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end.

[0030] Preferably, the applied active clamp flyback converter adopts trailing edge non-complementary control timing and operates in CCM mode.

[0031] Preferably, when the clamping tube in the active clamp flyback converter is an N-MOS tube, the switch tube Q3 is an N-MOS tube, and the switch tube Q4 is a P-MOS tube. For the switch tube Q3, the gate of the N-MOS tube is the control end of the switch tube Q3, the source of the N-MOS tube is one end of the switch tube Q3, and the drain of the N-MOS tube is the other end of the switch tube Q3. For the switch tube Q4, the gate of the P-MOS tube is the control end of the switch tube Q4, the source of the P-MOS tube is one end of the switch tube Q4, and the drain of the P-MOS tube is the other end of the switch tube Q4; or when When the clamping tube in the active clamp flyback converter is an N-MOS tube, the switch tube Q3 is an NPN transistor, and the switch tube Q4 is a PNP transistor. For the switch tube Q3, the base of the NPN transistor is the control end of the switch tube Q3, the emitter of the NPN transistor is one end of the switch tube Q3, and the collector of the NPN transistor is the other end of the switch tube Q3. For the switch tube Q4, the base of the PNP transistor is the control end of the switch tube Q4, the emitter of the PNP transistor is one end of the switch tube Q4, and the collector of the PNP transistor is the other end of the switch tube Q4.

[0032] Based on the above inventive concept, the fourth technical solution provided by the present invention is as follows:

[0033] A synchronous rectification control circuit is applied to an active clamp flyback converter, wherein the synchronous rectification control circuit at least comprises a synchronous rectification control chip U1; wherein:

[0034] The synchronous rectification control circuit further includes a switch tube Q5, a capacitor C1, a resistor R2, a comparator U3 and an isolation transformer T2. The synchronous rectification control chip U1 includes an enable signal pin SYN. ​​The switch tube Q5 and the clamp tube in the active clamp flyback converter are different types of switch tubes. The control end of the switch tube Q5 is used to input a signal synchronized with the drive signal of the clamp tube in the active clamp flyback converter. One end of the switch tube Q5 is used to input a working voltage VDD. The other end of the switch tube Q5 is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to one end of the resistor R2 and an input end of the comparator U3. The other end of the resistor R2 is connected to the primary ground GND. The other input end of the comparator U3 is used to input a reference voltage signal Vref. The output end of the comparator U3 is connected to one end of the primary side of the isolation transformer T2. The other end of the primary side of the isolation transformer T2 is connected to the primary ground GND. One end of the secondary side of the isolation transformer T2 is connected to the enable signal pin SYN. ​​The other end of the secondary side of the isolation transformer T2 is connected to the secondary ground signal Vo-.

[0035] The same-name end and the opposite-name end of the isolation transformer T2 are configured as follows: when one end of the primary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end, one end of the secondary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end; when one end of the primary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end, one end of the secondary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end.

[0036] Preferably, the applied active clamp flyback converter adopts trailing edge non-complementary control timing and operates in CCM mode.

[0037] Preferably, when the clamping tube is an N-MOS tube, the switch tube Q5 is a P-MOS tube, the gate of the P-MOS tube is the control end of the switch tube Q5, the source of the P-MOS tube is one end of the switch tube Q5, and the drain of the P-MOS tube is the other end of the switch tube Q5; or the switch tube Q5 is a PNP transistor, the base of the PNP transistor is the control end of the switch tube Q5, the emitter of the PNP transistor is one end of the switch tube Q5, and the collector of the PNP transistor is the other end of the switch tube Q5.

[0038] The present invention uses a switch tube and an isolation transformer to form a pulse signal control circuit to ensure that the active clamp flyback converter is in CCM mode and the synchronous rectification drive is turned off in advance before the primary main tube is turned on. Compared with the prior art, the present invention has the following beneficial effects:

[0039] (1) It can realize the active clamp flyback converter in CCM mode, and the secondary side synchronous rectification N-MOS tube works with the maximum conduction time to improve efficiency;

[0040] (2) The circuit is simple and the cost is low;

[0041] (3) The reliability of synchronous rectification control of the active clamp flyback converter in CCM is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 Schematic diagram of an active clamp flyback converter with N-MOS clamp switch;

[0043] Figure 2 Timing diagram of active clamp flyback converter in trailing edge non-complementary control mode;

[0044] Figure 3 Schematic diagram of an active clamp flyback converter using synchronous rectification on the secondary side;

[0045] Figure 4 The common timing diagram of the primary and secondary sides of the active clamp flyback converter in CCM mode;

[0046] Figure 5 is a circuit diagram of the first embodiment of the present invention;

[0047] Figure 6 is a control timing diagram of the first embodiment of the present invention;

[0048] Figure 7 is a circuit diagram of a second embodiment of the present invention;

[0049] Figure 8 is a circuit diagram of a third embodiment of the present invention;

[0050] Fig. 9 is a circuit diagram of a fourth embodiment of the present invention;

[0051] Fig.10 is a control timing diagram of a fourth embodiment of the present invention;

[0052] Fig.11 is a circuit diagram of a fifth embodiment of the present invention;

[0053] Fig.12 is a circuit diagram of a sixth embodiment of the present invention;

[0054] Fig.13 FIG. 4 is a control timing diagram of the sixth embodiment of the present invention.

[0055] The technical features corresponding to the marks in each timing diagram are:

[0056] GTL is responsible for the driving signal of Q1

[0057] The driving signal of GTH clamp tube Q2

[0058] Vds1 is the drain-source voltage of Q1

[0059] Vds2 is the drain-source voltage of clamp tube Q2

[0060] Vc is the voltage across the clamp capacitor Cc

[0061] Im is the current flowing through the transformer magnetizing inductance Lm

[0062] Ip is the current flowing through the primary winding of the transformer

[0063] Ids1 is the current flowing through the drain of the main Q1

[0064] Ids2 is the current flowing through the drain of clamp tube Q2

[0065] Id is the current flowing through the secondary rectifier diode

[0066] Vd is the reverse voltage of the secondary rectifier diode

[0067] Ids_SR Current of synchronous rectifier N-MOS tube SR1

[0068] Vds_SR Synchronous rectifier N-MOS tube SR1 drain-source voltage

[0069] Vgs_SR synchronous rectifier N-MOS tube SR1 drive signal

[0070] SYN enable control signal

[0071] The R pin level of the GTL / R trigger U2 is synchronized with the GTL

[0072] The S pin level of the GTH / S trigger U2 is synchronized with GTH

[0073] The Q pin level of Q flip-flop U2

[0074] Vg Gate signal of N-MOS tube Q3 DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0076] First embodiment

[0077] like Figure 5 As shown, it is a circuit diagram of the first embodiment of the present invention, the dotted box 501 is the synchronous rectification control circuit of the present invention, and Figure 3 The synchronous rectification control circuit in the embodiment is different in that it also includes: an N-MOS tube Q3, an isolation transformer T2, a resistor R2, a capacitor C3 and a resistor R3. In addition, the synchronous rectification control chip U1 also includes an enable signal pin SYN; one end of the resistor R2 is used to input the working voltage VDD, and the other end of the resistor R2 is simultaneously connected to the drain of the N-MOS tube Q3 and one end of the capacitor C3, the driving signal input to the gate of the N-MOS tube Q3 and the driving signal input to the gate of the clamp tube Q2 are both GTH, the source of the N-MOS tube Q3 is simultaneously connected to one end of the resistor R3, the primary side opposite-name terminal of the isolation transformer T2 and the primary side ground GND, the other end of the capacitor C3 is simultaneously connected to the other end of the resistor R3 and the primary side same-name terminal of the isolation transformer T2, the secondary side opposite-name terminal of the isolation transformer T2 is connected to the enable signal pin SYN, and the secondary side same-name terminal of the isolation transformer T2 is connected to the secondary side ground signal Vo-.

[0078] The working principle of this embodiment is as follows:

[0079] After the falling edge signal of the clamp tube drive signal GTH arrives, the N-MOS tube Q3 is turned off, and the working voltage VDD will charge the capacitor C3 through the resistor R3. The voltage across the capacitor C3 rises from 0V to VDD, and the voltage across the resistor R3 drops from VDD to 0V. The positive pulse voltage across the resistor R3 is converted into a positive pulse excitation signal in which the same-name end of the primary side of the isolation transformer T2 is higher than the opposite-name end of the primary side. The positive pulse excitation signal is coupled to the secondary side through the isolation transformer T2, and the coupled signal is also higher at the same-name end than at the opposite-name end. Since the same-name end of the secondary side of the isolation transformer T2 is connected to the secondary side ground signal Vo-, the opposite-name end of the secondary side of the isolation transformer T2 receives the negative pulse excitation signal SYN, and uses this negative pulse excitation signal SYN as an enable control signal to enable and control the synchronous rectification IC, and turn off the synchronous rectification drive, thereby avoiding the common phenomenon of the primary and secondary sides, wherein the change in the amplitude of the SYN signal can be achieved by changing the turns ratio of the isolation transformer T2.

[0080] like Figure 6 The control timing diagram of this embodiment is shown. When GTH changes from a high level to a low level, SYN is a negative pulse excitation signal induced by the secondary side of the isolation transformer T2. The negative pulse excitation signal SYN is used as an enable control signal to enable the synchronous rectification IC and turn off the synchronous rectification drive, thereby avoiding the common phenomenon of the original secondary side. The enable control circuit is simple and low-cost, and can achieve the secondary side synchronous rectification N-MOS tube working with the maximum conduction time in CCM mode, thereby improving efficiency and greatly improving the reliability of synchronous rectification control of the ACF converter in CCM.

[0081] Second embodiment

[0082] like Figure 7 As shown, it is a circuit schematic diagram of the second embodiment of the present invention, and the dotted box 701 is the synchronous rectification control circuit of the present invention. Compared with the first embodiment of the present invention, the difference of the second embodiment is that it also includes a diode D3, a capacitor C1, a capacitor C2 and a resistor R1, the anode of the diode D3 is connected to the primary opposite-name terminal of the isolation transformer T2, the cathode of the diode D3 is connected to the primary same-name terminal of the isolation transformer T2, the capacitor C2 is connected across the primary winding of the isolation drive transformer T2, and the capacitor C1 and the resistor R1 are connected in parallel across the secondary winding of the isolation transformer T2.

[0083] After adding diode D3 and capacitor C2, the high-frequency interference signal of the primary excitation voltage will be bypassed by capacitor C2, and the primary same-name terminal voltage of the isolation transformer T2 will be clamped by diode D3, thereby preventing the excessive voltage at both ends of the primary winding from being coupled to the secondary side, causing the secondary IC to be damaged due to excessive voltage stress.

[0084] After adding capacitor C1 and resistor R1, the high-frequency interference signal of the secondary negative pulse excitation signal SYN will be bypassed by capacitor C1, thereby improving the anti-interference ability of the circuit. The amplitude of the secondary negative pulse excitation signal SYN can be adjusted by resistor R1, so that the size of the enable signal SYN can be flexibly controlled.

[0085] Compared with the first embodiment of the present invention, the basic working principle of the second embodiment is essentially the same as that of the first embodiment, and will not be described in detail here.

[0086] Third embodiment

[0087] like Figure 8 As shown, it is a circuit schematic diagram of the third embodiment of the present invention, and the dotted box 801 is the synchronous rectification control circuit of the present invention. Compared with the second embodiment of the present invention, the difference of the third embodiment is that it also includes a diode D1 and a diode D2. The diode D1 and the diode D2 are connected in reverse parallel across the secondary winding of the isolation drive transformer T2.

[0088] By adding diodes D1 and D2, the voltage across the secondary winding of the isolation drive transformer T2 will be clamped by the diodes to ensure that the amplitude of the secondary excitation voltage signal SYN is not too large or too small to damage the synchronous rectification control chip U1, thereby increasing the reliability of the circuit.

[0089] Compared with the second embodiment of the present invention, the basic working principle of the third embodiment is essentially the same as that of the second embodiment of the present invention, and will not be described in detail herein.

[0090] Fourth embodiment

[0091] like Fig. 9 As shown, it is a circuit schematic diagram of the fourth embodiment of the present invention. The dotted box 901 is a synchronous rectification control circuit of the present invention, including an RS trigger U2, a P-MOS tube Q4, a resistor R1 and an isolation transformer T2. In addition, the synchronous rectification control chip U1 also includes an enable signal pin SYN; the signal input to the S pin of the trigger U2 and the drive signal input to the gate of the P-MOS tube Q4 are the same as the drive signal connected to the clamp tube Q2, which is GTH; the signal input to the R pin of the trigger U2 and the drive signal of the main tube Q1 are the same as GTL; the Q pin of the trigger U2 is connected to the source of the P-MOS tube Q4, the drain of the P-MOS tube Q4 is connected to one end of the resistor R1 and the primary same-name terminal of the isolation transformer T2, the other end of the resistor R1 is connected to the primary opposite-name terminal of the isolation transformer T2 and the primary ground GND, the secondary opposite-name terminal of the isolation transformer T2 is connected to the enable signal pin SYN pin, and the secondary same-name terminal of the isolation transformer T2 is connected to the secondary ground signal Vo-.

[0092] The working principle of this embodiment is as follows:

[0093] Depend on Figure 2It can be seen that when the driving signal GTH of the clamp tube Q2 is at a high level, the driving signal GTL of the main tube Q1 is at a low level, that is, the S pin of the trigger U2 is at a high level, and the R pin is at a low level. According to the principle of the RS trigger, the Q pin of the trigger U2 is at a high level at this time. After the opening time of the clamp tube Q2 is reached, the driving signal of the clamp tube Q2 changes from a high level to a low level, that is, the S pin of the trigger U2 changes from a high level to a low level, and the R pin of the trigger U2 continues to remain at a low level. According to the principle of the RS trigger, the Q pin of the trigger U2 remains at a high level. At this time, the source S of the P-MOS tube Q4 remains at a high level, and the gate of the P-MOS tube Q4 changes from a high level to a low level. MOS tube Q4 becomes on, and the voltage across resistor R1 becomes high level. The positive pulse voltage across resistor R1 is converted into a positive pulse excitation signal in which the same-name end of the primary side of isolation transformer T2 is higher than the opposite-name end of the primary side. The positive pulse excitation signal is coupled to the secondary side through the isolation transformer, and the coupled signal is also higher at the same-name end than at the opposite-name end. Since the same-name end of the secondary side of the isolation transformer is connected to Vo-, the opposite-name end of the secondary side of the isolation transformer receives the negative pulse excitation signal SYN, and uses the negative pulse excitation signal SYN as an enable control signal to enable and control the synchronous rectification control chip U1, and shut down the synchronous rectification drive, thereby avoiding the common phenomenon of the primary and secondary sides. The change in the amplitude of the SYN signal can be achieved by changing the turns ratio of the isolation transformer T2.

[0094] When the main tube Q1 is turned on, the driving signal GTL of the main tube Q1 changes from low level to high level. At this time, the driving signal GTH of the clamp tube Q2 is low level. According to the principle of the RS trigger, at this time, the Q pin of the trigger U2 changes from high level to low level, the source S of the P-MOS tube Q4 changes from high level to low level, the gate of the P-MOS tube Q4 continues to remain in a low level state, the P-MOS tube Q4 changes to a turned-off state, the voltage across the resistor R1 changes to a low level state, the two ends of the primary side of the isolation transformer T2 become a non-triggered state, and the SYN signal remains zero.

[0095] like Fig.10 The control timing diagram of this embodiment is shown as the control timing diagram of the fourth embodiment of the present invention. When GTH changes from a high level to a low level, SYN senses a negative pulse excitation signal, which ends when GTL changes from a low level to a high level. SYN senses a negative pulse excitation signal, and uses the negative pulse excitation signal SYN as an enable control signal to enable the synchronous rectification IC and turn off the synchronous rectification drive, thereby avoiding the common phenomenon of the original secondary side. The enable control circuit is simple in circuit and low in cost, and can realize the operation of the secondary side synchronous rectification N-MOS tube with the maximum conduction time in CCM mode, thereby improving efficiency and greatly improving the reliability of synchronous rectification control of the ACF converter in CCM.

[0096] Fifth embodiment

[0097] like Fig.11 As shown, it is a circuit schematic diagram of the fifth embodiment of the present invention. The dotted box 1101 is a synchronous rectification control circuit of the present invention, including an RS trigger U2, a P-MOS tube Q4, a resistor R1, an N-MOS tube Q3 and an isolation transformer T2. In addition, the synchronous rectification control chip U1 also includes an enable signal pin SYN; the signal input by the S pin of the trigger U2 and the driving signal input by the gate of the P-MOS tube Q4 and the driving signal of the clamp tube Q2 are all GTH, and the signal input by the R pin of the trigger U2 and the driving signal of the main tube Q1 are all GTL. The Q pin of the trigger U2 is connected to the source of the P-MOS tube Q4, the drain of the P-MOS tube Q4 is connected to one end of the resistor R1 and the gate of the N-MOS tube Q3, the other end of the resistor R1 is connected to the primary ground GND, the source of the N-MOS tube Q3 is connected to the primary ground GND, the drain of the N-MOS tube Q3 is connected to the primary opposite-name terminal of the isolation transformer T2, the primary same-name terminal of the isolation transformer T2 inputs the working voltage VDD, the secondary opposite-name terminal of the isolation transformer T2 is connected to the enable signal pin SYN pin, and the secondary same-name terminal of the isolation transformer T2 is connected to the secondary ground signal Vo-.

[0098] The working analysis of this embodiment is as follows:

[0099] Depend on Figure 2It can be seen that when the driving signal GTH of the clamp tube Q2 is at a high level, the driving signal GTL of the main tube Q1 is at a low level, that is, the S pin of the trigger U2 is at a high level, and the R pin is at a low level. According to the principle of the RS trigger, at this time, the Q pin of the trigger U2 is at a high level. After the opening time of the clamp tube Q2 is reached, the driving signal of the clamp tube Q2 changes from a high level to a low level, that is, the S pin of the trigger U2 changes from a high level to a low level, and the R pin of the trigger U2 continues to remain at a low level. According to the principle of the RS trigger, the Q pin of the trigger U2 remains at a high level. At this time, the source S of the P-MOS tube Q4 remains at a high level, and the gate of the P-MOS tube Q4 changes from a high level to a low level, and the P-MOS tube Q4 becomes conductive. state, both ends of the resistor R1 become high level state, the gate signal Vg of the N-MOS tube Q3 becomes high level, the N-MOS tube Q3 is turned on, and the working voltage VDD causes the isolation transformer T2 to sense a positive pulse excitation signal that is higher at the same-name end of the primary side than at the opposite-name end of the primary side. The positive pulse excitation signal is coupled to the secondary side through the isolation transformer, and the coupled signal is also higher at the same-name end than at the opposite-name end. Since the same-name end of the secondary side of the isolation transformer is connected to Vo-, the opposite-name end of the secondary side of the isolation transformer receives the negative pulse excitation signal SYN, and uses this negative pulse excitation signal SYN as an enable control signal to enable and control the synchronous rectification IC, and turn off the synchronous rectification drive, thereby avoiding the common phenomenon of the primary and secondary sides, wherein the change in the amplitude of the SYN signal can be achieved by changing the turns ratio of the isolation transformer T2.

[0100] When the main tube Q1 is turned on, the driving signal GTL of the main tube Q1 changes from low level to high level. At this time, the driving signal GTH of the clamp tube Q2 is low level. According to the principle of the RS trigger, at this time, the Q pin of the trigger U2 changes from high level to low level, the source S of the P-MOS tube Q4 changes from high level to low level, the gate of the P-MOS tube Q4 continues to maintain a low level state, the P-MOS tube Q4 changes to a turned-off state, the voltage across the resistor R1 changes to a low level state, the N-MOS tube Q3 is turned off, and the two ends of the primary side of the isolation transformer T2 become a non-triggered state.

[0101] The enabling control circuit is simple and low-cost, and can realize the operation of the secondary-side synchronous rectification N-MOS tube with the maximum conduction time in CCM mode, thereby improving efficiency and greatly improving the reliability of synchronous rectification control of the ACF converter in CCM.

[0102] Sixth embodiment

[0103] like Fig.12As shown, it is a circuit schematic diagram of the sixth embodiment of the present invention, the dotted box 1201 is the synchronous rectification control circuit of the present invention, including a P-MOS tube Q5, a capacitor C1, a resistor R2, a comparator U3 and an isolation transformer T2. In addition, the synchronous rectification control chip U1 also includes an enable signal pin SYN; the driving signal input to the gate of the P-MOS tube Q5 and the driving signal of the clamp tube Q2 are both GTH, the source of the P-MOS tube Q5 inputs the working voltage VDD, and the drain of the P-MOS tube Q5 is connected to the voltage One end of capacitor C1 and the other end of capacitor C1 are connected to one end of resistor R2 and the positive input end of comparator U3, the other end of resistor R2 is connected to the primary ground GND, the negative input end of comparator U3 is used to input a reference voltage signal Vref, the output end of comparator U3 is connected to the primary like-name end of isolation transformer T2, the primary unlike-name end of isolation transformer T2 is connected to the primary ground GND, the secondary unlike-name end of isolation transformer T2 is connected to the enable signal pin SYN, and the secondary like-name end of isolation transformer T2 is connected to the secondary ground signal Vo-.

[0104] The working principle of this embodiment is as follows:

[0105] After the falling edge signal of the clamp tube drive signal GTH arrives, the P-MOS tube Q5 is turned off, and the power supply voltage VDD will charge the capacitor C1 through the resistor R2. The voltage across the capacitor C1 rises from 0V to VDD, and the voltage across the resistor R2 drops from VDD to 0V. In the process of the voltage across the resistor R2 dropping from VDD to Vref, the positive voltage signal of the comparator U3 is higher than the negative voltage signal, and the output voltage signal of the comparator U3 is high. The isolation transformer T2 senses a positive pulse that the same-name end of the primary side is higher than the opposite-name end of the primary side. The positive pulse excitation signal is coupled to the secondary side through the isolation transformer. The coupled signal is also higher at the same-name end than at the opposite-name end. Since the same-name end of the secondary side of the isolation transformer is connected to Vo-, the opposite-name end of the secondary side of the isolation transformer receives the negative pulse excitation signal SYN. ​​This negative pulse excitation signal SYN is used as an enable control signal to enable and control the synchronous rectification IC and shut down the synchronous rectification drive, thereby avoiding the common phenomenon of the original secondary side. The change in the amplitude of the SYN signal can be achieved by changing the turns ratio of the isolation transformer T2.

[0106] like Fig.13 The control timing diagram of this embodiment is shown. When GTH changes from a high level to a low level, SYN senses a negative pulse excitation signal. The negative pulse excitation signal SYN is used as an enable control signal to enable the synchronous rectification control chip U1 and turn off the synchronous rectification drive, thereby avoiding the common phenomenon of the original secondary side. The enable control circuit is simple and low-cost. It can realize the operation of the secondary side synchronous rectification N-MOS tube with the maximum conduction time in CCM mode, thereby improving efficiency and greatly improving the reliability of the synchronous rectification control of the ACF converter in CCM.

[0107] The above are only preferred embodiments of the present invention. It should be pointed out that the above preferred embodiments should not be regarded as limiting the present invention. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the spirit and scope of the present invention. For example, the N-MOS tube in the above embodiment is changed to an NPN transistor, and the P-MOS tube in the above embodiment is changed to a PNP transistor; the two input ends of the comparator U1 are interchanged with the corresponding connection circuits, and then the phases of the isolation transformer windings connected to the output end of the comparator U1 are interchanged, etc. These improvements and modifications should also be regarded as the protection scope of the present invention. The embodiments will not be repeated here. The protection scope of the present invention shall be based on the scope defined by the claims.

Claims

1. A synchronous rectification control circuit, applied to an active clamp flyback converter, wherein the synchronous rectification control circuit comprises at least a synchronous rectification control chip U1; characterized in that: The synchronous rectification control circuit also includes a switch tube Q3, an isolation transformer T2, a resistor R2, a capacitor C3 and a resistor R3. The synchronous rectification control chip U1 includes an enable signal pin SYN. ​​The switch tube Q3 is the same type of switch tube as the clamp tube in the active clamp flyback converter. One end of the resistor R2 is used to input the working voltage VDD, and the other end of the resistor R2 is simultaneously connected to one end of the switch tube Q3 and one end of the capacitor C3. The control end of the switch tube Q3 is used to input a control signal synchronized with the clamp tube drive signal in the active clamp flyback converter. The other end of the switch tube Q3 is simultaneously connected to one end of the resistor R3, one end of the primary side of the isolation transformer T2 and the primary side ground GND. The other end of the capacitor C3 is simultaneously connected to the other end of the resistor R3 and the other end of the primary side of the isolation transformer T2. One end of the secondary side of the isolation transformer T2 is connected to the enable signal pin SYN, and the secondary side of the isolation transformer T2 is connected to the secondary side ground signal Vo-. The same-name end and the opposite-name end of the isolation transformer T2 are configured as follows: when one end of the primary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end, one end of the secondary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end; when one end of the primary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end, one end of the secondary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end.

2. The synchronous rectification control circuit according to claim 1, characterized in that: The applied active clamp flyback converter adopts trailing edge non-complementary control timing and operates in CCM mode.

3. The synchronous rectification control circuit according to claim 1 or 2, characterized in that: When the clamping tube in the active clamp flyback converter is an N-MOS tube, the switch tube Q3 is an N-MOS tube, the gate of the N-MOS tube is the control end of the switch tube Q3, the drain of the N-MOS tube is one end of the switch tube Q3, and the source of the N-MOS tube is the other end of the switch tube Q3; or when the clamping tube in the active clamp flyback converter is an N-MOS tube, the switch tube Q3 is an NPN transistor, the base of the NPN transistor is the control end of the switch tube Q3, the collector of the NPN transistor is one end of the switch tube Q3, and the emitter of the NPN transistor is the other end of the switch tube Q3.

4. The synchronous rectification control circuit according to claim 1 or 2, characterized in that: The synchronous rectification control circuit further comprises a diode D3, wherein the anode of the diode D3 is connected to the primary opposite-name terminal of the isolation transformer T2, and the cathode of the diode D3 is connected to the primary same-name terminal of the isolation transformer T2.

5. The synchronous rectification control circuit according to claim 1 or 2, characterized in that: The synchronous rectification control circuit further includes a capacitor C2, which is connected across the primary winding of the isolation transformer T2.

6. The synchronous rectification control circuit according to any one of claims 1 or 2, characterized in that: The synchronous rectification control circuit further includes a capacitor C1, which is connected across the secondary winding of the isolation transformer T2.

7. The synchronous rectification control circuit according to any one of claims 1 or 2, characterized in that: The synchronous rectification control circuit further includes a resistor R1, which is connected across two ends of the secondary winding of the isolation transformer T2.

8. The synchronous rectification control circuit according to any one of claims 1 or 2, characterized in that: The synchronous rectification control circuit further comprises a diode D1 and a diode D2. The diode D1 and the diode D2 are connected in reverse parallel and then connected across the secondary winding of the isolation transformer T2.

9. A synchronous rectification control circuit, applied to an active clamp flyback converter, the synchronous rectification control circuit at least comprising a synchronous rectification control chip U1; characterized in that: The synchronous rectification control circuit also includes an RS trigger U2, a switch tube Q4, a resistor R1 and an isolation transformer T2. The synchronous rectification control chip U1 includes an enable signal pin SYN. ​​The switch tube Q4 and the clamp tube in the active clamp flyback converter are different types of switch tubes. The S pin of the trigger U2 and the control end of the switch tube Q4 are both used to input a signal synchronized with the clamp tube drive signal in the active clamp flyback converter. The R pin of the trigger U2 is used to input a signal synchronized with the main tube drive signal in the active clamp flyback converter. The Q pin of the trigger U2 is connected to one end of the switch tube Q4, and the other end of the switch tube Q4 is connected to one end of the resistor R1 and one end of the primary side of the isolation transformer T2. The other end of the resistor R1 is connected to the other end of the primary side of the isolation transformer T2 and the primary side ground GND. One end of the secondary side of the isolation transformer T2 is connected to the enable signal pin SYN pin, and the other end of the secondary side of the isolation transformer T2 is connected to the secondary side ground signal Vo-. The same-name end and the opposite-name end of the isolation transformer T2 are configured as follows: when one end of the primary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end, one end of the secondary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end; when one end of the primary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end, one end of the secondary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end.

10. The synchronous rectification control circuit according to claim 9, characterized in that: The applied active clamp flyback converter adopts trailing edge non-complementary control timing and operates in CCM mode.

11. The synchronous rectification control circuit according to claim 9 or 10, characterized in that: When the clamping tube in the active clamp flyback converter is an N-MOS tube, the switch tube Q4 is a P-MOS tube, the gate of the P-MOS tube is the control end of the switch tube Q4, the source of the P-MOS tube is one end of the switch tube Q4, and the drain of the P-MOS tube is the other end of the switch tube Q4; or when the clamping tube in the active clamp flyback converter is an N-MOS tube, the switch tube Q4 is a PNP transistor, the base of the PNP transistor is the control end of the switch tube Q4, the emitter of the PNP transistor is one end of the switch tube Q4, and the collector of the PNP transistor is the other end of the switch tube Q4.

12. A synchronous rectification control circuit, applied to an active clamp flyback converter, the synchronous rectification control circuit at least comprising a synchronous rectification control chip U1; characterized in that: The synchronous rectification control circuit also includes an RS trigger U2, a switch tube Q4, a resistor R1, a switch tube Q3 and an isolation transformer T2. The synchronous rectification control chip U1 includes an enable signal pin SYN. ​​The switch tube Q4 and the clamp tube in the active clamp flyback converter are switch tubes of different types. The switch tube Q3 and the clamp tube in the active clamp flyback converter are switch tubes of the same type. The S pin of the trigger U2 and the control end of the switch tube Q4 are both used to input a signal synchronized with the clamp tube drive signal in the active clamp flyback converter. The R pin of the trigger U2 is used to input a signal synchronized with the active clamp flyback converter. The signal for synchronizing the driving signal in the source clamp flyback converter, the Q pin of the trigger U2 is connected to one end of the switch tube Q4, the other end of the switch tube Q4 is connected to one end of the resistor R1 and the control end of the switch tube Q3, the other end of the resistor R1 is connected to the primary ground GND, one end of the switch tube Q3 is connected to the primary ground GND, the other end of the switch tube Q3 is connected to one end of the primary side of the isolation transformer T2, the other end of the primary side of the isolation transformer T2 is used to input the working voltage VDD, one end of the secondary side of the isolation transformer T2 is connected to the enable signal pin SYN pin, and the other end of the secondary side of the isolation transformer T2 is connected to the secondary ground signal Vo-; The same-name end and the opposite-name end of the isolation transformer T2 are configured as follows: when one end of the primary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end, one end of the secondary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end; when one end of the primary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end, one end of the secondary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end.

13. The synchronous rectification control circuit according to claim 12, characterized in that: The applied active clamp flyback converter adopts trailing edge non-complementary control timing and operates in CCM mode.

14. The synchronous rectification control circuit according to claim 12 or 13, characterized in that: When the clamping tube in the active clamp flyback converter is an N-MOS tube, the switch tube Q3 is an N-MOS tube, and the switch tube Q4 is a P-MOS tube. For the switch tube Q3, the gate of the N-MOS tube is the control end of the switch tube Q3, the source of the N-MOS tube is one end of the switch tube Q3, and the drain of the N-MOS tube is the other end of the switch tube Q3. For the switch tube Q4, the gate of the P-MOS tube is the control end of the switch tube Q4, the source of the P-MOS tube is one end of the switch tube Q4, and the drain of the P-MOS tube is the other end of the switch tube Q4. Or when the clamping tube in the active clamp flyback converter is an N-MOS tube, the switch tube Q3 is an NPN transistor, and the switch tube Q4 is a PNP transistor. For the switch tube Q3, the base of the NPN transistor is the control end of the switch tube Q3, the emitter of the NPN transistor is one end of the switch tube Q3, and the collector of the NPN transistor is the other end of the switch tube Q3. For the switch tube Q4, the base of the PNP transistor is the control end of the switch tube Q4, the emitter of the PNP transistor is one end of the switch tube Q4, and the collector of the PNP transistor is the other end of the switch tube Q4.

15. A synchronous rectification control circuit, applied to an active clamp flyback converter, the synchronous rectification control circuit at least comprising a synchronous rectification control chip U1; characterized in that: The synchronous rectification control circuit further includes a switch tube Q5, a capacitor C1, a resistor R2, a comparator U3 and an isolation transformer T2. The synchronous rectification control chip U1 includes an enable signal pin SYN. ​​The switch tube Q5 and the clamp tube in the active clamp flyback converter are different types of switch tubes. The control end of the switch tube Q5 is used to input a signal synchronized with the drive signal of the clamp tube in the active clamp flyback converter. One end of the switch tube Q5 is used to input a working voltage VDD. The other end of the switch tube Q5 is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to one end of the resistor R2 and an input end of the comparator U3. The other end of the resistor R2 is connected to the primary ground GND. The other input end of the comparator U3 is used to input a reference voltage signal Vref. The output end of the comparator U3 is connected to one end of the primary side of the isolation transformer T2. The other end of the primary side of the isolation transformer T2 is connected to the primary ground GND. One end of the secondary side of the isolation transformer T2 is connected to the enable signal pin SYN. ​​The other end of the secondary side of the isolation transformer T2 is connected to the secondary ground signal Vo-. The same-name end and the opposite-name end of the isolation transformer T2 are configured as follows: when one end of the primary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end, one end of the secondary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end; when one end of the primary side of the isolation transformer T2 is the opposite-name end and the other end is the same-name end, one end of the secondary side of the isolation transformer T2 is the same-name end and the other end is the opposite-name end.

16. The synchronous rectification control circuit according to claim 15, characterized in that: The applied active clamp flyback converter adopts trailing edge non-complementary control timing and operates in CCM mode.

17. The synchronous rectification control circuit according to claim 15 or 16, characterized in that: When the clamping tube is an N-MOS tube, the switch tube Q5 is a P-MOS tube, the gate of the P-MOS tube is the control end of the switch tube Q5, the source of the P-MOS tube is one end of the switch tube Q5, and the drain of the P-MOS tube is the other end of the switch tube Q5; or the switch tube Q5 is a PNP transistor, the base of the PNP transistor is the control end of the switch tube Q5, the emitter of the PNP transistor is one end of the switch tube Q5, and the collector of the PNP transistor is the other end of the switch tube Q5.

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