Voltage Detection System, Battery Management System and Battery Management Chip

Abstract

The present disclosure provides a voltage detection system for detecting the voltage of the i-th battery in a battery pack formed by connecting N batteries in series, where i = 1 to N, including: an RC filtering unit, the input end of the RC filtering unit of the i-th battery is connected to the positive terminal of the i-th battery; a gating unit, having N gating branches, the input end of the i-th gating branch among the N gating branches is connected to the output end of the RC filtering unit of the i-th battery, and the i-th gating branch is composed of a series circuit of a gating switch and a first resistor, an operational amplifier unit, including a first input end and a second input end, the first input end is connected to the output end of the gating unit; and an analog-to-digital conversion unit, connected to the output end of the operational amplifier unit and converting the voltage from the operational amplifier unit into a digital signal. The present disclosure also provides a battery management system and a battery management chip.

Description

Technical Field

[0001] The present disclosure relates to a voltage detection system, a battery management system, and a battery management chip. Background Art

[0002] In a battery management system, it is necessary to measure the voltage of each battery cell. Usually, a selection circuit is used to select the battery cell to be measured, and then an analog-to-digital converter converts the collected voltage into a digital signal and provides it to a controller. The controller manages the battery according to the collected voltage signal, for example, can control the charge and discharge switch, etc.

[0003] For example, Chinese Patent CN101499671A provides a battery voltage conversion system. As shown in the drawings of this patent, however, in this patent, it cannot accurately detect the voltage of the battery. Especially when filtering the battery voltage, the filtering circuit will seriously interfere with the accuracy of the detected voltage value. Summary of the Invention

[0004] To solve one of the above technical problems, the present disclosure provides a voltage detection system, a battery management system, and a battery management chip.

[0005] According to one aspect of the present disclosure, a voltage detection system is used to detect the voltage of the i-th battery cell in a battery pack with N battery cells connected in series, where i = 1 to N, and includes:

[0006] An RC filtering unit, the input end of the RC filtering unit of the i-th battery cell is connected to the positive end of the i-th battery cell;

[0007] A selection unit, the selection unit has N selection branches, the input end of the i-th selection branch among the N selection branches is connected to the output end of the RC filtering unit of the i-th battery cell, and the i-th selection branch is composed of a series circuit of a selection switch and a first resistor.

[0008] An operational amplifier unit, the operational amplifier unit includes a first input end and a second input end, and the first input end is connected to the output end of the selection unit; and

[0009] An analog-to-digital conversion unit, the analog-to-digital conversion unit is connected to the output end of the operational amplifier unit and converts the voltage from the operational amplifier unit into a digital signal.

[0010] According to at least one embodiment of the present disclosure, a feedback circuit is connected between the output end of the operational amplifier unit and the first input end of the operational amplifier unit. The feedback circuit is a series circuit of a feedback switch and a feedback resistor, and the feedback switch is in a normally closed state.

[0011] According to at least one embodiment of the present disclosure, the feedback resistor is set in proportion to the resistance value of the first resistor, and the feedback switch is set in proportion to the on-resistance of the strobe switch.

[0012] According to at least one embodiment of the present disclosure, when 2≤i≤N, when the voltage detection system detects the battery voltage of the i-th battery, the positive terminal voltage and the negative terminal voltage of the i-th battery are measured and the battery voltage of the i-th battery is obtained based on the difference in the positive terminal voltage. When measuring the positive terminal voltage, the strobe switch in the strobe unit of the i-th battery is turned on, so as to measure the positive terminal voltage of the i-th battery. When measuring the negative terminal voltage, the strobe switch in the strobe unit of the (i - 1)-th battery is turned on, so as to measure the negative terminal voltage of the i-th battery.

[0013] According to at least one embodiment of the present disclosure, the feedback circuit is connected to the first input terminal of the operational amplifier unit, and the second input terminal of the operational amplifier unit is connected to a reference voltage.

[0014] According to at least one embodiment of the present disclosure, the operational amplifier unit includes a positive output terminal and a negative output terminal. A second feedback circuit is also connected between the output terminal of the operational amplifier unit and the second input terminal of the operational amplifier unit. The second feedback circuit is a series circuit of a second feedback switch and a second feedback resistor. The second feedback resistor is set in proportion to the resistance value of the first resistor, and the second feedback switch is set in proportion to the on-resistance of the strobe switch.

[0015] According to at least one embodiment of the present disclosure, when detecting the battery voltage of the i-th battery, the strobe switch of the strobe unit of the i-th battery and the strobe switch of the strobe unit of the (i - 1)-th battery are turned on, so as to provide the battery voltage of the i-th battery and the battery voltage of the (i - 1)-th battery to the first input terminal and the second input terminal of the operational amplifier unit.

[0016] According to at least one embodiment of the present disclosure, the operational amplifier unit includes a positive output terminal and a negative output terminal. A first feedback circuit is connected between the negative output terminal of the operational amplifier unit and the first input terminal of the operational amplifier unit. The first feedback circuit is a series circuit of a first feedback switch and a first feedback resistor. A second feedback circuit is also connected between the positive output terminal of the operational amplifier unit and the second input terminal of the operational amplifier unit. The second feedback circuit is a series circuit of a second feedback switch and a second feedback resistor. The second feedback resistor is set in proportion to the resistance value of the first resistor, and the second feedback switch is set in proportion to the on-resistance of the strobe switch.

[0017] The connection point between the second feedback circuit and the second input terminal of the operational amplifier unit is grounded through an adjustable ground resistor. When detecting the battery voltage of the i-th battery cell, the resistance value of the adjustable ground resistor is equal to the resistance value of the first resistor in the i-th selected branch.

[0018] According to at least one embodiment of the present disclosure, the operational amplifier unit includes a first comparator, a second comparator, a first operational amplifier, and first to seventh resistors. When measuring the battery voltage of the i-th battery cell, the positive input terminal of the first comparator is connected to the detected voltage of the positive terminal of the i-th battery cell, and the positive input terminal of the second comparator is connected to the detected voltage of the positive terminal of the (i - 1)-th battery cell.

[0019] The output terminal of the first comparator is connected to the positive output terminal of the first operational amplifier through a series circuit of a first resistor and a second resistor, and the negative input terminal of the first operational amplifier is connected to the connection node of the first resistor and the second resistor.

[0020] The output terminal of the second comparator is connected to the negative output terminal of the first operational amplifier through a series circuit of a third resistor and a fourth resistor, and the positive input terminal of the first operational amplifier is connected to the connection node of the third resistor and the fourth resistor.

[0021] The output terminal of the first comparator and the output terminal of the second comparator are connected through a series circuit of a fifth resistor, a sixth resistor, and a seventh resistor, and the negative input terminal of the first comparator is connected to the connection node of the fifth resistor and the sixth resistor, and the negative input terminal of the second comparator is connected to the connection node of the sixth resistor and the seventh resistor.

[0022] According to at least one embodiment of the present disclosure, it further includes a current compensation module. When obtaining the positive terminal voltage of the i-th battery cell, the current compensation module provides a compensation current to the output terminal of the RC filtering unit of the i-th battery cell, and the current value of the compensation current is the same as the current value of the current flowing through the filtering resistor of the RC filtering unit.

[0023] According to at least one embodiment of the present disclosure, it further includes a current compensation module.

[0024] When obtaining the positive terminal voltage of the i-th battery cell, the current compensation module provides a compensation current to the output terminal of the RC filtering unit of the i-th battery cell, and the current value of the compensation current is the same as the current value of the current flowing through the filtering resistor of the RC filtering unit;

[0025] When obtaining the positive terminal voltage of the (i - 1)-th battery cell, the current compensation module provides a compensation current to the output terminal of the RC filtering unit of the (i - 1)-th battery cell, and the current value of this compensation current is the same as the current value of the current flowing through the filtering resistor of the RC filtering unit.

[0026] According to at least one embodiment of the present disclosure, one end of a first compensation switch is connected to the output terminal of the RC filtering unit of the first-section battery, and one end of a series circuit composed of a first compensation resistor and a second compensation switch is connected thereto. The other end of the first compensation switch serves as a voltage output terminal, and the other end of the series circuit composed of the first compensation resistor and the second compensation switch is grounded.

[0027] When all the gating switches are turned off and the first compensation switch and the second compensation switch are turned on, a first measured voltage is obtained through the voltage output terminal.

[0028] When all the gating switches are turned off, the first compensation switch is turned on, and the second compensation switch is turned off, a second measured voltage is obtained through the voltage output terminal.

[0029] The analog-to-digital conversion unit calculates an accurate battery voltage based on the output voltage of the operational amplifier unit and the ratio of the first measured voltage to the second measured voltage.

[0030] According to at least one embodiment of the present disclosure, the first compensation resistor and the first resistor are of the same type, and the first compensation switch and the second compensation switch are of the same type as the gating switches.

[0031] According to at least one embodiment of the present disclosure, a current compensation circuit is further included. The current compensation circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a compensation operational amplifier. The sources of the first PMOS transistor and the second PMOS transistor are connected to the battery voltage of the i-th section battery. The gates of the first PMOS transistor and the second PMOS transistor are interconnected and connected to the drain of the first PMOS transistor. The drain of the second PMOS transistor serves as a compensation current to be provided to the output terminal of the RC filtering unit of the i-th section battery. The drain of the first PMOS transistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is connected to the source of the first NMOS transistor and grounded. The gates of the second NMOS transistor and the first NMOS transistor are connected to the output terminal of the compensation operational amplifier. The drain of the first NMOS transistor is connected to the source of the third NMOS transistor. The drain of the first NMOS transistor is connected to one input terminal of the compensation operational amplifier. The other input terminal of the compensation operational amplifier is connected to the output terminal of the operational amplifier unit. The drain of the third NMOS transistor is connected to the reference voltage via a resistor.

[0032] According to at least one embodiment of the present disclosure, a current compensation circuit is further included. The current compensation circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0033] The sources of the first PMOS transistor and the second PMOS transistor are interconnected and connected to the system voltage, the gates are connected to the bias voltage signal, the drain of the first PMOS transistor is connected to one end of the feedback resistor and to the drain of the first NMOS transistor, the source of the first NMOS transistor is grounded, the output terminal of the operational amplifier unit is connected to the gates of the first NMOS transistor and the second NMOS transistor, the source of the second NMOS transistor is grounded, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and is connected to the drain of the third PMOS transistor, the third PMOS transistor is connected to the gates of the third PMOS transistor and the fourth PMOS transistor and is connected to the drain of the third PMOS transistor, the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the voltage of the i-th battery cell, and the drain terminal of the fourth PMOS transistor provides a compensation current to be supplied to the output terminal of the RC filter unit of the i-th battery cell.

[0034] According to at least one embodiment of the present disclosure, it further includes a current compensation circuit, and the current compensation circuit includes:

[0035] A first PMOS transistor and a second PMOS transistor, and a first operational amplifier, wherein the sources of the first PMOS transistor and the second PMOS transistor are connected to the voltage VB of the i-th battery cell i , the gates of the first PMOS transistor and the second PMOS transistor are connected to the output of the first operational amplifier, one input terminal of the first operational amplifier is connected to the voltage of the negative input terminal of the operational amplifier unit, the other input terminal of the first operational amplifier is connected to the drain of the first PMOS transistor, and is connected to the positive terminal output voltage of the operational amplifier unit through a series circuit of a resistor and a switch, and the drain of the second PMOS transistor provides a first compensation current to be supplied to the output terminal of the RC filter unit of the i-th battery cell;

[0036] A third PMOS transistor and a fourth PMOS transistor, and a second operational amplifier, wherein the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the voltage VB of the i-th battery cell i , the gates of the third PMOS transistor and the fourth PMOS transistor are connected to the output of the second operational amplifier, one input terminal of the second operational amplifier is connected to the voltage of the positive input terminal of the operational amplifier unit, the other input terminal of the second operational amplifier is connected to the drain of the third PMOS transistor, and is connected to the negative terminal output voltage of the operational amplifier unit through a series circuit of a resistor and a switch, and the drain of the fourth PMOS transistor provides a second compensation current to be supplied to the output terminal of the RC filter unit of the (i - 1)-th battery cell.

[0037] According to at least one embodiment of the present disclosure, it further includes a current compensation circuit, and the current compensation circuit includes:

[0038] The first PMOS transistor, the second PMOS transistor, and the first operational amplifier. The sources of the first PMOS transistor and the second PMOS transistor are connected to the voltage VB of the i-th battery cell. i , the gates of the first PMOS transistor and the second PMOS transistor are connected to the output terminal of the first operational amplifier. The drain of the first PMOS transistor is connected to the positive output terminal of the operational amplifier unit via a switch and a resistor series circuit. The drain of the first PMOS transistor is connected to another input terminal of the first operational amplifier. One input terminal of the first operational amplifier is connected to one input terminal of the operational amplifier unit. The drain of the second PMOS transistor provides a first compensation current to be supplied to the output terminal of the RC filtering unit of the i-th battery cell;

[0039] The third PMOS transistor and the fourth PMOS transistor, and the second operational amplifier. The sources of the third PMOS transistor and the fourth PMOS transistor are connected to the voltage VB of the i-th battery cell. i , the gates of the third PMOS transistor and the fourth PMOS transistor are connected to the output of the second operational amplifier. One input terminal of the second operational amplifier is connected to the positive input terminal voltage of the operational amplifier unit. The other input terminal of the second operational amplifier is connected to the drain of the third PMOS transistor and is connected to the negative output voltage of the operational amplifier unit via a resistor and a switch series circuit. The drain of the fourth PMOS transistor provides a second compensation current to be supplied to the output terminal of the RC filtering unit of the (i - 1)-th battery cell.

[0040] According to at least one embodiment of the present disclosure, it further includes a current compensation circuit. The current compensation circuit is integrated into the operational amplifier unit. The integrated operational amplifier unit includes: a first amplifier, a second amplifier, and a third amplifier, where:

[0041] The two input terminals of the first amplifier are the first input terminal and the second input terminal of the operational amplifier unit, and the two output terminals of the first amplifier are respectively connected to the two input terminals of the second amplifier and the third amplifier. The positive output terminal of the second amplifier is connected to the gates of the first PMOS transistor and the second PMOS transistor, and the sources of the first PMOS transistor and the second PMOS transistor are connected to the system voltage. The negative output terminal of the second amplifier is connected to the gates of the first NMOS transistor and the second NMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are grounded. The third PMOS transistor and the fourth PMOS transistor form a current mirror circuit, wherein the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the voltage of the i-th battery. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and is connected to the drain of the third PMOS transistor. The drain of the third PMOS transistor is connected to the connection point of the second PMOS transistor and the second NMOS transistor. The drain of the fourth PMOS transistor provides a first compensation current to the output terminal of the RC filtering unit of the i-th battery;

[0042] The positive output terminal of the third amplifier is connected to the gates of the fifth PMOS transistor and the sixth PMOS transistor. The sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to the system voltage. The negative output terminal of the third amplifier is connected to the gates of the third NMOS transistor and the fourth NMOS transistor. The drain of the fifth PMOS transistor is connected to the drain of the third NMOS transistor, and the drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor. The sources of the third NMOS transistor and the fourth NMOS transistor are grounded. The seventh PMOS transistor and the eighth PMOS transistor form a current mirror circuit, wherein the sources of the seventh PMOS transistor and the eighth PMOS transistor are connected to the voltage of the i-th battery. The gates of the seventh PMOS transistor and the eighth PMOS transistor are connected and are connected to the drain of the seventh PMOS transistor. The drain of the seventh PMOS transistor is connected to the connection point of the sixth PMOS transistor and the fourth NMOS transistor. The drain of the eighth PMOS transistor provides a second compensation current to the output terminal of the RC filtering unit of the (i - 1)-th battery.

[0043] According to at least one embodiment of the present disclosure, the first PMOS transistor and the second PMOS transistor, and the fifth PMOS transistor and the sixth PMOS transistor are respectively composed of one or more PMOS transistors connected in series. The first NMOS transistor and the second NMOS transistor, and the third NMOS transistor and the fourth NMOS transistor are respectively composed of one or more NMOS transistors connected in series.

[0044] According to another aspect of the present disclosure, a battery management system includes the voltage detection system as described above.

[0045] According to at least one embodiment of the present disclosure, it further includes a control logic module and a switch driving module. The control logic module receives the digital signal converted by the analog-to-digital conversion module, and provides a control signal to the switch driving module at least based on the digital signal. The switch driving module controls the conduction of the charging switch and the discharging switch based on this control signal.

[0046] According to yet another aspect of the present disclosure, a battery management chip is characterized in that it integrates the voltage detection system as described above.

[0047] According to yet another aspect of the present disclosure, a battery management chip integrates the battery management system as described above. Description of the Drawings

[0048] The drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, are used to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are included in this specification and form a part of this specification.

[0049] Figure 1 A diagram of a battery management system according to an embodiment of the present disclosure is shown.

[0050] Figure 2 A schematic diagram of voltage detection according to an embodiment of the present disclosure is shown.

[0051] Figure 3 A schematic diagram of current compensation according to an embodiment of the present disclosure is shown.

[0052] Figure 4 A schematic diagram of current compensation according to an embodiment of the present disclosure is shown.

[0053] Figure 5 A schematic diagram of current compensation according to an embodiment of the present disclosure is shown.

[0054] Figure 6 A schematic diagram of digital compensation according to an embodiment of the present disclosure is shown.

[0055] Figure 7 A schematic diagram of voltage detection according to an embodiment of the present disclosure is shown.

[0056] Figure 8 A schematic diagram of current compensation according to an embodiment of the present disclosure is shown.

[0057] Figure 9Shows a schematic diagram of current compensation according to an embodiment of the present disclosure.

[0058] Figure 10 Shows a schematic diagram of voltage detection according to an embodiment of the present disclosure.

[0059] Figure 11 Shows a schematic diagram of current compensation according to an embodiment of the present disclosure.

[0060] Figure 12 Shows a schematic diagram of current compensation according to an embodiment of the present disclosure.

[0061] Figure 13 Shows a schematic diagram of voltage detection and current compensation according to an embodiment of the present disclosure.

[0062] Figure 14 Shows a schematic diagram of voltage detection according to an embodiment of the present disclosure. Detailed implementation manners

[0063] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific implementation manners described herein are only used to explain the relevant content and do not limit the present disclosure. Additionally, it should be noted that for the convenience of description, only the parts related to the present disclosure are shown in the drawings.

[0064] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the drawings and embodiments.

[0065] Unless otherwise specified, the exemplary embodiments / Examples shown will be understood to provide exemplary features of various details of some ways in which the technical concept of the present disclosure can be implemented in practice. Therefore, unless otherwise specified, without departing from the technical concept of the present disclosure, the features of various embodiments / Examples can be additionally combined, separated, interchanged, and / or rearranged.

[0066] In the drawings, the use of hatching and / or shading is generally used to make the boundaries between adjacent components clear. Thus, unless otherwise stated, the presence or absence of hatching or shading does not convey or imply any preference or requirement for the specific material, material properties, dimensions, proportions, commonality between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be exaggerated. When exemplary embodiments can be implemented differently, the specific process sequences may be performed in a different order than described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals denote the same components.

[0067] When a component is referred to as being "on" or "above" another component, "connected to" or "coupled to" another component, the component can be directly on the other component, directly connected to or directly coupled to the other component, or there may be intervening components. However, when a component is referred to as being "directly on" another component, "directly connected to" or "directly coupled to" another component, there are no intervening components. For this reason, the term "connected" can refer to a physical connection, an electrical connection, etc., and can have or not have intervening components.

[0068] For descriptive purposes, the present disclosure may use spatial relative terms such as "under", "below", "beneath", "lower", "above", "upper", "on", "over", "higher", and "side (e.g., as in "sidewall")" to describe the relationship of one component to another (other) component as shown in the drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawing is flipped, a component described as being "under" or "beneath" another component or feature will then be positioned "above" the other component or feature. Thus, the exemplary term "under" can encompass both the "above" and "below" orientations. In addition, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and accordingly, the spatial relative descriptors used herein are to be interpreted.

[0069] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. Further, when the terms "comprises" and / or "comprising" and variations thereof are used in this specification, it is specified that the stated features, integers, steps, operations, components, parts, and / or groups thereof exist, but do not preclude the existence or addition of one or more other features, integers, steps, operations, components, parts, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and thus they are used to explain the inherent deviations of measured, calculated, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0070] Figure 1 A schematic diagram of a battery management system according to an embodiment of the present disclosure is shown.

[0071] As Figure 1 shown, the battery management system 100 can be used to perform high-precision voltage acquisition and management on a battery. The battery can be a lithium battery pack, including multiple lithium batteries connected in series. Here, n or N below is an integer greater than 2.

[0072] The battery management system 100 may include a gating detection module 110, a voltage amplification module 120, an analog-to-digital conversion module 130, a control logic module 140, a switch driving module 150, a discharge switch MD, and a charging switch MC.

[0073] The gating detection module 110 gates and detects the voltage of each battery by gating the voltage of each battery B1~B n . Among them, the gating detection module 110 can be used to detect the filtered battery voltage, and the filtering can be achieved by an RC filter composed of filtering resistors R f1 ~R fn and filtering capacitors C1~C n .

[0074] The voltage amplification module 120 can amplify the voltage of each battery from the gating detection module 110.

[0075] The analog-to-digital conversion module 130 is used to perform analog-to-digital conversion on the voltage of each battery from the voltage amplification module 120, and provide the converted digital signal to the control logic module 140.

[0076] The control logic module 140 can provide a control signal to the switch driving module 150 at least according to the detected battery voltage, so as to control the discharge switch MD and the charging switch MC through the switch driving module 150, thereby realizing the charge and discharge control of the battery. When the battery is charged, it is charged through an external charger. When discharging, the battery management system is connected to an external load to discharge.

[0077] In addition, the battery management system 100 may further include a battery converter 160. The battery converter 160 is used to convert the highest voltage VCC of the battery, such as, into various different required voltages VDD. VDD can be, for example, one or more of 1.8V, 3.3V, or 5V, etc.

[0078] First Embodiment of Voltage Acquisition

[0079] Figure 2 A specific example of the strobe detection module 110 and the voltage discharge module according to an embodiment of the present disclosure is shown.

[0080] Among them, the RC filter is connected to the positive terminal of each battery connected in series, and has the function of filtering the voltage of each battery. And the input of the RC filter is connected to the PIN i terminal (i = 1~n), and the other end of the PIN i terminal is connected to one end of the first resistors R1~R n The first resistors R1~R n+ are connected to the first field effect transistors SW1~SW n wherein the conduction and disconnection of the first field effect transistors SW1~SW n are used to realize the gating of the i-th battery in the resistor, so as to detect the voltage of the i-th battery.

[0081] The first field effect transistors SW1~SW n are all connected to the first input terminal of the first operational amplifier OP1. The second input terminal of the first operational amplifier OP1 is connected to the reference voltage V R . And the output terminal of the first operational amplifier OP1 is connected to the analog-to-digital conversion module 130.

[0082] In addition, a second resistor R s and a second field effect transistor SW0 are also connected between the output terminal and the input terminal of the first operational amplifier OP1. The gate of the second field effect transistor SW0 is connected to the control signal G0, and the control signal G0 maintains a high level to keep the second field effect transistor SW0 always on.

[0083] In Figure 2 the shown schematic diagram, the output voltage value (the voltage detection value of each battery) V of the first operational amplifier OP1S =V R -(VB i -V R )*(R sw0 +R S ) / (R fi +R i +R swi ), where VB i is the voltage value of the i-th battery cell, R sw0 is the on-resistance value of the second field-effect transistor SW0, R s is the resistance value of the second resistor R s of, R fi is the resistance value of the i-th filter resistor in the RC filter, R i is the resistance value of the i-th resistor among the first resistors R1 to R n of, R swi is the on-resistance value of the i-th field-effect transistor among the first field-effect transistors SW1 to SW n .

[0084] This formula can be transformed into: VB i =V R +(V R -V S )*(R fi +R i +R swi ) / (R sw0 + R S ). Where V R is the known reference voltage value. V S is the output voltage of the first operational amplifier OP1, which can be accurately detected by the analog-to-digital conversion module 130. R fi is the resistance value of the filter resistor in the RC filter, which is also known. R i is the resistance value of the first resistors R1 to R n of, which is preset. R sw0 is the on-resistance value of the second field-effect transistor SW0, R swi is the on-resistance value of the i-th field-effect transistor among the first field-effect transistors SW1 to SW n .

[0085] Among them, the resistance values of the first resistor and the second resistor are set in equal proportion. For example, R1 = 2*R s , R2 = 2*R1,..., R n-1 = (n - 1)*R1, R n = n*R1.

[0086] In addition, the on-resistances of the second field-effect transistor and the first field-effect transistor are also set in equal proportion. For example, Rsw1 = 2 * R sw0 、R sw2 = 2 * R sw1 、……、R swn-1 = (n - 1) * R sw1 、R swn = n * R sw1 。 Here, the equal - ratio setting of the on - resistance of the second field - effect transistor and the first field - effect transistor can be achieved by setting the size of the switch in equal ratio.

[0087] In this embodiment, the key point is the addition of the second field - effect transistor SW0. In this way, through the equal - ratio setting of the on - resistance of the second field - effect transistor SW0 and the first field - effect transistors SW1 ~ SW n the voltage gain error brought by the first field - effect transistors SW1 ~ SW can be offset by the second field - effect transistor SW0. Because in the above formula, each parameter is a pre - set or known parameter, the node voltage of each battery can be measured. For example, for the i - th battery, its positive - terminal voltage VB n and VB i and VB i-1 can both be accurately measured, and the voltage of the i - th battery is equal to VB i - VB i-1 . By analogy, the voltages of each battery can be measured.

[0088] In Figure 2 the shown schematic diagram, during voltage acquisition, due to the existence of R fi in the RC filter, a voltage acquisition error will occur, that is, the voltage error generated by the sampling current I s flowing through the external filter resistor R f because I s = I fi . That is to say, I fi flowing through the resistor R fi causes the voltage error V fi = I fi * R fi .

[0089] According to the present disclosure, two methods are proposed to solve this problem. The first method is to adopt the dynamic current compensation method. The second method is to use the analog - to - digital conversion module 130 for measurement, so as to perform gain compensation in the digital circuit.

[0090] Figure 3 shows the dynamic current compensation method according to an embodiment of the present disclosure. As Figure 1 shown, the battery management system 100 may further include a current compensation module 170.

[0091] Figure 3 FIG. 1 is a schematic diagram showing the current compensation module 170, which may include a compensation current generating part to generate a compensation current I comp , and the corresponding PIN is switched by a plurality of parallel switches S31~S3n-1 connected to the compensation current generating part. n-1 The terminal provides compensation current.

[0092] exist Figure 3 In the embodiment, current compensation can be performed on each battery of the battery pack. The current compensation module 170 can be based on the voltage VB of each battery. i The current compensation module 170 receives the voltage V1 of the first battery and generates a compensation current I according to the voltage V1. comp , and through the switch S 31 , provided to the PIN1 terminal, for the n-1th battery, the current compensation module 170 receives the voltage V of the nth battery n-1 The current compensation module 170 is based on the voltage V n-1 Generate compensation current I comp , and through the switch S 3n-1 , provided to PIN n-1 For other battery cells, the principle is the same and will not be described here.

[0093] Dynamic current compensation can eliminate the current flowing through the filter resistor R of the RC filter. fi The current I fi , that is to say, it can make I fi =0, so V fi =I fi *R fi =0.

[0094] Figure 4 FIG. 1 shows a circuit diagram of a current compensation module 170 according to an embodiment of the present disclosure.

[0095] like Figure 4 As shown, the current compensation module includes a first PMOS transistor MP41, a second PMOS transistor MP42, a first NMOS transistor MN41, a second NMOS transistor MN42, a third NMOS transistor MN43, a first resistor R41 and a second operational amplifier OP2.

[0096] The sources of the first PMOS transistor MP41 and the second PMOS transistor MP42 are connected to the voltage VB of the i-th battery. i, the gates of the sources of the first PMOS transistor MP41 and the second PMOS transistor MP42 are connected, and the drain of the second PMOS transistor MP42 provides a compensation current I comp . The gate and drain of the first PMOS transistor MP41 are connected to each other, and the drain of the first PMOS transistor MP41 is connected to the drain of the second NMOS transistor MN42. The drains of the first NMOS transistor MN41 and the second NMOS transistor MN42 are connected and grounded. The gates of the first NMOS transistor MN41 and the second NMOS transistor MN42 are connected to the output terminal of the first operational amplifier OP1. One input terminal (negative input terminal) of the second operational amplifier OP2 is connected to the output voltage V of the first amplifier OP1 s . The other input terminal (positive input terminal) of the first amplifier OP1 is connected to the drain of the first NMOS transistor MN41 and the source of the third NMOS transistor MN43. The gate of the third NMOS transistor MN43 is connected to the control signal G cmp , and its drain is connected to the reference voltage V through the first resistor R41 R .

[0097] As Figure 4 shown, the mirror circuit composed of the PMOS transistors MP41 and MP42 receives the voltage VB of the i-th battery i . In addition, the circuit composed of the NMOS transistors MN41, MN42, MN43 and the second operational amplifier OP2 can be used to enable the mirror circuit to generate a compensation current I based on the voltage VB i . Wherein one input terminal of the second operational amplifier OP2 is connected to the output voltage V of the first amplifier OP1 comp , and the output terminal is used to control the on and off of the NMOS transistors MN41 and MN42. The NMOS transistor MN43 is turned on and off through the control signal G s , and is connected to the reference voltage V through the resistor R41 cmp . R .

[0098] In this way, through the circuit as Figure 4 shown, a compensation current I can be generated based on the voltage VB i etc., and then through comp the switch SW shown in Figure 3 ~SW 31 ~SW 3n-1 the supplementary current is provided to the PIN i terminal, thereby eliminating the error caused by the filtering resistor R of the RC filter fi .

[0099] Figure 5Shows a current compensation method according to another embodiment of the present disclosure.

[0100] In Figure 5 shows the compensation method of a battery B i The compensation methods of other batteries are the same as that of this battery and will not be elaborated here.

[0101] The current compensation module may include a first PMOS transistor MP51, a second PMOS transistor MP52, a third PMOS transistor MP53, a fourth PMOS transistor MP54, a first NMOS transistor MN51, a second NMOS transistor MN52, and a first comparison amplifier A1 (first operational amplifier).

[0102] The sources of the first PMOS transistor MP51 and the second PMOS transistor MP52 are interconnected and connected to the system voltage VDD, and the gates are connected to the bias voltage signal V BIAS , the drain of the first PMOS transistor MP51 is connected to one end of the second resistor R s and connected to the drain of the first NMOS transistor MN51. The source of the first NMOS transistor MN51 is grounded. The first comparison amplifier A1 is connected to the gates of the first NMOS transistor MN51 and the second NMOS transistor MN52. The source of the second NMOS transistor MN52 is grounded. The drain of the second PMOS transistor MP52 is connected to the drain of the second NMOS transistor MN52 and connected to the drain of the third PMOS transistor MP53. The third PMOS transistor MP53 is connected to the gate of the fourth PMOS transistor MP54 and connected to the drain of the third PMOS transistor MP53. The sources of the third PMOS transistor MP53 and the fourth PMOS transistor MP54 are connected to the voltage VB i of the i-th battery. The drain terminal of the fourth PMOS transistor MP54 provides a compensation current I comp .

[0103] As Figure 5 shown, the circuit may include a comparison amplifier A1. The two input terminals of the comparison amplifier A1 are respectively connected to the voltages V F and V R . The output terminal of the comparison amplifier A1 is connected to the gates of the two NMOS transistors MN51 and MN52 to control their conduction and disconnection. In addition, the gates of the PMOS transistors MP51 and MP52 are controlled to conduct and disconnect through the bias voltage signal V BIAS , and the sources are connected to the system voltage VDD. The mirror circuit composed of the PMOS transistors MP53 and MP54 generates a compensation current I i based on VB comp .

[0104] The generated compensation current I comp is provided to the corresponding PIN terminal through Figure 3 the gating of the switches S 31 ~S 3n-1 to eliminate the error caused by the filtering resistor R of the RC filter i in the RC filter. fi

[0105] Figure 6 Fig. shows a method of performing measurement using the analog-to-digital conversion module 130 to perform gain compensation in the digital circuit.

[0106] In Figure 6 the example shown, the battery voltage VB of B1 is used as an example for measurement. For the measurement of the battery voltage of other cells, the principle is the same and will not be elaborated here. i Figure 6 On the basis of Figure 2 current compensation is added. For the same parts, reference can be made to Figure 2 the description of Figure 2 .

[0107] The resistor R t and the resistors R1~R n are of the same type of resistor. The NMOS transistors SW t0 and SW t1 and SW0~SW n are of the same type of switch. And the NMOS transistors SW t1 and SW t2 can be composed of PMOS transistors, and can also be formed by connecting multiple NMOS transistors or PMOS transistors in series. The NMOS transistors SW t0 and SW t1 are respectively connected to the PIN1 terminal. And as shown in Figure 6 Fig., a resistor R t0 is connected in the branch of the transistor SW t .

[0108] Before the circuit starts to collect the battery voltage, the ratio between R f1 and (Rt + R SWt0 ) needs to be obtained, so as to compensate for the voltage gain error caused by the filtering resistor R fi in the digital circuit.

[0109] First, make the control signals G1~G n be at low level, so that the switches SW1~SW n are disconnected, and G t1 and G t0 are at high level, so that the switches SW t0 and SW​​t1 Conduct. At this time, the voltage V can be measured t11 =VB1*R f1 / (R f1 +R t +R swt0 ), where R swt0 is the on-resistance of the switch SW t0 . In this way, the voltage V t11 is accurately sampled and input into the analog-to-digital conversion module 130. The analog-to-digital conversion module 130 outputs a binary conversion code D Vt11 based on this voltage, which can be denoted as d1.

[0110] Then, make the control signals G1~G n be at a low level, so that the switches SW1~SW n are turned off, and G t1 is at a high level, while G t0 is at a low level, so that the switch SW t0 is turned off and the switch SW t1 is turned on. The voltage V t12 =VB1 (because the analog-to-digital conversion module uses a capacitive sampling method, so there is no current flowing through the filter resistor R f1 ). In this way, the voltage V t12 is accurately sampled and input into the analog-to-digital conversion module 130. The analog-to-digital conversion module 130 outputs a binary conversion code D Vt12 based on this voltage, which can be denoted as d2.

[0111] In this way, V t11 / V t12 =d1 / d2=[VB1*R f1 / (R f1 +R t +R SWt0 )] / VB1.

[0112] After conversion, we get: R f1 / (R f1 +R t +R SWt0 )=d1 / d2.

[0113] By solving, we get: R f1 =(R t +R SWt0 )*( d1 / d2) / (1- d1 / d2).

[0114] Because the resistor R t and the resistors R1~R n are of the same type, and the NMOS transistors SW t0 and SW t1 and SW0~SWn are switches of the same type. That is, R t = R1, R SWt0 = R SW0 = 0.5 * R SW1 , where R SW1 is the on - resistance of switch SW1.

[0115] Thus, R f1 can be transformed into R f1 =(R1 + R SWt0 ) * (d1 / d2) / (1 - d1 / d2).

[0116] Also, because VB1 = V R +(V R - V S ) * (R f1 + R1 + R sw1 ) / (R sw0 + R S ), where R sw1 is the on - resistance of switch SW1, and R sw0 is the on - resistance of switch SW0.

[0117] Substitute the transformed R f1 into the above VB1, and we get:

[0118] VB1 = V R +(V R - V S ) * ((R1 + R sw1 ) * (d1 / d2) / (1 - d1 / d2)+ R1 + R sw1 ) / (R sw0 + R S ).

[0119] Since R SW0 = 0.5 * R SW1 , R s = 0.5 * R1,

[0120] Then the above formula can be expressed as:

[0121] VB1 = V R +(V R - V S ) * ((R1 + R sw1 ) * (d1 / d2) / (1 - d1 / d2)+ R1 + R sw1 ) / 0.5(R sw1 + R1).

[0122] After simplification, we can get:

[0123] VB1 = VR +(V R -V S )*2*(1 + 1)*(d1 / d2) / (1 - d1 / d2).

[0124] It should be noted that for the above three VB1 formulas, when it is the voltage VB of the i-th battery cell i , they are as follows in sequence:

[0125] VB1 = V R +(V R -V S )*((R1 + R sw1 )*(d1 / d2) / (1 - d1 / d2)+n*R1 + n*R sw1 ) / (R sw0 + R S ),

[0126] VB1 = V R +(V R -V S )*((R1 + R sw1 )*(d1 / d2) / (1 - d1 / d2)+n*R1 + n*R sw1 ) / 0.5(R sw1 + R1)

[0127] VB1 = V R +(V R -V S )*2*(1 + n)*(d1 / d2) / (1 - d1 / d2).

[0128] where n is the i-th battery cell.

[0129] From the formula VB1 = V R +(V R -V S )*2*(1 + n)*(d1 / d2) / (1 - d1 / d2), it can be seen that the influence of the filter resistor R f1 on the detected battery voltage VB1 is completely eliminated, and thus the gain error brought by the filter resistor R f1 is eliminated. That is to say, the voltage error brought by the filter resistor R f1 can be measured by (d1 / d2) / (1 - d1 / d2).

[0130] Second Embodiment of Voltage Acquisition

[0131] Figure 7 shows a voltage acquisition method according to a second embodiment of the present disclosure, wherein, by switches SWP1~SWP n and switches SWN1~SWNn constitute the gating detection module 110.

[0132] Switches SWP1 to SWP n are respectively connected to PIN1 to PIN n at one end, and the other ends of switches SWP1 to SWP n are connected to each other. Switches SWN1 to SWN n are respectively connected to PIN1 to PIN n at one end, and the other ends of switches SWN1 to SWN n are connected to each other. The interconnected end of switches SWP1 to SWP n is connected to the positive end of the battery pack voltage, and the interconnected end of switches SWN1 to SWN n is connected to the negative end of the battery pack voltage.

[0133] By switching switches SWP1 to SWP n and SWN1 to SWN n , for example, when measuring the battery voltage of the i-th battery, the gating switch of the i-th battery is turned on and the gating switch of the (i - 1)-th battery is turned on.

[0134] Two outputs of the gating detection module 110 are respectively connected to two input terminals of the operational amplifier OP7 (corresponding voltages are V FN and V FP ), and feedback loops composed of switches and resistors are respectively connected between the two input terminals of the operational amplifier OP7 and its positive and negative output terminals (V OP and V ON respectively).

[0135] Among them, switches SWP0 and SWN0 are respectively set in proportion to the on-resistances of switches SWP1 to SWP n and SWN1 to SWN n , and resistors RP S and RN S are respectively set in proportion to resistors RP and RN. The principle can refer to the above description, for example, switches SWP0 and SWN0 are kept in a normally on state, etc.

[0136] The positive and negative output terminals of the operational amplifier OP7 are connected to the analog-to-digital conversion module 130 to perform analog-to-digital conversion on the collected voltage.

[0137] In addition, in order to perform current compensation to eliminate the influence brought by the filtering resistor, the compensation current I comp1 can be input to the PIN i terminal, by inputting the compensation current I comp2 to the PIN i-1 terminal.

[0138] Figure 8 A schematic diagram of a generation circuit for two compensation currents is shown. The principle of each generation circuit is the same as that described above.

[0139] In Figure 9 is shown Figure 8 the specific circuit diagrams of two generation circuits of Figure 9 In the left side view of i the generation circuit may include a first PMOS transistor MP91 and a second PMOS transistor MP92, and an operational amplifier OP91. The sources of the first PMOS transistor MP91 and the second PMOS transistor MP92 are connected to the voltage VB of the i-th battery FN , the gates of the first PMOS transistor MP91 and the second PMOS transistor MP92 are connected to the output of the operational amplifier OP91, and one input terminal (negative) of the operational amplifier OP91 is connected to the negative input terminal voltage V of the operational amplifier OP7 OP . The other input terminal (positive) of the operational amplifier OP91 is connected to the drain of the first PMOS transistor MP91 and is connected to the positive terminal output voltage V of the operational amplifier OP7 through a resistor and a switch series circuit comp1 . The drain of the second PMOS transistor MP92 provides a compensation current I

[0140] In Figure 9 the right side view of FP which is substantially the same as the left side view, only the differences are described here. One input terminal (negative) of the operational amplifier OP91 is connected to the negative input terminal voltage V of the operational amplifier OP7 ON . The other input terminal (positive) of the operational amplifier OP91 is connected to the negative terminal output voltage V of the operational amplifier OP7 through a resistor and a switch parallel circuit comp2 . The drain of the PMOS transistor MP94 provides a compensation current I

[0141] In Figure 9 a control signal is generated by the operational amplifier OP91 based on V FN to control the on and off of the PMOS transistors MP91 and MP92, so that a corresponding compensation current I can be generated based on VB i . comp1

[0142] In Figure 9 a control signal is generated by the operational amplifier OP92 based on V FP to control the on and off of the PMOS transistors MP93 and MP94, so that a corresponding compensation current I can be generated based on VB i . comp2

[0143] Third Embodiment of Voltage Acquisition

[0144] Figure 10 Shows a voltage acquisition scheme according to the third embodiment of the present disclosure.

[0145] As Figure 10 shown, the gating detection module 110 can be composed of a series circuit of switches SWN1~SWN n and resistors R1~R n . One end of each series circuit is respectively connected to PIN1~PIN n , and the other ends of each series circuit are connected together and connected to an input terminal of the operational amplifier OP10.

[0146] A feedback loop composed of switches SWP0 and SWN0 and resistors RP S and RN S is respectively connected between the two input terminals of the operational amplifier OP10 and its positive and negative output terminals. Among them, one end of the series circuit composed of the switch SWP0 and the resistor RP S is connected to the V FN voltage input terminal of the operational amplifier OP10. One end of the series circuit composed of the switch SWN0 and the resistor RN S is connected to the V FP voltage input terminal of the operational amplifier OP10. The V FP voltage input terminal is grounded through the resistor R 10 . Among them, the resistor R 10 is variable. For example, when used to measure the voltage of the first battery, the resistance value of the resistor R 10 is equal to R1. When measuring the voltage of the second battery, the resistance value of the resistor R 10 is equal to R2, and so on.

[0147] Among them, the switches SWP0 and SWN0 are respectively set in proportion to the on-resistances of the switches SWP1~SWP n and SWN1~SWN n . The resistors RP S and RN S are respectively set in proportion to the resistors R1 and R n . The principle can refer to the above description. For example, the switches SWP0 and SWN0 are kept in a normally-on state, etc.

[0148] The positive and negative output terminals of the operational amplifier OP10 are connected to the analog-to-digital conversion module 130 to perform analog-to-digital conversion on the acquired voltage.

[0149] At Figure 10 and Figure 7In the manner shown, the voltage of the battery is detected in a differential manner by an operational amplifier. For example, taking Figure 10 as an example ( Figure 7 the principle is the same), the detection of the i-th battery is taken as an example. BAT n is the voltage of the i-th battery itself.

[0150] VB i = VB i-1 + BAT i . (Vop - Von) i = VB i * R2 / R i = [VB i-1 + BAT i * R2 / R i . (Vop - Von) i-1 = VB i-1 * R2 / R i-1 . (Vop - Von) i - (Vop - Von) i-1 = [VB i-1 + BAT i * R2 / R i - VB i-1 * R2 / R i-1 . If R i-1 = R i , then (Vop - Von) i - (Vop - Von) i-1 = BAT i * R2 / R i . In addition, taking the on-resistance of the switch into account, the principle is the same.

[0151] Figure 11 shows a schematic diagram of the compensation current generation circuit. The principle of the generation circuit is the same as that described above.

[0152] In Figure 12 is shown Figure 11 the specific circuit diagram of the generation circuit. In Figure 12 , an operational amplifier OP12 is used to generate a control signal based on V FN / V PN to control the on and off of PMOS transistors MP121 and MP122, so that a corresponding compensation current I i can be generated based on VB comp . And the circuit is input to the corresponding PIN i terminal. Similar to the Figure 9 structure, it will not be described in words.

[0153] Figure 13 A schematic diagram of a generating circuit of another compensation circuit is shown. In this generating circuit, two compensation currents I comp1 and I comp2 are generated. The compensation method of the compensation circuit can refer to the above description and will not be elaborated here.

[0154] As shown in this drawing, for example, the compensation circuit can be integrated into a voltage amplification module. For example, this voltage amplification module can be in the form of an operational amplifier, so that the compensation current can be realized by the current taken from the operational amplifier itself. In this embodiment, the compensation current can be generated by the output stage of the operational amplifier.

[0155] It may include amplifier A131, amplifier A13P, and amplifier A13N. Two input terminals of amplifier A131 are respectively connected to voltages V FN and V FP . And two output terminals of amplifier A131 are respectively connected to two output terminals of amplifier A13P and amplifier A13N. The positive output terminal of amplifier A13P is connected to the gates of PMOS transistors MP11 and MP12, and the sources of PMOS transistors MP11 and MP12 are connected to the system voltage. The negative output terminal of amplifier A13P is connected to the gates of NMOS transistors MN11 and MN12. The drain of PMOS transistor MP11 is connected to the drain of NMOS transistor MN11, and the drain of PMOS transistor MP12 is connected to the drain of NMOS transistor MN12. And the sources of NMOS transistors MN11 and MN12 are grounded. PMOS transistors MP21 and PMOS transistor MP22 form a current mirror circuit. The sources of PMOS transistors MP21 and PMOS transistor MP22 are connected to the voltage VB i of the i-th battery. The gate of PMOS transistor MP21 is connected to the gate of MP22 and is also connected to the drain of MP21. The drain of MP21 is connected to the connection point of MP12 and MN12. The drain of PMOS transistor MP22 serves as the output terminal of the compensation current I comp1 .

[0156] The positive output terminal of amplifier A13N is connected to the gates of PMOS transistors MP13 and MP14, and the sources of PMOS transistors MP14 and MP14 are connected to the system voltage. The negative output terminal of amplifier A13N is connected to the gates of NMOS transistors MN13 and MN14. The drain of PMOS transistor MP13 is connected to the drain of NMOS transistor MN13, and the drain of PMOS transistor MP14 is connected to the drain of NMOS transistor MN14. The sources of NMOS transistors MN13 and MN14 are grounded. PMOS transistors MP23 and PMOS transistor MP24 form a current mirror circuit, where the sources of PMOS transistors MP23 and PMOS transistor MP24 are connected to the voltage VB of the i-th battery i , the gate of PMOS transistor MP23 is connected to the gate of MP24 and also to the drain of MP23. The drain of MP23 is connected to the connection point of MP14 and MN14. The drain of PMOS transistor MP24 serves as the output terminal of the compensation current I comp2 .

[0157] In addition, as Figure 13 shown by the dashed box, PMOS transistors MP11 and MP12, PMOS transistors MP13 and MP14, NMOS transistors MN11 and MN12, and NMOS transistors MN13 and MN14 can be respectively composed of two or more series-connected transistors of the same type, and the gates of other transistors included therein can be connected to the bias voltage V bias . In Figure 13 a series form of two is shown.

[0158] Fourth Embodiment of Voltage Acquisition

[0159] Figure 14 Fig. shows a voltage acquisition scheme according to the fourth embodiment of the present disclosure.

[0160] As Figure 14 shown, a voltage amplification module 120 is formed by amplifiers A141 and A142, operational amplifier OP14, and resistors R 141 to R 147 .

[0161] The operational amplifier unit includes a first amplifier A141, a second amplifier A142, a first operational amplifier OP14, and first to seventh resistors R 141 to R 147 . When measuring the battery voltage of the i-th battery, the positive input terminal of the first comparator is connected to the detection voltage of the positive terminal of the i-th battery, and the positive input terminal of the second comparator is connected to the detection voltage of the positive terminal of the (i - 1)-th battery

[0162] The output terminal of the first comparator is connected to the positive output terminal of the first operational amplifier through a series circuit of a first resistor and a second resistor, and the negative input terminal of the first operational amplifier is connected to the connection node of the first resistor and the second resistor.

[0163] The output terminal of the second comparator is connected to the negative output terminal of the first operational amplifier through a series circuit of a third resistor and a fourth resistor, and the positive input terminal of the first operational amplifier is connected to the connection node of the third resistor and the fourth resistor.

[0164] The output terminal of the first comparator and the output terminal of the second comparator are connected through a series circuit of a fifth resistor, a sixth resistor and a seventh resistor, and the negative input terminal of the first comparator is connected to the connection node of the fifth resistor and the sixth resistor, and the negative input terminal of the second comparator is connected to the connection node of the sixth resistor and the seventh resistor.

[0165] In Figure 14 the embodiment of, V FP and V FN the input terminals of are the gates of the amplifier. Since the gate oxide layer is in a high-resistance state, the input current is 0. That is to say, no current flows through R fi when collecting the voltage, I fi =0. That is to say, the filter resistor R fi will not cause voltage acquisition error.

[0166] Therefore, this voltage acquisition method is suitable for large filter resistors, increases the system reliability, and prevents battery short circuit.

[0167] Although various current compensation methods have been described in the above embodiments, those skilled in the art should understand that various current compensation methods can be interchanged and can be used in different embodiments.

[0168] In summary, through the embodiments of the present disclosure, the voltage of the battery can be detected with high precision, so that the battery can be managed based on the accurate battery voltage.

[0169] In the description of this specification, the descriptions with reference to terms such as "one embodiment / way", "some embodiments / ways", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / way or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments / ways or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments / ways or examples described in this specification and the features of different embodiments / ways or examples.

[0170] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0171] Those skilled in the art should understand that the above embodiments are only for clearly explaining the present disclosure and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications can be made on the basis of the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A voltage detection system for detecting the voltage of the i-th battery in a battery pack formed by connecting N batteries in series, where i = 1 to N, characterized in that, Comprising: An RC filtering unit, the input end of the RC filtering unit of the i-th battery is connected to the positive end of the i-th battery; A gating unit, the gating unit has N gating branches, the input end of the i-th gating branch among the N gating branches is connected to the output end of the RC filtering unit of the i-th battery, and the i-th gating branch is composed of a series circuit of a gating switch and a first resistor, An operational amplifier unit, the operational amplifier unit includes a first input end and a second input end, the first input end is connected to the output end of the gating unit; An analog-to-digital conversion unit, the analog-to-digital conversion unit is connected to the output end of the operational amplifier unit and converts the voltage from the operational amplifier unit into a digital signal; A current compensation circuit, the current compensation circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor and a compensation operational amplifier, wherein the sources of the first PMOS transistor and the second PMOS transistor are connected to the battery voltage of the i-th battery, the gates of the first PMOS transistor and the second PMOS transistor are interconnected and connected to the drain of the first PMOS transistor, the drain of the second PMOS transistor serves as a compensation current to be provided to the output end of the RC filtering unit of the i-th battery, the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the source of the first NMOS transistor and grounded, the gates of the second NMOS transistor and the first NMOS transistor are connected to the output end of the compensation operational amplifier, the drain of the first NMOS transistor is connected to the source of the third NMOS transistor, the drain of the first NMOS transistor is connected to an input end of the compensation operational amplifier, the other input end of the compensation operational amplifier is connected to the output end of the operational amplifier unit, and the drain of the third NMOS transistor is connected to the reference voltage via a resistor.

2. The voltage detection system according to claim 1, wherein A feedback circuit is connected between the output end of the operational amplifier unit and the first input end of the operational amplifier unit, the feedback circuit is a series circuit of a feedback switch and a feedback resistor, and the feedback switch is in a normally-on state.

3. The voltage detection system according to claim 2, characterized in that, Alternatively, the current compensation circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor; The sources of the first PMOS transistor and the second PMOS transistor are interconnected and connected to the system voltage, the gates are connected to the bias voltage signal, the drain of the first PMOS transistor is connected to one end of the feedback resistor and to the drain of the first NMOS transistor, the source of the first NMOS transistor is grounded, the output terminal of the operational amplifier unit is connected to the gates of the first NMOS transistor and the second NMOS transistor, the source of the second NMOS transistor is grounded, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and is connected to the drain of the third PMOS transistor, the third PMOS transistor is connected to the gates of the third PMOS transistor and the fourth PMOS transistor and is connected to the drain of the third PMOS transistor, the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the voltage of the i-th battery cell, and the drain terminal of the fourth PMOS transistor provides a compensation current to be supplied to the output terminal of the RC filtering unit of the i-th battery cell.

4. The voltage detection system according to claim 2, wherein The feedback resistor is set in proportion to the resistance value of the first resistor, and the feedback switch is set in proportion to the on-resistance of the gating switch.

5. The voltage detection system according to claim 4, characterized in that, When 2 ≤ i ≤ N, when the battery voltage of the i-th battery cell is detected by the voltage detection system, the positive terminal voltage and the negative terminal voltage of the i-th battery cell are measured and the battery voltage of the i-th battery cell is obtained based on the difference of the positive terminal voltage. When the positive terminal voltage is measured, the gating switch in the gating unit of the i-th battery cell is turned on, so as to measure the positive terminal voltage of the i-th battery cell. When the negative terminal voltage is measured, the gating switch in the gating unit of the (i - 1)-th battery cell is turned on, so as to measure the negative terminal voltage of the i-th battery cell.

6. The voltage detection system according to claim 5, wherein The feedback circuit is connected to the first input terminal of the operational amplifier unit, and the second input terminal of the operational amplifier unit is connected to the reference voltage; Or, When the battery voltage of the i-th battery cell is detected, the gating switch of the gating unit of the i-th battery cell and the gating switch of the gating unit of the (i - 1)-th battery cell are turned on, so as to supply the battery voltage of the i-th battery cell and the battery voltage of the (i - 1)-th battery cell to the first input terminal and the second input terminal of the operational amplifier unit; Or, The operational amplifier unit includes a positive output terminal and a negative output terminal. A first feedback circuit is connected between the negative output terminal of the operational amplifier unit and the first input terminal of the operational amplifier unit. The first feedback circuit is a series circuit of a first feedback switch and a first feedback resistor. A second feedback circuit is also connected between the positive output terminal of the operational amplifier unit and the second input terminal of the operational amplifier unit. The second feedback circuit is a series circuit of a second feedback switch and a second feedback resistor. The second feedback resistor is set in proportion to the resistance value of the first resistor, and the second feedback switch is set in proportion to the on-resistance of the gating switch. The connection point of the second feedback circuit and the second input terminal of the operational amplifier unit is grounded through an adjustable grounding resistor. When the battery voltage of the i-th battery cell is detected, the resistance value of the adjustable grounding resistor is equal to the resistance value of the first resistor in the i-th gating branch.

7. The voltage detection system according to claim 1, wherein The operational amplifier unit includes a first comparator, a second comparator, a first operational amplifier, and first to seventh resistors. When measuring the battery voltage of the i-th battery cell, the positive input terminal of the first comparator is connected to the detected voltage of the positive terminal of the i-th battery cell, and the positive input terminal of the second comparator is connected to the detected voltage of the positive terminal of the (i - 1)-th battery cell. The output terminal of the first comparator is connected to the positive output terminal of the first operational amplifier through a series circuit of a first resistor and a second resistor, and the negative input terminal of the first operational amplifier is connected to the connection node of the first resistor and the second resistor. The output terminal of the second comparator is connected to the negative output terminal of the first operational amplifier through a series circuit of a third resistor and a fourth resistor, and the positive input terminal of the first operational amplifier is connected to the connection node of the third resistor and the fourth resistor. The output terminal of the first comparator and the output terminal of the second comparator are connected through a series circuit of a fifth resistor, a sixth resistor, and a seventh resistor. The negative input terminal of the first comparator is connected to the connection node of the fifth resistor and the sixth resistor, and the negative input terminal of the second comparator is connected to the connection node of the sixth resistor and the seventh resistor.

8. The voltage detection system according to any one of claims 1 to 6, wherein Alternatively, the current compensation circuit includes: The first PMOS transistor, the second PMOS transistor, and the first operational amplifier, wherein the sources of the first PMOS transistor and the second PMOS transistor are connected to the voltage VB of the ith battery cell i , the gates of the first PMOS transistor and the second PMOS transistor are connected to the output of the first operational amplifier, one input terminal of the first operational amplifier is connected to the negative input terminal voltage of the operational amplifier unit, the other input terminal of the first operational amplifier is connected to the drain of the first PMOS transistor, and is connected to the positive terminal output voltage of the operational amplifier unit through a resistor and a switch series circuit, and the drain of the second PMOS transistor provides a first compensation current to be provided to the output terminal of the RC filtering unit of the ith battery cell; The third PMOS transistor, the fourth PMOS transistor, and the second operational amplifier, wherein the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the voltage VB of the ith battery i , the gates of the third PMOS transistor and the fourth PMOS transistor are connected to the output of the second operational amplifier, one input terminal of the second operational amplifier is connected to the positive input voltage of the operational amplifier unit, the other input terminal of the second operational amplifier is connected to the drain of the third PMOS transistor, and is connected to the negative output voltage of the operational amplifier unit through a resistor and a switch series circuit, and the drain of the fourth PMOS transistor provides a second compensation current to be provided to the output terminal of the RC filter unit of the (i - 1)th battery; Alternatively, the current compensation circuit is integrated into the operational amplifier unit. The integrated operational amplifier unit includes: a first amplifier, a second amplifier, and a third amplifier, wherein: Two input terminals of the first amplifier are the first input terminal and the second input terminal of the operational amplifier unit, and two output terminals of the first amplifier are respectively connected to two input terminals of the second amplifier and the third amplifier. The positive output terminal of the second amplifier is connected to the gates of a first PMOS transistor and a second PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are connected to the system voltage. The negative output terminal of the second amplifier is connected to the gates of a first NMOS transistor and a second NMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are grounded. A third PMOS transistor and a fourth PMOS transistor form a current mirror circuit. The sources of the third PMOS transistor and the fourth PMOS transistor are connected to the voltage of the i-th battery cell. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and is connected to the drain of the third PMOS transistor. The drain of the third PMOS transistor is connected to the connection point of the second PMOS transistor and the second NMOS transistor. The drain of the fourth PMOS transistor provides a first compensation current to the output terminal of the RC filter unit of the i-th battery cell. The positive output terminal of the third amplifier is connected to the gates of the fifth PMOS transistor and the sixth PMOS transistor. The sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to the system voltage. The negative output terminal of the third amplifier is connected to the gates of the third NMOS transistor and the fourth NMOS transistor. The drain of the fifth PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor. The sources of the third NMOS transistor and the fourth NMOS transistor are grounded. The seventh PMOS transistor and the eighth PMOS transistor form a current mirror circuit. The sources of the seventh PMOS transistor and the eighth PMOS transistor are connected to the voltage of the i-th battery cell. The gates of the seventh PMOS transistor and the eighth PMOS transistor are connected and connected to the drain of the seventh PMOS transistor. The drain of the seventh PMOS transistor is connected to the connection point of the sixth PMOS transistor and the fourth NMOS transistor. The drain of the eighth PMOS transistor provides a second compensation current to the output terminal of the RC filtering unit of the (i - 1)-th battery cell; The first PMOS transistor and the second PMOS transistor, and the fifth PMOS transistor and the sixth PMOS transistor are respectively composed of one or more PMOS transistors connected in series. The first NMOS transistor and the second NMOS transistor, and the third NMOS transistor and the fourth NMOS transistor are respectively composed of one or more NMOS transistors connected in series.

9. A battery management system, characterized in that, It includes the voltage detection system according to any one of claims 1 to 8.

10. The battery management system according to claim 9, characterized in that, It further includes a control logic module and a switch driving module. The control logic module receives the digital signal converted by the analog-to-digital conversion unit and provides a control signal to the switch driving module at least based on the digital signal. The switch driving module controls the conduction of the charging switch and the discharging switch based on this control signal.

11. A battery management chip, characterized in that, Integrate the voltage detection system according to any one of claims 1 to 8, or integrate the battery management system according to claim 9 or 10.

Images