Method for manufacturing semiconductor structure
By forming a hydrophobic layer on the back of the semiconductor wafer, the problem of debris on the front of the wafer is solved, the defective rate is reduced, and product quality is improved.
Patent Information
- Application Number
- CN202010566943.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-06-19
- Publication Date
- 2025-01-21
- Estimated Expiration
- 2040-06-19
AI Technical Summary
In the prior art, when manufacturing semiconductor wafers, fine fragments are often found on the front of the wafer, resulting in a high failure rate of semiconductor manufacturing.
A hydrophobic layer is formed on the front, side and at least part of the back of the substrate on which the silicon nitride film is deposited to slow down or eliminate the penetration and damage of the chemical liquid to the back coating of the wafer.
By forming a hydrophobic layer on the back of the wafer, the penetration rate of chemical liquids is reduced, the degree of shedding of the silicon nitride film and the P-TEOS coating is reduced, and the formation and movement of debris to the front of the wafer is reduced, thereby improving the products of semiconductor manufacturing. Yield.
Smart Images

Figure CN113823549B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a semiconductor structure. Background Art
[0002] Wafer is the substrate (also known as base) for manufacturing semiconductor transistors or integrated circuits. Since wafers are made of crystalline materials and are round in shape, they are called wafers. The manufacture of wafers requires multiple processes, such as the dual-gate oxide process. In the process of manufacturing wafers in the prior art, small fragments are often found on the front of the wafer. These fragments greatly affect the quality of the wafer, resulting in a significant increase in the defective rate of semiconductor manufacturing. Summary of the invention
[0003] The object of the present invention is to provide a method for manufacturing a semiconductor structure to solve the technical problem of high semiconductor defect rate in the prior art.
[0004] The present invention also provides a method for manufacturing a semiconductor structure, comprising:
[0005] providing a substrate into which well implantation has been completed;
[0006] performing dual gate oxide deposition;
[0007] performing silicon nitride deposition;
[0008] A hydrophobic layer is formed on the front surface, the side surface and at least a portion of the back surface of the substrate on which the silicon nitride film is deposited.
[0009] In the above technical scheme, by forming an appropriate hydrophobic layer on the back of the wafer (i.e., substrate), the back of the wafer can also have a hydrophobic function, thereby effectively alleviating the penetration of chemical liquid into the damaged position of the outermost coating on the back of the wafer during wet etching, slowing down or eliminating the problem of fragments formed on the back of the wafer due to coating shedding, so that the front of the wafer is not affected by the falling of the fragments, thereby improving the product yield of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0011] Figure 1 Schematic diagram of the process of wafer backside coating peeling off to form fragments in the prior art Figure 1 ;
[0012] Figure 2 Schematic diagram of the process of wafer backside coating peeling off to form fragments in the prior art Figure 2 ;
[0013] Figure 3 Schematic diagram of the process of wafer backside coating peeling off to form fragments in the prior art Figure 3 ;
[0014] Figure 4 Schematic diagram of the process of wafer backside coating peeling off to form fragments in the prior art Figure 4 ;
[0015] Figure 5 A state diagram of a chemical liquid attached to a hydrophobic layer of a wafer provided by an embodiment of the present invention;
[0016] Figure 6 It is a schematic diagram of the liquid state of the chemical liquid attached to the hydrophilic area in the prior art;
[0017] Figure 7 A schematic diagram of a liquid state of a chemical liquid attached to a hydrophobic area provided by an embodiment of the present invention;
[0018] Figure 8 A schematic diagram of wafer manufacturing in the prior art;
[0019] Fig. 9 It is a layer structure diagram of a wafer in the prior art;
[0020] Fig.10 A schematic diagram of wafer manufacturing provided by one embodiment of the present invention;
[0021] Fig.11 A layer structure diagram of a wafer provided by an embodiment of the present invention;
[0022] Fig.12 A layer structure diagram of a wafer provided for another embodiment of the present invention.
[0023] Reference numerals:
[0024] 100, substrate; 200, hydrophobic layer; 300, silicon nitride film; 400, P-TEOS coating; 500, debris; 600, chemical liquid; 700, processing chamber; 800, hydrophobic substance. DETAILED DESCRIPTION
[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0026] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0027] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.
[0028] After studying the manufacturing process of wafers in the prior art, it is found that after the wafer is processed by the DGO (Dual Gate Oxide) process, the SIN (Silicon Nitride) process will continue to be deposited on it. When performing the SIN process, it is generally necessary to use a clamping mechanism or a guiding mechanism to clamp or lift the wafer. At this time, the clamping mechanism or the guiding mechanism will contact the back of the wafer, which will cause the silicon nitride film 300 at the contact position to be damaged by force.
[0029] refer to Figures 1 to 4 As shown, at this time, the back of the wafer 100 is formed with a P-TEOS coating 400 and a silicon nitride film 300 in sequence, and the P-TEOS coating 400 is located in the inner layer of the silicon nitride film 300, which is also the outermost coating on the back of the wafer. The silicon nitride film 300 will be damaged due to force. During the wet etching process, the etching chemical liquid 600 will penetrate into the inner layer of the silicon nitride film 300 along the damaged part of the silicon nitride film 300, and corrode the P-TEOS (Plasma tetraethylorthosilicate) coating of the inner layer of the silicon nitride film 300. At this time, the silicon nitride film 300 will lack adhesion due to the corrosion of the P-TEOS coating 400, and will be removed from the wafer together with the P-TEOS coating 400 to form small fragments 500, which move to the front of the wafer. This is also the source of the fragments 500 on the front of the wafer, and is also the fundamental factor affecting the yield of semiconductor products.
[0030] refer to Figures 5 to 11As shown, the present invention also provides a method for manufacturing a semiconductor structure, including: providing a substrate 100 into which well implantation has been completed; performing dual gate oxide deposition; performing silicon nitride deposition; and forming a hydrophobic layer 200 on the front, side and at least a portion of the back of the substrate 100 on which the silicon nitride film 300 is deposited.
[0031] Therefore, by forming the hydrophobic layer 200 on the side and at least a portion of the back of the substrate 100 (ie, the wafer), the hydrophobic layer 200 can transform the side and at least a portion of the back of the substrate 100 from a hydrophilic region to a hydrophobic region. Figure 5 As shown in FIG. 1 , the chemical liquid 600 forms different contact angles in the hydrophilic region and the hydrophobic region. Figure 6 and Figure 7 As shown, the contact angle of the chemical liquid 600 in the hydrophobic area is significantly larger.
[0032] Taking the structure in which the P-TEOS coating 400 and the silicon nitride film 300 are sequentially formed on the back of the wafer as an example, the chemical liquid 600 being etched at this time will form a larger contact angle on the back of the substrate 100 due to the hydrophobic layer 200, thereby forming a water drop shape. This effectively reduces the penetration speed of the chemical liquid 600 at the damaged part of the silicon nitride film 300, and effectively alleviates the corrosion of the chemical liquid 600 on the inner layer of the P-TEOS coating 400 of the silicon nitride film 300. Therefore, this can effectively reduce the degree of shedding of the silicon nitride film 300 and the P-TEOS coating 400, reduce the number of fragments 500 formed, reduce the impact on the front of the substrate 100, and thus improve the product quality of the substrate 100.
[0033] As can be seen from the above, when the substrate 100 is subjected to the wet etching process, the etched chemical liquid 600 will form a larger contact angle on the back of the substrate 100 due to the hydrophobic layer 200, thereby forming a water drop shape. This can effectively reduce the penetration speed of the chemical liquid 600 at the damaged part of the outermost coating on the back of the substrate 100, effectively alleviate the corrosion of the chemical liquid 600 on the inner coating, slow down the shedding of the coating and the formation of fragments 500, reduce or prevent the fragments 500 from moving to the front of the substrate 100, and improve the product yield of semiconductor manufacturing.
[0034] At the same time, the hydrophobic layer 200 formed on the back side of the substrate 100 is located at the edge position of the back side of the substrate 100, and the substrate 100 can also be controlled to move by making the substrate 100 contact with the edge position of the substrate 100 through a clamping mechanism or a guiding mechanism. At this time, after the edge position of the coating on the back side of the substrate 100 is damaged, the hydrophobic layer 200 located at the edge of the back side of the substrate 100 can produce a hydrophobic effect on the chemical liquid 600, thereby reducing the penetration rate of the damaged coating position.
[0035] In addition, for those skilled in the art, the hydrophobic layer 200 can be formed on the substrate 100 by an attachment process. Preferably, the attachment process is to place the substrate 100 deposited with the silicon nitride film 300 into the processing chamber 700, and pass a precursor gas containing a hydrophobic substance 800 to form the hydrophobic layer 200. For the hydrophobic substance 800 forming the hydrophobic layer 200, preferably, the hydrophobic substance 800 is hexamethyldisilazane. In addition, those skilled in the art can also select other formation methods or select other hydrophobic substances 800 according to needs, which will not be repeated or limited here.
[0036] refer to Figure 8 and Fig. 9 As shown, in the prior art, when manufacturing the substrate 100, the back side of the substrate 100 is close to the bottom of the inner cavity of the processing chamber 700, and the precursor gas containing the hydrophobic substance 800 is only formed on the front side of the substrate 100. Figures 10 to 12 As shown, in one embodiment of the specific manufacture of the semiconductor structure, a hydrophobic layer is first attached to the front side of the substrate 100 on which the silicon nitride film 300 is deposited; then the side and back sides are attached to form a hydrophobic layer 200 on the substrate 100 through a precursor gas containing a hydrophobic substance 800. Preferably, an exhaust valve is provided at the bottom of the processing chamber 700, the substrate 100 is lifted horizontally, and the exhaust valve is opened so that the precursor gas containing the hydrophobic substance 800 passes through the side and reaches the back side for attachment.
[0037] Therefore, the substrate 100 is exposed not only on the front side but also on the back side of the substrate 100 in the inner cavity of the processing chamber 700. After the gaseous hydrophobic substance 800, such as hexamethyldisilazane, is introduced into the processing chamber 700 in the form of vapor, the hexamethyldisilazane vapor can contact both the front side and the back side of the substrate 100 in the processing chamber 700, thereby forming a hydrophobic layer 200 on the back side of the substrate 100.
[0038] In the operation of lifting the substrate 100, a hole may be punched in the bottom of the processing chamber 700 and a support assembly, such as a support rod, may be inserted therein, so that the substrate 100 may be lifted from the inside of the processing chamber 700 by the support rod. In addition, other mechanisms with a support function or structures with a lifting function may be provided inside the processing chamber 700. Those skilled in the art may set them according to requirements, and no further description is given here.
[0039] Preferably, at least three pins are used to horizontally lift the substrate 100, and the lifting height is 1 mm to 15 mm. For example, the distance between the two can be controlled at 1 mm, 3 mm, 6 mm, 9 mm, 12 mm or 15 mm. At this time, the hexamethyldisilazane vapor can be introduced from the upper and lower parts of the processing chamber 700, that is, the gas pipeline is passed from the upper and lower parts of the processing chamber 700. The hexamethyldisilazane vapor introduced from the upper part of the processing chamber 700 can be deposited on the front of the substrate 100, and the hexamethyldisilazane vapor introduced from the lower part of the processing chamber 700 can be released controllably on the back of the substrate 100, and by adjusting the position of the lower pipeline, the precursor gas containing the hydrophobic substance 800 can be released in a targeted manner to the predetermined position on the back of the substrate 100. After continuously releasing the hexamethyldisilazane vapor to the predetermined position, the hydrophobic layer 200 can be formed at the predetermined position on the back of the substrate 100.
[0040] In addition, according to specific needs, the substrate 100 can be lifted in an inclined manner or in an upright manner, and the direction and position of the release of the hexamethyldisilazane vapor in the processing chamber 700 can be controlled according to needs, so that the hydrophobic layer 200 can be controllably formed at other positions of the substrate 100. Those skilled in the art can set this according to needs, and it will not be repeated here.
[0041] In the above steps or other corresponding steps, the precursor gas containing the hydrophobic substance 800 is controlled to be discharged from the processing chamber 700 at a pressure of 1Pa to 5Pa. For example, the pressure of the precursor gas containing the hydrophobic substance 800 can be controlled to be 1Pa, 2.5Pa, 3Pa, 3.5Pa or 5Pa. In addition, when releasing the precursor gas containing the hydrophobic substance 800, preferably, the time for attaching the side and back surfaces is controlled to be 1s to 100s, such as 15s, 30s, 60s, 80s or 85s. Those skilled in the art can select appropriate pressure parameters and release time according to specific process requirements, which will not be described in detail here.
[0042] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.
[0043] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate into which well implantation has been completed; performing dual gate oxide deposition; performing silicon nitride deposition; forming a hydrophobic layer on the front surface, the side surface and at least a portion of the back surface of the substrate on which the silicon nitride film is deposited; forming the hydrophobic layer on the substrate by an attachment process; The attachment process is to place a substrate with a silicon nitride film deposited thereon into a processing chamber, an exhaust valve is arranged at the bottom of the processing chamber, the substrate is lifted horizontally, a gas containing hexamethyldisilane is introduced for deposition to form the hydrophobic layer, and the exhaust valve is opened during the deposition process; The method also includes firstly attaching the hydrophobic layer to the front side of the substrate on which the silicon nitride film is deposited, and then attaching the hydrophobic layer to the side and back side.
2. The manufacturing method according to claim 1, characterized in that: The method also includes a wet etching process after forming the hydrophobic layer.
3. The manufacturing method according to claim 1, characterized in that: The hydrophobic layer formed on the back side of the substrate is located at the edge of the back side of the substrate.
4. The production method according to any one of claims 1 to 3, characterized in that When forming the hydrophobic layer, at least three pins are used to horizontally lift the substrate, and the lifting height is 1 mm to 15 mm.
5. The manufacturing method according to any one of claims 1 to 3, characterized in that: The gas containing hexamethyldisilane is controlled to be exhausted from the processing chamber at a pressure of 1 Pa to 5 Pa.
6. The manufacturing method according to any one of claims 1 to 3, characterized in that: The time for attaching the side surface and the back surface is controlled to be 1s to 100s.
Citation Information
Patent Citations
Substrate processing method, substrate processing apparatus, and manufacturing method of semiconductor device
CN101005015A
Method for forming resist pattern, and semiconductor device manufactured by the method
JP2008277748A