A SiC MOSFET device and preparation method thereof

Abstract

The present application relates to the field of silicon carbide power devices, and discloses a SiC MOSFET device and a preparation method thereof, wherein the SiC MOSFET device comprises a substrate, an epitaxial bottom layer, a base layer, a source layer, a gate, a gate dielectric layer, a protective layer, a channel section, a channel length reduction section, a floating section, an isolation layer, a source and a drain; the SiC MOSFET device is prepared based on the following method, including: forming an epitaxial bottom layer and a base layer on a first surface of the substrate, forming a protective layer in the epitaxial bottom layer and the base layer, forming a source layer and a base junction on the base layer, forming a gate, a gate dielectric layer, a channel section, a channel length reduction section and a floating section in a groove, forming an isolation layer on the gate layer, forming a source on the isolation layer and the source layer, and forming a drain on the second surface of the substrate. The gate dielectric layer of the present application has low defect density, high breakdown voltage and high reliability.

Description

Technical Field

[0001] The present application relates to the field of silicon carbide power devices, and in particular to a SiC MOSFET device and a method for preparing the same. Background Art

[0002] Due to its large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation rate and strong radiation resistance, silicon carbide power semiconductor devices can be used in high temperature, high pressure, high frequency and strong radiation working environments.

[0003] Vertical MOSFETs mainly include planar double-injection MOSFETs and trench MOSFETs. Among them, trench MOSFET devices do not have JFET region resistance and have higher cell density, so they are considered to have wider application prospects.

[0004] However, in trench MOSFET, the gate oxide is directly exposed to the drift region, and the electric field is concentrated at the gate oxide corner. The dielectric constant of SiC is 2.5 times that of SiO2. In the blocking state, the gate oxide corner at the bottom of the trench has been broken down in advance before reaching the SiC critical breakdown electric field, and the device reliability is reduced. Summary of the invention

[0005] In order to solve the problem of premature gate oxide breakdown of trench SiC MOSFET devices and improve the reliability of trench SiC MOSFET devices, the present application provides a SiC MOSFET device and a method for preparing the same.

[0006] In a first aspect, the present application provides a SiC MOSFET device, which adopts the following technical solution:

[0007] A SiC MOSFET device, comprising:

[0008] a substrate having a first surface and an opposing second surface;

[0009] An epitaxial layer disposed on the first surface of the substrate, the epitaxial layer comprising an epitaxial bottom layer, a base layer disposed on the epitaxial bottom layer, a source layer disposed on the base layer, and a protective layer disposed within the epitaxial bottom layer and the base layer, the epitaxial layer being provided with a groove, the groove penetrating the source layer and the base layer and extending to the epitaxial bottom layer, the groove having a groove bottom disposed in the epitaxial bottom layer, the upper opening width of the groove being greater than the width of the lower groove bottom thereof, the angle between the inclined sidewalls on both sides of the groove and the groove side of the first surface being between 50° and 70°, and the protective layer being disposed between the grooves;

[0010] The epitaxial layer is formed with a redefined channel layer in accordance with the inner shape of the trench, and the redefined channel layer includes a channel section located at the upper part of the inclined sidewalls on both sides, a channel length reduction section located at the lower part of one or both inclined sidewalls, and a floating section located at the bottom of the trench;

[0011] a gate dielectric layer covering the redefined channel layer;

[0012] A gate is arranged in the trench, and the bottom of the gate is controlled to be within the height range of the channel length reduction section.

[0013] Through the above technical solution, the width of the upper opening of the groove of the present application is greater than the width of the bottom of the groove at the bottom, and the angle between the inclined side walls on both sides of the groove and the groove side of the first surface is between 50° and 70°, so the defect density of the gate dielectric layer in the groove can be reduced, and the carrier mobility of the groove can be improved, and the on-resistance can be reduced. In addition, the redefined channel layer set in the groove of the present application can redefine the channel length to reduce the defect density of the gate oxide, and can also resist the electric field of the DS pole reverse breakdown voltage, effectively reducing the electric field strength borne by the gate dielectric layer, and playing a role in protecting the gate dielectric layer. Further, the protective layer set in the epitaxial bottom layer and the base layer of the present application can introduce a new electric field peak, which plays a shielding role on the electric field of the gate dielectric layer, thereby playing a role in increasing the breakdown voltage of the device. Furthermore, since the two sides of the groove are mainly the base layer, the base layer with the same conductive type as the gate can further resist the electric field of the DS pole reverse breakdown voltage, protect the gate dielectric layer, and improve the reliability of the device.

[0014] Preferably, the SiC MOSFET device further includes:

[0015] an isolation layer disposed on the gate;

[0016] A source electrode disposed on the isolation layer and the epitaxial layer;

[0017] a drain electrode disposed on the second surface of the substrate;

[0018] The crystal plane of the inclined sidewall of the trench is (0327), (0328), (0329), (0337), (0338) or (0339).

[0019] Researchers have found that the etching rate of SiC material on the above crystal plane is slower than that of other crystal planes. Therefore, the crystal plane of the inclined sidewall of the trench is the above crystal plane. The defect density of the gate dielectric layer formed in the trench on the above crystal plane can be as low as 1E10~1E11 cm -3 ; In addition, the electron mobility of the above-mentioned crystal surface groove is high, which ultimately reduces the on-resistance per unit area of ​​the device.

[0020] Preferably, the gate dielectric layer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed at the bottom of the trench, and the second dielectric layer covers the oblique sidewalls on both sides of the trench and is integrally connected to the first dielectric layer, so that the dielectric thickness at the bottom of the trench is greater than the dielectric thickness at the oblique sidewalls on both sides;

[0021] The defect density of the first dielectric layer of the gate dielectric layer is 1E10~1E11 cm -3 .

[0022] The gate dielectric layer of the present application has low defect density, high breakdown voltage, is not easily broken down prematurely, and has high reliability.

[0023] Preferably, the material of the first dielectric layer is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and high-K materials; the material of the second dielectric layer is selected from one or more of silicon oxide, aluminum oxide and high-K materials.

[0024] Since the gate oxide at the corner of the trench bottom of the related art has been broken down in advance before reaching the SiC critical breakdown electric field, the present application can increase the thickness of the gate dielectric layer at the trench bottom through the cooperation of the first dielectric layer and the second dielectric layer, prevent the gate dielectric layer of the present application from being broken down in advance at the corner, and further improve the reliability of the gate dielectric layer. In addition, the present application sets the first dielectric layer at the bottom of the gate, which can make the gate dielectric layer withstand a higher electric field and prevent the gate dielectric layer at the bottom of the trench from being broken down or damaged by the electric field.

[0025] Preferably, the thickness of the first dielectric layer is 600-2000 angstroms, and the thickness of the second dielectric layer is 400-1200 angstroms.

[0026] Through the above technical solution, the second dielectric layer in the above thickness range can effectively suppress the short trench effect and maintain a good subthreshold slope. The first dielectric layer in the above thickness range can withstand a higher electric field while preventing the gate dielectric layer at the bottom of the trench from being broken down or damaged by the electric field. In addition, in order to ensure the depth of the trench so that the gate in the trench is in the base layer and the epitaxial layer at the same time, the top surface of the first dielectric layer is lower than the bottom surface of the base layer.

[0027] Preferably, the upper end of the channel length reducing section extends into the height range of the base layer.

[0028] Since the implant thickness of the base layer can tolerate a relatively large process error, a channel length reduction section is provided at the lower portion of the inclined sidewalls on both sides of the groove, which can not only adjust the channel length but also stabilize the implant concentration of the channel section.

[0029] Preferably, the epitaxial layer also includes a base junction, which is located in the source layer on the base layer, so that the source layer is patterned on the exposed surface of the epitaxial layer. The base junction does not extend to the groove opening of the groove and is located directly above the protective layer.

[0030] Through the above technical solution, the protective layer arranged in the epitaxial bottom layer and the base layer cooperates with the base junction located directly above it to strengthen the shielding effect of the electric field of the gate dielectric layer and further improve the reliability of the gate dielectric layer.

[0031] In a second aspect, the present application provides a method for preparing a SiC MOSFET device, using the following technical solution:

[0032] A method for preparing a SiC MOSFET device, used for preparing the above-mentioned SiC MOSFET device, comprises the following steps:

[0033] An epitaxial layer is formed on the first surface of the substrate, the epitaxial layer comprising an epitaxial bottom layer, a base layer located on the epitaxial bottom layer, a source layer located on the base layer, and a protective layer located in the epitaxial bottom layer and the base layer, the epitaxial layer is provided with a groove, the groove penetrates the source layer and the base layer and extends to the epitaxial bottom layer, the groove has a groove bottom located in the epitaxial bottom layer, the upper opening width of the groove is greater than the width of the lower groove bottom, the angle between the inclined sidewalls on both sides of the groove and the groove side of the first surface is between 50° and 70°, and the protective layer is located between the grooves;

[0034] A redefined channel layer, a gate dielectric layer and a gate are formed in the trench, wherein the redefined channel layer includes a channel section located at the upper part of the oblique sidewalls on both sides, a channel length reduction section located at the lower part of one or both oblique sidewalls, and a floating section located at the bottom of the trench, and the gate dielectric layer covers the gate dielectric layer of the redefined channel layer and wraps the gate;

[0035] forming an isolation layer on the gate layer;

[0036] forming a source electrode on the isolation layer and the source electrode layer;

[0037] A drain is formed on the second surface of the substrate.

[0038] Through the above technical solution, the preparation method of the present application is simple and the reliability of the device can be improved without adding too many processes.

[0039] Preferably, the method for forming the epitaxial layer comprises the following steps:

[0040] forming a first epitaxial bottom layer on the first surface of the substrate;

[0041] Ions are implanted into the surface of the first epitaxial bottom layer by an ion implantation method to form the protective layer in the first epitaxial bottom layer, the implantation energy is 30-400 kev, and the implantation dose is 1E13-9E14 cm -2 , the implantation depth is 0.3~1μm, the ion implantation temperature is 400~500℃ when high temperature implantation is adopted, or the ion implantation temperature is 15~35℃ when low temperature implantation is adopted;

[0042] forming a second epitaxial bottom layer on the first epitaxial bottom layer and the protective layer, wherein the first epitaxial bottom layer and the second epitaxial bottom layer constitute the epitaxial bottom layer;

[0043] Ions are implanted into the surface of the second epitaxial bottom layer by an ion implantation method to form the base layer connected to the protective layer in the second epitaxial bottom layer, the ion implantation energy is 30-400kev, and the implantation dose is 1E13-9E14cm -2 , the injection depth is 0.3~1μm;

[0044] Ions are implanted into the surface of the substrate using an ion implantation method to form a source layer in the substrate. The implantation energy is 30-190 kev and the total implantation dose is 1E13-9E15 cm -2 .

[0045] Through the above scheme, the protective layer set in the epitaxial bottom layer and the base layer of the present application can introduce a new electric field peak, which shields the electric field of the gate dielectric layer, thereby increasing the breakdown voltage of the device.

[0046] Preferably, the method for forming the groove comprises the following steps:

[0047] The source layer, the base layer and the epitaxial bottom layer are etched by plasma to form a vertical groove, the bottom of the groove is located in the epitaxial bottom layer, and the first etching gas used is SF6, or a mixed gas of SF6 and O2;

[0048] Plasma is used to etch the sidewalls of the vertical groove to form an inverted trapezoidal groove with an upper opening width greater than the lower groove bottom width, the angle between the inclined sidewalls on both sides of the groove and the groove side of the first surface is between 50° and 70°, the second etching gas used is selected from a mixed gas of Cl2 and O2, a mixed gas of BCl3 and O2, a mixed gas of SF6 and O2, and a mixed gas of CF4 and O2, and the etching temperature is 800~1000℃.

[0049] The present application uses a two-step etching method to first etch a vertical groove, and then uses plasma to etch the oblique sidewalls of the vertical groove, thereby finally forming an inverted trapezoidal groove with an upper width greater than the lower width and an angle of 50° to 80° between the oblique sidewall and the substrate. In the second etching process, the present application uses a second etching gas to etch the oblique sidewalls of the groove, and uses the characteristics of the second etching gas and SiC material to finally form an oblique sidewall of the groove with a crystal plane of (0327), (0328), (0329), (0337), (0338) or (0339), so as to improve the electron mobility of the groove and reduce the on-resistance of the device.

[0050] Preferably, the method for forming the redefined channel layer comprises the following steps:

[0051] Ions are implanted into the bottom and sidewalls of the trench to form the initial layer of the redefined channel. The implantation energy is 30-400 kev and the implantation dose is 1E12-9E13 cm -2 , the implantation depth is 0.1~0.5μm, the ion implantation temperature is 400~500℃ when high temperature implantation is adopted, or the ion implantation temperature is 15~35℃ when low temperature implantation is adopted;

[0052] Performing high temperature annealing on the redefined channel initial layer to activate ions in the redefined channel initial layer, the annealing temperature is 1500-1900° C., the annealing time is 10-60 min, and the annealing atmosphere is argon or nitrogen;

[0053] The formation area of ​​the channel length reduction section (63) is defined by photolithography, and ions are implanted into the preset area of ​​the redefined channel initial layer by an ion implantation method to form the channel length reduction section (63), the implantation energy is 30-190kev, and the total implantation dose is 1E12-9E14 cm -2 ;

[0054] The redefined channel initial layer located on the upper part of the inclined sidewalls on both sides is the channel segment, and the redefined channel initial layer located at the bottom of the groove is the floating segment, wherein the channel segment, the channel length reduction segment and the floating segment constitute the redefined channel layer.

[0055] Through the above technical scheme, the present application implants ions into the bottom of the groove or the bottom and inclined side wall of the groove to form the channel section. The method is simple. Since the ion implantation dose is high, its doping concentration is higher than the doping concentration of the base layer. In addition, the present application can reduce damage and improve the electron mobility of the channel section by performing high-temperature annealing on the channel section. The channel section formed by this method effectively reduces the electric field strength borne by the gate dielectric layer, plays a role in protecting the gate dielectric layer, further avoids the gate dielectric layer from being broken down prematurely, and increases the breakdown voltage of the device.

[0056] In related SiC MOSFET devices, the base layer generally defines the channel length before the grooves are formed. In this embodiment, the channel length is redefined after the grooves are formed, which can reduce the defect density of the gate oxide.

[0057] Preferably, the method for forming the gate dielectric layer comprises the following steps:

[0058] A first dielectric layer is formed, wherein the preparation method of the first dielectric layer comprises:

[0059] Depositing one or more materials selected from high-K material, silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide at the bottom of the trench by a deposition method to form a first dielectric layer with a thickness of 600 to 2000 angstroms; or,

[0060] Depositing single crystal silicon at the bottom of the trench by a deposition method, and then forming silicon oxide from the single crystal silicon by a thermal oxidation method to form a first dielectric layer with a thickness of 600 to 2000 angstroms;

[0061] A second dielectric layer is formed, wherein the preparation method of the second dielectric layer comprises:

[0062] Depositing one or more materials selected from high-K material, silicon oxide and aluminum oxide on the bottom and the inclined sidewall of the trench by a deposition method to form a second dielectric layer with a thickness of 400 to 1200 angstroms; or,

[0063] Depositing single crystal silicon on the bottom and the oblique sidewall of the trench by a deposition method, and then forming silicon oxide from the single crystal silicon by a thermal oxidation method at an oxidation temperature of 600-900° C. to form a first dielectric layer with a thickness of 400-1200 angstroms; or,

[0064] Forming an oxide layer with a thickness of 400-1200 angstroms on the bottom and the oblique sidewalls of the trench by a thermal growth method at a growth temperature of 1100-1400° C., then annealing in a nitrogen or phosphorus atmosphere at a temperature of 1100-1300° C., and finally performing a secondary annealing in an argon atmosphere at a temperature of 1100-1300° C. to form the second dielectric layer;

[0065] The growth order of the first dielectric layer and the second dielectric layer can be swapped.

[0066] The present application has various methods for preparing the gate dielectric layer, and effectively reduces the defect density of the gate dielectric layer and improves the reliability of the gate dielectric layer. Specifically, the present application can increase the thickness of the gate dielectric layer at the bottom of the groove through the cooperation of the first dielectric layer and the second dielectric layer, prevent the corner of the gate dielectric layer of the present application from being broken down prematurely, and further improve the reliability of the gate dielectric layer. In addition, the present application sets the first dielectric layer at the bottom of the gate groove, which can make the gate dielectric layer withstand a higher electric field, while preventing the gate dielectric layer at the bottom of the groove from being broken down or damaged by the electric field.

[0067] In addition, the second dielectric layer formed by the thermal growth method helps to ensure the uniformity of the second dielectric layer, which is beneficial to improving device performance; high-temperature annealing is performed to passivate the interface between the first or second dielectric layer and the epitaxial layer and the base layer. During the annealing process, nitrogen or phosphorus can diffuse to the interface between the first or second dielectric layer and the epitaxial layer and the base layer to fill the interface dangling bonds or compensate for the charge, thereby reducing the interface state density and improving the carrier mobility; at the same time, annealing also helps to eliminate the lattice defects of the first or second dielectric layer itself to further improve its density, which helps to form a good protection for the gate and prevent impurity atoms in subsequent processes from diffusing into the gate and causing the resistance of the gate to increase.

[0068] In summary, the present application includes at least one of the following beneficial technical effects:

[0069] 1. This application optimizes the SiC MOSFET device structure. The design of the trench gate structure helps to reduce the device on-resistance and on-power consumption, and can also make the device have a smaller input capacitance, increase the device switching rate, and reduce switching power consumption; the conductive groove is changed from horizontal to vertical, which can effectively save device area and increase power density.

[0070] 2. The upper opening width of the trench of the SiC MOSFET of the present application is greater than the width of the lower trench bottom, so that the trench has a slope of 50°~70°, thereby reducing the defect density of the gate dielectric layer in the trench, and improving the carrier mobility of the trench and reducing the on-resistance.

[0071] 3. The redefined channel layer of the present application can redefine the channel length after grooving to reduce the defect density of the gate oxide.

[0072] 4. The protective layer provided in the epitaxial bottom layer and the base layer of the present application can introduce a new electric field peak, shielding the electric field of the gate dielectric layer, thereby increasing the breakdown voltage of the device.

[0073] 5. The defect density of the gate dielectric layer of the SiC MOSFET in this application is 1E10~1E11 cm -3 , which is significantly lower than the gate oxide of related technologies (generally 1E12 cm -3), therefore, the gate dielectric layer of the present application has a high breakdown voltage, is not easily broken down prematurely, and has high reliability.

[0074] 6. The gate dielectric layer of the SiC MOSFET of the present application can resist the electric field of the DS pole reverse breakdown voltage, reduce the electric field strength borne by the gate dielectric layer, protect the gate dielectric layer from premature breakdown, and thus improve the reliability of the gate dielectric layer.

[0075] 7. The preparation method of the SiC MOSFET of the present application is simple and the reliability of the device can be improved without adding too many processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 4 is a cross-sectional view of a SiC MOSFET device according to a preferred embodiment of the present application.

[0077] Figure 2 It is a three-dimensional cross-sectional view of a SiC MOSFET device according to a preferred embodiment of the present application.

[0078] Figure 3 It is a schematic diagram of forming a first epitaxial bottom layer on a substrate during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0079] Figure 4 It is a schematic diagram of forming a protective layer in the first epitaxial bottom layer during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0080] Figure 5 It is a schematic diagram of forming a second epitaxial bottom layer on a first epitaxial bottom layer and a protective layer in the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0081] Figure 6 It is a schematic diagram of forming a base layer within an epitaxial bottom layer during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0082] Figure 7 It is a schematic diagram of forming a source layer and a base junction in a base layer during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0083] Figure 8 It is a schematic diagram of forming a vertical groove in the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0084] Fig. 9 It is a schematic diagram of forming an inverted trapezoidal trench in the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0085] Fig.10It is a schematic diagram of forming a channel section at the bottom and inclined sidewall of a trench during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0086] Fig.11 It is a schematic diagram of forming a first dielectric layer in the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0087] Fig.12 It is a schematic diagram of forming a SiN dielectric layer during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0088] Fig.13 It is a schematic diagram of the etching area for forming the SiN dielectric layer in the process of preparing the SiC MOSFET device according to the preferred embodiment of the present application.

[0089] Fig.14 It is a schematic diagram of removing the first dielectric layer used as a photoresist during the process of preparing a SiC MOSFET device in a preferred embodiment of the present application.

[0090] Fig.15 It is a schematic diagram of forming a channel length reduction section in a preset area of ​​a channel section during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0091] Fig.16 It is a schematic diagram of removing the SiN dielectric layer and the first dielectric layer used as a photoresist on the trench oblique sidewalls during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0092] Fig.17 It is a schematic diagram of forming a second dielectric layer in the process of preparing a SiC MOSFET device in a preferred embodiment of the present application.

[0093] Fig.18 It is a schematic diagram of forming a gate in a trench during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0094] Fig.19 It is a schematic diagram of exposing the source layer and the base junction in the process of preparing the SiC MOSFET device in the preferred embodiment of the present application.

[0095] Fig. 20 It is a schematic diagram of forming an isolation layer on the gate during the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0096] Fig.21 It is a schematic diagram of forming a source and a drain in the process of preparing a SiC MOSFET device according to a preferred embodiment of the present application.

[0097] Fig. 22 A cross-sectional view of a SiC MOSFET device according to another embodiment of the present application.

[0098] Description of reference numerals:

[0099] 10. Substrate; 11. First surface; 12. Second surface; 20. Epitaxial bottom layer; 21. Protective layer; 22. First epitaxial bottom layer; 23. Second epitaxial bottom layer; 30. Base layer; 40. Source layer; 50. Base junction; 60. Gate; 61. Groove; 62. Channel section; 63. Channel length reduction section; 64. Floating section; 65. Gate dielectric layer; 651. First dielectric layer; 652. Second dielectric layer; 66. Redefine channel initial layer; 67. SiN dielectric layer; 68. Mask; 70. Isolation layer; 80. Source; 90. Drain. DETAILED DESCRIPTION

[0100] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments for understanding the inventive concept of the present application, and cannot represent all the embodiments, nor are they interpreted as the only embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field on the premise of understanding the inventive concept of the present application are within the scope of protection of the present application.

[0101] It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application, the directional indications are only used to explain the relative position relationship and movement of the components in a certain posture. If the specific posture changes, the directional indications will also change accordingly. In order to facilitate the understanding of the technical solution of the present application, the field effect transistor structure and the manufacturing method thereof of the present application are further described and explained in detail below, but they are not limited to the scope of protection of the present application.

[0102] The failure of SiC MOSFET devices often starts with the failure of the gate oxide layer, so the reliability of the gate oxide layer plays a vital role in SiC MOSFET devices. The failure of the gate oxide layer is often manifested as a gradual increase in the leakage current of the device until breakdown occurs.

[0103] SiC material contains Si atoms, and can form SiO2 gate oxide film by thermal oxidation method. However, since it contains C atoms, it cannot completely turn into gas and leave the oxide layer during the actual thermal oxidation process, and the residual C will cause structural defects. In addition, since the barrier height of SiC to the conduction band of SiO2 is also low, all these make the interface trap charge in SiO2 / SiC system two orders of magnitude more than that in SiO2 / Si system.

[0104] This embodiment improves the reliability of the gate dielectric layer by using a gate dielectric layer with low lattice defects. In addition, the channel segment is used to prevent the electric field strength of the trench gate dielectric layer from being reduced, thereby avoiding premature breakdown of the trench gate dielectric layer.

[0105] See also Figure 1 and Figure 2 , a SiC MOSFET device provided in this embodiment includes a substrate 10, an epitaxial layer, a gate 60, a gate dielectric layer 65, an isolation layer 70, a source 80, a drain 90 and a redefined channel layer, wherein the epitaxial layer includes an epitaxial bottom layer 20, a protective layer 21, a base layer 30, a source layer 40 and a base junction 50, and the redefined channel layer includes a channel section 62, a channel length reduction section 63 and a floating section 64; wherein the conductivity type of the substrate 10, the epitaxial bottom layer 20, the source layer 40 and the channel length reduction section 63 is a first conductivity type, and the conductivity type of the base layer 30, the base junction 50, the gate 60, the channel section 62 and the floating section 64 is a second conductivity type. Specifically, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type. Preferably, the first conductivity type is N-type and the second conductivity type is P-type.

[0106] The substrate 10 has a first surface 11 and an opposite second surface 12 , wherein the epitaxial bottom layer 20 includes the epitaxial bottom layer 20 located on the first surface 11 of the substrate 10 , a base layer 30 located on the epitaxial bottom layer 20 , and a source layer 40 located on the base layer 30 .

[0107] The materials of the substrate 10 and the epitaxial bottom layer 20 are both SiC. The crystal plane of the substrate 10 is (0001). The inventors have found that the SiC material on this crystal plane is conducive to the growth of the epitaxial bottom layer 20, and can improve the interface characteristics of the substrate 10 and the epitaxial bottom layer 20. In addition, the epitaxial bottom layer 20 is grown 4° to 8° off-axis on the SiC substrate 10 with a crystal plane of (0001), which can further improve the interface characteristics of the substrate 10 and the epitaxial bottom layer 20. The thickness and doping concentration of the epitaxial bottom layer 20 are designed according to the requirements of the device, and are not specifically limited in this embodiment.

[0108] The base layer 30 is formed by implanting Al ions into the surface of the epitaxial bottom layer 20 by an ion implantation method. The conductivity type of the base layer 30 is opposite to that of the epitaxial bottom layer 20. In addition, in this embodiment, other ions may be implanted into the surface of the epitaxial bottom layer 20 to form a base layer 30 having a conductivity type opposite to that of the epitaxial bottom layer 20. The implantation energy, implantation dose and implantation depth of the ions determine the doping concentration and thickness of the base layer 30.

[0109] Preferably, the ion implantation energy of the base layer 30 is 30-400 kev, exemplified by 30 kev, 50 kev, 100 kev, 150 kev, 200 kev, 250 kev, 300 kev, 350 kev, 400 kev. More preferably, the ion implantation energy of the base layer 30 is 100-300 kev.

[0110] Preferably, the ion implantation dose of the base layer 30 is 1E13-9E14 cm -2 , exemplified by 1E13cm -2 、3E13cm -2 、5E13cm -2 、8E13cm -2 、1E14cm -2 、3E14cm -2 、5E14cm -2 、7E14cm -2 、9E14cm -2 Preferably, the ion implantation dose of the base layer 30 is 5E13-5E14 cm -2 .

[0111] Preferably, the ion implantation depth of the base layer 30 is 0.3-1 μm, exemplified by 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, and 1 μm. More preferably, the ion implantation dose of the base layer 30 is 0.5-0.8 μm.

[0112] It should be noted that the ions of the base layer 30 may be implanted at high temperature or at room temperature. Preferably, the implantation temperature of the ions of the base layer 30 is 400-500° C. or 15-35° C.

[0113] The protective layer 21 is located inside the epitaxial bottom layer 20 and the base layer 30, and is formed by implanting Al ions into the epitaxial bottom layer 20 by an ion implantation method. The conductivity type of the protective layer 21 is opposite to that of the epitaxial bottom layer 20. In addition, in this embodiment, other ions may be implanted into the epitaxial bottom layer 20 to form a protective layer 21 having a conductivity type opposite to that of the epitaxial bottom layer 20. The implantation energy, implantation dose, and implantation depth of the ions determine the doping concentration and thickness of the protective layer 21.

[0114] Preferably, the ion implantation energy of the protective layer 21 is 30-400 kev, exemplified by 30 kev, 50 kev, 100 kev, 150 kev, 200 kev, 250 kev, 300 kev, 350 kev, 400 kev. More preferably, the ion implantation energy of the protective layer 21 is 100-300 kev.

[0115] Preferably, the ion implantation dose of the protective layer 21 is 1E13-9E14 cm -2 , exemplified by 1E13cm -2 、3E13cm -2 、5E13cm -2 、8E13cm -2 、1E14cm -2 、3E14cm -2 、5E14cm -2 、7E14cm -2 、9E14cm -2 More preferably, the ion implantation dose of the protective layer 21 is 5E13-5E14 cm -2 .

[0116] Preferably, the ion implantation depth of the protective layer 21 is 0.3-1 μm, exemplified by 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, and 1 μm. More preferably, the ion implantation dose of the protective layer 21 is 0.5-0.8 μm.

[0117] It should be noted that the ions of the protective layer 21 may be implanted at high temperature or at room temperature. Preferably, the implantation temperature of the ions of the protective layer 21 is 400-500° C. or 15-35° C.

[0118] The source layer 40 is patterned by photolithography, and then ions are implanted at the surface of the base layer 30 corresponding to the source layer 40 to form a source layer 40 with the same conductivity type as the epitaxial base layer 20. Preferably, the ion implantation energy in the source layer 40 is 30-190 kev, and the implantation dose is 1E13-1E15 cm -2 .

[0119] The base junction 50 is located in the source layer 40 on the base layer 30 , so that the source layer 40 is patterned on the exposed surface of the epitaxial layer, wherein the base junction 50 does not extend to the trench opening of the trench 61 .

[0120] The base junction 50 is patterned by photolithography, and then ions are implanted at the position corresponding to the base junction 50 on the surface of the base layer 30 to form a base junction 50 with a conductivity type opposite to that of the epitaxial base layer 20. Preferably, the implantation energy of the ions in the base junction 50 is 30-190keV, and the implantation dose is 1E14-1E15 cm -2 .

[0121] In another embodiment of the present application, the epitaxial layer may not have a base junction.

[0122] Preferably, the base junction 50 is located directly above the protection layer 21 .

[0123] Specifically, the epitaxial bottom layer 20 is provided with a groove 61, the groove 61 penetrates along the source layer 40 and the base layer 30 and extends to the epitaxial bottom layer 20, the groove 61 has a groove bottom located in the epitaxial bottom layer 20, the upper opening width of the groove 61 is greater than the width of the lower groove bottom, and the angle between the two oblique side walls of the groove 61 and the groove side of the first surface 11 is between 50° and 70°. In this embodiment, the upper opening width of the groove 61 is greater than the width of the lower groove bottom, so that the angle between the two oblique side walls of the groove 61 and the groove side of the first surface 11 is between 50° and 70°, so that the SiC on the oblique side walls of the groove 61 can further form the following crystal planes: (0327), (0328), (0329), (0337), (0338) or (0339). Researchers have found that the etching rate of SiC material on the above crystal plane is slower than that of other crystal planes. Therefore, the crystal plane of the oblique sidewall of the trench 61 is the above crystal plane. The defect density of the gate dielectric layer 65 formed in the above crystal plane trench 61 can be as low as 1E10~1E11 cm -3 , thereby improving the electron mobility of the groove 61, thereby reducing the on-resistance of the device, and finally reducing the on-resistance per unit area of ​​the device.

[0124] It should be noted that after the groove 61 is formed, the epitaxial bottom layer 20 is formed with a redefined channel layer in accordance with the shape of the groove 61. The redefined channel layer includes a channel section 62 located at the upper part of the inclined side walls on both sides, a channel length reduction section 63 located at the lower part of one or both inclined side walls, and a floating section 64 located at the bottom of the groove.

[0125] In the related SiC MOSFET device, the base layer 30 generally defines the channel length before the groove is formed. In the present embodiment, the channel length is redefined after the groove is formed, so that the defect density of the gate oxide can be reduced.

[0126] Specifically, carriers can directly enter the base layer 30 through the channel length reducing section 63 , thereby reducing the channel length.

[0127] Preferably, the upper end of the channel length reducing section 63 extends to the height range of the base layer 30 .

[0128] Since the thickness of the base layer 30 depends on the product design requirements, that is, the thickness of the base layer 30 is predetermined as a common structure, based on the need to adjust the groove length, when the adjustment range is small, a groove length reduction section 63 can be provided at the lower part of the inclined side wall on one side of the groove, such as Fig. 22 When the adjustment range is large, a channel length reduction section 63 may be provided at the lower portion of the inclined side walls on both sides of the groove, such as Figure 1 As shown; in this way, SiC MOSFET devices with different channel lengths can be manufactured under the base layer 30 implanted in the public version.

[0129] In addition, since the implant thickness of the base layer 30 can tolerate a larger process error, a channel length reduction section 63 is provided at the lower portion of the inclined sidewalls on both sides of the trench, which can not only adjust the channel length but also stabilize the implant concentration of the channel section 62 .

[0130] The redefined channel layer of this embodiment can be formed by ion implantation, by implanting ions into the SiC surface of the bottom and the oblique sidewall of the trench 61; it can also be formed by depositing SiC. The redefined channel layer of this embodiment is used to resist the electric field of the DS pole reverse breakdown voltage, so as to reduce the electric field strength borne by the gate dielectric layer 65, protect the gate dielectric layer 65, prevent the gate dielectric layer 65 from being broken down in advance, and increase the breakdown voltage of the device.

[0131] In addition, the base layer 30 disposed on both sides of the trench 61 and having the same conductivity type as the gate 60 can also resist the electric field of the DS pole reverse breakdown voltage, effectively protecting the gate dielectric layer 65 and improving the reliability of the device.

[0132] The channel length reduction section 63 of the present embodiment can be formed by ion implantation in a preset area of ​​the channel section 62 by ion implantation. It can be formed on one side of the channel section 62 by unilateral ion implantation, or on both sides of the channel section 62 by bilateral ion implantation.

[0133] Preferably, the potential of the channel length reduction section 63 of this embodiment is the same as that of the base layer 30, and is connected between the epitaxial base layer 20 and the base layer 30. The channel length reduction section 63 of this embodiment can prevent the gate 60 from floating, which is beneficial to improving the dynamic characteristics of the device when there is no point floating.

[0134] The gate dielectric layer 65 of this embodiment is covered on the redefined channel layer, and includes a first dielectric layer 651 and a second dielectric layer 652, wherein the first dielectric layer 651 is arranged at the bottom of the trench 61, and the second dielectric layer 652 covers the oblique side walls on both sides of the trench 61 and is integrally connected to the first dielectric layer 651, so that the dielectric thickness on the bottom of the trench 61 is greater than the dielectric thickness on the oblique side walls on both sides, thereby eliminating the gate oxide effect at the bottom of the trench.

[0135] The gate 60 of the present embodiment is disposed in the trench 61 , and the bottom of the gate 60 is controlled within the height range of the channel length reduction section 63 .

[0136] Specifically, the gate 60 is made of polysilicon, whose conductivity type is opposite to that of the epitaxial bottom layer 20, and whose doping concentration is 10 18 ~10 20 ions / cm 3 Preferably, the doping concentration of the gate 60 may be the same as the doping concentration of the substrate 10 to improve the conduction performance of the gate 60 .

[0137] In order to prevent the corner of the gate dielectric layer 65 at the bottom of the groove 61 from being broken down prematurely when the SiC critical breakdown electric field is not reached, the second dielectric layer 652 of this embodiment covers the two side oblique side walls of the groove 61 and is integrally connected to the first dielectric layer 651, so that the dielectric thickness on the bottom of the groove 61 is greater than the dielectric thickness on the two side oblique side walls.

[0138] Preferably, the material of the first dielectric layer 651 is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and high-K materials; the material of the second dielectric layer 652 is selected from one or more of silicon oxide, aluminum oxide and high-K materials.

[0139] Through the cooperation of the materials of the trench 61, the redefined channel layer, the first dielectric layer 651 and the second dielectric layer 652, the defect density of the gate dielectric layer 65 of this embodiment is 1E10-1E11 cm -3 , which is significantly lower than the gate oxide of related technologies (generally 1E12cm -3 ), therefore, the gate dielectric layer 65 of this embodiment has a high breakdown voltage, is not easily broken down prematurely, and has high reliability.

[0140] In addition, in this embodiment, the first dielectric layer 651 and the second dielectric layer 652 cooperate to increase the thickness of the gate dielectric layer 65 at the bottom of the trench 61, thereby preventing the corner of the gate dielectric layer 65 of this embodiment from being broken down in advance, and further improving the reliability of the gate dielectric layer 65. In addition, in this embodiment, the first dielectric layer 651 is provided at the bottom of the gate 60, so that the gate dielectric layer 65 can withstand a higher electric field, while preventing the bottom gate dielectric layer 65 from being broken down or damaged by the electric field.

[0141] Preferably, the materials of the first dielectric layer 651 and the second dielectric layer 652 are selected from high-K materials. Under the same equivalent oxide layer thickness, the high-K material has a thicker material thickness, which can reduce the direct tunneling current between the gate and the trench 61. Specifically, the high-K material is hafnium dioxide or zinc oxide.

[0142] More preferably, the material of the first dielectric layer 651 is zinc peroxide, and the material of the second dielectric layer 652 is hafnium dioxide.

[0143] The isolation layer 70 is disposed on the gate 60 and is made of an insulating material to isolate the gate 60 from the source 80. The material of the isolation layer 70 is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric material, and low-k dielectric material. Preferably, the material of the isolation layer 70 is USG (uranium silicate glass) and / or BPSG (boron phospho-silicate glass). In this embodiment, the source 80 is disposed on the isolation layer 70, the source layer 40 and the base junction 50, and is made of metal.

[0144] The drain electrode 90 is disposed on the second surface of the substrate 10 and is also made of metal. Preferably, the metal material of the source electrode 80 and the drain electrode 90 is selected from one of Al, AlCu and AlSiCu.

[0145] This embodiment also provides a method for preparing a SiC MOSFET device, which is used to prepare the above-mentioned SiC MOSFET device, comprising the following steps:

[0146] S1, forming an epitaxial layer on a first surface of a substrate;

[0147] Specifically, the following steps are included:

[0148] S11, forming a first epitaxial bottom layer on the first surface of the substrate;

[0149] See also Figure 3 The substrate 10 has a first surface 11 and an opposite second surface 12. Specifically, a first epitaxial bottom layer 22 of SiC is formed on the SiC substrate 10 with a crystal plane of (0001) at an offset of 4° to 8°. Preferably, the conductivity type of the substrate 10 and the first epitaxial bottom layer 22 is N-type.

[0150] The inventors have found that the SiC material on this crystal plane is conducive to the growth of the first epitaxial bottom layer 22, and can improve the interface characteristics between the substrate 10 and the first epitaxial bottom layer 22. The thickness and doping concentration of the first epitaxial bottom layer 22 are designed according to the requirements of the device, and are not specifically limited in this embodiment.

[0151] S12, forming in the first epitaxial bottom layer

[0152] See also Figure 4 , photolithography defines the protection zone to form a photoresist, and after development, ions are implanted into the surface of the protection zone of the first epitaxial bottom layer 22 by an ion implantation method to form a protection layer 21 in the first epitaxial bottom layer 22, the implantation energy is 30-400 kev, and the total implantation dose is 1E13-9E14 cm -2The implantation depth is 0.3-1 μm, and the ion implantation temperature is 400-500° C. when high-temperature implantation is used, or 15-35° C. when low-temperature implantation is used. The implantation method may be a single implantation or multiple implantations.

[0153] Preferably, the implanted ions are Al ions, correspondingly forming a P-type protective layer 21 in the first epitaxial bottom layer 22 .

[0154] S13, forming a second epitaxial bottom layer on the first epitaxial layer and the protective layer;

[0155] See also Figure 5 A second epitaxial bottom layer 23 is formed on the original first epitaxial bottom layer 22 and the protective layer 21 , wherein the first epitaxial bottom layer 22 and the second epitaxial bottom layer 23 constitute an epitaxial bottom layer 20 .

[0156] Preferably, the thickness of the second epitaxial bottom layer 23 is 0.3-1 μm to ensure that the base layer 30 formed subsequently can be connected to the protective layer 21 .

[0157] S14, forming a base layer in the epitaxial bottom layer;

[0158] See also Figure 6 , photolithography is used to define the base layer area to form a photoresist, and after development, ions are implanted into the surface of the base layer area of ​​the second epitaxial bottom layer 23 by an ion implantation method to form a base layer 30 connected to the protective layer 21 in the epitaxial bottom layer 20, the implantation energy is 30-400kev, and the total implantation dose is 1E13-9E14 cm -2 The implantation depth is 0.3-1 μm, and the ion implantation temperature is 400-500° C. when high-temperature implantation is used, or 15-35° C. when low-temperature implantation is used. The implantation method may be a single implantation or multiple implantations.

[0159] Preferably, the implanted ions are Al ions, corresponding to forming a P-type base layer 30 in the second epitaxial bottom layer 23 .

[0160] S15, forming a source layer in the base layer;

[0161] See also Figure 7 , the source region is defined by photolithography to form a photoresist (not shown in the figure), and after development, ions are implanted into the surface of the source region of the base layer 30 by an ion implantation method to form a source layer 40 in the base layer 30, with an implantation energy of 30-190kev and a total implantation dose of 1E13-9E15 cm -2 The injection method may be a single injection or multiple injections.

[0162] Preferably, the implanted ions are P ions, correspondingly forming an N-type source layer 40 in the base layer 30 .

[0163] See also Figure 7 , while defining the source region by photolithography, the base region is defined. After the source layer is formed, the photoresist is removed, and ions are implanted into the surface of the base layer 30 outside the source region by ion implantation to form a base junction 50 in the base layer 30. The implantation energy is 30~190kev, and the total implantation dose is 1E14~1E15 cm -2 The injection method may be a single injection or multiple injections.

[0164] Preferably, the implanted ions are Al ions, corresponding to forming a P-type base junction 50 in the base layer 30 .

[0165] S16, forming a groove;

[0166] Specifically, the following steps are included:

[0167] S161, forming a vertical groove;

[0168] See also Figure 8 , forming a SiO2 mask of 5000~30000 angstroms (not shown in the figure), defining the groove area by photolithography, using plasma to etch the source layer 40 and the epitaxial bottom layer 20, forming a vertical groove 61 with a depth of 0.5~2μm, and the first etching gas used is SF6, or a mixed gas of SF6 and O2.

[0169] The trench 61 penetrates the source layer 40 and the base layer 30 and extends to the epitaxial bottom layer 20 . The trench 61 has a bottom located in the epitaxial bottom layer 20 .

[0170] S162, forming an inverted trapezoidal groove;

[0171] See also Fig. 9 The inclined sidewalls of the groove 61 are etched by plasma to form an inverted trapezoidal groove 61 whose upper opening width is greater than the width of the lower groove bottom. The angle between the inclined sidewalls on both sides of the groove 61 and the groove side of the first surface 11 is between 50° and 70°. The second etching gas used is selected from a mixed gas of Cl2 and O2, a mixed gas of BCl3 and O2, a mixed gas of SF6 and O2, or a mixed gas of CF4 and O2. The etching temperature is 800~1000℃.

[0172] In this embodiment, a two-step etching method is used to firstly etch a vertical groove 61 , and then plasma is used to etch the inclined sidewall of the groove 61 to obtain an inverted trapezoidal groove 61 with high precision and little loss.

[0173] In addition, in the second etching process, the present embodiment uses a second etching gas to etch the oblique sidewalls of the groove 61. By utilizing the characteristics of the second etching gas and the SiC material, it is found that the etching rate of the SiC material crystal plane (0327), (0328), (0329), (0337), (0338) or (0339) is slower than the etching rate of other crystal planes, thereby forming the oblique sidewalls of the groove 61 of the above crystal planes. Since the SiC material of the above crystal planes has a relatively low interface state, when the gate dielectric layer 65 is subsequently formed, the defect density of the gate dielectric layer 65 can be reduced, and at the same time, the electron mobility of the groove 61 is improved, thereby reducing the on-resistance of the device.

[0174] Preferably, the second etching gas is a mixed gas of Cl2 and O2, and the gas flow rate ratio of Cl2 to O2 is (1~2):1.

[0175] S2, forming a redefinition channel initial layer;

[0176] See also Fig.10 , the protection zone is defined by photolithography, and ions are implanted into the oblique sidewalls and bottom of the trench 61 by ion implantation to form a redefinition channel initial layer 66, with an implantation energy of 30-400 kev and a total implantation dose of 1E12-9E13 cm -2 The implantation depth is 0.1-0.5 μm, and the ion implantation temperature is 400-500° C. when high-temperature implantation is used, or 15-35° C. when low-temperature implantation is used. The implantation method may be a single implantation or multiple implantations.

[0177] Preferably, the implanted ions are Al ions, correspondingly forming a P-type redefinition channel initial layer 66 in the SiC at the slanted sidewalls and bottom of the trench 61 .

[0178] Preferably, the ion implantation angle of the inclined sidewall of the trench 61 is 0-40°, which can ensure the thickness uniformity of the redefinition channel initial layer 66 .

[0179] Preferably, after forming the redefined channel initial layer 66, the following steps are also included: high temperature annealing is performed on the redefined channel initial layer 66 to activate Al ions in the redefined channel initial layer 66, the annealing temperature is 1500~1900℃, the annealing time is 10~60min, and the annealing atmosphere is argon or nitrogen.

[0180] Since the trench 61 will have losses and a rough surface during the etching process, if Al ions are directly implanted into the trench 61 , the quality of the redefined channel initial layer 66 will be affected.

[0181] Preferably, before forming the redefined channel initial layer 66, a sacrificial oxide layer (not shown in the figure) is formed on the bottom and oblique sidewalls of the trench 61 by thermal oxidation, the thickness of the sacrificial oxide layer is 200-1000 angstroms, and the growth temperature is 800-1200°C; the sacrificial oxide layer is removed by wet etching. Forming the sacrificial oxide layer before forming the redefined channel initial layer 66 and then removing it can reduce defects formed by etching the trench 61, reduce the roughness of the surface of the trench 61, and improve the formation quality of the redefined channel initial layer 66.

[0182] In this embodiment, Al ions are implanted into the oblique sidewalls and the bottom of the groove 61 to form a redefined channel initialization layer 66. The method is simple. Since the implantation dose of Al ions is high, its doping concentration is higher than the doping concentration of the base layer 30. In addition, in this embodiment, by performing high-temperature annealing on the redefined channel initialization layer 66, damage can be reduced and the electron mobility of the redefined channel initialization layer 66 can be improved. The redefined channel initialization layer 66 formed by this method effectively reduces the electric field strength borne by the gate dielectric layer 65, plays a role in protecting the gate dielectric layer 65, further avoids the gate dielectric layer 65 from being broken down prematurely, and increases the breakdown voltage of the device.

[0183] S3, forming a redefined channel layer and a gate dielectric layer;

[0184] Specifically, the following steps are included:

[0185] S31, forming a first dielectric layer;

[0186] See also Fig.11 The first dielectric layer 651 covers the redefinition channel initial layer 66 and the surface outside the trench 61 (the source layer 40 and the base junction 50). The preparation method of the first dielectric layer 651 includes the following three methods:

[0187] The first method is to deposit one or more materials selected from the group consisting of high-K material, silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide at the bottom of the trench 61 by a deposition method to form a first dielectric layer 651 with a thickness of 600 to 2000 angstroms;

[0188] The second method is to deposit single crystal silicon at the bottom of the trench 61 by a deposition method, and then to form silicon oxide by a thermal oxidation method to form a first dielectric layer 651 with a thickness of 600-2000 angstroms.

[0189] In order to use the first dielectric layer 651 as a photoresist to form a channel length reduction section 63 in the redefinition channel initial layer 66, the following steps are also included:

[0190] The first dielectric layer 651 on the oblique sidewall of the trench 61 is etched to reduce the thickness of the first dielectric layer 651 on the oblique sidewall of the trench 61 to 300-900 angstroms.

[0191] S32, forming a redefinition channel layer;

[0192] Specifically, the following steps are included:

[0193] See also Fig.12 , depositing a SiN dielectric layer 67 with a thickness of 2000-10000 angstroms on the first dielectric layer 651;

[0194] See also Fig.13 , photolithography defines the etching area of ​​the SiN dielectric layer 67 through the mask 68, and then develops and etches the etching area of ​​the SiN dielectric layer 67;

[0195] The etched area of ​​the SiN dielectric layer 67 is located on one side or both sides of the SiN dielectric layer 67, and the etched area cannot completely leak out of the base layer 30;

[0196] See also Fig.14 , the first dielectric layer 651 used as a photoresist exposed in the etched area of ​​the SiN dielectric layer 67 is removed, and the preset area of ​​the redefining channel initial layer 66 is exposed; in other embodiments of the present application, the first dielectric layer 651 used as a photoresist exposed in the etched area of ​​the SiN dielectric layer 67 can be removed after the channel length reduction section 63 is formed.

[0197] See also Fig.15 ion implantation is used to implant ions into a preset region of the initial layer of the redefined channel to form a channel length reduction section 63, with an implantation energy of 30-190 kev and a total implantation dose of 1E12-9E14 cm -2 The injection method may be a single injection or multiple injections.

[0198] It should be noted that the redefined channel initial layer 66 located on the upper part of the inclined side walls on both sides is the channel section 62, and the redefined channel initial layer 66 located at the bottom of the groove is the floating section 64, wherein the channel section 62, the channel length reduction section 63 and the floating section 64 constitute the redefined channel layer, and the redefined channel layer of the present application is formed in accordance with the shape of the groove 61.

[0199] Preferably, the implanted ions are P ions, correspondingly forming an N-type channel length reduction section 63 in the redefined channel initial layer 66 .

[0200] Preferably, the ion implantation angle of the oblique sidewall of the redefined channel initial layer 66 is 20°-40°, so as to ensure that the ions are implanted into a predetermined area of ​​the redefined channel initial layer 66 .

[0201] The channel length reduction section 63 is subjected to high temperature annealing to activate P ions in the channel length reduction section 63 . The annealing temperature is 1500-1900° C., the annealing time is 10-60 minutes, and the annealing atmosphere is argon or nitrogen.

[0202] See also Fig.16 , removing the SiN dielectric layer 67 and the first dielectric layer 651 used as a photoresist on the oblique sidewalls of the trench 61, and retaining the first dielectric layer 651 on the bottom of the trench 61, the source layer 40 and the base junction 50;

[0203] S43, forming a second dielectric layer;

[0204] See also Fig.17 The second dielectric layer 652 covers the redefined channel layer and the surface outside the trench 61 (the source layer 40 and the base junction 50). The preparation method of the first dielectric layer 651 includes the following three methods:

[0205] The first method is to deposit one or more materials selected from high-K material, silicon oxide and aluminum oxide on the bottom and the inclined sidewall of the trench 61 by a deposition method to form a second dielectric layer 652 with a thickness of 400 to 1200 angstroms;

[0206] The second method is to deposit single crystal silicon on the bottom and the inclined sidewall of the trench 61 by a deposition method, and then to form silicon oxide by a thermal oxidation method at an oxidation temperature of 600-900° C. to form a second dielectric layer 652 with a thickness of 400-1200 angstroms;

[0207] The third method is to use a thermal growth method to form an oxide layer with a thickness of 400~1200 angstroms on the bottom and inclined side walls of the groove 61, with a growth temperature of 1100~1400℃, and then annealing is performed in an atmosphere of nitrogen or phosphorus at a temperature of 1100~1300℃, and finally a secondary annealing is performed in an argon atmosphere at a temperature of 1100~1300℃ to form a second dielectric layer 652.

[0208] In this embodiment, the three preparation methods of the second dielectric layer 652 can effectively reduce the defect density of the gate dielectric layer 65 .

[0209] It should be noted that the smaller the defect density of the gate dielectric layer 65, the lower the degree of carrier scattering, the greater the mobility of the device, the smaller the resistivity, the smaller the power consumption and the greater the current carrying capacity when the same current passes through. Among them, the key to determining the life of the gate dielectric layer 65 lies in the oxide layer structural defects caused by heavy ions in the gate dielectric layer 65.

[0210] Specifically, 1. a high-K material is deposited by a deposition method to form the second dielectric layer 652, which can reduce the vacancy density and defects in the film; 2. a single crystal silicon is first formed by a deposition method and then oxidized to form silicon oxide to form the second dielectric layer 652, and low-temperature oxidation at 600-900° C. can reduce the vacancy density and defects in the film; 3. a second dielectric layer 652 is formed by a thermal growth method, which helps to ensure the uniformity of the second dielectric layer 652 and is beneficial to improving device performance; a high-temperature annealing is performed to passivate the first or second dielectric layer 652 and the At the interface between the epitaxial bottom layer 20 and the base layer 30, during the annealing process, nitrogen or phosphorus can diffuse to the interface between the first or second dielectric layer 652 and the epitaxial bottom layer 20 and the base layer 30 to fill the interface dangling bonds or compensate for the charges, thereby reducing the interface state density and improving the carrier mobility; at the same time, annealing also helps to eliminate the lattice defects of the first or second dielectric layer 652 itself to further improve its density, which helps to form a good protection for the gate 60 and prevent impurity atoms in subsequent processes from diffusing into the gate 60, resulting in an increase in the resistance of the gate 60.

[0211] It should be noted that, in other embodiments, after forming the redefined channel initial layer 66, the channel length reduction section 63 can be formed in the preset area of ​​the redefined channel initial layer 66 by photolithography to define the protection area, form a photoresist, etc., and then form the first dielectric layer 651 and the second dielectric layer 652, that is, after step 3 is completed, step S42 is performed first, and then steps S61 and S43 are performed, wherein the steps of forming the first dielectric layer 651 and the second dielectric layer 652 may need to be slightly adjusted. In addition, in other embodiments, the steps of forming the first dielectric layer 651 and the second dielectric layer 652 can also be interchanged.

[0212] S4, forming a gate in the trench;

[0213] Specifically, the following steps are included:

[0214] S41, see Fig.18 , polysilicon is deposited in the trench 61 by LPCVD, and then ions are doped or implanted by in-situ method to form a gate 60 having a conductivity type opposite to that of the epitaxial bottom layer 20, and the doping concentration of the gate 60 is 10 18 ~10 20 ions / cm 3 , with a thickness of 1000~1500 angstroms.

[0215] S42, see Fig.19 The top gate 60 and gate dielectric layer 65 are removed by etching or planarization (CMP) to expose the source layer 40 and base junction 50.

[0216] Preferably, the upper surface of the gate 60 in the trench 61 is lower than the upper surface of the source layer 40 and the base junction 50, so as to facilitate the subsequent formation of the isolation layer 70. More preferably, the upper surface of the gate 60 in the trench 61 is 10-1000 angstroms lower than the upper surface of the source layer 40 and the base junction 50.

[0217] S5, forming an isolation layer;

[0218] See also Fig. 20 An isolation layer 70 is formed on the gate 60 by high-density plasma deposition, and then the isolation layer 70 outside the gate 60 is etched away by photolithography to expose the source layer 40 and the base junction 50.

[0219] S6, forming a source and a drain;

[0220] See also Fig.21 , depositing metal on the surfaces of the isolation layer 70, the source layer 40 and the base junction 50 to form a source 80; thinning the substrate 10, and depositing metal on the second surface of the substrate 10 to form a drain 90. Preferably, the metal material of the source 80 and the drain 90 is selected from one of Al, AlCu and AlSiCu.

Claims

1. A SiC MOSFET device, characterized in that: include: A substrate (10) having a first surface (11) and an opposite second surface (12); An epitaxial layer is provided on the first surface (11) of the substrate (10), the epitaxial layer comprising an epitaxial bottom layer (20), a base layer (30) located on the epitaxial bottom layer (20), a source layer (40) located on the base layer (30), and a protective layer (21) located within the epitaxial bottom layer (20) and the base layer (30), wherein the protective layer (21) is located between the grooves (61) and is used to introduce a new electric field peak to shield the electric field of the gate dielectric layer; the epitaxial layer is provided with a groove (61) The groove (61) penetrates the source layer (40) and the base layer (30) and extends to the epitaxial bottom layer (20), the groove (61) has a groove bottom located in the epitaxial bottom layer (20), the upper opening width of the groove (61) is greater than the width of the lower groove bottom, and the angle between the inclined side walls on both sides of the groove (61) and the groove side of the first surface (11) is between 50° and 70°, so as to reduce the defect density of the gate dielectric layer in the groove, and also to improve the carrier mobility of the groove and reduce the on-resistance; The epitaxial layer is formed with a redefined channel layer in accordance with the shape of the groove (61), the redefined channel layer comprising a channel section (62) located at the upper part of the inclined side walls on both sides, a channel length reduction section (63) located at the lower part of one or both inclined side walls, and a floating section (64) located at the bottom of the groove, the redefined channel layer is used to redefine the channel length to reduce the defect density of the gate dielectric layer; a gate dielectric layer (65) covering the redefined channel layer; A gate (60) disposed in the trench (61), wherein the bottom of the gate (60) is controlled to be within the height range of the channel length reduction section (63); The epitaxial layer further comprises a base junction (50), the base junction (50) being located in the source layer (40) on the base layer (30), so that the source layer (40) is patterned on the exposed surface of the epitaxial layer, the base junction (50) does not extend to the groove opening of the groove (61), and is located directly above the protective layer (21); The conductivity type of the substrate (10), the epitaxial bottom layer (20), the source layer (40) and the channel length reduction section (63) is a first conductivity type, the conductivity type of the base layer (30), the base junction (50), the gate (60), the channel section (62) and the floating section (64) is a second conductivity type, and the conductivity type of the protective layer (21) is opposite to the conductivity type of the epitaxial bottom layer (20); the upper end of the channel length reduction section (63) extends to the height range of the base layer (30).

2. The SiC MOSFET device according to claim 1, wherein: The SiC MOSFET device further comprises: an isolation layer (70) disposed on the gate (60); a source electrode (80) disposed on the isolation layer (70) and the epitaxial layer; A drain electrode (90) disposed on the second surface (12) of the substrate (10); The crystal plane of the inclined side wall of the groove (61) is (0327), (0328), (0329), (0337), (0338) or (0339).

3. The SiC MOSFET device according to claim 1 or 2, characterized in that: The gate dielectric layer (65) comprises a first dielectric layer (651) and a second dielectric layer (652), wherein the first dielectric layer (651) is arranged at the bottom of the groove (61), and the second dielectric layer (652) covers the oblique side walls on both sides of the groove (61) and is integrally connected to the first dielectric layer (651), so that the dielectric thickness at the bottom of the groove (61) is greater than the dielectric thickness at the oblique side walls on both sides; The first dielectric layer (651) of the gate dielectric layer (65) has a defect density of 1E10-1E11 cm -3 ; The material of the first dielectric layer (651) is selected from silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide; the material of the second dielectric layer (652) is selected from silicon oxide or aluminum oxide; The thickness of the first dielectric layer (651) is 600 to 2000 angstroms, and the thickness of the second dielectric layer (652) is 400 to 1200 angstroms.

4. A method for preparing a SiC MOSFET device, for preparing a SiC MOSFET device as claimed in any one of claims 1 to 3, characterized in that: The following steps are involved: An epitaxial layer is formed on a first surface (11) of a substrate (10), the epitaxial layer comprising an epitaxial bottom layer (20), a base layer (30) located on the epitaxial bottom layer (20), a source layer (40) located on the base layer (30), and a protective layer (21) located in the epitaxial bottom layer (20) and the base layer (30), the epitaxial layer is provided with a groove (61), the groove (61) penetrates the source layer (40) and the base layer (30) and extends to the epitaxial bottom layer (20), the groove (61) has a groove bottom located in the epitaxial bottom layer (20), the upper opening width of the groove (61) is greater than the width of the lower groove bottom, the angle between the inclined side walls on both sides of the groove (61) and the groove side of the first surface (11) is between 50° and 70°, and the protective layer (21) is located between the grooves (61); A redefined channel layer, a gate dielectric layer (65) and a gate electrode (60) are formed in the trench (61), wherein the redefined channel layer comprises a channel section (62) located at the upper part of the oblique sidewalls on both sides, a channel length reduction section (63) located at the lower part of one or both oblique sidewalls, and a floating section (64) located at the bottom of the trench, and the gate dielectric layer (65) covers the redefined channel layer and wraps the gate electrode (60); forming an isolation layer (70) on the gate (60); forming a source electrode (80) on the isolation layer (70) and the source electrode layer (40); A drain electrode (90) is formed on the second surface (12) of the substrate (10).

5. The method for preparing a SiC MOSFET device according to claim 4, characterized in that: The method for forming the epitaxial layer comprises the following steps: Forming a first epitaxial bottom layer (22) on the first surface (11) of the substrate (10); Ions are implanted into the surface of the first epitaxial bottom layer (22) by an ion implantation method to form the protective layer (21) in the first epitaxial bottom layer (22), the implantation energy being 30 to 400 kev and the implantation dose being 1E13 to 9E14 cm -2 , the implantation depth is 0.3 to 1 μm, the ion implantation temperature is 400 to 500° C. when high temperature implantation is used, or the ion implantation temperature is 15 to 35° C. when low temperature implantation is used; forming a second epitaxial bottom layer (23) on the first epitaxial bottom layer (22) and the protective layer (21), wherein the first epitaxial bottom layer (22) and the second epitaxial bottom layer (23) constitute the epitaxial bottom layer (20); Ions are implanted into the surface of the second epitaxial bottom layer (23) by an ion implantation method, so as to form the base layer (30) connected to the protective layer (21) in the second epitaxial bottom layer (23), wherein the ion implantation energy is 30 to 400 kev and the implantation dose is 1E13 to 9E14 cm -2 , the injection depth is 0.3~1μm; Ions are implanted into the surface of the base layer (30) by an ion implantation method to form a source electrode layer (40) in the base layer (30), the implantation energy is 30 to 190 keV, and the total implantation dose is 1E13 to 9E15 cm -2 .

6. The method for preparing a SiC MOSFET device according to claim 5, characterized in that: The method for opening the groove (61) comprises the following steps: The source layer (40), the base layer (30) and the epitaxial bottom layer (20) are etched by plasma to form a vertical groove (61), wherein the bottom of the groove (61) is located in the epitaxial bottom layer (20), and the first etching gas used is SF6, or a mixed gas of SF6 and O2; The sidewalls of the vertical groove (61) are etched by plasma to form an inverted trapezoidal groove (61) whose upper opening width is greater than the lower groove bottom width, and the angle between the inclined sidewalls on both sides of the groove (61) and the groove side of the first surface (11) is between 50° and 70°. The second etching gas used is selected from a mixed gas of Cl2 and O2, a mixed gas of BCl3 and O2, a mixed gas of SF6 and O2, and a mixed gas of CF4 and O2, and the etching temperature is 800 to 1000°C.

7. The method for preparing a SiC MOSFET device according to claim 6, characterized in that: The method for forming a redefined channel layer comprises the following steps: Ions are implanted into the bottom and the oblique sidewall of the trench (61) by an ion implantation method to form a redefinition channel initial layer (66), the implantation energy is 30-400kev, and the implantation dose is 1E12-9E13 cm -2 , the implantation depth is 0.1 to 0.5 μm, the ion implantation temperature is 400 to 500° C. when high temperature implantation is used, or the ion implantation temperature is 15 to 35° C. when low temperature implantation is used; Performing high temperature annealing on the redefined channel initial layer (66) to activate ions in the redefined channel initial layer (66), the annealing temperature is 1500-1900° C., the annealing time is 10-60 minutes, and the annealing atmosphere is argon or nitrogen; The formation area of ​​the channel length reduction section (63) is defined by photolithography, and ions are implanted into a preset area of ​​the redefined channel initial layer by an ion implantation method to form the channel length reduction section (63), the implantation energy is 30 to 190 keV, and the total implantation dose is 1E12 to 9E14 cm -2 ; The redefined channel initial layer (66) located on the upper part of the inclined side walls on both sides is the channel section (62), and the redefined channel initial layer (66) located at the bottom of the groove is the floating section (64), wherein the channel section (62), the channel length reduction section (63) and the floating section (64) constitute the redefined channel layer.

8. The method for preparing a SiC MOSFET device according to claim 7, characterized in that: The method for forming the gate dielectric layer (65) comprises the following steps: A first dielectric layer (651) is formed, wherein the method for forming the first dielectric layer (651) comprises: Depositing silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide at the bottom of the trench (61) by a deposition method to form a first dielectric layer (651) with a thickness of 600 to 2000 angstroms; or, Depositing single crystal silicon at the bottom of the groove (61) by a deposition method, and then forming silicon oxide from the single crystal silicon by a thermal oxidation method to form a first dielectric layer (651) with a thickness of 600 to 2000 angstroms; A second dielectric layer (652) is formed, wherein the method for forming the second dielectric layer (652) comprises: Depositing silicon oxide or aluminum oxide on the bottom and the inclined sidewall of the trench (61) by a deposition method to form a second dielectric layer (652) with a thickness of 400 to 1200 angstroms; or, Depositing single crystal silicon on the bottom and the oblique sidewall of the trench (61) by a deposition method, and then forming silicon oxide from the single crystal silicon by a thermal oxidation method at an oxidation temperature of 600 to 900° C. to form a second dielectric layer (652) with a thickness of 400 to 1200 angstroms; or, Forming an oxide layer with a thickness of 400 to 1200 angstroms on the bottom and the oblique sidewalls of the trench (61) by a thermal growth method at a growth temperature of 1100 to 1400° C., then annealing in a nitrogen or phosphorus atmosphere at a temperature of 1100 to 1300° C., and finally performing a secondary annealing in an argon atmosphere at a temperature of 1100 to 1300° C., so as to form the second dielectric layer (652); The growth order of the first dielectric layer (651) and the second dielectric layer (652) can be swapped.

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