Semiconductor device and method for forming the same

Abstract

A semiconductor device and a method for forming the same, wherein the semiconductor device comprises: a substrate; a gate structure located on the substrate and comprising a first region and a second region, wherein the gate structure length of the first region is greater than the gate structure length of the second region; a segment located within the gate structure of the first region, wherein the top surface of the segment is higher than the top surface of the gate structure; and a segment formed within the gate structure, wherein the top surface of the segment is higher than the top surface of the gate structure. In this way, when a metal layer is subsequently formed on the gate structure as an interconnection layer, the short circuit problem between the metal layer and the gate structure is solved, thereby improving the quality of the formed semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] The electronics industry is constantly moving toward smaller and faster electronic devices, which can simultaneously support a greater number of increasingly complex and sophisticated functions. Consequently, a continuing trend in the semiconductor industry is toward manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down semiconductor IC sizes (e.g., minimum feature size (CD)) to increase production efficiency and reduce associated costs. However, this scaling down also increases the complexity of semiconductor manufacturing processes. Consequently, continued advancements in semiconductor ICs and devices require simultaneous advancements in semiconductor manufacturing processes and technologies.

[0003] As part of the device, the gate structure's material significantly impacts device performance. Traditional polysilicon gate processes suffer from the "polysilicon depletion" effect, which affects device conduction. Therefore, metal gates were introduced. After the metal gates were introduced, an interconnect metal layer needed to be formed on top of them to establish electrical connections with the outside world.

[0004] However, in the prior art, problems such as short circuits are easily generated between the interconnected metal layer and the metal gate, and the quality of the formed semiconductor device needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, by forming a segment in the gate structure, the top surface of the segment is higher than the top surface of the gate structure, so that when a metal layer is subsequently formed on the gate structure as an interconnection layer, the short circuit problem between the metal layer and the gate structure is solved, thereby improving the quality of the formed semiconductor device.

[0006] To solve the above problems, the present invention provides a semiconductor device, comprising: a substrate; a gate structure located on the substrate, comprising a first region and a second region, wherein the gate structure length of the first region is greater than the gate structure length of the second region; a segmentation segment located within the gate structure of the first region, wherein the top surface of the segmentation segment is higher than the top surface of the gate structure.

[0007] Optionally, a top surface of the segment is 10 nanometers to 50 nanometers higher than a top surface of the gate structure.

[0008] Optionally, the material of the dividing segment is silicon nitride, silicon oxide or silicon oxynitride.

[0009] Optionally, the base includes a substrate and a plurality of fins located on the substrate, and the fins include a sparse area and a dense area.

[0010] Optionally, the gate structure is located on the substrate and spans the fins, the gate structure in the first region is located between the fins in the sparse region, and the gate structure in the second region is located between the fins in the dense region.

[0011] Optionally, the method further includes: an isolation layer, wherein the isolation layer is located on the substrate and covers a portion of the sidewall of the fin.

[0012] Optionally, the method further includes: a dielectric layer, wherein the dielectric layer is located on the top surface of the gate structure and on the sidewalls and top surface of the segment that are higher than the gate structure.

[0013] Optionally, it further includes: a hard mask layer, the hard mask layer is located on the top surface of the gate structure, the dielectric layer is located on the top surface of the hard mask layer and is located on the sidewalls and top surface of the segment higher than the hard mask layer.

[0014] Optionally, the method further includes: a metal layer, wherein the metal layer is located in the dielectric layer, and the bottom surface of the metal layer contacts the top surface of the gate structure at one side of the segment.

[0015] Correspondingly, the present invention also provides a method for forming a semiconductor device, comprising: providing a substrate, forming a gate structure on the substrate, the gate structure comprising a first region and a second region, the gate structure length of the first region being greater than the gate structure length of the second region; forming a sacrificial layer on the gate structure; etching the sacrificial layer and the gate structure of the first region at the bottom of the sacrificial layer to expose the surface of the substrate, forming a first opening in the gate structure of the first region and the sacrificial layer; forming a segment in the first opening, the segment filling the first opening; and removing the sacrificial layer.

[0016] Optionally, the material of the sacrificial layer is amorphous silicon, amorphous carbon or amorphous germanium.

[0017] Optionally, the sacrificial layer has a thickness of 10 nanometers to 50 nanometers.

[0018] Optionally, the process of forming the segmented segments includes an atomic layer deposition process or a chemical vapor deposition process.

[0019] Optionally, the material of the dividing segment is silicon nitride, silicon oxide or silicon oxynitride.

[0020] Optionally, the base includes a substrate, and a plurality of discretely arranged fins are formed on the substrate, wherein the fins include a sparse area and a dense area.

[0021] Optionally, the gate structure is formed on the substrate and spans the fins, the gate structure in the first region is located between the fins in the sparse region, and the gate structure in the second region is located between the fins in the dense region.

[0022] Optionally, after forming the fin and before forming the gate structure, the method further includes: forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the sidewall of the fin.

[0023] Optionally, after removing the sacrificial layer, the method further includes: forming a dielectric layer on the top surface of the gate structure and on the top and part of the sidewall of the segment.

[0024] Optionally, the method further includes: forming a hard mask layer on the top surface of the gate structure before forming the sacrificial layer.

[0025] Optionally, after forming the dielectric layer, it also includes: etching the dielectric layer to form a second opening in the dielectric layer, the bottom of the second opening exposing the side wall surface, part of the top surface and part of the top surface of the gate structure at the side wall surface on one side of the segmentation segment.

[0026] Optionally, after forming the second opening, the method further includes forming a metal layer, wherein the metal layer completely fills the second opening.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] The semiconductor device of the present invention forms a segment within the gate structure, and the top surface of the segment is higher than the top surface of the gate structure. When a metal layer is subsequently formed on the gate structure in the first area on one side of the segment as an interconnection layer, the distance between the gate structure in the first area on the other side of the segment and the metal layer is increased. Since the top surface of the segment is higher than the top surface of the gate structure, the distance between the metal layer and the gate structure on the other side of the segment is increased, thereby reducing the probability of a short circuit between the metal layer and the gate structure, thereby improving the performance stability and quality of the formed semiconductor device, and helping to expand the scope of use of the semiconductor device.

[0029] In the method for forming a semiconductor device of the present invention, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure includes a first region and a second region, the gate structure length of the first region is greater than the gate structure length of the second region, a sacrificial layer is formed on the gate structure, the sacrificial layer and the gate structure of the first region at the bottom of the sacrificial layer are etched until the surface of the substrate is exposed, a first opening is formed in the gate structure of the first region, a segment is formed in the first opening, the segment fills the first opening, and then the sacrificial layer is removed; a sacrificial layer is formed on the gate structure, and then the sacrificial layer and the structure at the bottom of the sacrificial layer are etched to form the first opening, a segment is formed in the first opening, the segment fills the first opening, so that after the sacrificial layer is removed, the top surface of the formed segment is higher than the top surface of the gate structure, so that when a metal layer is subsequently formed on the gate structure of the first region on one side of the segment and located in the interconnection layer, the distance between the gate structure of the first region on the other side of the segment and the metal layer is increased, thereby avoiding a short circuit between the gate structure and the metal layer, thereby enhancing the performance and improving the quality of the formed semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 7 It is a schematic diagram of the cross-sectional structure of each step in the formation process of a semiconductor device;

[0031] Figures 8 to 18 1 is a schematic diagram of the cross-sectional structure of each step of the first embodiment of the semiconductor device and the method for forming the same according to the present invention;

[0032] Figure 19 It is a schematic diagram of the cross-sectional structure of each step of the second embodiment of the semiconductor device and the method for forming the same according to the present invention. DETAILED DESCRIPTION

[0033] In the prior art, when a metal layer is formed as an interconnect layer on the gate structure on one side of a segment, a short circuit easily occurs between the gate structure and the metal layer on the other side of the segment, thereby reducing the performance of the semiconductor device. This will be described in detail below with reference to the accompanying drawings.

[0034] Figures 1 to 7 It is a schematic structural diagram of each step in the formation process of a semiconductor device.

[0035] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 A top view of Figure 2 yes Figure 1 A cross-sectional view along line AA is provided. A substrate 100 is provided. A gate structure 130 is formed on the substrate 100 . The gate structure 130 includes a first region 131 and a second region 132 . The gate structure length of the first region 131 is greater than the gate structure length of the second region 132 .

[0036] The base 100 includes a substrate 110 and a plurality of fins 120 located on the substrate 110 . The fins 120 are distributed in a sparse area 121 and a dense area 122 .

[0037] The gate structure 130 spans the fins 120 . The gate structure in the first region 131 is located between the fins in the sparse region 121 , and the gate structure in the second region 132 is located between the fins in the dense region 122 .

[0038] The gate structure length refers to the gate structure distance between adjacent fins, which is perpendicular to the extending direction of the fins.

[0039] Please refer to Figure 3 A first opening 140 is formed in the gate structure 130 in the first region 131 . The first opening 140 penetrates the gate structure 130 along a substrate normal direction, and the bottom of the first opening 140 exposes the surface of the substrate 110 .

[0040] The first opening 140 is located between adjacent fins 120 in the sparse region 121 .

[0041] Please refer to Figure 4 The first opening 140 is filled with a partition layer material, and the surface of the partition layer is planarized to form a partition segment 150 . The top surface of the partition segment 150 is flush with the top surface of the gate structure 130 .

[0042] Please refer to Figure 5 , a dielectric layer 160 is formed on the gate structure 130 and the segment 150 .

[0043] Please refer to Figure 6 , the dielectric layer 160 is etched to expose the top surface of the gate structure 130 on one side of the segment 150 , and a second opening 170 is formed in the dielectric layer 160 , the bottom of the second opening 170 also exposes a portion of the top of the segment 150 .

[0044] Please refer to Figure 7 A metal layer 180 is formed in the second opening 170 , and the metal layer 180 serves as an interconnection layer to subsequently form an electrical connection with the outside.

[0045] The inventors discovered that in the semiconductor device formed by this method, the distance d between the metal layer 180 and the gate structure 130 on the other side of the segment 150 is too small. When in use, the metal layer 180 on one side of the segment 150 is prone to short circuit with the gate structure 130 on the other side of the segment 150, thereby affecting the performance of the semiconductor device and limiting the use of the semiconductor device.

[0046] The inventors have discovered that before forming the first opening, a sacrificial layer is formed on the gate structure, the sacrificial layer and the gate structure at the bottom of the sacrificial layer are etched, a first opening is formed in the gate structure in the first area, a segment is formed in the first opening, the sacrificial layer is removed, and the top surface of the segment formed is higher than the top surface of the gate structure. When a metal layer is subsequently formed on the gate structure on one side of the segment, since the top surface of the segment is higher than the top surface of the gate structure, the distance between the metal layer and the gate structure on the other side of the segment is increased, so that the probability of short circuit between the metal layer and the gate structure on the other side of the segment is reduced, thereby enhancing the stability of the performance of the semiconductor device and contributing to the improvement of the performance of the semiconductor device.

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] First embodiment

[0049] Figures 8 to 18 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor device according to the first embodiment of the present invention.

[0050] Please refer to Figure 8 , providing a substrate 200.

[0051] In this embodiment, the base 200 includes a substrate 210 and a plurality of separate fins 220 located on the substrate 210 .

[0052] In this embodiment, the material of the substrate 210 is single crystal silicon. In other embodiments, the substrate 210 may also be polycrystalline silicon or amorphous silicon. The material of the substrate 210 may also be a semiconductor material such as germanium, silicon germanium, gallium arsenide, silicon on insulator (SOI), or germanium on insulator (GOI).

[0053] In this embodiment, the method for forming the substrate 210 and the fin 220 includes: providing an initial substrate (not shown); forming a patterned layer on the initial substrate; and etching the initial substrate using the patterned layer as a mask to form the substrate 210 and the fin 220 .

[0054] In this embodiment, the material of the fin 220 is single crystal silicon. In other embodiments, the material of the fin may also be single crystal silicon germanium or other semiconductor materials.

[0055] In other embodiments, the substrate 200 may also be a structure without the fin portion.

[0056] In this embodiment, there are multiple fins 220 , and the distances between adjacent fins are different. The fin area with a large distance between adjacent fins is defined as a sparse area 221 , and the fin area with a small distance between adjacent fins is defined as a dense area 222 .

[0057] Please refer to Figure 9 , an isolation layer 201 is formed on the substrate 210 , and the isolation layer 201 covers a portion of the sidewall of the fin 220 .

[0058] The method for forming the isolation layer 201 includes: forming an initial isolation layer (not shown) on the substrate 210, wherein the initial isolation layer covers the fin 220; performing a planarization process on the initial isolation layer until the top surface of the fin 220 is exposed; after the planarization process, removing a portion of the initial isolation layer to form the isolation layer 201, wherein the top surface of the isolation layer 201 is lower than the top surface of the fin 220.

[0059] In other embodiments, the method for forming the isolation layer 201 may further include spin-on coating (SoC), selective growth, atomic layer deposition, patterning, etc.

[0060] In this embodiment, the material of the isolation layer 201 includes silicon oxide; in other embodiments, the material of the isolation layer 201 may also include one or more combinations of materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon carbon boron nitride (SiCBN).

[0061] Please refer to Figure 10 and Figure 11 , Figure 10 yes Figure 11 A top view of Figure 11 yes Figure 10 In the cross-sectional view taken along line AA, a gate structure 230 is formed on the substrate 200 .

[0062] In this embodiment, the gate structure 230 is formed on the substrate 210 , and the gate structure 230 spans across a plurality of the fins 220 .

[0063] In this embodiment, the gate structure 230 includes a first region 231 and a second region 232 . The gate structure length of the first region 231 is greater than the gate structure length of the second region 232 .

[0064] The gate structure length refers to a gate structure distance perpendicular to the extension direction of the fin 220 and spanning between adjacent fins.

[0065] In this embodiment, the gate structure 230 in the first region 231 is located between the fins 220 in the sparse region 221 , and the gate structure 230 in the second region 232 is located between the fins 220 in the dense region 222 .

[0066] In this embodiment, the process for forming the gate structure 230 is a gate-last process; in other embodiments, the process for forming the gate structure 230 may also be a gate-first process.

[0067] In this embodiment, the gate structure 230 includes a gate dielectric layer 233 and a gate electrode layer 234 located on the gate dielectric layer 233 .

[0068] In this embodiment, the gate dielectric layer 233 is made of a high-K dielectric material, such as oxides such as Al2O3, HfO2, Ta2O5, TiO2, ZrO2, etc. In other embodiments, the gate dielectric layer 233 may include other dielectric materials with a dielectric constant higher than 3.9.

[0069] In this embodiment, the gate electrode layer 234 is made of metal, including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the gate electrode layer 234 is made of tungsten.

[0070] In this embodiment, the gate structure 230 further includes sidewall spacers (not shown in the figure) on the sidewall surfaces of the gate electrode layer 234 and the gate dielectric layer 233 .

[0071] The material of the sidewall spacer includes one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbon boron nitride (SiCBN), etc. In this embodiment, the sidewall spacer is made of silicon nitride.

[0072] Please refer to Figure 12 , forming a sacrificial layer 240 on the gate structure 230 .

[0073] The material of the sacrificial layer 240 can be amorphous silicon (a-Si), amorphous carbon (aC), or amorphous germanium (a-Ge). In this embodiment, the material of the sacrificial layer 240 is amorphous silicon (a-Si).

[0074] In this embodiment, amorphous silicon is used as the sacrificial layer 240 because: since amorphous silicon has a higher etching selectivity relative to the gate electrode layer 234, it is easier to remove the amorphous silicon without damaging the gate electrode layer 234 (especially its surface), which not only helps to simplify the process, but more importantly, ensures the performance of the semiconductor device finally formed.

[0075] In this embodiment, the process for forming the sacrificial layer 240 is a chemical vapor deposition process; in other embodiments, the process for forming the sacrificial layer 240 may also be a physical vapor deposition process or an atomic layer deposition process.

[0076] In this embodiment, the thickness of the sacrificial layer 240 is 10 nanometers to 50 nanometers; when the thickness of the sacrificial layer 240 is less than 10 nanometers, because the thickness of the sacrificial layer 240 is equivalent to the height difference between the top surface of the subsequently formed segment and the top surface of the gate structure, if the formed sacrificial layer 240 is too thin, the height difference between the top surface of the segment and the top surface of the gate structure is too small, and the segment cannot effectively separate the gate structure on the other side of the segment from the metal layer on the gate structure on one side of the segment, and still cannot avoid the short circuit between the metal layer on the gate structure on one side of the segment and the gate structure on the other side of the segment; when the thickness of the sacrificial layer 240 is greater than 50 nanometers, the thickness of the sacrificial layer 240 formed at this time is too thick, and its deposition process and subsequent removal process will result in cost waste, which is not conducive to improving production efficiency.

[0077] Please refer to Figure 13 , the sacrificial layer 240 and the gate structure 230 in the first region 231 at the bottom of the sacrificial layer 240 are etched to expose the surface of the substrate 200 , and a first opening 250 is formed in the gate structure 230 in the first region 231 .

[0078] In this embodiment, the sacrificial layer 240 and the gate electrode layer 234 of the first region 231 at the bottom of the sacrificial layer 240 are etched to expose the surface of the gate dielectric layer 233, and a first opening 250 is formed in the gate structure 230 of the first region 231 and the sacrificial layer 240, wherein the sidewalls of the first opening 250 do not expose the fin structure 220, nor do they expose the gate dielectric layer 233 covering the surface of the fin structure 220.

[0079] In this embodiment, the process of forming the first opening 250 is a dry etching process; in other embodiments, the process of forming the first opening 250 may also be a wet etching process.

[0080] Please refer to Figure 14, a dividing segment 251 is formed in the first opening 250 , and the dividing segment 251 completely fills the first opening 250 .

[0081] In this embodiment, the process of forming the segment 251 is an atomic layer deposition process; in other embodiments, the process of forming the segment 251 may also include a chemical vapor deposition process.

[0082] In this embodiment, the step of forming the segmentation segment 251 includes: forming a segmentation layer in the first opening 250 and on the sacrificial layer 240 , planarizing the segmentation layer until the top surface of the sacrificial layer 240 is exposed, and forming the segmentation segment 251 in the first opening 250 .

[0083] In this embodiment, the atomic layer deposition process is used to form the segmentation layer because the atomic layer deposition process can form the segmentation layer with a better coverage gradient, can fill the first opening 250 to a higher degree, and improve the quality of the formed segmentation segment 251.

[0084] In this embodiment, the material of the dividing segment 251 is silicon nitride; in other embodiments, the material of the dividing segment 251 may also be one or more combinations of insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon carbon boron nitride (SiCBN).

[0085] Please refer to Figure 15 , remove the sacrificial layer 240.

[0086] In this embodiment, the process for removing the sacrificial layer 240 is a wet etching process; this is because during the wet etching process, the sacrificial layer 240 has a higher etching selectivity relative to the gate electrode layer 234. Using a wet etching process to remove the sacrificial layer 240 can ensure that in the process of removing the sacrificial layer 240, not only can the remnants of the sacrificial layer 240 be removed efficiently and cleanly, but more importantly, the gate structure 230 at the bottom of the sacrificial layer 240 will not be damaged, thereby ensuring the quality of the gate structure 230.

[0087] from Figure 15 It can be seen that after the sacrificial layer 240 is removed, the top surface of the segment 251 is higher than the top surface of the gate structure 230. In this way, when a metal layer is subsequently formed on the gate structure 230 on one side of the segment 251, the segment 251 can isolate the metal layer from the gate structure 230 on the other side of the segment 251 to prevent a short circuit between the two.

[0088] Please refer to Figure 16A dielectric layer 260 is formed on the top surface of the gate structure 230 and on the top and a portion of the sidewall of the segment 251 .

[0089] In this embodiment, the material of the dielectric layer 260 is silicon nitride; in other embodiments, the material of the dielectric layer 260 may also be one or more combinations of dielectric materials such as silicon oxide, silicon carbide, silicon oxynitride, silicon nitride, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0090] In this embodiment, the step of forming the dielectric layer 260 includes: forming an initial dielectric layer on the top surface of the gate structure 230 and on the top and part of the side wall of the segment 251, flattening the initial dielectric layer to form the dielectric layer 260, and the surface of the dielectric layer 260 does not expose the surface of the segment 251.

[0091] Please refer to Figure 17 , etching the dielectric layer 260 to form a second opening 261 in the dielectric layer 260, the bottom of the second opening 261 exposing the sidewall surface and a portion of the top surface of one side of the segment 251 and exposing a portion of the top surface of the gate structure 230 located at the sidewall surface of one side of the segment 251.

[0092] In this embodiment, the purpose of forming the second opening 261 is to provide space for the subsequent formation of a metal layer.

[0093] In this embodiment, the process of forming the second opening 261 is a dry etching process; in other embodiments, the process of forming the second opening 261 may also be a wet etching process.

[0094] Please refer to Figure 18 After the second opening 261 is formed, a metal layer 270 is formed in the second opening 261 , and the metal layer 270 completely fills the second opening 261 .

[0095] In this embodiment, the metal layer 270 serves as an electrical conductive interconnection layer for achieving electrical connection with the outside.

[0096] In this embodiment, the material of the metal layer 270 is tungsten; in other embodiments, the material of the metal layer 270 may also be copper, aluminum, titanium, etc.

[0097] In this embodiment, please refer to Figure 18The metal layer 270 is formed on the side wall surface and part of the top surface on one side of the segment 251 and on part of the top surface of the gate structure 230 located at the side wall surface on one side of the segment 251. Since the top surface of the segment 251 is higher than the top surface of the gate structure 230, the distance D between the metal layer 270 and the gate structure 230 located on the other side of the segment 251 is increased, thereby avoiding the formation of a short circuit between the gate structure 230 on the other side of the segment 251 and the metal layer 270, thereby enhancing the performance of the formed semiconductor device and improving the quality.

[0098] Second embodiment

[0099] The only difference between this embodiment and the first embodiment is that a hard mask layer is formed on the top surface of the gate structure before forming the sacrificial layer.

[0100] The process from providing the substrate to forming the gate structure is the same as that in the first embodiment, please refer to Figures 8 to 11 .

[0101] Please refer to Figure 19 , a hard mask layer 202 is formed on the gate structure 230 , and a sacrificial layer 240 is formed on the hard mask layer 202 .

[0102] The purpose of forming the hard mask layer 202 on the gate structure 230 is to prevent a short circuit between the gate structure 230 and the source / drain doping layer (not shown in the figure), thereby achieving electrical isolation.

[0103] For details on the process from forming the sacrificial layer 240 on the hard mask layer 202 to forming the metal layer 270, please refer to Figures 13 to 18 .

[0104] Correspondingly, the present invention also provides a semiconductor device, comprising: a base 200, wherein the base 200 includes a substrate 210, and a plurality of discretely arranged fins 220 located on the substrate 210, including a sparse area 221 and a dense area 222; a gate structure 230, located on the base 200, including a first area 231 and a second area 232, wherein the gate structure length of the first area 231 is greater than the gate structure length of the second area 232, the gate structure 230 is located on the substrate 210 and spans the fins 220, the gate structure of the first area 231 is located between the fins in the sparse area 221, and the gate structure of the second area 232 is located between the fins in the dense area 222; a segment 251, located in the gate structure of the first area 231, and the top surface of the segment 251 is higher than the top surface of the gate structure 230.

[0105] Since the top surface of the segment 251 is higher than the top surface of the gate structure 230, when a metal layer is subsequently formed on the gate structure 230 on one side of the segment 251, the segment 251 can isolate the metal layer from the gate structure 230 on the other side of the segment 251 to prevent a short circuit between the two, thereby improving the performance and quality of the formed semiconductor device.

[0106] In this embodiment, the top surface of the segmentation segment 251 is 10 nanometers to 50 nanometers higher than the top surface of the gate structure 230; when the height of the top surface of the segmentation segment 251 is less than 10 nanometers higher than the top surface of the gate structure 230, the height difference between the segmentation segment 251 and the gate structure 230 is too small, and the segmentation segment 251 cannot play a role in segmentation and isolation; when the top surface of the segmentation segment 251 is greater than 50 nanometers higher than the top surface of the gate structure 230, the height of the segmentation segment 251 is too high, resulting in material waste and reduced production efficiency.

[0107] In this embodiment, the material of the dividing segment 251 is silicon nitride; in other embodiments, the material of the dividing segment 251 can also be one or more combinations of insulating materials such as silicon oxide, silicon oxynitride, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon carbon boron nitride (SiCBN).

[0108] In this embodiment, the structure further includes an isolation layer 201 , which is located on the substrate 210 and covers a portion of the sidewall of the fin 220 .

[0109] In this embodiment, the gate structure 230 includes a gate dielectric layer 233 and a gate electrode layer 234 . The gate electrode layer 234 is made of a metal material.

[0110] In this embodiment, the dielectric layer 260 is further included. The dielectric layer 260 is located on the top surface of the gate structure 230 and on the sidewalls and top surface of the segment 251 that are higher than the gate structure 230 .

[0111] In this embodiment, it also includes: a hard mask layer 202, the hard mask layer 202 is located on the top surface of the gate structure 230, the dielectric layer 260 is located on the top surface of the hard mask layer 202 and is located on the sidewalls and top surface of the segment 251 higher than the hard mask layer 202.

[0112] In this embodiment, the structure further includes a metal layer 270 . The metal layer 270 is located in the dielectric layer 260 , and a bottom surface of the metal layer 270 contacts a top surface of the gate structure 230 at one side of the segment 251 .

[0113] Since the top surface of the segment 251 is higher than the top surface of the gate structure 230, when the metal layer 270 is formed as an interconnection layer on the gate structure 230 in the first area 231 on one side of the segment 251, the distance D between the gate structure 230 in the first area 231 on the other side of the segment 251 and the metal layer 270 is increased. In this way, the probability of a short circuit between the metal layer 270 and the gate structure 230 on the other side of the segment 251 is reduced, thereby improving the performance stability and quality of the formed semiconductor device, which helps to expand the scope of use of semiconductor devices.

[0114] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a gate structure located on the substrate, comprising a first region and a second region, wherein a gate structure length of the first region is greater than a gate structure length of the second region, and the gate structure comprises a gate dielectric layer; a segmentation segment located in the gate structure of the first region, wherein a top surface of the segmentation segment is higher than a top surface of the gate structure, and a bottom of the segmentation segment is located on a surface of the gate dielectric layer; A metal layer, a bottom surface of the metal layer contacts a top surface of the gate structure at one side of the segment, and the segment isolates the metal layer from the gate structure at the other side of the segment.

2. The semiconductor device according to claim 1, wherein A top surface of the segment is 10 nanometers to 50 nanometers higher than a top surface of the gate structure.

3. The semiconductor device according to claim 1, wherein The dividing segment is made of silicon nitride, silicon oxide or silicon oxynitride.

4. The semiconductor device according to claim 1, wherein The base includes a substrate and a plurality of fins located on the substrate, wherein the fins include a sparse area and a dense area.

5. The semiconductor device according to claim 4, wherein The gate structure is located on the substrate and spans the fins. The gate structure in the first region is located between the fins in the sparse region, and the gate structure in the second region is located between the fins in the dense region.

6. The semiconductor device according to claim 4, wherein Also includes: An isolation layer is located on the substrate and covers a portion of a sidewall of the fin.

7. The semiconductor device according to claim 1, wherein Also includes: A dielectric layer is located on a top surface of the gate structure and on a sidewall and a top surface of the segment that is higher than the gate structure.

8. The semiconductor device according to claim 7, wherein Also includes: A hard mask layer is located on a top surface of the gate structure. The dielectric layer is located on a top surface of the hard mask layer and on sidewalls and a top surface of the segment that are higher than the hard mask layer.

9. The semiconductor device according to claim 7 or 8, wherein The metal layer is located in the dielectric layer.

10. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, forming a gate structure on the substrate, the gate structure comprising a first region and a second region, the gate structure length of the first region being greater than the gate structure length of the second region, and the gate structure comprising a gate dielectric layer; forming a sacrificial layer on the gate structure; Etching the sacrificial layer and the gate structure of the first region at the bottom of the sacrificial layer to expose the surface of the gate dielectric layer, and forming a first opening in the gate structure of the first region and the sacrificial layer; forming a segment in the first opening, wherein the segment completely fills the first opening; removing the sacrificial layer; The method further includes forming a metal layer, wherein a bottom surface of the metal layer contacts a top surface of the gate structure at one side of the segment, and the segment isolates the metal layer from the gate structure at the other side of the segment.

11. The method for forming a semiconductor device according to claim 10, wherein: The sacrificial layer is made of amorphous silicon, amorphous carbon or amorphous germanium.

12. The method for forming a semiconductor device according to claim 10, wherein: The thickness of the sacrificial layer is 10 nanometers to 50 nanometers.

13. The method for forming a semiconductor device according to claim 10, wherein: The process of forming the segmented segments includes an atomic layer deposition process or a chemical vapor deposition process.

14. The method for forming a semiconductor device according to claim 10, wherein: The dividing segment is made of silicon nitride, silicon oxide or silicon oxynitride.

15. The method for forming a semiconductor device according to claim 10, wherein: The base includes a substrate, on which a plurality of discretely arranged fins are formed, and the fins include a sparse area and a dense area.

16. The method for forming a semiconductor device according to claim 15, wherein: The gate structure is formed on the substrate and spans the fins. The gate structure in the first region is located between the fins in the sparse region, and the gate structure in the second region is located between the fins in the dense region.

17. The method for forming a semiconductor device according to claim 15, wherein: After forming the fin and before forming the gate structure, the method further includes: forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the sidewall of the fin.

18. The method for forming a semiconductor device according to claim 10, wherein: After removing the sacrificial layer, the method further includes: forming a dielectric layer on the top surface of the gate structure and on the top and part of the sidewall of the segment.

19. The method for forming a semiconductor device according to claim 18, wherein: Also includes: Before forming the sacrificial layer, a hard mask layer is formed on the top surface of the gate structure.

20. The method for forming a semiconductor device according to claim 18, wherein: After forming the dielectric layer, it also includes: etching the dielectric layer to form a second opening in the dielectric layer, the bottom of the second opening exposing the side wall surface, part of the top surface and part of the top surface of the gate structure at the side wall surface on one side of the segmentation segment.

21. The method for forming a semiconductor device according to claim 20, wherein: The metal layer completely fills the second opening.

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