Multi-voltage operation for driving multi-mode channels

Abstract

This application relates to multi-voltage operation for driving a multimode channel. A transmitting and receiving device can be coupled via a channel, and the channel can support multiple modes, such as a terminated mode and an unterminated mode. A driver can be coupled to the channel, and a voltage supply for the driver can be adjusted based on the mode of the channel, for example, based on whether the channel is terminated or unterminated. For each mode of the channel, adjusting the voltage supply can produce a similar or other desired voltage level on the channel.

Description

[0001] Cross-references

[0002] This patent application claims priority to PCT / US2020 / 028466, filed April 16, 2020, by Brox et al., entitled "MULTI-VOLTAGE OPERATION FOR DRIVING A MULTI-MODE CHANNEL," which claims priority to U.S. Patent Application No. 16 / 849,746, filed April 15, 2020, by Brox et al., entitled "MULTI-VOLTAGE OPERATION FOR DRIVING A MULTI-MODE CHANNEL," and U.S. Patent Application No. 16 / 849,746, filed April 22, 2019, by Brox et al., entitled "MULTI-VOLTAGE OPERATION FOR DRIVING A MULTI-MODE CHANNEL." Priority to U.S. Provisional Patent Application No. 62 / 836,870, entitled “CHANNEL”, each of which is assigned to the assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to multi-voltage operation for driving multi-mode channels. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, frequently represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from external power.

[0006] In some systems, a device may be coupled to one or more other devices via one or more channels, wherein the device and the other devices can communicate via the channels. A set of one or more channels may be referred to as an interface. For example, in a memory system, a memory device may be coupled to a host device (e.g., a processor) via one or more interfaces, each of which may include at least one channel. Summary of the Invention

[0007] Describe a method. The method may include: identifying that a channel between a first device and a second device is in a first mode, in which the channel is terminated; setting a voltage supply for a driver coupled to the channel to a first voltage, at least in part based on the channel termination; identifying that the channel is in a second mode after the voltage supply is set to the first voltage, in which the channel is unterminated; and adjusting the voltage supply for the driver to a second voltage lower than the first voltage, at least in part based on the unterminated channel.

[0008] Describe a method. The method may include: monitoring the channel for signaling with a voltage swing when operating the channel between the first device and the second device using a first impedance; switching the channel to a second impedance having a higher impedance than the first impedance; and monitoring the channel for signaling with the voltage swing when operating the channel using the second impedance.

[0009] Describe an apparatus. The apparatus may include: a driver coupled to a channel for communication with the apparatus; a voltage power supply coupled to the driver; and a controller coupled to the voltage power supply and configured to cause the apparatus to: identify that the channel is in a termination mode associated with a first data rate; set the voltage power supply for the driver to a first voltage corresponding to the termination mode; identify that after setting the voltage power supply to the first voltage, the channel is in an unterminated mode associated with a second data rate lower than the first data rate; and set the voltage power supply for the driver to a second voltage corresponding to the unterminated mode, the second voltage being at least partially based on a channel voltage associated with the termination mode. Attached Figure Description

[0010] Figure 1 Examples of systems supporting multi-voltage operation for driving multi-mode channels are shown, based on the examples disclosed herein.

[0011] Figure 2 Examples of memory dies supporting multi-voltage operation for driving multi-mode channels are shown, based on the examples disclosed herein.

[0012] Figure 3A Examples of systems supporting multi-voltage operation for driving multi-mode channels are shown, based on the examples disclosed herein.

[0013] Figure 3B Examples of signals associated with multi-voltage operation for driving a multi-mode channel are shown, based on the examples disclosed herein.

[0014] Figure 4A Examples of systems supporting multi-voltage operation for driving multi-mode channels are shown, based on the examples disclosed herein.

[0015] Figure 4B Examples of signals associated with multi-voltage operation for driving a multi-mode channel are shown, based on the examples disclosed herein.

[0016] Figure 5A An example of a timing diagram associated with multi-voltage operation for driving a multi-mode channel is shown, based on the examples disclosed herein.

[0017] Figure 5B Examples of signals associated with multi-voltage operation for driving a multi-mode channel are shown, based on the examples disclosed herein.

[0018] Figure 5C Examples of signals associated with multi-voltage operation for driving a multi-mode channel are shown, based on the examples disclosed herein.

[0019] Figure 6Examples of process flows supporting multi-voltage operation for driving multi-mode channels are shown, based on the examples disclosed herein.

[0020] Figure 7 A block diagram is shown that supports a means for driving multi-voltage operation of a multi-mode channel according to aspects of this disclosure.

[0021] Figure 8 A block diagram is shown that supports a means for driving multi-voltage operation of a multi-mode channel according to aspects of this disclosure.

[0022] Figures 9 to 11 A flowchart is shown, illustrating one or more methods for supporting multi-voltage operation of a multi-mode channel, based on examples disclosed herein. Detailed Implementation

[0023] In some cases, channels between devices in a computing system may include one or more terminations, wherein the terminations may be configured (e.g., by reducing noise, reducing crosstalk, or through other mechanisms) to facilitate the integrity of signals exchanged via the channel. For example, the channel may be low-level terminated, in which case the channel may be coupled via a configured impedance component (termination) to a voltage reference lower than at least one other voltage reference in the system, such as a ground reference or negative voltage reference, which may be referred to as VSS. As another example, the channel may be high-level terminated, in which case the channel may be coupled via a configured impedance component (termination) to a voltage reference higher than at least one other voltage reference in the system, such as a positive voltage reference, which may be referred to as VDD. Channels that are low-level terminated or high-level terminated are generally referred to as terminated channels or in terminated mode, and the impedance of the configured impedance component may be referred to as termination impedance or channel impedance.

[0024] While terminating a channel can improve signal integrity, it can also increase power consumption by reducing the impedance between the channel and the voltage reference coupled to the terminating impedance. Conversely, removing the terminating impedance, at least in theory (e.g., ignoring parasitic effects), would result in an open circuit between the channel and the voltage reference, except for any current paths within the device coupled to the channel. A channel operating without a configured terminating impedance is often referred to as an unterminated channel or unterminated mode.

[0025] Therefore, there may be a trade-off between the signal integrity benefits that may be associated with a terminated channel and the power consumption benefits that may be associated with an unterminated channel. As described herein, a computing system can take advantage of this trade-off by including one or more channels that can be switched from terminated to unterminated (e.g., as part of an interface). In some cases, whether a channel is in terminated or unterminated mode may be related to the current mode of the computing system. For example, a first mode of the computing system may correspond to a high-power, high-speed mode, which may involve processing-intensive functions. Alternatively, this first mode may be associated with high data rates and the use of one or more terminated channels between system devices (e.g., between a memory device and a host device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)) for the memory device). As another example, a second mode of the computing system may correspond to a low-power mode in which processing requirements or demands may be minimal, similar to an idle mode. Alternatively, this second mode may be associated with low data rates between system devices, and a channel terminated in the first mode may be unterminated in the second mode.

[0026] In some cases, changing a channel from terminated mode to unterminated mode can affect the voltage swing (range) of signaling on the channel. For example, in low-terminated mode, the terminating impedance can act as a voltage divider, causing the upper limit of signaling on the channel to be a portion of the supply voltage of the driver that generates the signaling (e.g., if the driver's supply voltage is VDD, the voltage on the channel may be limited to half of VDD due to impedance matching between the driver and the terminating impedance). However, in unterminated mode, the upper limit of signaling on the channel may be equal to the supply voltage of the driver that generates the signaling (e.g., VDD), and the voltage on the channel may swing between rails (e.g., from VSS to VDD, where VSS is the lower supply voltage of the driver).

[0027] Compared to when the channel is terminated, the different (e.g., increased) voltage swing of signaling on the channel when it is unterminated can have one or more associated disadvantages. For example, in some systems, the channel may be associated with a maximum operating voltage. The maximum operating voltage of the channel can be based on one or more components of the receiving signaling device. In some cases, for example, the receiving device may employ one or more transistors with voltage tolerances (e.g., gate oxide breakdown voltage), and if the voltage on the channel exceeds the voltage tolerance of the transistors, the transistors may be damaged or otherwise rendered unusable. Transistors with lower voltage tolerances (e.g., thinner gate oxide layers) may provide faster switching speeds, smaller form factor, or other benefits in some cases, but when used in a receiving device, such transistors may limit the maximum operating voltage of the channel. Therefore, when the channel is unterminated, the different (e.g., increased) voltage swing of signaling on the channel can cause the voltage on the channel to exceed the voltage tolerance, which may limit the ability of the receiving device to include transistors or other components with desired performance characteristics. As another example, when the channel is unterminated, the different (e.g., increased) voltage swings of signaling on the channel can lead to increased complexity at the receiver, as the receiver may need to monitor signaling with different voltage levels depending on the channel pattern.

[0028] However, the systems and techniques described herein can support the use of different voltage levels at the transmitting device based on channel mode. For example, the voltage supply of the driver at the transmitting device can be adjusted based on channel impedance (e.g., based on whether the channel is terminated or unterminated). In some cases, the voltage supply of the driver can be set to a first (e.g., high) voltage when the channel is terminated and a second (e.g., low) voltage when the channel is unterminated. The first and second voltages can be configured such that the voltage on the channel remains constant or largely constant when the channel switches between terminated and unterminated modes. For example, when the voltage supply is set to the first voltage and the channel is terminated, signaling on the channel can reach an upper limit, and the second voltage can be configured to be equal to said upper limit. Furthermore, in some cases, the driver can be configured to output signaling on the channel at a different data rate (e.g., a higher baud rate, a higher modulation order, or both) when the channel is terminated compared to when the channel is unterminated. In some cases, the transmitting device can be a memory device, and the receiving device can be a host device of the memory device, or vice versa.

[0029] Therefore, for example, the systems and techniques described herein can enable channel termination when higher data rates or other performance benefits are required, and channel unterminated when lower power consumption or other performance benefits are required. Alternatively, the systems and techniques described herein can enable the use of components with lower voltage tolerances (e.g., transistors with faster switching speeds or smaller form factors) at the receiving device, reducing the complexity of one or more aspects of the receiving device, or providing other benefits.

[0030] Firstly, in reference Figure 1 and 2 Features of this disclosure are described within the context of the memory systems and devices described herein. Features of this disclosure are described within the context of the system supporting multi-voltage operation for driving multi-mode channels, the associated signals on the channels, and the associated process flow, as illustrated in Figures 3-6. (This is in conjunction with the reference...) Figure 7-10 The device diagrams and flowcharts described for driving multi-voltage operation of multi-mode channels further illustrate and describe these and other features of this disclosure.

[0031] Figure 1 An example of a system 100 utilizing one or more memory devices according to the examples disclosed herein is shown. System 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 to the memory device 110. System 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0032] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, or graphics processing devices. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, Internet-connected device, etc. Memory device 110 may be a component of the system configured to store data for one or more other components of system 100. In some instances, system 100 is configured for bidirectional wireless communication with other systems or devices using a base station or access point. In some instances, system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0033] At least a portion of system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to execute processes, such as a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, and some other fixed or portable electronic device. In some cases, host device may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device. In some instances, system 100 is a graphics card.

[0034] In some cases, memory device 110 may be a separate device or component configured to communicate with other components of system 100 and provide physical memory addresses or other spaces that are available for use or reference by system 100. In some instances, memory device 110 may be configured to cooperate with at least one or more different types of system 100. Signaling between components of system 100 and memory device 110 may be used to support modulation schemes for modulated signals, different pin designs for transmitting signals, different packages of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions and / or other factors.

[0035] Memory device 110 may be configured to store data for components of system 100. In some cases, memory device 110 may act as a slave device to system 100 (e.g., responding to and executing commands provided by system 100 via external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (e.g., memory chips) supporting a desired or specified capacity for data storage. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or package (also known as a multi-chip memory or package).

[0036] System 100 may further include processor 120, basic input / output system (BIOS) component 125, one or more peripheral components 130, and input / output (I / O) controller 135. The components of system 100 may be electrically connected to each other via bus 140.

[0037] Processor 120 may be configured as at least part of control system 100. Processor 120 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or a combination of these types of components. In such cases, processor 120 may be an instance of central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), and other instances.

[0038] BIOS component 125 may be a software component containing a BIOS operating as firmware, which initializes and runs various hardware components of system 100. BIOS component 125 may also manage data flow between processor 120 and various components of system 100, such as peripheral components 130, I / O controllers 135, etc. BIOS component 125 may contain programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0039] Peripheral component 130 can be any input or output device, or an interface for such a device, which can be integrated into or with system 100. Examples may include a disk controller, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, serial or parallel port, or peripheral card slot, such as Peripheral Component Interconnect (PCI) or dedicated graphics port. Peripheral component 130 can be other components that are understood by those skilled in the art to be peripheral devices.

[0040] I / O controller 135 manages data communication between processor 120 and peripheral components 130, inputs 145, or outputs 150. I / O controller 135 can manage peripheral devices not integrated into system 100 or not integrated with said system. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0041] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or it may be managed by I / O controller 135.

[0042] Output 150 may represent a device or signal external to system 100, configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, audio speaker, printing device, or another processor on a printed circuit board. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0043] The components of system 100 may consist of general-purpose or special-purpose circuit systems designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive components.

[0044] Memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., a grid), wherein each memory cell is configured to store at least one digital data bit. Reference Figure 2 The characteristics of memory array 170 and / or memory cells are described in more detail.

[0045] Memory device 110 can be an example of a two-dimensional (2D) memory cell array or a three-dimensional (3D) memory cell array. For example, a 2D memory device may contain a single memory die 160. A 3D memory device may contain two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a layer, hierarchy, stack, or die. A 3D memory device may contain any number of stacked memory dies 160-N (e.g., dual-block, triple-block, quad-block, quintuple-block, hexa-block, hepta-block, octa-block). Compared to a single 2D memory device, this can increase the number of memory cells that can be located on a substrate, thereby reducing manufacturing costs or improving the performance of the memory array, or both. In a 3D memory device, different layers may share at least one common access line, such that some layers may share at least one of word lines, digital lines and / or board lines.

[0046] Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110. Therefore, device memory controller 155 may include hardware, firmware, and software that enables memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information concerning memory device 110. Device memory controller 155 may be configured to communicate with external memory controller 105, one or more memory dies 160, or processor 120. In some cases, memory device 110 may receive data and / or commands from external memory controller 105. For example, memory device 110 may receive a write command instructing memory device 110 to store certain data on behalf of a component of system 100 (e.g., processor 120), or a read command instructing memory device 110 to provide certain data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, device memory controller 155 may be combined with a local memory controller 165 of memory die 160 to control the operation of memory device 110 as described herein. Examples of components included in the device memory controller 155 and / or local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, amplifiers, filters, etc.

[0047] A local memory controller 165 (e.g., local to memory die 160) may be configured to control the operation of memory die 160. Furthermore, the local memory controller 165 may be configured to communicate with device memory controller 155 (e.g., to receive and transmit data and / or commands). The local memory controller 165 may support device memory controller 155 in controlling the operation of memory device 110 as described herein. In some cases, memory device 110 may not include device memory controller 155, and either local memory controller 165 or external memory controller 105 may perform the various functions described herein. Therefore, the local memory controller 165 may be configured to communicate with device memory controller 155, communicate with other local memory controllers 165, or communicate directly with external memory controller 105 or processor 120.

[0048] External memory controller 105 may be configured to facilitate the communication of information, data, and / or commands between components of system 100 (e.g., processor 120) and memory device 110. External memory controller 105 may act as a communication link between components of system 100 and memory device 110, allowing components of system 100 to operate without needing to know the operational details of the memory device. Components of system 100 may present requests (e.g., read or write commands) to external memory controller 105 that external memory controller 105 can fulfill. External memory controller 105 may translate or interpret the communications exchanged between components of system 100 and memory device 110. In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0049] In some cases, the external memory controller 105 or other components of system 100, or the functions described herein, may be implemented by processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by processor 120 or other components of system 100. Although the external memory controller 105 is depicted as being external to memory device 110, in some cases, the external memory controller 105, or the functions described herein, may be implemented by memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across processor 120 and memory device 110, such that portions of the external memory controller 105 are implemented by processor 120, and other portions are implemented by device memory controller 155 or local memory controller 165. Similarly, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may be performed by the external memory controller 105 (separate from or included in the processor 120).

[0050] Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some instances, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may contain one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal comprising one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. Pins may be instances of conductive input or output points of devices of system 100, and pins may be configured to act as part of a channel.

[0051] In some cases, the pins or pads of the terminals may be part of the signal path of channel 115. Additional signal paths may be coupled to the terminals of the channel for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., within memory device 110 or its components, such as within memory die 160) that route signals from the terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0052] In some instances, channel 115 may be associated with a maximum operating voltage that cannot be exceeded (voltage limit). For example, external memory controller 105 or another aspect of system 100 may include one or more transistors with voltage tolerances that, if exceeded, may improperly impair the operation of the transistors, which may limit the voltage that can be used on channel 115 coupled to the external memory controller.

[0053] In some cases, as described herein, the terminating impedance between channel 115 and a voltage reference (e.g., a ground reference or VSS) can be configured, including dynamically during operation of system 100 (e.g., depending on the operating mode of system 100). For example, a device coupled to channel 115 (e.g., external memory controller 105) can couple channel 115 to a corresponding terminating impedance to place the channel in a terminated mode, and can decouple channel 115 from a corresponding terminating impedance to place the channel in an unterminated mode.

[0054] In the context of a channel 115 carrying signaling between a transmitting device (e.g., memory device 110) and a receiving device (e.g., external memory controller 105), either the transmitting or receiving device may configure (adjust, switch, change) the terminating impedance and indicate the mode of the channel (e.g., impedance, termination, and untermination) to other devices. Although the examples described herein may depict the receiving device as operating channel 115 (e.g., configuring the terminating impedance of the channel) and transmitting relevant indications to the transmitting device, it should be understood that the examples described herein are applicable to a transmitting device operating channel 115 (e.g., configuring the terminating impedance of the channel) and possibly transmitting one or more relevant indications to the receiving device.

[0055] To ensure that the voltage on the channel does not exceed the channel's maximum operating voltage, the voltage supply for a driver (e.g., a driver associated with memory device 110) coupled to another device coupled to channel 115 can be adjusted (e.g., dynamically) based on whether channel 115 is terminated or unterminated, or based on the impedance of channel 115, regardless of its impedance. For example, when channel 115 is unterminated, the voltage supply for the driver can be set to a lower voltage than when channel 115 is terminated.

[0056] Channel 115 (and associated signal paths and terminals) can be dedicated to conveying a specific type of information. In some cases, channel 115 can be an aggregated channel and therefore can contain multiple individual channels, each of which can be individually switched between terminated and unterminated. For example, data channel 190 can be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), x16 (containing sixteen signal paths), etc. Signals conveyed via the channel can use dual data rate (DDR) signaling. For example, some symbols of the signal can be recorded on the rising edge of the clock signal, and other symbols of the signal can be recorded on the falling edge of the clock signal. Signals conveyed on the channel can use single data rate (SDR) signaling. For example, one symbol of the signal can be recorded for each clock cycle.

[0057] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to transmit commands between external memory controller 105 and memory device 110, including control information (e.g., address information) associated with the command. For example, CA channel 186 may contain a read command for the address of desired data. In some cases, CA channel 186 may be registered on the rising and / or falling clock edges. In some cases, CA channel 186 may contain any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0058] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channels 188 may be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between high and low states and coordinate the operation of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., CK_t and CK_c signals) and the signal paths of CK channels 188 may be configured accordingly. In some cases, the clock signals may be single-ended. CK channels 188 may contain any number of signal paths. In some cases, clock signals CK (e.g., CK_t and CK_c signals) may provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Clock signals CK may therefore be referred to differently as control clock signals CK, command clock signals CK, or system clock signals CK. The system clock signal CK can be generated by the system clock, which may include one or more hardware components (e.g., oscillator, crystal, logic gate, transistor, etc.).

[0059] In some cases, channel 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to communicate data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may communicate (e.g., bidirectionally) information to be written to or read from memory device 110.

[0060] In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may contain any number of signal paths.

[0061] In some cases, other channels 192 may include one or more write clock (WCK) channels. While the 'W' in WCK nominally stands for "write," the write clock signals WCK (e.g., WCK_t and WCK_c signals) provide a timing reference generally used for access operations of memory device 110 (e.g., a timing reference for both read and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write or read operations) between the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t and WCK_c signals), and the signal paths of the WCK channel may be configured accordingly. The WCK channel may contain any number of signal paths. The data clock signal WCK can be generated by a data clock, which may include one or more hardware components (e.g., oscillator, crystal, logic gate, transistor, etc.).

[0062] In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels can be configured to convey error detection signals, such as checksums, to improve system reliability. EDC channels can contain any number of signal paths.

[0063] Channel 115 can use a variety of different architectures to couple external memory controller 105 to memory device 110. Examples of various architectures may include buses, point-to-point connections, cross switches, high-density in-cell modules such as silicon in-cell modules, or channels formed in an organic substrate, or combinations thereof. For example, in some cases, the signal path may at least partially contain high-density in-cell modules, such as silicon in-cell modules or glass in-cell modules.

[0064] Various modulation schemes can be used to modulate the signal transmitted on channel 115. In some cases, binary symbol (or binary level) modulation schemes can be used to modulate the signal transmitted between external memory controller 105 and memory device 110. A binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M equals two. Each symbol in a binary symbol modulation scheme can be configured to represent one bit of digital data (e.g., a symbol can represent logic 1 or logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), single-pole coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), etc.

[0065] In some cases, multi-symbol (or multi-level) modulation schemes can be used to modulate signals transmitted between external memory controller 105 and memory device 110. The multi-symbol modulation scheme can be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme can be configured to represent more than one digital data bit (e.g., the symbol can represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) can be a signal modulated using a modulation scheme comprising at least three levels for encoding more than one information bit. Multi-symbol modulation schemes and symbols are alternatively referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0066] In some instances, a driver for a transmission device can output signaling using a first modulation scheme on the channel when the channel has a first impedance (e.g., terminated), and output signaling using a second modulation scheme on the channel when the channel has a second impedance (e.g., unterminated). The first modulation scheme may be of a higher order than the second modulation scheme (e.g., PAM2 or NRZ) (e.g., PAM3 or PAM4).

[0067] Figure 2 An example of a memory die 200 according to an example disclosed herein is shown. The memory die 200 may be a reference. Figure 1 An example of memory die 160 is described. In some cases, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, memory cell 205 may be configured to store one digital logic bit at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one digital logic bit at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0068] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material to store charge representing a programmable state. Other memory devices and components are also possible in other memory architectures. For example, a nonlinear dielectric material may be used.

[0069] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210 and / or digital line 215. In some cases, digital line 215 may also be referred to as bit line. The references to access line, word line, and digital line or the like are interchangeable without affecting understanding or operation. Activating or selecting word line 210 or digital line 215 may involve applying a voltage to the corresponding line.

[0070] The memory die 200 may include access lines (e.g., word lines 210 and digital lines 215) arranged in a grid pattern. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215. A single memory cell 205 can be accessed at its intersection by biasing word lines 210 and digital lines 215 (e.g., by applying a voltage to word lines 210 or digital lines 215).

[0071] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 260 and activate word lines 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 260 and activate digital lines 215 based on the received column addresses. For example, memory die 200 may contain multiple word lines 210 labeled WL_1 to WL_M and multiple digital lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Therefore, by activating word lines 210 and digital lines 215, such as WL_1 and DL_3, memory cell 205 at their intersection can be accessed. The intersection of word lines 210 and digital lines 215 arranged in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205.

[0072] Memory cell 205 may include logic storage components, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell board reference voltage, such as Vpl, or may be grounded, such as Vss. In some cases, voltage source 240 may be an example of a board line coupled to a board line driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes an electronic connection between two components.

[0073] The selection or deselection of memory cell 205 can be achieved by activating or deactivating switch assembly 235. Capacitor 230 can be electrically connected to digital line 215 using switch assembly 235. For example, when switch assembly 235 is deactivated, capacitor 230 can be isolated from digital line 215, and when switch assembly 235 is activated, capacitor 230 can be coupled to digital line 215. In some cases, switch assembly 235 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the transistor's threshold voltage. In some cases, switch assembly 235 can be a p-type transistor or an n-type transistor. Word line 210 can be electrically connected to the gate of switch assembly 235, and the activation / deactivation of switch assembly 235 can be based on the voltage applied to word line 210.

[0074] Word line 210 may be a conductive line electrically connected to memory cell 205 for performing access operations on memory cell 205. In some architectures, word line 210 may be electrically connected to the gate of switching component 235 of memory cell 205 and may be configured to control the switching component 235 of memory cell 205. In some architectures, word line 210 may be electrically connected to the node of capacitor in memory cell 205, and memory cell 205 may not include a switching component.

[0075] Digital line 215 may be a wire connecting memory cell 205 and sensing component 245. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during portions of an access operation. For example, word line 210 and switching component 235 of memory cell 205 may be configured to couple and / or isolate capacitor 230 of memory cell 205 and digital line 215. In some architectures, memory cell 205 may be electrically connected (e.g., constantly) to digital line 215.

[0076] Sensing component 245 may be configured to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. In some cases, the charge stored by memory cell 205 may be extremely small. Therefore, sensing component 245 may include one or more sensing amplifiers to amplify the signal output from memory cell 205. The sensing amplifier may detect small changes in charge on digital line 215 during a read operation and may generate a signal corresponding to logic state 0 or logic state 1 based on the detected charge. During a read operation, capacitor 230 of memory cell 205 may output a signal (e.g., release charge) to its corresponding digital line 215. The signal may change the voltage of digital line 215. Sensing component 245 may be configured to compare the signal received from memory cell 205 across digital line 215 with a reference signal 250 (e.g., a reference voltage). Sensing component 245 may determine the stored state of memory cell 205 based on the comparison. For example, in binary signaling, if digital line 215 has a voltage higher than reference signal 250, then sensing component 245 can determine that the storage state of memory cell 205 is logic 1, and if digital line 215 has a voltage lower than reference signal 250, then sensing component 245 can determine that the storage state of memory cell 205 is logic 0. Sensing component 245 may include various transistors or amplifiers to detect and amplify the difference in signals. In some cases, sensing component 245 may be part of another component (e.g., column decoder 225, row decoder 220). In some situations, sensing component 245 may be electronically connected to row decoder 220 or column decoder 225.

[0077] The local memory controller 260 can control the operation of the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, and sensing component 245). The local memory controller 260 can be a reference... Figure 1 An example of a local memory controller 165 is described. In some cases, one or more of the row decoder 220, column decoder 225, and sensing component 245 may be located in the same position as the local memory controller 260. The local memory controller 260 may be configured to receive data from an external memory controller 105 (or refer to...). Figure 1The described device memory controller 155 receives commands and / or data, translates the commands and / or data into information usable by the memory die 200, performs one or more operations on the memory die 200, and, in response to performing one or more operations, transmits data from the memory die 200 to the external memory controller 105 (or the device memory controller 155). The local memory controller 260 can generate row and column address signals to activate target word lines 210 and target digital lines 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or varied, and may differ for the various operations discussed in operating the memory die 200.

[0078] In some cases, the local memory controller 260 may be configured to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logical state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify the target memory cell 205 to which the write operation will be performed. The local memory controller 260 may identify the target word line 210 and target digital line 215 (e.g., the address of the target memory cell 205) that are electrically connected to the target memory cell 205. The local memory controller 260 may activate the target word line 210 and target digital line 215 (e.g., apply a voltage to the word line 210 or digital line 215) to access the target memory cell 205. The local memory controller 260 may apply a specific signal (e.g., voltage) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205, the specific state (e.g., charge) indicating a desired logic state.

[0079] In some cases, the local memory controller 260 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logic state stored in the memory cells 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify the target memory cell 205 to which the read operation will be performed. The local memory controller 260 may identify a target word line 210 and a target digital line 215 (e.g., the address of the target memory cell 205) that are electrically connected to the target memory cell 205. The local memory controller 260 may activate the target word line 210 and the target digital line 215 (e.g., apply a voltage to the word line 210 or the digital line 215) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 245 in response to a bias access line. The sensing component 245 may amplify the signal. The local memory controller 260 can trigger the sensing component 245 (e.g., a latching sensing component) to compare the signal received from the memory cell 205 with the reference signal 250. Based on the comparison, the sensing component 245 can determine the logical state stored in the memory cell 205. As part of a read operation, the local memory controller 260 can transmit the logical state stored in the memory cell 205 to the external memory controller 105 (or the device memory controller 155).

[0080] In some memory architectures, accessing memory cell 205 may degrade or corrupt the logic state stored in memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. Local memory controller 260 may perform a rewrite or refresh operation to restore the memory cell to its original logic state. Local memory controller 260 may rewrite the logic state to the target memory cell after a read operation. In some situations, a rewrite operation may be considered part of a read operation. Additionally, activating a single access line (e.g., word line 210) may interfere with the state stored in some memory cells electrically connected to said access line. Therefore, a rewrite or refresh operation may be performed on one or more memory cells that may not have been accessed yet.

[0081] Figure 3A An example of a system 300, as disclosed herein, supporting multi-voltage operation for driving a multi-mode channel is shown. System 300 may include a transmitting device 305 and a receiving device 310. In some cases, either the transmitting device 305 or the receiving device 310 may be as described in the references. Figure 1 and 2Examples of the described memory device 110 or host device (e.g., external memory controller 105). The transmitting device 305 and the receiving device 310 may be coupled by a channel 325, which may be as described in the reference... Figure 1 An instance of channel 115 as described.

[0082] The driver 345 may be included in (e.g., as an on-chip driver) the transmission device 305, or otherwise associated with (e.g., controlled by) the transmission device. The transmission device 305 may operate the driver 345 to generate signaling and output signaling on channel 325, which may be received by the receiving device 310.

[0083] Driver 345 may have an upper voltage supply (e.g., coupled to an upper voltage supply), the voltage of which may be referred to as VDD. The driver may also have a lower voltage supply (e.g., coupled to a lower voltage supply), the voltage of which may be referred to as VSS. VSS may be a voltage lower than VDD. In some cases, VSS may be ground or a negative voltage. In some cases, one or both of VDD and VSS may be generated internally (e.g., as an internal voltage reference) or received from an external source. For example, in some cases, VDD may correspond to a voltage at a pin of transmission device 305, such as the output stage drain supply voltage (VDDQ) pin as defined in an industry standard or specification (e.g., a Joint Electronic Devices Engineering Committee (JEDEC) specification).

[0084] Driver 345 may include one or more internal impedances. For example, in an example of system 300, driver 345 may be a push-pull driver and include pull-up impedance 330 (e.g., between the output of driver 345 and an upper voltage supply) and pull-down impedance (e.g., between the output of driver 345 and a lower voltage supply).

[0085] The receiving device 310 may include a terminal component 315 and a receiving component 320. The receiving component 320 may be configured to monitor and process signaling received via channel 325 (e.g., from the transmitting device 305).

[0086] Termination component 315 may include termination impedance 340, and the impedance of channel 325 may depend on (based on) the impedance of termination impedance 340. The impedance of channel 325 may be variable (e.g., capable of dynamically changing during operation of system 300). For example, termination component 315 may be configured to selectively couple or decouple channel 325 from termination impedance 340 (e.g., via a switching component, such as one or more transistors, that can be coupled to channel 325 and termination impedance 340). When channel 325 is coupled to termination impedance 340, channel 325 may be in a terminated mode. When channel 325 is decoupled from termination impedance 340, channel 325 may be in an unterminated mode. Alternatively or additionally, the impedance of termination impedance 340 may be configured by termination component 315 (e.g., dynamically configured), for example by selectively incorporating or removing impedance sensing components from termination impedance 340. Termination impedance 340 may be coupled to a voltage reference, the voltage of which may be below VDD and, in some cases, equal to VSS.

[0087] In an example of system 300, terminal component 315 is included in receiving device 310. However, in some examples, terminal component 315 may be an element of transmitting device 305. Alternatively, in some examples, terminal component 315 may be separate from both transmitting device 305 and receiving device 310, but may be controlled by one or both of transmitting device 305 and receiving device 310.

[0088] As described above, channel 325 can sometimes operate in a terminated mode (e.g., high-level or low-level termination mode) and sometimes in an unterminated mode. When channel 325 is in a terminated mode, the upper voltage supply of driver 345 can be set to a first value, which can be referred to as VDD_1 (i.e., when channel 325 is in a terminated mode, VDD can be equal to VDD_1).

[0089] Figure 3A This illustrates a system 300 operating (configured) with channel 325 in low-level termination mode. When channel 325 is in low-level termination mode, the voltage of channel 325 can vary from a lower limit to an upper limit, where the lower limit is equal to or approximately equal to VSS, and the upper limit is based on VDD_1, the first pull-up impedance 330, and the termination impedance 340, as referenced. Figure 3B Further description.

[0090] In some instances, it may be necessary to keep the voltage of channel 325 below a certain limit. For example, one or more transistors included in receiver 320 may have voltage tolerances, and if the voltage of channel 325 exceeds the voltage tolerance, the transistors may degrade or fail. For example, the transistors included in receiver 320 may be short-channel and / or thin oxide transistors, which can provide fast switching speeds or other performance benefits. Whether for this reason or another, exceeding the voltage limit of channel 325 may cause reliability problems with system 300, or may be undesirable (e.g., may cause transistor failure at receiver 310).

[0091] Figure 3B An example of an eye diagram 350 based on a signal used to drive a multi-voltage channel, as disclosed herein, is shown. (See reference...) Figure 3A As described in the system 300 shown, eye diagram 350 illustrates an instance of signaling 370 on the channel when the channel 325 is in termination mode.

[0092] As shown in eye diagram 350, when channel 325 is terminated, signaling 370 can vary from the lower limit 365 to the upper limit 360, and therefore can have a voltage swing (range) equal to the difference between the upper limit 360 and the lower limit 365. When driver 345 drives channel 325 low, because the lower voltage supply (lower rail) of driver 345 is at the same voltage as the voltage reference (VSS) to which the terminating impedance 340 is coupled, no (or minimal) current can flow through the terminating impedance 340 or the pull-down impedance 335, and therefore there may be no voltage drop between the terminating impedance 340 and the pull-down impedance 335. Therefore, the lower limit 365 can correspond to (e.g., equal to or approximately equal to) the lower rail or the lower voltage supply (VSS) of driver 345.

[0093] However, when driver 345 drives channel 325 high, current may flow through termination impedance 340 and pull-up impedance 330 due to the voltage difference between the upper voltage supply (upper rail) (VDD_1) of driver 345 and the voltage reference (VSS) to which termination impedance 340 is coupled. Therefore, a voltage drop may occur between pull-up impedance 330 and termination impedance 340 when driver 345 drives channel 325 high. Therefore, the upper limit 360 can be less than VDD_1, as shown in eye diagram 350 (where VDD_1 is shown as voltage 355). For example, the pull-up impedance 330 and the terminating impedance 340 can form a voltage divider, and the upper limit 360 can be based on the relationship (ratio) between the corresponding impedances of the pull-up impedance 330 and the terminating impedance 340—for example, the upper limit 360 can be equal to a fraction of VDD_1, where (i) the numerator of the fraction is the impedance of the terminating impedance 340, and (ii) the denominator of the fraction is the sum of the impedances of the pull-up impedance 330 and the terminating impedance 340 (their combined impedance). Therefore, for example, when the pull-up impedance 330 and the terminating impedance 340 each have the same impedance, the upper limit 360 can be half (1 / 2) of VDD_1.

[0094] Although system 300 and eye diagram 350 are shown and described in the context of low-level termination mode, those skilled in the art will understand that the systems and techniques described herein can be similarly applied to high-level termination mode, in which case signaling 370 may have the same voltage swing (range) but the lower limit is equal to the voltage at the upper limit 360 and the upper limit is equal to voltage 355 (VDD_1). Furthermore, although system 300 is shown with one channel 325, the components and techniques described herein can be applied to interfaces containing any number of channels 325.

[0095] Figure 4A An example of system 300 is shown when channel 325 is operating (configured) in unterminated mode. For example, when channel 325 is in unterminated mode, termination component 315 can decouple terminating impedance 340 from channel 325 (or, when channel 325 is in terminated mode, decouple terminating impedance 340 from the voltage reference to which terminating impedance 340 is coupled). Therefore, with Figure 3A different, Figure 4A System 300 is shown without terminating impedance 340, because the terminating impedance can be electrically isolated from the shown aspect of system 300.

[0096] The voltage of the power supply for driver 345 (or another voltage reference related to the driver output voltage) can be adjusted (set, configured) based on the impedance of channel 325 (e.g., whether channel 325 is in terminated or unterminated mode). For example, as previously referenced Figure 3AAs described, when channel 325 is in termination mode, the voltage supply for driver 345 can be set to a first voltage, referred to as VDD_1. And when channel 325 is in unterminated mode, the voltage supply for driver 345 can be set to a second voltage, referred to as VDD_2. In some cases, the second voltage (VDD_2) may be lower than the first voltage (VDD_L). For example, in some cases, when channel 325 is in termination mode, VDD_2 may be equal to the upper limit 360 of signaling 370.

[0097] Different voltages supplied to driver 345 can result in similar voltage levels (range, upper limit) on channel 325 for both unterminated and terminated operations, as referenced. Figure 4B Further description. For example, both VDD_2 and VDD_1 can be configured such that the signaling voltage on channel 325 remains below a threshold (e.g., the maximum operating voltage of channel 325, such as a limitation imposed by an industry standard or based on the voltage tolerance of one or more components of receiver 310) regardless of whether channel 325 is terminated or unterminated. Additional factors that may affect the value of the second voltage (VDD_2) relative to the first voltage (VDD_1) may include a speed or data rate metric of system 300, a power consumption metric of system 300, or any combination thereof.

[0098] Therefore, channel 325 can be operated using two voltages (e.g., supply voltages) of driver 345 such that when channel 325 is unterminated, the voltage on channel 325 is substantially lower than the voltage of driver 345 when channel 325 is terminated. For example, when channel 325 is unterminated, the voltage on channel 325 may be less than or equal to half of the supply voltage of driver 345 when channel 325 is terminated (e.g., it may have an upper limit less than or equal to half of VDD_1).

[0099] In some cases, the transmitting device 305 can generate both VDD_1 and VDD_2. In some cases, the transmitting device 305 can receive VDD_1 (e.g., via a pin, such as the VDDQ pin) and can generate VDD_2 when channel 325 is in unterminated mode (e.g., based on down-converted VDD_1). In some cases, the transmitting device 305 can receive VDD_1 (e.g., via a pin) when channel 325 is in terminated mode and receive VDD_2 (e.g., via a pin) when channel 325 is in unterminated mode—in which case another device (e.g., receiving device 310) can adjust the power supply outside the transmitting device 305 to switch between VDD_1 and VDD_2.

[0100] In some cases, the voltages of one or both of VDD_1 and VDD_2 may be configured dynamically or as part of a boot sequence by the receiving device 310 or another component of the programmable system 300 (e.g., another processor or controller). For example, the transmitting device 305 may receive signaling, execute a fuse loading procedure, or otherwise receive (acquire) indications of one or both of VDD_1 and VDD_2, and may store the corresponding values ​​in one or more mode registers.

[0101] In some cases, the transmitting device 305 may receive signaling from the receiving device 310 (e.g., through channel 325 if channel 325 is bidirectional, or through another channel) indicating a change from a terminated channel to an unterminated channel, and vice versa. The indication may be or include indications of data rate, modulation scheme, driver power supply voltage, or other parameters associated with operating channel 325 in the mode to which channel 325 is changed. In some instances, the data rate of communication on channel 325 may be reduced when channel 325 is changed to unterminated mode and increased when channel 325 is changed to terminated mode.

[0102] In some instances, the impedance of driver 345 (e.g., output impedance) can be configurable (e.g., dynamically adjustable). For example, driver 345 can be configured such that when channel 325 operates in unterminated (or other higher impedance) mode, one or both of pull-up impedance 330 and pull-down impedance 335 have a higher impedance than when operating in terminated (or other lower impedance) mode. This can allow (or at least improve) impedance matching between driver 345 and channel 325 as the impedance of channel 325 changes. In some cases, this can further eliminate or mitigate capacitance increases at the pins of channel 325 or other aspects (e.g., pins of transmitting device 305 or receiving device 310 that may be included in channel 325).

[0103] Figure 4B An example is shown based on an eye diagram 450 for driving multi-voltage operation of a multi-mode channel, as disclosed herein. (See reference...) Figure 4A As described in the system 400 shown, eye diagram 450 illustrates an instance of signaling 470 on the channel when the channel 425 is in unterminated mode.

[0104] As shown in eye diagram 350, when channel 325 is terminated, signaling 370 can vary from the lower limit 465 to the upper limit 460, and therefore can have a voltage swing (range) equal to the difference between the upper limit 460 and the lower limit 465. When driver 345 drives channel 325 low, because there is an open circuit (excluding parasitic effects) between channel 325 and the voltage reference to which it is coupled in termination mode, no (or minimal) current can flow through terminating impedance 340 or pull-down impedance 335. Therefore, there may be no voltage drop between terminating impedance 340 or pull-down impedance 335, and the lower limit 465 may correspond to (e.g., equal to or approximately equal to) the lower rail or lower voltage supply (VSS) of driver 345.

[0105] Similarly, when driver 345 drives channel 325 high in unterminated mode, because there is an open circuit (excluding parasitic effects) between channel 325 and the voltage reference it is coupled to in terminated mode, no (or minimal) current can flow through termination impedance 340 or pull-up impedance 330. Therefore, there may be no voltage drop between termination impedance 340 and pull-up impedance 330, and upper limit 460 may correspond to (e.g., equal to or approximately equal to) the upper rail or upper voltage supply (VDD) of driver 345.

[0106] Therefore, when channel 325 is unterminated, the upper limit 460 can be equal to the voltage supply of driver 345. Thus, if the voltage of the voltage supply of driver 345 is adjusted to be below a threshold (e.g., below the maximum operating voltage of channel 325, such as the voltage tolerance of one or more transistors contained in receiver 310) when channel 325 is unterminated, the upper limit 460 can be below the threshold. Furthermore, if the adjusted (reduced) voltage (VDD_2) of the voltage supply of driver 345 is configured to be equal to the upper limit 360 (as associated with operating the channel in termination mode) when channel 325 is unterminated, the upper limit 460 can be equal to the upper limit 360. Alternatively, when the channel is unterminated, the signaling on channel 325 can have the same voltage swing as when the channel is terminated (e.g., the same upper limit, the same lower limit, the same range). Therefore, when the channel is unterminated, the receiving device 310 (e.g., receiving component 320) can monitor the channel 325 to perform signaling with the same voltage swing (or any amount of the same voltage level, such as the same upper and lower limits) as when the channel is terminated.

[0107] Although system 300 and eye diagram 450 are shown and described in the context of low-level termination mode, those skilled in the art will understand that the systems and techniques described herein can be similarly applied to high-level termination mode, in which case signaling 470 may have the same voltage swing (range) but the lower limit is equal to the voltage at the upper limit 460 and the upper limit is equal to voltage 455. Furthermore, although system 300 is shown with one channel 325, the components and techniques described herein can be applied to interfaces containing any number of channels 325.

[0108] Furthermore, although the system 300 and eye diagrams 350, 450 are shown and described in the context of the channel 325 varying between a first mode terminated by the channel 325 and a second mode unterminated by the channel 325, the teachings herein can be applied to any number of modes corresponding to any number of various terminating impedances 340 of the channel 325.

[0109] Furthermore, although system 300 and eye diagrams 350, 450 are shown and described in the context of channel 325-based mode adjustment for the power supply voltage of driver 345, the teachings herein can be applied to adjust one or more other voltages associated with driver 345 to maintain a desired voltage level on channel 325.

[0110] Figure 5A An example of a timing diagram 500 for driving a multi-voltage channel according to the disclosure herein is shown. Timing diagram 500 illustrates how the voltage of the voltage supply of driver 345 may be adjusted over time according to the mode (e.g., terminated or unterminated) of the channel 325 driven by driver 345.

[0111] Figure 5A It includes three time periods: time period 505, time period 510, and time period 515, where a time period can be a period of time. During time periods 505 and 515, the channel can be in a first (e.g., terminated, low impedance) mode, and the power supply voltage of the driver 345 can be at a first voltage 520 (e.g., VDD_1 as described with reference to Figures 3 and 4).

[0112] During period 510, the channel may be in a second (e.g., unterminated, high-impedance) mode, and the power supply voltage of driver 345 may be at a second voltage 525 (e.g., VDD_2 as described with reference to Figures 3 and 4). The second voltage 525 may be lower than the first voltage 520 (e.g., a fraction of VDD_1, such as half of VDD_1). Therefore, when channel 325 is in unterminated mode, the power supply voltage of driver 345 may be adjusted (e.g., reduced) compared to when channel 325 is in terminated mode.

[0113] Figure 5AThe diagram further illustrates a gap 530 between time periods 505 and 510, and between time periods 510 and 515. Gap 530 may correspond to the elapsed time associated with switching channel 325 between a first mode and a second mode, adjusting the voltage supply of driver 345 from a first voltage 520 to a second voltage 525 (or vice versa), or both. When the voltage transitions between the first voltage 520 and the second voltage 525, the driver may (e.g., during a period of time in gap 530) avoid generating signaling and outputting signaling on channel 325.

[0114] Figure 5B Eye diagram 550 is shown, which includes an example of signaling for driving multi-voltage operation of a multi-mode channel according to the disclosure herein. Eye diagram 555 may represent signaling on channel 325 when channel 325 is in a first mode (e.g., during time period 505 or 515), while eye diagram 560 may represent signaling on channel 325 when channel is in a second mode (e.g., during time period 510).

[0115] like Figure 5B As shown, when channel 325 is in the second mode (e.g., unterminated), changing (e.g., reducing) the power supply voltage for driver 345 from the first voltage 520 to the second voltage 525 allows signaling on channel 325 to have the same voltage swing (range), the same upper limit 570, or both, as when channel 325 is in the first mode (e.g., terminated). Therefore, receiver 310 can monitor signaling with the same voltage swing (range), the same upper limit 570, or both, regardless of whether channel 325 is in the first or second mode (e.g., terminated or unterminated). This simplifies the design of receiver 310, supports the use of components with lower voltage tolerances (e.g., transistors) or both at receiver 310, and offers other benefits. For example, in Figure 5B In this context, voltage 565 can be VDD_1, as described with reference to Figures 3 and 4, and the voltage at the upper limit 570 can be VDD_2, as described with reference to Figures 3 and 4. When channel 325 is terminated and when channel 325 is not terminated, the upper limit of the signaling on channel 325 can, for example, be the voltage at the upper limit 570.

[0116] Figure 5C Eye diagram 575 is shown, which includes an example of signaling for driving multi-voltage operation of a multi-mode channel according to the disclosure herein. Eye diagram 580 may represent signaling on channel 325 when channel 325 is in a first mode (e.g., during time period 505 or 515), while eye diagram 585 may represent signaling on channel 325 when channel is in a second mode (e.g., during time period 510).

[0117] like Figure 5CAs shown, when channel 325 is in the second mode (e.g., unterminated), changing (e.g., reducing) the power supply voltage for driver 345 from the first voltage 520 to the second voltage 525 allows signaling on channel 325 to have the same voltage swing (range), the same upper limit 595, or both, as when channel 325 is in the first mode (e.g., terminated). Therefore, receiver 310 can monitor signaling with the same voltage swing (range), the same upper limit 595, or both, regardless of whether channel 325 is in the first or second mode (e.g., terminated or unterminated). This simplifies the design of receiver 310, supports the use of components with lower voltage tolerances (e.g., transistors) or both at receiver 310, and offers other benefits. For example, in Figure 5C In this context, voltage 590 can be VDD_1, as described with reference to Figures 3 and 4, and the voltage at the upper limit 595 can be VDD_2, as described with reference to Figures 3 and 4. When channel 325 is terminated and when channel 325 is not terminated, the upper limit of signaling on channel 325 can, for example, be the voltage at the upper limit 595.

[0118] In some cases, signaling on channel 325 can occur at a higher data rate when channel 325 is terminated, compared to the lower data rate when channel is unterminated. In some instances, a higher data rate can be achieved by increasing the modulation order used for signaling on channel 325. For example, as discussed above, operating channel 325 in terminated mode provides signal integrity and related benefits, and therefore channel 325 can support higher data rates when in terminated mode. Conversely, also as discussed above, operating channel 325 in unterminated mode provides power efficiency and related benefits, and therefore unterminated channel 325 can be used to save power during lower power or idle modes while still supporting signaling, although possibly at a reduced data rate. Therefore, the termination mode of channel 325 may correspond to, or be referred to as, a high-speed, high-performance, or high-power mode in some cases, and the unterminated mode of channel 325 may correspond to, or be referred to as, a low-speed, low-performance, or low-power mode in some cases.

[0119] Compared to when channel 325 is in unterminated mode, when channel 325 is in terminated mode, the data rate can be increased by increasing the symbol (baud) rate on channel 325, increasing the modulation order used for signaling on channel 325, or both. Therefore, in some cases, receiving device 310 may indicate a mode change of channel 325 to transmitting device 305 based on a change in the data rate on channel 325 (e.g., indicating a target data rate higher or lower than a threshold, or a target data rate different from the current (existing) data rate or data rate range). Similarly, transmitting device 305 may change the mode of channel 325 based on a change (e.g., determining a change) or by receiving an indication of a change in the data rate on channel 325.

[0120] As described above, in some cases, the modulation scheme can switch from a lower modulation order (e.g., binary) to a higher modulation order (e.g., non-binary) and vice versa based on the mode of channel 325 (e.g., to achieve a change in data rate). For example, as shown in eye diagram 580, when the channel is in a first (e.g., terminated) mode, driver 345 can output signaling using a first modulation scheme (e.g., PAM4) on channel 325. And as shown in eye diagram 585, when the channel is in a second (e.g., unterminated) mode, driver 345 can output signaling using a second modulation scheme (e.g., NRZ or PAM2) on channel 325. The first modulation scheme may have a higher order than the second modulation scheme, and therefore the first modulation scheme may be, for example, a PAM3 modulation scheme or a PAM4 modulation scheme with at least three voltage levels. The second modulation scheme may be, for example, a PAM2 modulation scheme or an NRZ modulation scheme. Therefore, in some instances, when the channel 325 has a first impedance, the receiving device 310 can monitor the channel 325 to perform signaling corresponding to the first modulation step, and when the channel 325 has a second impedance, the receiving device 310 can monitor the channel 325 to perform signaling corresponding to the second modulation step.

[0121] Additionally, the transmitting device 305 and the receiving device 310 can exchange signaling to indicate the mode of channel 325 (e.g., indicating a switch between a first mode and a second mode). In some cases, the indication may be or include an indication of a reduced data rate on channel 325. The signaling indicating the mode of channel 325 may be transmitted on channel 325 (where channel 325 is bidirectional) or on one or more other channels (e.g., channel 325 may be DQ channel 190, and the indication may be transmitted on one or more C / A channels 186).

[0122] Figure 6An example of a process flow 600 supporting multi-voltage operation for driving a multi-mode channel is shown according to the examples disclosed herein. Process flow 600 may illustrate the functionality and communication between a transmitting device 605 and a receiving device 610. The transmitting device 605 and the receiving device 610 may be coupled to and communicate with each other via a channel. The transmitting device 605 and the receiving device 610 may be examples of transmitting device 305 and receiving device 310, respectively, as described with reference to Figures 3-5. For example, the transmitting device 305 may be a memory device 110, and the receiving device may be a host device of the memory device 110 (e.g., an external memory controller 105), or vice versa.

[0123] At 615, the receiving device 610 can operate the channel in a first mode. In the first mode, the channel may have a first impedance. For example, when operating in the first mode, the channel may be terminated. In some cases, the first mode may correspond to a first operating mode of the system including the receiving device 610, such as a high-speed, high-performance, or high-power mode of the system.

[0124] In 615-a, when operating the channel in the first mode, the receiving device 610 can monitor the channel for signaling according to the first mode. The signaling according to the first mode may include signaling with a first voltage swing (range, upper limit, and lower limit). Alternatively, the signaling according to the first mode may include signaling with a first data rate (e.g., a data rate higher than a threshold) on the channel. Alternatively, the signaling according to the first mode may include signaling modulated according to a first modulation scheme (e.g., a higher-order non-binary modulation scheme, such as PAM3 or PAM4, which can support a first data rate higher than the threshold).

[0125] At 620, the transmitting device 605 can identify that the channel operates in a first mode. In some cases, the transmitting device 605 can identify that the channel operates in the first mode based on one or more signals received by the transmitting device 605 (e.g., from the receiving device 610). For example, the transmitting device 605 can receive an indication of the channel mode via one or more other channels (e.g., the channel could be DQ channel 190, and the transmitting device 605 could receive an indication of the channel mode via C / A channel 186). In some cases, the indication of the channel mode can be an indication of the channel's target or requested data rate (e.g., a requested data rate above a threshold data rate). In some cases (not shown), the transmitting device 605 can control the channel mode and can indicate the channel mode to the receiving device 610.

[0126] At 625, based on the channel being in a first mode, the transmission device 605 can set the voltage supply for the driver to a first voltage (e.g., VDD_1) corresponding to the first mode, which can support signaling with a first voltage swing. The transmission device 305 can also configure the driver to generate and output signaling on the channel according to the first mode (e.g., according to a first modulation scheme, having a first data rate). In some cases, based on the channel being in the first mode, the transmission device 305 can also set the output impedance of the driver to a first output impedance corresponding to the first mode.

[0127] At 630, the transmission device 605 can output signaling according to a first mode on the channel, which can be received by the receiving device 610.

[0128] At 635, the receiving device 610 can switch the channel to a second mode. In the second mode, the channel can have a second impedance, which may be higher than the first impedance. For example, when operating in the second mode, the channel may be unterminated. In some cases, the second mode may correspond to a second operating mode of the system including the receiving device 610, such as a low-speed, low-performance, or low-power mode of the system.

[0129] At 640, the receiving device 610 can transmit an indication to the transmitting device 605 to switch to the second mode. In some cases, the indication to switch to the second mode may be an indication of a second data rate, a second modulation scheme, or any other characteristic associated with the second mode. The indication may be transmitted at 640 through a channel different from the channel being switched to the second mode (e.g., C / A channel 186). In some cases (not shown), the transmitting device 605 may control the mode of the channel and may switch the channel to the second mode and indicate to the receiving device 610 to switch to the second mode.

[0130] At 645, the receiving device 610 can operate the channel in the second mode.

[0131] In 645-a, when operating the channel in the second mode, the receiving device 610 can monitor the channel to perform signaling according to the second mode. The signaling according to the second mode may include signaling having a second voltage swing (range, upper limit, and lower limit) with the same voltage swing as the first voltage swing. Alternatively, the signaling according to the second mode may have an upper limit below a threshold, wherein the signaling according to the first mode also has an upper limit below a threshold.

[0132] Alternatively or alternatively, the signaling according to the second mode may include signaling having a second data rate on the channel (e.g., below a threshold data rate, or otherwise below a first data rate). Alternatively or alternatively, the signaling according to the second mode may include signaling modulated according to a second modulation scheme, which may be of a lower order than the first modulation scheme (e.g., the second modulation scheme may be a binary modulation scheme, such as PAM2 or NRZ, which may correspond to a second data rate below the first data rate). Alternatively or alternatively, the signaling according to the second mode may have a second baud rate, wherein the signaling according to the first mode may have a first (e.g., higher) baud rate.

[0133] At 650, the transmission device 605 can identify that the channel is operating in the second mode. In some cases, the transmission device 605 can identify that the channel is operating in the second mode based on an indication received at 640.

[0134] At 655, based on the channel being in the first mode, the transmission device 605 can adjust (set) the voltage power supply for the driver to a second voltage (e.g., VDD_2) corresponding to the second mode. The second voltage may be lower than the first voltage. When the channel is in the second mode, setting the voltage power supply for the driver to the second voltage can support signaling on the channel with an upper limit (e.g., voltage swing) below a voltage threshold (e.g., the maximum operating voltage of the channel). In some cases, the second voltage may be equal to the upper limit of the signaling output at 630 (when the channel operates in the first mode). Alternatively, the second voltage may be half of the first voltage. The transmission device 305 may also configure the driver to generate and output signaling on the channel according to the second mode (e.g., according to the second modulation scheme, having a second data rate).

[0135] In some cases, based on the channel being in the second mode, the transmission device 305 may also set the output impedance of the driver to a second output impedance corresponding to the second mode, which may be higher than the first output impedance corresponding to the first mode.

[0136] At 660, the transmission device 605 can output signaling according to a second mode on the channel, the second mode of signaling being received by the receiving device 610.

[0137] Although example process flow 600 illustrates a channel switching from a first mode to a second mode, and the voltage supply for the driver correspondingly switching from a first voltage to a second voltage, it should be understood that the channel can also switch from the second mode to the first mode, and the voltage supply for the driver can correspondingly switch from the second voltage to the first voltage. Furthermore, although example process flow 600 illustrates a channel switching mode once, and the voltage supply for the driver correspondingly switching voltage once, it should be understood that the channel mode and the voltage supply voltage can be changed any number of times. Similarly, the channel can have any number of modes (e.g., any number of combinations of various channel impedances, data rates on the channel, and modulation schemes for signaling on the channel), and the voltage supply for the driver can have any number of corresponding voltages.

[0138] Figure 7 A block diagram 700 is shown illustrating an apparatus 705 for supporting multi-voltage operation for driving a multi-mode channel, according to an example disclosed herein. Apparatus 705 may be as described in reference... Figure 1-6 Examples of described aspects of memory systems or other computing systems include, for example, transmission device 305. Device 705 may include a pattern recognition component 710, a voltage power supply component 715, a signal output component 720, a signal output modulation component 725, a receiving component 730, a communication component 735, and a driver configuration component 740. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses).

[0139] Pattern recognition component 710 can identify that the channel between the first device (device 705) and the second device is in a first mode, in which the channel is terminated. In some instances, the first device may be a memory device, and the second device may be a host device coupled to the memory device. Voltage power supply component 715 can set the voltage power supply for the driver coupled to the channel to a first voltage based on the channel termination. In some instances, the first device may be a memory device, and the second device may be a host device coupled to the memory device.

[0140] In some instances, after the voltage power supply assembly 715 sets the voltage power supply to a first voltage, the pattern recognition assembly 710 can identify that the channel is in a second mode, in which the channel is unterminated. In some instances, the pattern recognition assembly 710 can identify that the channel changes from the first mode to the second mode. In some instances, the voltage power supply assembly 715 can adjust the voltage power supply for the driver to a second voltage lower than the first voltage based on the unterminated channel. In some instances, the second voltage can be half of the first voltage. In some instances, the first mode can correspond to a first impedance between the channel and a voltage reference, the second mode can correspond to a second impedance between the channel and the voltage reference, the second impedance being greater than the first impedance, and the second voltage can be based at least partially on the first impedance and the impedance of the driver. Additionally, in some instances, the voltage reference can be at a voltage lower than the second voltage.

[0141] The signal output component 720 may include a driver, and when the channel is in a first mode, the driver may output a signaling on the channel with a first voltage swing less than a threshold. In some instances, the signal output component 720 may output a signaling on the channel with a second voltage swing less than a threshold when the channel is in a second mode and based on adjusting the voltage supply to a second voltage.

[0142] In some instances, the signal output component 720 can be driven by a driver to output signaling with an upper limit for the first mode when the channel is in a first mode, wherein adjusting the voltage supply for the driver to a second voltage includes setting the voltage supply to be equal to the upper limit of the signaling for the first mode. In some instances, the signal output component 720 can be driven by a driver to avoid outputting signaling on the channel for a period of time based on the channel changing from the first mode to the second mode.

[0143] The signal output modulation component 725 can output signaling using a first modulation scheme on the channel by the driver when the channel is in a first mode. In some instances, the signal output modulation component 725 can output signaling using a second modulation scheme on the channel by the driver when the channel is in a second mode. In some instances, the first modulation scheme may have a higher order than the second modulation scheme. Additionally, in some instances, the first modulation scheme may be a Pulse Amplitude Modulation 3 (PAM3) or Pulse Amplitude Modulation 4 (PAM4) modulation scheme, and the second modulation scheme may be a Pulse Amplitude Modulation 2 (PAM2) or Non-Return-to-Zero (NRZ) modulation scheme.

[0144] The receiving component 730 can receive at the first device an indication of a change from the channel being in a first mode to the channel being in a second mode, wherein identifying the channel as being in the second mode is based on receiving the indication. In some instances, the indication of the change can indicate the data rate associated with the second mode.

[0145] Communication component 735 can communicate on the channel using a first data rate when the channel is in a first mode. In some instances, communication component 735 can communicate on the channel using a second data rate lower than the first data rate when the channel is in a second mode.

[0146] The driver configuration component 740 can configure the driver to have a first impedance when the channel is terminated. In some instances, the driver configuration component 740 can configure the driver to have a second impedance when the channel is unterminated, the second impedance being higher than the first impedance.

[0147] Figure 8 A block diagram 800 is shown illustrating an apparatus 805 for supporting multi-voltage operation for driving a multi-mode channel, according to an example disclosed herein. Apparatus 805 may be as described in reference... Figure 1-6 Examples of aspects of the described memory system or other computing system, such as receiving device 310. Device 805 may include channel monitoring component 810, channel operation component 815, and transmission component 820. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses).

[0148] The channel monitoring component 810 can monitor the channel for signaling with voltage swing when operating the channel between the first and second devices using a first impedance. In some instances, the channel monitoring component 810 can monitor the channel for signaling with voltage swing when operating the channel using a second impedance. In some instances, the channel monitoring component 810 can monitor the channel for signaling according to a first modulation order when operating the channel using a first impedance. In some instances, the channel monitoring component 810 can monitor the channel for signaling according to a second modulation order lower than the first modulation order when operating the channel using a second impedance. In some instances, the signaling according to the first modulation order may include three or more voltage levels.

[0149] Channel operation component 815 can operate the channel (e.g., by controlling, as referenced) Figure 3A The described terminal component 315). In some instances, the channel operation component 815 can operate the channel using a first impedance when the channel is in a first mode, and operate the channel using a second impedance when the channel is in a second mode. In some cases, the channel operation component 815 can switch the channel to a second impedance with a higher impedance than the first impedance.

[0150] The transmission component 820 can transmit an indication to the second device of switching from a first impedance to a second impedance. In some instances, the indication of switching from the first impedance to the second impedance can include an indication of a reduction in the data rate on the channel. Furthermore, in some instances, operating the channel using the first impedance can include operating the channel in a termination mode, and operating the channel using the second impedance can include operating the channel in an untermination mode.

[0151] Figure 9 A flowchart illustrating one or more methods 900 supporting multi-voltage operation for driving a multi-mode channel according to aspects of this disclosure is provided. Operation of method 900 may be implemented by means or components thereof as described herein. For example, operation of method 900 may be performed by means as described in reference... Figure 7 The described device performs the function. In some instances, the device can execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the device may use dedicated hardware to perform aspects of the described function.

[0152] At 905, the device can identify that the channel between the first device (e.g., the device itself) and the second device is in a first mode, in which the channel is terminated. Operation of 905 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of operation of 905 can be as described in reference... Figure 7 The described pattern recognition component is used to perform this.

[0153] In 910, the device can set the voltage supply for the driver coupled to the channel to a first voltage based on the channel termination. Operation of 910 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 910 can be determined by, as shown in reference... Figure 7 The voltage power supply component described is used to perform this.

[0154] In 915, the device can recognize that after the voltage supply is set to a first voltage, the channel is in a second mode, in which the channel is unterminated. Operation of 915 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of operation of 915 can be as described in reference... Figure 7 The described pattern recognition component is used to perform this.

[0155] In 920, the device can adjust the voltage supply for the driver to a second voltage lower than the first voltage based on the unterminated channel. Operation of 920 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 920 can be determined by, as shown in reference... Figure 7 The voltage power supply component described is used to perform this.

[0156] In some instances, the device described herein can perform one or more methods, such as method 900. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: identifying that a channel between a first means (e.g., the device) and a second means is in a first mode, in which the channel is terminated; setting a voltage supply for a driver coupled to the channel to a first voltage based on the channel termination; identifying that the channel is in a second mode after the voltage supply is set to the first voltage, in which the channel is unterminated; and adjusting the voltage supply for the driver to a second voltage lower than the first voltage based on the unterminated channel.

[0157] Method 900 and some examples of the devices described herein may further include operations, features, components, or instructions for performing the following: when the channel is available in a first mode, the driver outputs a signaling on the channel with a first voltage swing that may be less than a threshold; and when the channel is available in a second mode, the driver outputs a signaling on the channel with a second voltage swing that may be less than a threshold based on adjusting the voltage power supply to a second voltage.

[0158] Method 900 and some examples of the devices described herein may further include operations, features, components, or instructions for performing the following: when the channel is available in a first mode, the driver outputs signaling for the first mode that may have an upper limit, wherein adjusting the voltage supply for the driver to a second voltage includes setting the voltage supply to be equal to the upper limit of the signaling for the first mode.

[0159] In some instances of method 900 and the devices described herein, the second voltage may be half of the first voltage.

[0160] Method 900 and some examples of the apparatus described herein may further include operations, features, components, or instructions for performing the following: when the channel is available in a first mode, the driver outputs signaling on the channel using a first modulation scheme; and when the channel is available in a second mode, the driver outputs signaling on the channel using a second modulation scheme.

[0161] In some instances of method 900 and the devices described herein, the first modulation scheme may have a higher order than the second modulation scheme.

[0162] In some instances of method 900 and the device described herein, the first modulation scheme may be a pulse amplitude modulation three (PAM3) or pulse amplitude modulation four (PAM4) modulation scheme; and the second modulation scheme may be a pulse amplitude modulation two (PAM2) or non-return-to-zero (NRZ) modulation scheme.

[0163] Method 900 and some examples of the devices described herein may further include operations, features, components, or instructions for receiving an indication at a first device of a change from a channel being in a first mode to a channel being in a second mode, wherein identifying the channel being in the second mode may be based on receiving the indication.

[0164] In method 900 and some instances of the devices described herein, the changing indication indicates the data rate associated with the second mode.

[0165] Method 900 and some examples of the devices described herein may further include operations, features, components, or instructions for performing the following: when the channel is in a first mode, communicating on the channel using a first data rate; and when the channel is in a second mode, communicating on the channel using a second data rate that may be lower than the first data rate.

[0166] In some instances of method 900 and the device described herein, the first mode corresponds to a first impedance between the channel and a voltage reference; the second mode corresponds to a second impedance between the channel and a voltage reference, the second impedance being greater than the first impedance; and the second voltage may be based on the first impedance and the impedance of the driver.

[0167] In some instances of method 900 and the devices described herein, the voltage reference may be at a voltage lower than the second voltage.

[0168] Method 900 and some examples of the devices described herein may further include operations, features, components, or instructions for performing the following: configuring the driver to have a first impedance when the channel is terminated; and configuring the driver to have a second impedance when the channel is unterminated, the second impedance being higher than the first impedance.

[0169] Method 900 and some instances of the device described herein may further include operations, features, components, or instructions for performing the following: identifying a channel transition from a first mode to a second mode; and, based on the channel transition from the first mode to the second mode, having the driver avoid outputting signaling on the channel for a period of time.

[0170] In some instances of method 900 and the devices described herein, the first device may be a memory device and the second device may be a host device coupled to the memory device.

[0171] Figure 10 A flowchart illustrating one or more methods 1000 supporting multi-voltage operation for driving a multi-mode channel according to aspects of this disclosure is provided. Operation of method 1000 may be implemented by means or components thereof as described herein. For example, operation of method 1000 may be performed by means as described in reference... Figure 7The described device performs the function. In some instances, the device can execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the device may use dedicated hardware to perform aspects of the described function.

[0172] At 1005, the device can identify that the channel between the first device and the second device is in a first mode, in which the channel is terminated. The operation of 1005 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 1005 can be as described in reference... Figure 7 The described pattern recognition component is used to perform this.

[0173] In 1010, the device can set the voltage supply for the driver used to couple with the channel to a first voltage based on the channel termination. Operation of 1010 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 1010 can be as described in reference... Figure 7 The voltage power supply component described is used to perform this.

[0174] In 1015, the device can output signaling with a first voltage swing less than a threshold on the channel by the driver when the channel is in the first mode. The operation of 1015 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 1015 can be as described in reference... Figure 7 The described signal output component is used to perform this action.

[0175] In 1020, the device can recognize that after the voltage supply is set to a first voltage, the channel is in a second mode, in which the channel is unterminated. Operation of 1020 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of operation of 1020 can be as described in reference... Figure 7 The described pattern recognition component is used to perform this.

[0176] In 1025, the device can adjust the voltage supply for the driver to a second voltage lower than the first voltage based on the unterminated channel. Operation of 1025 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 1025 can be as described in reference... Figure 7 The voltage power supply component described is used to perform this.

[0177] In 1030, the device can, when the channel is in the second mode, output signaling with a second voltage swing less than a threshold on the channel by a driver based on adjusting the voltage supply to a second voltage. The operation of 1030 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 1030 can be as described in reference... Figure 7 The described signal output component is used to perform this action.

[0178] Figure 11 A flowchart illustrating one or more methods 1100 supporting multi-voltage operation for driving a multi-mode channel according to aspects of this disclosure is shown. Operation of method 1100 may be implemented by means or components thereof as described herein. For example, operation of method 1100 may be performed by means as described in reference... Figure 8 The described device performs the function. In some instances, the device can execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the device may use dedicated hardware to perform aspects of the described function.

[0179] At 1105, the device can monitor the channel for signaling with voltage swing when operating the channel between the first device (e.g., the device) and the second device using the first impedance. The operation of 1105 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 1105 can be as described in reference... Figure 8 The described channel monitoring component is used to perform this.

[0180] At 1110, the device can switch the channel to a second impedance with a higher impedance than the first impedance. The operation of 1110 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 1110 can be as described in reference... Figure 8 The described channel switching component is used to perform this.

[0181] At 1115, the device can monitor the channel to perform signaling with a voltage swing (i.e., the same voltage swing monitored at 1105) when using the second impedance operation channel. The operation of 1115 can be performed according to the method described with reference to Figures 3 to 6. In some instances, aspects of the operation of 1115 can be determined by, as referenced... Figure 8 The described channel monitoring component is used to perform this.

[0182] In some instances, the device described herein can perform one or more methods, such as method 1100. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: monitoring the channel to perform signaling with a voltage swing when operating the channel between the first device (e.g., the device) and the second device using a first impedance; switching the channel to a second impedance having a higher impedance than the first impedance; and monitoring the channel to perform signaling with a voltage swing when operating the channel using the second impedance.

[0183] Method 1100 and some examples of the apparatus described herein may further include operations, features, components, or instructions for performing the following: monitoring the channel for signaling according to a first modulation order when using a first impedance-operated channel; and monitoring the channel for signaling according to a second modulation order that may be lower than the first modulation order when using a second impedance-operated channel.

[0184] In some instances of method 1100 and the devices described herein, the signaling according to the first modulation step includes three or more voltage levels.

[0185] Method 1100 and some examples of the devices described herein may further include operations, features, components or instructions for transmitting an indication to a second device to switch from a first impedance to a second impedance.

[0186] In some instances of method 1100 and the devices described herein, the indication of switching from a first impedance to a second impedance includes an indication of a reduction in the data rate on the channel.

[0187] In some instances of method 1100 and the device described herein, the operation channel using a first impedance can be included in the operation channel in a termination mode; and the operation channel using a second impedance can be included in the operation channel in an untermination mode.

[0188] In some instances of method 1100 and the devices described herein, the first device may be a memory device and the second device may be a host device coupled to the memory device.

[0189] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0190] In some instances, a device or apparatus may perform aspects of the functions described herein. The apparatus may include a driver coupled to a channel for communication with the device, a voltage supply coupled to the driver, and a controller coupled to the voltage supply. The controller may be configured to cause the device to: identify that the channel is in a first (terminated) mode associated with a first data rate; set the voltage supply for the driver to a first voltage corresponding to the first (terminated) mode; identify that after setting the voltage supply to the first voltage, the channel is in a second (unterminated) mode associated with a second data rate lower than the first data rate; and set the voltage supply for the driver to a second voltage corresponding to the second (unterminated) mode, wherein the second voltage is at least partially based on the channel voltage associated with the termination mode.

[0191] In some instances, the controller can be used to enable the device to: configure the driver to generate symbols representing more than one information bit when the channel is in terminated mode; and configure the driver to generate symbols representing one information bit when the channel is in unterminated mode.

[0192] In some instances, the device may further include an output pin coupled to a driver (the driver is coupled to the channel via the pin), wherein the output pin includes a DQ pin or a C / A pin.

[0193] In some instances, the second voltage may be based at least in part on the ratio between the impedance of the channel used for termination mode and the impedance of the driver.

[0194] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, wherein the bus can have various bit widths.

[0195] As used herein, the term "virtual ground" refers to a circuit node that is maintained at approximately zero volts (0V) without being directly coupled to ground. Therefore, the voltage of a virtual ground may fluctuate temporarily and return to approximately 0V. Virtual grounding can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "being virtually grounded" means connected to approximately 0V.

[0196] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that allows the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0197] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0198] The term "isolation" refers to the relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller separates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0199] As used herein, the terms “basically” and “approximately” mean that the modified characteristic (e.g., a verb or adjective modified by the terms “basically” or “approximately”) does not have to be absolute but must be close enough to obtain the advantage of the characteristic.

[0200] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-segments of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0201] The switching components or transistors discussed in this article can represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals can be connected to other electronic components via a conductive material (e.g., a metal). The source and drain can be conductive and can include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain can be separated by lightly doped semiconductor regions or channels. If the channel is n-type (e.g., most carriers are signals), then the FET can be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET can be called a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor is "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor is "off" or "deactivated."

[0202] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0203] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0204] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0205] The various illustrative blocks and modules described in this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0206] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0207] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for accessing a memory device, comprising: The memory device is identified as being in a first mode, in which the channel coupled to the driver of the memory device is unterminated; The driver transmits first signaling modulated according to a first modulation scheme on an unterminated channel according to the first mode, the first modulation scheme having a first number of voltage levels, the first number being equal to two. After transmitting the first signaling modulated according to the first modulation scheme on the unterminated channel, the memory device is identified as being in a second mode, in which the channel coupled to the driver is terminated. as well as The driver transmits second signaling modulated according to a second modulation scheme on a terminated channel according to the second mode, the second modulation scheme being different from the first modulation scheme used to transmit the first signaling on the unterminated channel, and having a second number of voltage levels greater than the first number of voltage levels, the second number being equal to three.

2. The method of claim 1, wherein the first signaling on the channel has a first voltage swing less than a threshold, and wherein the second signaling on the channel has a second voltage swing less than the threshold.

3. The method of claim 1, wherein the first signaling has an upper limit, the method further comprising: Adjusting the voltage supply for the driver from a first voltage for the first mode to a second voltage for the second mode, wherein adjusting the voltage supply includes setting the voltage supply to be equal to the upper limit of the first signaling for the first mode.

4. The method of claim 1, wherein the voltage power supply for the driver is set to a first voltage for the first mode and to a second voltage for the second mode, and wherein the second voltage is half of the first voltage.

5. The method of claim 1, further comprising: The memory device receives an indication of a change from the first mode to the second mode, wherein identifying the memory device as being in the second mode is at least in part based on receiving the indication.

6. The method of claim 5, wherein the change in the indication indicates the data rate associated with the second mode.

7. The method of claim 1, further comprising: When the channel is in the first mode, communication is performed on the channel using the first data rate; as well as When the channel is in the second mode, communication is performed on the channel using a second data rate lower than the first data rate.

8. The method according to claim 1, wherein: The first mode corresponds to the first impedance between the channel and the voltage reference; and The second mode corresponds to a second impedance between the channel and the voltage reference, the second impedance being greater than the first impedance.

9. The method of claim 8, wherein the voltage power supply for the driver is set to a first voltage for the first mode and to a second voltage for the second mode, and wherein the voltage reference is at a voltage lower than the second voltage.

10. The method of claim 1, further comprising: The memory device is identified as changing from the first mode to the second mode; as well as At least in part, based on the memory device changing from the first mode to the second mode, the driver avoids transmitting signaling on the channel for a period of time.

11. The method of claim 1, wherein the channel couples the memory device and the host device.

12. A method for accessing a memory device, comprising: On a channel coupled to a driver of the memory device and when the memory device is operated in a first mode where the channel is unterminated, a first signaling modulated according to a first modulation scheme and having a voltage swing is received, the first modulation scheme having a first number of voltage levels, the first number being equal to two. Switch from operating the memory device in the first mode to operating the memory device in the second mode terminated on the channel; as well as When the memory device is operated in the second mode, a second signaling modulated according to a second modulation scheme is received on the channel, the second modulation scheme having a second number of voltage levels greater than the first number of voltage levels, the second number being equal to three.

13. The method of claim 12, further comprising: Receive an instruction to switch from the first mode to the second mode.

14. The method of claim 13, wherein the indication of switching from the first mode to the second mode includes an indication of a reduction in the data rate on the channel.

15. The method according to claim 12, wherein: Operating the memory device in the first mode includes operating the channel having a first impedance; and Operating the memory device in the second mode includes operating the channel having a second impedance.

16. A memory device comprising: A driver that can be coupled to a channel used for communication with a host device; A voltage power supply, which is coupled to the driver; as well as A controller, coupled to the driver and configured to cause the memory device to perform the following operations: The memory device is identified as being in a first mode, in which the channel is unterminated and the first mode is associated with a first data rate; The driver is configured to transmit first signaling over an unterminated channel according to the first mode and the first modulation scheme, the first modulation scheme having a first number of voltage levels, the first number being equal to two. After transmitting the first signaling on the unterminated channel, the memory device is identified as being in a second mode, in which the channel is terminated and the second mode is associated with a second data rate lower than the first data rate; as well as The driver is configured to transmit second signaling on a terminated channel according to the second mode and the second modulation scheme, the second modulation scheme having a second number of voltage levels greater than the first number of voltage levels, the second number being equal to three.

17. The memory device of claim 16, wherein the controller is further configured to cause the memory device to perform the following operations: Configure the driver to generate symbols representing more than one information bit for the first signaling when the channel is unterminated; and The driver is configured to generate symbols for the second signaling, each representing an information bit, when the channel is terminated.

18. The memory device of claim 16, further comprising: Output pins coupled to the driver, wherein the output pins include data (DQ) pins or command / address (C / A) pins.

19. The memory device of claim 16, wherein the channel has a first impedance when unterminated and a second impedance when terminated.

Images