Heterojunction power device based on group III nitride power semiconductor and manufacturing method thereof, and heterojunction chip with at least three terminals

Abstract

The present disclosure relates to power semiconductor devices in GaN technology. The present disclosure proposes an integrated auxiliary (dual) gate terminal and a pull-down network to realize a normally-off (E-mode) GaN transistor with a threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high voltage active GaN device and a low voltage auxiliary GaN device, wherein the high voltage GaN device has a gate (10) connected to the source (12) of the integrated auxiliary low voltage GaN transistor and a drain as an external high voltage drain terminal (9) and a source as an external source terminal (8), while the low voltage auxiliary GaN transistor has a gate (first auxiliary electrode 15) connected to the drain (second auxiliary electrode 16) serving as an external gate terminal. In an embodiment, the pull-down network for turning off the high threshold voltage GaN transistor is formed by an additional auxiliary low voltage GaN transistor (34) and a resistive element connected in parallel or in series with the low voltage auxiliary GaN transistor.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device, for example, to a heterostructure aluminum gallium nitride / gallium nitride (AlGaN / GaN) high electron mobility transistor (HEMT) or a rectifier. Background Art

[0002] A power semiconductor is a semiconductor device used as a switch or rectifier in power electronics (e.g. a DC to AC inverter for motor control, or a DC to DC converter for a switched-mode power supply). A power semiconductor is typically used in "commutation mode" (i.e. it is either on or off) and therefore has a design optimized for such use.

[0003] Typically, power devices have voltage ratings (i.e., the potential difference that the device must withstand between its major terminals in the off state) in excess of 20V and conduct in excess of 100mA during the on state. More commonly, power devices are rated at over 60V and over 1A. These values ​​make power devices very different from low-power devices, which operate at voltages below 5V and typical currents under 1mA, and more commonly in the µAs or sub-µAs range. Another difference between power devices and other types of devices, such as low power or RF, is that they operate primarily with large signals and they behave like switches. Exceptions are found in high voltage or power amplifiers, which use specialized power transistors.

[0004] Silicon bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs) are common types of power semiconductor switching devices. Their applications range from portable consumer electronics, home appliances, hybrid and electric vehicles, motor control and power supplies to radio frequency and microwave circuits and telecommunication systems.

[0005] Gallium nitride (GaN) is increasingly being recognized as a very promising material for use in power devices with the potential for increased power density, reduced on-resistance, and high-frequency response. g =3.39eV) leads to a high critical electric field (E c =3.3MV / cm), this high critical electric field can lead to the design of devices with shorter drift regions and therefore lower on-state resistance when compared to silicon-based devices with the same breakdown voltage [1]. The use of AlGaN / GaN heterostructures also allows the formation of a two-dimensional electron gas (2DEG) at the heterointerface, where carriers can achieve very high mobility (μ = 2000cm 2 / (Vs)) value [1]. In addition, the piezoelectric charges present at the AlGaN / GaN heterostructure lead to a high electron density in the 2DEG layer (e.g., 1x10 13 cm -2 ). These properties allow the development of high electron mobility transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters [2], [3]. A lot of research is focused on the development of power devices using AlGaN / GaN heterostructures.

[0006] However, the 2DEG inherently present at the AlGaN / GaN heterointerface presents a challenge when trying to design a normally-off device rather than a normally-on device. Nevertheless, since normally-off transistors are preferred in most power electronics applications, several approaches have been proposed that can lead to enhancement-mode devices, including the use of metal-insulator-semiconductor structures[4], the use of fluorine treatments[5], recessed gate structures[6], and the use of p-type cap layers[7][8]. Due to the relative maturity and controllability of epitaxial growth of pGaN layers (compared to other technologies), the pGaN / AlGaN / GaN HEMT is considered the leading structure for commercialization.

[0007] Figure 1 A cross section of the active region of a prior art pGaN HEMT is schematically shown. The device shown is a lateral three-terminal device with an AlGaN / GaN heterostructure epitaxially grown on a standard silicon wafer 4. A transition layer 3 is used to allow the growth of a high quality GaN layer 2 despite the significant lattice mismatch between GaN and Si. Carbon p-type doping is typically added to the GaN layer [9]. Finally, a thin cap GaN layer 11 is typically added to form a GaN layer with a capacitance greater than 1x10 19 cm- 3 The gate has a magnesium (Mg) p-type doping density of 1.

[0008] Typical pGaN gate devices have a threshold voltage of about 1.5 to 2V and a gate open circuit bias of about 8V. The threshold voltage and gate open circuit voltage in enhancement mode GaN devices are of great concern because if the threshold voltage is low, there may be some problems in operation, such as the device accidentally turning on when it should be off. Secondly, gate turn-on may be a problem due to the non-insulated gate structure. It is therefore obvious that pGaN gate devices operate at gate voltages in the range of 2V to 8V, and preferably between 5V and 7V to minimize the on-state resistance of the device while ensuring a low leakage voltage through the gate (lower than the open circuit voltage).

[0009] In the prior art devices, there is a trade-off between the threshold voltage of the device and the carrier density in the 2DEG of the device and the device on-state resistance. 19 cm -3 For pGaN doping, the threshold voltage does not change significantly by using different gate metals or the thickness of the pGaN layer

[10] . Therefore, unlike their silicon counterparts

[12] , a narrow operating window (with gate voltages in the range of 4 V to 7 V relative to the source) is specified in these devices

[11] . The lower boundary is defined by the gate bias required to fully form a channel (2DEG) under the gate (this is called the threshold voltage Vth), while the upper boundary is limited by the point at which the gate is turned on and significant current starts to flow through it.

[0010] Another area of ​​interest in AlGaN / GaN HEMTs is their fast switching capability. Due to the higher critical electric field, the high mobility of carriers in the 2DEG and the short drift region result in a very low drift region charge Qgd for a given breakdown. In addition, the device gate charge Qg is about an order of magnitude lower than the corresponding prior art silicon devices

[11] ,

[12] . Therefore, GaN HEMTs can switch at much higher speeds than silicon MOSFETs. While this is beneficial in many applications, it can cause unexpected oscillations due to the presence of parasitic components at both the device and circuit levels

[13] . To avoid oscillatory behavior, one possible solution proposed is to add an external gate resistor to the device to reduce the observed dV / dt and dI / dt rates

[13] .

[0011] In

[14] , attempts were made to expand the operating window defined by the threshold voltage and the opening of the pGaN / AlGaN junction by varying the composition of the gate metal. This attempt was unsuccessful as discussed in

[10] , where it was shown that for gates greater than 1x10 19 cm -3 The threshold voltage cannot be significantly changed by doping the pGaN, using different gate metals or by changing the thickness of the pGaN layer.

[0012] In

[16] , a technique for higher Vth on the P-gate was achieved via the “Through Recessed Regrowth Gate (TRRG)” technique. This process technique is based on the complete removal of the AlGaN barrier layer and subsequent regrowth of it via epitaxial regrowth. This showed that the threshold voltage was more stable at elevated temperatures and that it was possible to achieve Vth up to 2.3V by controlling the thickness of the AlGaN layer. Although this is an interesting process technique to achieve stable threshold voltages, it does have an impact on Ron when Vth>2V is reached. Furthermore, the high Vth solution proposed in

[16] does not address the problem of Rg-related oscillations during fast switching of high voltage transistors, nor does it solve the high gate leakage problem of pGaN gate technology.

[0013] In

[17] , an integrated dual-gate technology for achieving high Vth (>2.8V) was demonstrated. The dual-gate technology proposed in

[17] is based on the integration of a high voltage normally-on (D-mode) and a low voltage normally-off (E-mode) GaN transistor. However, in this configuration, the two transistors are connected in series and therefore the total on-state resistance will be affected by the series contribution of the on-state resistance of the low voltage device.

[0014] Other proposed dual-gate technologies exist in the literature and are so called because they have a second gate electrode located above the gate passivation layer

[18] or buried in the heterostructure stack

[19] . These devices are mainly aimed at improving the dynamic performance of the transistor by mitigating the current collapse phenomenon, which is actually a reduction in the current in the on-state when the device is repeatedly subjected to high voltage in the off-state.

[0015] In

[20] an attempt was made to increase the Vth of a normally off (enhancement mode - E-mode) GaN transistor using a circuit configuration with a diode and a second gate electrode. In this document, a diode is used as a voltage switch and is connected in series with the gate of the high voltage GaN device. A device implementing the voltage switch with a transistor is also described. However, in this particular case, the drain terminal of the voltage switch transistor is connected to the high voltage drain terminal of the GaN device. The implication of this connection is that the driver device will have to maintain the high voltage in blocking mode and is therefore designed as a high voltage transistor with a longer drift region than the low voltage device. The device will therefore have an increased area consumption and the reliability of this additional transistor must be considered. In addition, no upper boundary limit is mentioned in

[20] .

[0016] The resistive loads connected between the gate and source of a GaN HEMT or power MOSFET are also generally known, and their goal can be to reduce oscillations during high voltage switching, protect the device from electrostatic discharge, and generally ensure robust operation. For example, in the datasheet of a GaN system component

[21] , it is recommended to add a 3kΩ resistor between the gate terminal (gate bus) and the source (or ground).

[0017] In US9882553B2 and US10411681B2, devices are described which expand the operating window of III-V semiconductor devices.

[0018] In US 1 0 374 591 B2 a gate drive circuit for controlling the operation of a wide bandgap semiconductor switch is described.

[0019] In US2020007119A1, a voltage regulation circuit is described that uses GaN HEMT technology to provide a stable output voltage suitable for applications (e.g., GaN power transistor gate drivers and low-voltage auxiliary power supplies for GaN integrated circuits). Summary of the invention

[0020] The object of the present invention is to propose a solution for p-gate GaN E-mode transistors that simultaneously results in the following features: (i) a reduction in gate leakage current, (ii) an increase in threshold voltage, and (iii) an increase in gate voltage operating window. The result of these three features is (i) avoiding turn-on re-triggering during turn-off and limiting oscillations under certain turn-off conditions (where high dV / dt rates are present), and (ii) improving the switching performance of the overall configuration through an integrated pull-down network.

[0021] According to the present invention, we propose a GaN power device with high threshold voltage, very large gate voltage operating range with less or no risk of p-GaN junction opening, and the ability of oscillation-free or reduced oscillation switching behavior. The details of the present invention will be discussed considering but not limited to pGaN gate E-mode technology.

[0022] GaN transistors utilizing the present disclosure are intended for, but not limited to, applications in the medium and low voltage range. Low voltage capable devices (<200V but above 20V) will be suitable for point-of-load applications, i.e., low voltage DC-DC converters for IT or consumer electronics applications. Such devices can also be used in linear electronics to improve efficiency, however, there is a huge market potential in the 600V range for applications such as power factor correction (PFC), uninterruptible power supplies (UPS), motor drives, and photovoltaic (PV) system inverters. 600V GaN devices can also be used as chargers for hybrid electric vehicles (HEV) and / or electric vehicles (EV), which is a rapidly growing market. GaN transistors with a breakdown capability of up to 1.2kV and a power rating of up to 7.2kW can lead to GaN transistors for EV and HEV converters and inverters, where high frequency operation will allow for reduced system size, which is an important parameter when considering mobile systems. Ultimately, if the power rating is large enough, GaN transistors can find applications in wind turbines (1.7kV). Recent applications that require reliable operation in the MHz range, such as wireless charging in the IT (mobile phones, laptops) and automotive (EV, HEV) fields, may be very suitable for the present disclosure. In addition, applications other than power conversion are also envisioned, such as class-D audio amplifiers.

[0023] Broadly speaking, the present disclosure relates to power semiconductor devices using GaN technology. The present disclosure proposes an integrated auxiliary gate terminal and a pull-down network to realize a normally-off (E-mode) GaN transistor with a threshold voltage above 2V, low gate leakage current, and possibly enhanced switching performance. The high threshold voltage GaN transistor has a high voltage active GaN device and an auxiliary GaN device (preferably a low voltage device), wherein the high voltage GaN device has a gate connected to the source of the integrated auxiliary GaN transistor and a drain as an external high voltage drain terminal and a source as an external source terminal, and the auxiliary GaN transistor has a gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) serving as an external gate terminal. In other embodiments, the pull-down network for turning off the high threshold voltage GaN transistor is formed by a parallel connection of a diode, a resistor, or both connected in parallel with the auxiliary GaN transistor.

[0024] In other embodiments, the pull-down network for turning off the active (high voltage) GaN transistor is formed by an additional auxiliary low voltage GaN transistor and a resistive element connected in parallel or in series with the low voltage auxiliary GaN transistor.

[0025] In other embodiments, the pull-down network for turning off the active (high voltage) GaN transistor is formed by an active Miller clamp.

[0026] In other embodiments, the overvoltage protection circuit is formed by a resistor or resistive element and a low voltage enhancement mode (or depletion mode) transistor to limit the maximum potential at the gate of the active (high voltage) transistor.

[0027] In other embodiments, an overcurrent protection circuit is formed from a current sensing resistor or resistive element and a low voltage enhancement mode (or active depletion mode) transistor to act as protection from overcurrent events.

[0028] According to a second aspect of the present invention, there is provided a heterojunction (gallium nitride) chip (also called or referred to as a GaN chip or a GaN power integrated circuit or a GaN smart device or a GaN high-voltage integrated circuit) having at least three terminals (a high-voltage terminal, a low-voltage terminal and a control terminal),

[0029] and comprises at least one high voltage active GaN device (also referred to as a main power heterojunction transistor) having an internal gate (whose source and drain are respectively connected to the low voltage and high voltage terminals of the GaN chip), a pull-down circuit, an auxiliary gate circuit comprising at least one low voltage heterojunction transistor, and a current control circuit, wherein:

[0030] an auxiliary gate circuit having one connection to an internal gate of the at least one main power heterojunction transistor, a second connection to a control terminal, and at least one more connection connecting a gate of at least one low voltage heterojunction transistor to a pull-down circuit;

[0031] The pull-down circuit has at least one connection to the current control circuit and at least one connection to the source terminal of the at least one main power heterojunction transistor;

[0032] The current control circuit has a connection to the control terminal

[0033] And wherein the auxiliary gate partially controls the voltage and current level entering the internal gate of at least one main power heterojunction transistor, the current control circuit controls the current level entering the pull-down circuit, and determines the voltage level applied to the control terminal in combination with the pull-down circuit design, at which voltage level the pull-down circuit actively pulls down the gate voltage of the at least one low-voltage heterojunction transistor to clamp the voltage of the internal gate of at least one main power heterojunction transistor.

[0034] The auxiliary gate block (circuit) integrated in the GaN chip consists of an auxiliary GaN transistor (preferably a low-voltage device), where the gate of the high-voltage active GaN device (main power heterojunction transistor) is connected to the source of the integrated auxiliary GaN transistor, and the drain of the auxiliary GaN transistor is connected to the GaN chip control terminal.

[0035] An integrated current control block (circuit) is connected between the drain and gate terminals of the auxiliary GaN transistor.

[0036] The integrated pull-down circuit block (circuit) is connected between the gate terminal of the auxiliary GaN transistor and the source terminal of the high voltage active GaN device.

[0037] The threshold voltage of the GaN chip (the potential applied to the control terminal of the GaN chip relative to the low-voltage terminal at which its main power heterojunction transistor starts to conduct current) may be higher than the intrinsic threshold voltage of the separate main power heterojunction single transistor. This can be achieved by the additional voltage drop on the integrated auxiliary gate block when a voltage signal is applied to the control terminal of the GaN chip (also known as the external gate terminal). Therefore, the potential on the internal gate (also known as the active gate terminal) is lower than the potential applied to the control terminal of the GaN chip.

[0038] When the voltage signal on the external gate terminal (control terminal) increases linearly, the voltage drop on the auxiliary gate block (circuit) is nonlinear.

[0039] The low gate leakage current of the high voltage active GaN device (main power heterojunction transistor) is achieved by limiting the potential on the internal gate (active gate) terminal. This is achieved by allowing a voltage drop across the integrated auxiliary gate block. The limitation of the potential of the active gate terminal is defined by appropriately designing the current control block and the pull-down circuit block so that when the gate signal of the external gate terminal (the control terminal of the GaN chip) increases above a certain level, the gate of the auxiliary gate transistor is pulled down. Therefore, the gate voltage operating window of the GaN chip (i.e., the voltage operating window applied to the control terminal) is increased compared to the gate voltage operating window of the conventional GaN HEMT.

[0040] The maximum voltage signal that can be applied to the device's external gate (the control terminal of the GaN chip) can be designed to be above 10V (e.g., 20V), making it possible to use conventional silicon gate drivers and controllers to drive the GaN chip.

[0041] Furthermore, the current control block (and other circuits) need to be designed appropriately to strike a balance between fast turn-on, avoiding overshoot of the active gate terminal (internal gate terminal) during turn-on, and low gate driver power dissipation during on-state operation of the device.

[0042] The integrated current control circuit (current control block) may be a resistor element or a combination of resistor elements. Alternatively, the current control circuit may be or include a current source. The current source may be composed of a low voltage depletion mode HEMT and a resistor element. The resistor element may be connected between the gate and source terminals of the low voltage depletion mode HEMT. The drain terminal of the depletion mode HEMT is connected to the drain terminal of the auxiliary gate HEMT, and the gate terminal of the depletion mode HEMT is connected to the gate terminal of the auxiliary gate HEMT.

[0043] In similar embodiments, an RCL network may be included in parallel with a resistive element or current source to improve dynamic characteristics during device turn-on or turn-off transients.

[0044] The current control block may also include circuitry to produce an additional voltage drop. The current control block may also include circuitry to adapt the current in the current control block according to operating conditions (e.g., switching, on, or off conditions). Such current adaptation circuitry may include a depletion mode HEMT or an enhancement mode HEMT in series or parallel with a resistive element in the current source.

[0045] In some embodiments, the integrated pull-down circuit (block) may be or include one or more HEMTs connected in parallel or in series. The gate potential of the pull-down HEMT is controlled to set the voltage drop across the pull-down HEMT, thereby setting the gate voltage of the auxiliary gate block and the voltage drop across the auxiliary gate block.

[0046] The pull-down circuit block may also include elements for compensating for or reducing the effect of temperature on the voltage drop across the pull-down circuit block.

[0047] In another embodiment, the auxiliary gate may include a low voltage depletion mode transistor instead of a low voltage enhancement mode transistor. This embodiment may not be as effective in achieving an increased threshold voltage for the GaN chip, but may achieve an increased operating range by allowing an increase in the maximum allowed control signal (external gate signal) level. Since a channel exists in the depletion mode transistor when the potential on the active gate is high and the potential on the external gate terminal is low, the GaN transistor can be used as part of the device shutdown network.

[0048] In other embodiments, some or all of the described functional blocks may be used together to add enhanced functionality.

[0049] Although the auxiliary GaN transistor is preferably a low voltage device, the source and drain terminals can be interchanged because they are usually made in a symmetrical (or similar) manner. Low voltage devices refer to devices with a rated breakdown voltage typically less than 20V and limited current capability (less than 100mA). However, it should be understood that the auxiliary gate can also be a high power or high voltage device, although this will increase cost and complexity.

[0050] Most of the embodiments described herein according to the present disclosure relate to integrated auxiliary transistors, whereby the auxiliary transistors and the active transistors are fabricated on the same substrate (in the same chip). Although the integration of the two may have several advantages (e.g., fewer pads, low area consumption, compact size, lower cost, and lower complexity), the auxiliary transistors may also be fabricated on a separate substrate and connected to the active transistors in a discrete or hybrid manner. The auxiliary transistors and the active transistors may be located side by side in the same package or module, or discretely connected on a board, and are not necessarily integrated in the same GaN chip.

[0051] This also applies to the other functional blocks described.

[0052] According to one aspect of the present invention, there is provided a heterojunction power device based on a group III nitride semiconductor, the heterojunction power device comprising:

[0053] 1. An active heterojunction transistor, formed on a substrate, the active heterojunction transistor comprising:

[0054] 2. A first III-nitride semiconductor region comprising a first heterojunction, wherein the first heterojunction comprises an active two-dimensional carrier gas of a second conductivity type;

[0055] 3. A first terminal operatively connected to the Group III nitride semiconductor region;

[0056] 4. a second terminal laterally spaced apart from the first terminal and operatively connected to the Group III nitride semiconductor region;

[0057] 5. an active gate region formed on the Group III nitride semiconductor region, wherein the active gate region is formed between the first terminal and the second terminal;

[0058] An auxiliary heterojunction transistor is formed on the substrate or another substrate, and the auxiliary heterojunction transistor includes:

[0059] 6. A second III-nitride semiconductor region comprising a second heterojunction, wherein the second heterojunction comprises an auxiliary two-dimensional carrier gas of a second conductivity type;

[0060] 7. A first additional terminal operatively connected to the second Group III nitride semiconductor region;

[0061] 8. a second additional terminal laterally spaced apart from the first additional terminal and operatively connected to the second Group III-nitride semiconductor region;

[0062] 9. An auxiliary gate region formed on the second Group III nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;

[0063] wherein the first additional terminal is operatively connected to the auxiliary gate region, and wherein the second additional terminal is operatively connected to the active gate region,

[0064] wherein the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and wherein the heterojunction power device further comprises a second auxiliary heterojunction transistor operatively connected in parallel with the first auxiliary transistor, and wherein the first additional terminal of the first auxiliary heterojunction transistor is operatively connected to the source terminal of the second auxiliary heterojunction transistor, and the second additional terminal of the first auxiliary heterojunction transistor is operatively connected to the drain terminal of the second auxiliary heterojunction transistor,

[0065] The auxiliary heterojunction transistor is configured to (or the auxiliary heterojunction transistor is added to) lead to an increase in the threshold voltage of the heterojunction power device and / or an increase in the operating voltage range of the first additional terminal.

[0066] Here, the term "operably connected" means that the terminals are electrically connected. In other words, the first additional terminal is electrically connected to the auxiliary gate, and the second additional terminal is electrically connected to the active gate region. In addition, in one embodiment, the first terminal is the source terminal of the active transistor, and the second terminal is the drain terminal of the active transistor. On the other hand, the first additional terminal is the drain terminal of the auxiliary transistor, and the second additional terminal is the source terminal of the auxiliary transistor. In an embodiment, the connected first additional terminal and the auxiliary gate region form a high voltage terminal (or form an external gate terminal), to which a relatively higher voltage is applied than the second additional terminal. Therefore, the second additional terminal can be referred to as a low voltage terminal of the auxiliary transistor. Here, the term "III-nitride semiconductor region" generally refers to the entire region including the GaN layer and the AlGaN layer formed on the GaN layer. The two-dimensional carrier gas is generally formed at the interface between the GaN layer and the AlGaN layer in the III-nitride semiconductor region. In an embodiment, the two-dimensional carrier gas refers to a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG).

[0067] When integrated on the same substrate (monolithic integration), the heterojunction power device may further include an isolation region between the active heterojunction transistor and the auxiliary heterojunction transistor. The isolation region separates the active two-dimensional carrier gas from the auxiliary two-dimensional carrier gas. The isolation region may separate the first and second III-nitride semiconductor regions.

[0068] In use, when the first additional terminal and the auxiliary gate region can be biased at a potential (or voltage), the carrier density in a portion of the auxiliary two-dimensional carrier gas under the auxiliary gate region is controlled so that an auxiliary two-dimensional carrier gas connection is established between the first and second additional terminals. Typically, a two-dimensional electron gas (2DEG) is formed under the first and second additional terminals. When a voltage is applied to the auxiliary gate region (or high voltage terminal), it controls the carrier density in the 2DEG under the auxiliary gate so that a 2DEG connection is formed between the 2DEG under the first and second additional terminals.

[0069] The active gate region can be configured to be turned on by an auxiliary two-dimensional carrier gas (e.g., 2DEG) connection between the first and second additional terminals. A change in the resistance of the 2DEG connection below the auxiliary gate region can also turn on the active gate. The auxiliary 2DEG connection can be used as an internal resistance of the active gate region. This internal gate resistance can be used to slow down fast dV / dt during switching or prevent high oscillations caused by di / dt effects.

[0070] The first additional terminal and the auxiliary gate region may be configured such that a portion of the potential is used for forming the auxiliary 2DEG connection and another portion of the potential is used for turning on the active gate region.

[0071] The first Group III nitride semiconductor region may include an active aluminum gallium nitride (AlGaN) layer in direct contact with the first terminal, the active gate region, and the second terminal.

[0072] The second Group III nitride semiconductor region may include an auxiliary aluminum gallium nitride (AlGaN) layer in direct contact with the first additional terminal, the auxiliary gate region, and the second additional terminal.

[0073] The thicknesses of the active AlGaN layer and the auxiliary AlGaN layer may be the same or different.

[0074] The doping concentrations of the active AlGaN layer and the auxiliary AlGaN layer may be the same or different.

[0075] The aluminum mole fractions of the active AlGaN layer and the auxiliary AlGaN layer may be the same or different.

[0076] The active gate region may include a p-type gallium nitride (pGaN) material. The metal contact on the active pGaN gate may be Schottky or Ohmic. Alternatively, the active gate region may include a recessed Schottky contact.

[0077] The first terminal, the second terminal, the first additional terminal, and the second additional terminal may each include a surface ohmic contact. Alternatively, the first terminal, the second terminal, the first additional terminal, and the second additional terminal may each include a recessed ohmic contact.

[0078] The auxiliary gate region may include a field plate extending towards the first additional terminal, and wherein the field plate extends over the field oxide region.

[0079] The power device may have a staggered layout, wherein the gate metal pad is directly connected to the auxiliary gate region and the first additional terminal, and the active gate region includes a gate finger connected to the second additional terminal. Alternatively, the device may have a staggered layout, wherein the auxiliary gate region, the first additional terminal, and the second additional terminal are located below the source metal pad. Advantageously, compared to prior art designs, no additional wafer area is required to include the auxiliary gate structure.

[0080] In an embodiment, the second additional terminal and the active gate region may be connected in a third dimension of the device.

[0081] Compared with the active heterojunction transistor, the active heterojunction transistor may be a high voltage transistor, and the auxiliary heterojunction transistor may be a low voltage transistor.

[0082] The heterojunction power device may also include a diode connected in parallel between the first and second additional terminals of the auxiliary heterojunction transistor. The parallel diode acts as a pull-down network during the turn-off period of the entire configuration connected from the gate terminal of the active GaN transistor to ground. When a positive bias (on-state) is applied to the auxiliary gate, the diode will be reverse biased and zero current will flow through it, which will not affect the electrical behavior of the entire high voltage configuration. When zero bias (off-state) is applied to the auxiliary gate, the diode will be forward biased and the turn-off current flowing through it will discharge the gate capacitance of the active transistor, thereby enabling the entire configuration to be turned off. In the off-state, the gate of the active transistor will remain biased to a minimum voltage (equal to the turn-on voltage of the diode). Therefore, the diode is designed to keep its turn-on voltage as low as possible, ideally a few millivolts. The diode can be formed monolithically with the device. The diode can be a simple Schottky diode. The diode typically pulls the active gate down to the diode V during turn-off. th , so the diode needs to be designed to have the lowest possible threshold voltage. One feature that can achieve this is to use a recessed anode so that it makes direct contact with the 2DEG.

[0083] Alternatively, a normally-on (depletion mode) GaN power device that is not available in the prior art can be used. Such a normally-on device can include a gate structure based on a discontinuous p-GaN layer (or a discontinuous region of the first conductivity type) containing an island within a stripe or a closed shape surrounding a unit, which is used to modulate the conductive path given by a 2D electron gas (or a two-dimensional carrier gas of the second conductivity type) between a high voltage terminal and a low voltage terminal when a gate voltage is provided. All such islands can be connected to the same gate electrode. It should be understood that a discontinuous island means that there is no p-GaN layer between adjacent islands, so that there is a direct, unobstructed conductive path provided by the 2D electron gas between the source terminal and the drain terminal. However, adjacent islands are located together in a direction that intersects (orthogonal) the current path, so that the potential applied to the p-GaN gate island modulates the conductive region between the islands, thereby modulating the direct path between the source and the drain. The p-GaN layer in the continuous and discontinuous gate structures is completed in the same process step, and the distinction between continuous and discontinuous is achieved by a layout change of the same mask.

[0084] The operation of this normally-on (depletion mode) device is characterized by the presence of two threshold voltages. The first threshold voltage may be negative and equivalent to the threshold voltage of a classical normally-on transistor, indicating a transition from an off state to an on state. The second threshold voltage is preferably positive and characterized by a sharp current increase. The second threshold voltage may be the same value as an integrated normally-off device with a continuous p-GaN gate.

[0085] The two threshold voltages are clearly discussed and identified in more detail below.

[0086] In addition to epitaxy / process modifications, the first threshold voltage, referred to herein as the device threshold voltage, can also be adjusted by layout modifications. Furthermore, the depletion mode (normally-on) device proposed herein can allow for an increased positive gate bias (>7V) to be applied before the dominant conduction state channel changes from drain-source to gate-source. Such a device can be implemented in a fabrication process that does not provide a Schottky contact on the surface of the AlGaN layer.

[0087] Alternatively, a normally-on depletion device using discontinuous pGaN islands can be used in diode mode by connecting the gate and source together (or the anode terminal due to the symmetry of connecting the drain and gate together). The distance (spacing) between the pGaN islands can be used to adjust the voltage level at which the diode conducts current in the forward mode. This is particularly advantageous over prior art techniques using a continuous pGaN layer, which results in a large forward voltage. For example, the spacing between pGaN islands (or multiple strips of pGaN islands) can be used to adjust this open circuit forward voltage to 0.3 to 0.5 V, which is typical of Schottky diodes in silicon. To avoid undesirable negative open circuit voltages for the diode, the spacing between the pGaN islands should be very small (on the order of tens or hundreds of nanometers), or the source of the HEMT connected in the diode configuration can have a Schottky contact.

[0088] When a 2DEG is formed beneath the pGaN layer, during forward conduction, a second increase in current occurs at a higher voltage level (above the open circuit voltage level). In forward conduction, it is desirable for the diode to operate above this second voltage level to minimize the on-state resistance.

[0089] In all embodiments, the contacts to the pGaN islands may be made by Ohmic or Schottky metallization.

[0090] The first additional terminal (or drain (gate) terminal) and the second additional terminal (or source terminal) of the (first) auxiliary heterojunction transistor may each be used as an external gate terminal.

[0091] In the present invention, the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and the heterojunction device also includes a second auxiliary heterojunction transistor operatively connected in parallel with the first auxiliary transistor, and the first additional terminal (or drain (gate) terminal) of the first auxiliary heterojunction transistor can be connected to the source terminal of the second auxiliary heterojunction transistor, and the second additional terminal (or source terminal) of the first auxiliary heterojunction transistor can be operatively connected to the drain (gate) terminal of the second auxiliary heterojunction transistor.

[0092] The pull-down network through the second auxiliary heterojunction transistor may also include a resistor added in series with the second auxiliary transistor between the gate and drain terminals of the second auxiliary transistor. The resistor is between the gate and drain terminals of the second auxiliary transistor. Therefore, the resistor does not form a common node between the first auxiliary transistor and the gate of the active transistor. The role of the resistor is to reduce the active gate capacitance discharge time through the pull-down network during the shutdown of the heterojunction power device. The additional resistance element performs this function by generating an increased potential of the gate terminal of the second auxiliary transistor compared to the drain terminal of the second auxiliary transistor during the shutdown. The additional resistor can be connected between the drain terminal of the second auxiliary transistor and the source terminal of the active power transistor. During the shutdown of the active device, the additional resistor acts as a parallel pull-down network. Therefore, it can be understood that the additional resistor is not connected by connecting the common node of the source of the first auxiliary transistor and the gate of the active transistor. During the active device on and on state, the additional resistor can act as a voltage limiting component to protect the gate terminal of the active device.

[0093] The pull-down network through the second auxiliary heterojunction transistor may also include a third auxiliary transistor added in series with the second auxiliary transistor between the gate and drain terminals of the second auxiliary transistor. The role of the third auxiliary transistor is to reduce the active gate capacitance discharge time through the pull-down network during the shutdown of the heterojunction power device. The third auxiliary transistor performs this function by generating an increased potential at the gate terminal of the second auxiliary transistor compared to the drain terminal of the second auxiliary transistor during shutdown. The third auxiliary transistor may be a depletion mode low voltage transistor. Depletion mode devices may use Fig.18 The p-GaN islands shown may be made as Fig.19 The diode shown. The gate terminal of the third auxiliary transistor can be connected to the source or drain terminal of the third auxiliary transistor. The additional resistor can be connected between the drain terminal of the second auxiliary transistor and the source terminal of the active (high voltage) transistor. In other words, it can be understood that the additional resistor is not connected through a common node connecting the source of the first auxiliary transistor and the gate of the active transistor. During the active device shutdown, the additional resistor acts as a parallel pull-down network. During the active device turn-on and conduction state, the additional resistor can act as a voltage limiting component to protect the gate terminal of the active device.

[0094] The heterojunction power device also includes a voltage limiting circuit including two resistors forming a voltage divider and an actively switched low voltage enhancement mode transistor. The drain-source path of the actively switched low voltage enhancement mode transistor is connected between the gate and source of the active power transistor. The voltage divider is connected between the first additional terminal (or drain (gate) terminal) of the first auxiliary heterojunction transistor and the source terminal of the active (high voltage) transistor. The midpoint of the voltage divider is connected to the gate terminal of the low voltage enhancement mode transistor. When the voltage of the first additional terminal (or drain (gate) terminal) rises above a certain value (which can be controlled by the selection of resistors in the described voltage divider), the enhancement mode transistor can be turned on, thereby adjusting the resistance between the active device gate terminal and the active (high voltage) device source terminal. This function can protect the active gate terminal from overvoltage events.

[0095] The heterojunction power device may also include a voltage limiting circuit as described above, wherein the low voltage enhancement mode transistor is replaced by a low voltage depletion mode transistor. In this embodiment, when the potential of the first additional terminal (or drain (gate) terminal) of the first auxiliary heterojunction transistor increases, the resistance of the depletion mode transistor may be reduced, thereby adjusting the resistance between the active (high voltage) device gate terminal and the active device source terminal. The voltage divider formed by the resistor determines the potential at the gate terminal of the depletion mode transistor. The described circuit may protect the active gate terminal from overvoltage events.

[0096] The heterojunction power device may also include an overcurrent protection circuit consisting of a current sensing resistor and an actively switched low-voltage enhancement mode transistor. The active region of the active (high-voltage) transistor is divided into two regions, which form two parallel transistors. The drain and gate terminals of the two transistors are electrically connected. The two transistors in parallel are a low-resistance (main power) transistor and a high-resistance (current sensing) transistor, respectively. The first terminal of the current sensing resistor is connected to the source terminal of the high-resistance transistor. The actively switched enhancement mode transistor is connected between the gate terminal of the active (high-voltage) transistor and the second terminal of the current sensing resistor. The gate terminal of the low-voltage enhancement mode transistor is connected to the first terminal of the current sensing resistor. As the current through the high-resistance transistor increases, the potential drop across the current sensing resistor increases, increasing the potential on the gate of the low-voltage enhancement mode resistor, thereby adjusting its resistance. The critical current through the low-voltage transistor can turn on the low-voltage enhancement mode transistor, thereby limiting the potential on the gate of the active power transistor. The described circuit can protect the circuit from overcurrent events. The described components can be monolithically included in the design.

[0097] The heterojunction power device may also include an overcurrent protection circuit as described above, wherein the low voltage enhancement mode transistor is replaced by a low voltage depletion mode transistor. Similarly, the potential at the gate terminal of the depletion mode transistor increases as the current through the current sensing resistor increases. As the current through the current sensing resistor increases, the resistance of the depletion mode transistor decreases, reducing the resistance of the path between the gate and source of the active (high voltage) device, thereby limiting the potential on the active gate terminal. The described circuit can protect the circuit from overcurrent events.

[0098] Heterojunction power devices may also include an active Miller clamp to provide an additional pull-down network for the active (high voltage) device gate terminal during the device turn-off transient. The active Miller clamp consists of a logic inverter and a transistor that acts as an active ground switch for the pull-down network. The logic inverter may consist of a resistor or resistive element (i.e., a load transistor) and an enhancement mode transistor.

[0099] The actively switched transistor can be either an enhancement mode or a depletion mode transistor. In operation, the active Miller clamp uses the voltage bias of the external gate terminal (i.e., the terminal connected to the gate driver) to adjust the resistance of the actively switched transistor, thereby providing a low resistance pull-down path when the main power device is turning off or in the off state. When the gate driver signal is high, the bias on the gate of the actively switched transistor in the Miller clamp is low (hence its resistance is high), and vice versa.

[0100] The resistors (in any of the embodiments shown here) can be made from metal layers in the process, AlGaN layers or preferably from 2DEG. For high packing density, the resistors can be made into a meandering shape. The above functional blocks can be included in the design discreetly, monolithically or in the form of a hybrid package.

[0101] The depletion mode transistors in the described functional blocks may be Schottky gate HEMTs as described in the prior art.

[0102] Furthermore, the normally-on (depletion mode) transistors in the described functional blocks may be the pGaN island transistors described above.

[0103] It should be understood that, as already mentioned, the auxiliary heterojunction transistor can have interchanged sources and drains. Unlike the active (high voltage) transistor, the source and drain in the auxiliary heterojunction can be symmetrical or made and arranged in a similar way so that the source can act as the drain and vice versa.

[0104] According to a second aspect of the present disclosure, there is provided a gallium nitride (GaN) chip comprising a III-nitride semiconductor-based heterojunction power device according to the aforementioned aspect and an auxiliary low-voltage transistor according to the aforementioned aspect, but wherein the auxiliary gate region terminal is operatively connected to a control circuit (block) and a pull-down circuit (block).

[0105] The current control block can be connected between the first additional terminal and the auxiliary gate region. The pull-down circuit block can be connected between the auxiliary gate terminal and the first terminal (source) of the heterojunction power device (the same as the low voltage terminal of the GaN chip).

[0106] The GaN chip may further include an overcurrent protection circuit as described above, wherein the low voltage transistor is connected in parallel with the pull-down circuit.

[0107] The GaN chip may also include an integrated current control circuit (block). As described above, the current control block provides current to charge and discharge the gate of the auxiliary HEMT in the auxiliary gate circuit. The current control block may be connected between the first additional terminal and the gate of the auxiliary HEMT.

[0108] In some embodiments, the integrated current control block may be a resistor element. The resistor element may be made using a metal layer or a 2DEG layer.

[0109] In other embodiments, the current control block may be or include a current source. The current source may be composed of a low voltage depletion mode HEMT and a resistance element. The drain of the low voltage HEMT may be connected to the first additional terminal, the source is connected to the first terminal of the resistance element, and the gate is connected to the second terminal of the resistance element. The second terminal of the resistance element may also be connected to the gate terminal of the auxiliary HEMT.

[0110] In similar embodiments, an RCL network may be included in parallel or series with a resistive element or current source to improve the characteristics of the current control block.

[0111] The current control block may also include a circuit to generate an additional voltage drop. Such a circuit may be one or more low voltage diodes, one or more low voltage HEMTs with gates connected to the source, or a low voltage enhancement mode HEMT with a voltage divider connected between the drain and source terminals of the HEMT with the midpoint of the voltage divider connected to the gate terminal of the HEMT.

[0112] The current control block may also include circuitry to adapt the current in the current control block. Such current reduction circuitry may include a depletion mode HEMT or an enhancement mode HEMT connected in series or in parallel with a resistive element in the current source. The gate of the HEMT may be connected to a voltage divider between the gate and the first terminal of the auxiliary HEMT or to a node within the integrated pull-down circuit.

[0113] The heterojunction GaN chip may also include an integrated pull-down circuit block. The pull-down circuit block may be connected between the gate of the auxiliary HEMT and the first terminal (the source terminal of the main power heterojunction transistor - the same as the low voltage terminal of the GaN chip).

[0114] In some embodiments, the integrated pull-down circuit block may be one or more normally-on or normally-off HEMTs in parallel or series. There may be additional capacitors or resistors in series with the HEMTs. The gate potential of the pull-down HEMT is controlled to set the voltage drop across the pull-down HEMT, thereby setting the gate voltage of the auxiliary gate block and the voltage drop across the auxiliary gate block.

[0115] In one embodiment, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the gate terminal of the auxiliary HEMT and the first terminal.

[0116] In another embodiment, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the source terminal of the HEMT and the first terminal in the current source of the current control block.

[0117] In further embodiments, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the active gate and the first terminal.

[0118] In a fourth embodiment, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the first additional terminal and the first terminal.

[0119] In a further embodiment, an additional current control block is connected to the first additional terminal. The additional current control block is connected to an additional pull-down circuit (connected to the first terminal). In this embodiment, the gate terminal of the first pull-down HEMT may be connected to the output of the voltage divider on the additional pull-down circuit.

[0120] In all of these embodiments of the pull-down circuit, the voltage divider may be comprised of a resistive element, such as a resistor formed of a metal or a 2DEG; a capacitor; a current source formed of a depletion mode HEMT with its source connected to a first terminal of the resistive element and its gate connected to a second terminal; a Schottky diode, an enhancement mode HEMT with its gate terminal connected to its source terminal; a HEMT with its gate terminal connected to the output of the voltage divider between its drain and source; or a similar voltage divider circuit.

[0121] The pull-down circuit or the current control or auxiliary gate circuit may also include an element to compensate or reduce the temperature effects. This element is a specific embodiment of a voltage divider as part of the pull-down circuit. The first part of the voltage divider may include an integrated resistor, while the second part of the voltage divider may include a current source consisting of a normally-on HEMT with its source connected to the first terminal of the additional resistor and the gate connected to the second terminal of the resistor. The first part of the voltage divider may also include a similar current source in parallel with the resistor. The second part of the voltage divider may also include a resistor in parallel with the current source.

[0122] The two parts of the voltage divider will increase in voltage drop as temperature increases at a given current. But the current source and the resistor change the voltage drop at different rates. By sizing the normally-on HEMT and the resistor, the output of the voltage divider can be set by design so that the voltage drop across the pull-down circuit and / or the voltage drop across the auxiliary HEMT has less temperature dependence.

[0123] In other embodiments, the gate of the pull-down HEMT is controlled by an over-current protection circuit or an over-temperature protection circuit.

[0124] In further embodiments, the gate of the pull-down HEMT is controlled directly or indirectly by an external circuit or by additional circuitry integrated on the GaN device.

[0125] The GaN chip may include more than one main power device. For example, a half-bridge configuration in which a low-side power device is connected in series with a high-side main power device is possible. A full bridge consisting of two half-bridge arms or a three-phase GaN chip configuration is also possible. According to this aspect of the invention, at least one main power device in these configurations (half-bridge or full-bridge or three-phase) includes an auxiliary gate circuit, a pull-down circuit, and a current control circuit as described above.

[0126] According to another aspect of the present disclosure, a method for manufacturing a heterojunction power device based on a group III nitride semiconductor is provided, the method comprising:

[0127] 10. Forming an active heterojunction power transistor on a substrate, the active heterojunction transistor comprising:

[0128] 11. A first III-nitride semiconductor region comprising a first heterojunction, wherein the first heterojunction comprises an active two-dimensional carrier gas;

[0129] 12. A first terminal operatively connected to the Group III nitride semiconductor region;

[0130] 13. A second terminal laterally spaced apart from the first terminal and operatively connected to the Group III nitride semiconductor region;

[0131] 14. an active gate region formed on the Group III nitride semiconductor region, the active gate region being formed between the first terminal and the second terminal;

[0132] A first auxiliary heterojunction transistor is formed on the substrate or on another substrate, wherein the auxiliary heterojunction transistor comprises:

[0133] 15. A second III-nitride semiconductor region comprising a second heterojunction, wherein the second heterojunction comprises an auxiliary two-dimensional carrier gas;

[0134] 16. A first additional terminal operatively connected to the second Group III nitride semiconductor region;

[0135] 17. A second additional terminal laterally spaced apart from the first additional terminal and operatively connected to the second Group III-nitride semiconductor region;

[0136] 18. An auxiliary gate region formed on the second Group III nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;

[0137] forming a second auxiliary heterojunction transistor on the substrate or the further substrate,

[0138] operatively connecting the first additional terminal to the auxiliary gate region, and

[0139] operatively connecting the second additional terminal to the active gate region,

[0140] connecting the second auxiliary heterojunction transistor in operative parallel connection with the first auxiliary transistor,

[0141] operatively connecting a first additional terminal of the first auxiliary heterojunction transistor to a source terminal of the second auxiliary heterojunction transistor, and

[0142] The second additional terminal of the first auxiliary heterojunction transistor is operatively connected to the drain terminal of the second auxiliary heterojunction transistor.

[0143] The method may further include forming an isolation region between the active heterojunction transistor and the auxiliary heterojunction transistor, which separates the active two-dimensional carrier gas from the auxiliary two-dimensional carrier gas.

[0144] The method may further include forming the first Group III nitride semiconductor region simultaneously with forming the second Group III nitride semiconductor region.

[0145] The method may further include forming an active gate region simultaneously with forming the auxiliary gate region.

[0146] The method may further include simultaneously forming a metallization layer for the first terminal, the second terminal, the first additional terminal, and the second additional terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0147] The present disclosure will become more fully understood from the following detailed description and drawings, however, the present disclosure should not be considered limited to the particular embodiments shown, which are for illustration and understanding only.

[0148] Figure 1 schematically shows a cross section in the active region of a prior art pGaN HEMT;

[0149] Figure 2 shows a schematic representation of a cross section of an active region according to one embodiment of the present disclosure of the proposed disclosure;

[0150] Figure 3 The proposed disclosure is shown in Figure 2 A schematic representation of a circuit of one embodiment shown in a schematic cross-section of;

[0151] Figure 4A A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein a low on-state voltage diode is connected in parallel between the drain and source of the auxiliary transistor;

[0152] Figure 4B Shows Figure 4A 3D schematic representation of an embodiment of;

[0153] Figure 4C Shows Figure 4A A cross section of a low voltage diode used in an embodiment of the present invention;

[0154] Figure 5 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the drain (gate) terminal and the source terminal of the auxiliary transistor may be used as external gate terminals;

[0155] Figure 6 A schematic representation of a circuit showing a further embodiment of the proposed disclosure, wherein a second auxiliary transistor is connected in parallel with a first auxiliary transistor, wherein the drain (gate) terminal of the first low auxiliary transistor is connected with the source terminal of the second auxiliary transistor, and the source terminal of the first low auxiliary transistor is connected with the drain (gate) terminal of the second auxiliary transistor;

[0156] Figure 7 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a resistor is added between the drain terminal and the gate terminal of the second auxiliary transistor;

[0157] Figure 8A schematic representation of a circuit showing a further embodiment of the proposed disclosure wherein an additional resistor is added between the source terminal of the auxiliary transistor (the drain terminal of the second auxiliary transistor) and the source terminal of the active device;

[0158] Fig. 9 A schematic representation of a circuit showing a further embodiment of the proposed disclosure, wherein a third auxiliary transistor is added between the drain terminal and the gate terminal of the second auxiliary transistor; the gate terminal of the third auxiliary transistor is connected to the source terminal of the third auxiliary transistor;

[0159] Fig.10 A schematic representation of a circuit of a further embodiment of the proposed disclosure is shown, wherein a third auxiliary transistor is added between the drain terminal and the gate terminal of the second auxiliary transistor; the gate terminal of the third auxiliary transistor is connected to the drain terminal of the third auxiliary transistor;

[0160] Fig.11 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which a voltage limiting circuit consisting of two resistors forming a voltage divider and an actively switched low voltage enhancement mode transistor is implemented;

[0161] Fig.12 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which a voltage limiting circuit consisting of two resistors forming a voltage divider and an actively switched low voltage depletion mode transistor is implemented;

[0162] Fig.13 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which an overcurrent protection circuit consisting of a resistor and an actively switched low voltage enhancement mode transistor is implemented;

[0163] Fig.14 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein an overcurrent protection circuit consisting of a resistor and an actively switched low voltage depletion mode transistor is implemented;

[0164] Fig.15 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein an active Miller clamp circuit consisting of a resistor, an actively switched low voltage enhancement mode transistor, and an actively switched depletion mode transistor is implemented;

[0165] Fig.16 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein an active Miller clamp circuit consisting of a resistor, an actively switched low voltage enhancement mode transistor, and an actively switched depletion mode transistor is implemented;

[0166] Fig.17A schematic representation of a cross section of an active region of a depletion mode device proposed in the prior art that can be used as an actively switched transistor is shown;

[0167] Fig.18 A three-dimensional schematic representation of the active region of a proposed depletion mode device with pGaN islands (not found in the prior art) that can be used as an actively switched transistor is shown;

[0168] Fig.19 shows the diode mode operation with Fig.18 A three-dimensional schematic representation of the active region of a depletion mode device of a pGaN island is shown; and

[0169] Fig. 20 Shows Fig.18 The transfer characteristic of a depletion mode device is shown.

[0170] Fig.21 A schematic representation of a cross section of an active area according to another embodiment of the present disclosure is shown. In this embodiment, the first additional terminal 16 and the auxiliary gate terminal 15 are not operatively connected.

[0171] Fig. 22 The proposed disclosure is shown in Fig.21 Schematic representation of the circuit of one embodiment shown in schematic cross section.

[0172] Fig.23 A schematic representation of a second aspect of one embodiment of the proposed disclosure is shown, wherein a gate terminal of an auxiliary gate block is controlled by a current control block and a pull-down circuit block.

[0173] Fig.24 The relationship between the external gate voltage bias and the active gate voltage is shown.

[0174] Fig.25 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein the current control block is composed of resistive elements and the pull-down circuit comprises a HEMT in a threshold multiplier configuration.

[0175] Fig.26 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein the current control block includes a resistive element having a resistive element in parallel with a capacitive element, and wherein the pull-down circuit includes a HEMT in a threshold multiplier configuration with an additional capacitive element.

[0176] Fig. 27A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein the current control block comprises a normally-on HEMT and a resistive element in series, wherein the gate of the normally-on HEMT is connected to the second terminal of the resistive element; and wherein the pull-down circuit comprises the HEMT in a threshold multiplier configuration. In this embodiment, the auxiliary gate block comprises an enhancement mode low voltage HEMT and a Schottky diode in parallel.

[0177] Fig.28 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein the current control block comprises a normally-on HEMT and a resistive element in series, wherein a gate of the normally-on HEMT is connected to a second terminal of the resistive element; and wherein the pull-down circuit comprises the HEMT in a threshold multiplier configuration.

[0178] Fig.29 A schematic representation of a circuit showing a further embodiment of the proposed disclosure, wherein the auxiliary gate block comprises a second auxiliary transistor connected in parallel with the first auxiliary transistor, wherein the gate terminal of the second auxiliary transistor is connected to the source terminal of the first auxiliary transistor;

[0179] Fig.30 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein the pull-down circuit comprises a HEMT in a threshold multiplier configuration. In this embodiment, the voltage divider of the pull-down circuit comprises a temperature compensation circuit comprising a current source in parallel with a resistive element.

[0180] Fig.31 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein a voltage divider of a pull-down circuit is connected to a source terminal of a HEMT of a current control block.

[0181] Fig.32 A schematic representation of one embodiment of the proposed disclosure is shown, wherein the gate terminal of the auxiliary gate block is controlled by a current control block and a pull-down circuit block; and wherein the Miller clamp HEMT is controlled by a logic inverter. The logic inverter is powered by the output voltage of the integrated DC / DC voltage regulator. In addition, the input of the logic inverter is the output of the VG to Vlogic voltage regulator, limiting the voltage from the first additional terminal to a level optimized for the integrated GaN HEMT included in the inverter circuit.

[0182] Fig.33 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein the auxiliary gate block comprises a normally-on HEMT.

[0183] Fig.34A schematic representation of a circuit showing a further embodiment of the proposed disclosure, wherein the auxiliary gate block comprises a normally-on HEMT and wherein the auxiliary gate block comprises a second auxiliary transistor connected in parallel with the first auxiliary transistor, wherein a gate terminal of the source of the second auxiliary transistor is connected to a source terminal of the first auxiliary transistor;

[0184] Fig.35 A circuit schematic representation showing a further embodiment of the proposed disclosure, wherein the auxiliary gate block comprises a normally-on HEMT and wherein the auxiliary gate block comprises a second auxiliary normally-on HEMT connected in parallel with the first auxiliary transistor, wherein the gate terminal of the second auxiliary transistor is connected with the first terminal;

[0185] Fig.36 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein a voltage divider of a pull-down circuit is connected to the active gate terminal.

[0186] Fig.37 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein a voltage divider of a pull-down circuit is connected to the active gate terminal, and wherein the voltage divider comprises a series of source-gate connected E-HEMTs.

[0187] Fig.38 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein a voltage divider of a pull-down circuit is connected to the active gate terminal, and wherein the voltage divider comprises a HEMT in a threshold multiplier configuration.

[0188] Fig.39 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein a voltage divider of the pull-down circuit is connected to the first additional terminal, and wherein the voltage divider comprises a HEMT in a threshold multiplier configuration.

[0189] Fig.40 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein a voltage divider of the pull-down circuit is connected to the first additional terminal, and wherein the voltage divider comprises a current source (formed by a normally-on HEMT and a resistor) and the HEMT in a threshold multiplier configuration. In this embodiment, the output of the voltage divider is the gate terminal of the HEMT in the threshold multiplier configuration.

[0190] Fig.41 A staggered device layout of another embodiment of the present disclosure is shown, which incorporates an assist gate structure with a current control block and a pull-down circuit block.

[0191] Fig.42 A staggered device layout of another embodiment of the present disclosure is shown, where an auxiliary gate with a current control block and a pull-down circuit block and a terminal region is located below the source pad metal.

[0192] Fig.43 A block diagram of a further embodiment of the proposed disclosure is shown, wherein any one of the embodiments of the GaN chip power device according to the present disclosure is in a half-bridge configuration.

[0193] Fig.44 A block diagram of a further embodiment of the proposed disclosure is shown, wherein any one of the embodiments of the GaN chip power device according to the present disclosure is in a three-phase half-bridge configuration. DETAILED DESCRIPTION

[0194] Figure 2 A schematic representation of a cross section of an active region according to one embodiment of the present disclosure of the proposed disclosure is shown. In use, current flows in the active region of the semiconductor device. In this embodiment, the device includes a semiconductor (e.g., silicon) substrate 4 defining a major (horizontal) surface at the bottom of the device. There is a substrate terminal 5 below the substrate 4. The device includes a first region of a transition layer 3 above the semiconductor substrate 4. The transition layer 3 includes a combination of III-V semiconductor materials, which is used as an intermediate step to allow subsequent growth of high-quality III-V semiconductor materials.

[0195] There is a second region 2 above the transition layer 3. The second region 2 is a high-quality III-V semiconductor (e.g., GaN) and includes several layers. A third region 1 of the III-V semiconductor containing a molar fraction of aluminum is formed above the second region 2. The third region 1 is formed so that a heterostructure is formed at the interface between the second region 2 and the third region 1, thereby forming a two-dimensional electron gas (2DEG).

[0196] A fourth region 11 of a highly p-doped III-V semiconductor is formed in contact with the third region 1. This has the effect of reducing the 2DEG carrier concentration when the device is unbiased, and in this embodiment is a pGaN material. The gate control terminal 10 is configured above the fourth region 11 to control the carrier density of the 2DEG at the interface of the second region 2 and the third region 1. The high voltage drain terminal 9 is arranged in physical contact with the third region 1. The high voltage drain terminal forms an ohmic contact with the 2DEG. The low voltage source terminal 8 is also arranged in physical contact with the third region 1 and also forms an ohmic contact with the 2DEG.

[0197] A portion of the surface passivation dielectric 7 is formed over the fourth region 1 and between the drain terminal 9 and the source terminal 8. A SiO2 passivation layer 6 is formed over the surface passivation dielectric 7 and the source 8 and drain 9 terminals.

[0198] The device is divided into two cross sections by a vertical cut line. The two cross sections are not necessarily located in the same plane. The above features are on one side of the vertical cut line (e.g., the right hand side). This is referred to as an active device 205. The other side of the vertical cut line (e.g., the left hand side) is referred to as an auxiliary device 210, which also includes a semiconductor substrate 4, a transition layer 3, a second region 2, and a SiO2 passivation region 6.

[0199] A fifth region 17 of a III-V semiconductor containing a molar fraction of aluminum is located above the second region 2 in the auxiliary device, so that a heterostructure is formed at the interface between the fifth region 17 and the second region 2. This results in the formation of a second two-dimensional electron gas (2DEG) in a region that will be referred to as the auxiliary gate. The AlGaN layer 17 of the auxiliary device 210 can be the same as or different from the AlGaN layer 1 in the active device 205. The AlGaN layer thickness and the aluminum molar fraction are key parameters because they affect the carrier density of electrons in the 2DEG

[15] .

[0200] A sixth region 14 of a highly p-doped III-V semiconductor is formed over and in contact with the fifth region 17. This has the function of reducing the 2DEG carrier concentration when the auxiliary gate is unbiased. The auxiliary gate control terminal 15 is configured to be over the sixth region 14 to control the carrier density of the 2DEG at the interface of the fifth region 17 and the second region 2. The auxiliary gate pGaN layer 14 can be the same or different from the active gate pGaN layer 11. Key parameters that may be different include, but are not limited to, pGaN doping and width along the x-axis (as shown).

[0201] An isolation region 13 is formed downward along the vertical cut line. This cuts off the electrical connection between the 2DEG formed in the active device 205 and the 2DEG formed in the auxiliary device 210.

[0202] The first additional terminal 16 is arranged above the fifth region 17 of the auxiliary device 210 and is in physical contact with the fifth region 17. This forms an ohmic contact to the 2DEG of the auxiliary device 210 and is also electrically connected (via interconnect metal) to the auxiliary gate control terminal 15 configured to be above the sixth region (pGaN) 14. The first additional terminal 16 is biased at the same potential as the auxiliary gate terminal 15 of the auxiliary device. The second additional terminal 12 is also arranged above the fifth region 17 of the auxiliary device 210 and is in physical contact with it. This forms an ohmic contact to the 2DEG of the auxiliary device 210 and is also electrically connected (via interconnect metal) to the active gate control terminal 10 configured to be above the fourth region 11 of the active device 205. The interconnection between the second additional terminal 12 of the auxiliary device 210 and the active gate terminal 10 of the active device 205 can be made in the third dimension, and different metal layers can be used in the process. Note that this interconnection is not in Figure 2A similar, but not necessarily identical, AlGaN / GaN structure is used in the auxiliary gate.

[0203] When the device is in use, the auxiliary gates 14, 15 drive the active gates 10, 11. The auxiliary 2DEG layer formed between the first and second additional terminals 16, 12 and the portion below the auxiliary p-GaN gate 14 is controlled by a potential applied to the auxiliary gate terminal 15.

[0204] When the auxiliary gate terminal 15 and the shorted first additional terminal 16 are at 0 V, part of the auxiliary 2DEG is depleted under the auxiliary pGaN gate 14. As the auxiliary gate bias (both terminals 15, 16) is increased, a 2DEG starts to form under the pGaN gate 14, which connects to the already formed 2DEG layer, which connects to the first additional terminal 16 and the second additional terminal 12. The 2DEG connection is now between the first additional terminal 16 and the second additional terminal 12.

[0205] The device can now be turned on when the second additional terminal 12 is connected to the active gate 10. A positive (and desired) shift in the device threshold voltage is observed using this structure, since not all of the potential applied to the auxiliary gate 15 is transferred to the active gate 10. A portion of this potential is used to form an auxiliary 2DEG under the auxiliary gate 15, and only a portion is transferred to the second additional terminal 12 connected to the active gate 10.

[0206] The auxiliary gate provides the added advantage of being able to more easily control the gate resistance of the device. This can be achieved by changing the field plate design or the distance between terminals 12 and 15 or 15 and 16. This can be used to control unexpected oscillations observed due to the fast switching of these devices.

[0207] Different embodiments of the device may include terminals 10, 15 that are Schottky or Ohmic contacts or any combination of the two.

[0208] Figure 3 The proposed disclosure is shown in Figure 2 A schematic representation of the circuit of one embodiment is shown in a schematic cross section. Figure 3 The features shown in Figure 2 Features in the same reference numerals.

[0209] Figure 4A A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein a low on-state voltage diode is connected in parallel between the drain and source of an auxiliary transistor, as shown in FIG. Figure 4B Many features of this embodiment are shown in the schematic 3D diagram of FIG. Figure 2The features of the auxiliary transistor are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this embodiment, a low on-state voltage diode 31 is connected in parallel between the drain 16 and source 12 of the auxiliary transistor. During the turn-off period of the entire configuration that connects the gate terminal 10 of the active GaN transistor to ground, the parallel diode 31 acts as a pull-down network. When a forward bias (referred to as the on-state) is applied to the auxiliary gate, the diode will be reverse biased and zero current will flow through it, which will not affect the electrical behavior of the entire high voltage configuration. When zero bias (off state) is applied to the auxiliary gate 15, the diode 31 will be forward biased and the off current flowing through it will discharge the gate capacitance of the active transistor, thereby enabling the entire configuration to be turned off. In the off state, the gate of the active device 10 will remain biased to a minimum voltage equal to the turn-on voltage of the diode. Therefore, the diode 31 is designed so that its turn-on voltage is as low as possible, ideally a few millivolts. Figure 4B 31 is shown how a diode 31 may be included monolithically. The diode may be a simple Schottky diode, or may be a normal pn diode. The diode 31 pulls the active gate 10 down to the diode V during turn-off. th , so the diode needs to be designed to have the lowest possible threshold voltage. Figure 4C As shown, one feature that can achieve this is the use of a recessed anode so as to make direct contact with the 2DEG.

[0210] Figure 5 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, in which the drain (gate) terminal 16 and the source terminal 12 of the auxiliary transistor can be used as external gate terminals. Many features of this embodiment are similar to Figure 2 The features of FIG. 4 are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this case, the external gate terminal is split into two terminals. Since the gate driver receiver output pin can now be directly connected to the source terminal of the auxiliary transistor providing the pull-down path, component 31 in FIG. 4 may (or may not) be omitted.

[0211] Figure 6 A schematic circuit representation of a further embodiment of the proposed disclosure is shown, wherein a second auxiliary transistor 34 (which may advantageously be low voltage) is connected in parallel with a first auxiliary transistor, wherein the drain (gate) terminal 16 of the first auxiliary transistor is connected to the source terminal of the second auxiliary transistor, and the source terminal 12 of the first low auxiliary transistor is connected to the drain (gate) terminal of the second auxiliary transistor. Many features of this embodiment are similar to Figure 2 The features of the transistor are similar and therefore have the same reference numerals, namely semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this case, the pull-down network during the off period of the entire configuration is the second auxiliary transistor 34.

[0212] Figure 7 1 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which a resistor 41 is added between the drain terminal 12 and the gate terminal 10 of the second auxiliary transistor 34. Many features of this embodiment are similar to Figure 6 The features of the second auxiliary transistor 34 are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the role of the resistor 41 is to reduce the active gate capacitance discharge time through the pull-down network during the turn-off of the active device. The additional resistor performs this function by generating an increased potential of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12 during the turn-off period.

[0213] Figure 8 A circuit schematic representation of a further embodiment of the proposed disclosure is shown in which an additional resistor 42 is added between the source terminal of the auxiliary transistor (the drain terminal 12 of the second auxiliary transistor) and the source terminal 8 of the active device. Many features of this embodiment are similar to Figure 7The features of the active device 30 are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34 and resistance element 41. In this embodiment, the additional resistance element 42 acts as an additional pull-down network during the turn-off of the active device. During the turn-on and conduction state of the active device, the additional resistance 42 can act as a voltage limiting component to protect the gate terminal of the active device.

[0214] Fig. 9 A circuit schematic representation of a further embodiment of the proposed disclosure is shown in which a third auxiliary transistor 58 is added between the drain terminal 12 and the gate terminal 10 of the second auxiliary transistor. Many features of this embodiment are similar to Figure 8 The features of the third auxiliary transistor 58 are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34 and additional resistance element 41. In this embodiment, the role of the third auxiliary transistor is to reduce the active gate capacitance discharge time through the pull-down network during the shutdown of the heterojunction power device. The third auxiliary transistor 58 performs this function by generating an increased potential of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12 during shutdown. The third auxiliary transistor is a depletion mode device. The gate terminal of the third auxiliary transistor is connected to the source terminal of the third auxiliary transistor.

[0215] Fig.10 A circuit schematic representation of a further embodiment of the proposed disclosure is shown in which a third auxiliary transistor 59 is added between the drain terminal 12 and the gate terminal 10 of the second auxiliary transistor. Many features of this embodiment are similar to Figure 8The features of the third auxiliary transistor 59 are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34 and additional resistance element 41. In this embodiment, the role of the third auxiliary transistor is to reduce the active gate capacitance discharge time through the pull-down network during the shutdown of the heterojunction power device. The third auxiliary transistor 59 performs this function by generating an increased potential of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12 during shutdown. The third auxiliary transistor is a depletion mode device. The gate terminal of the third auxiliary transistor is connected to the drain terminal of the third auxiliary transistor.

[0216] Fig.11 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, in which a voltage limiting circuit consisting of a resistor 44, a resistor 45 (forming a voltage divider) and an actively switched low voltage enhancement mode transistor 43 is implemented. Many features of this embodiment are similar to Figure 6 The features of the embodiment of the present invention are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, when the potential of the first additional terminal 16 (or drain (gate) terminal 16) rises above a certain value (which value can be controlled by the selection of resistors (44, 45) in the described voltage divider), the enhancement mode transistor 43 can be turned on, thereby adjusting the resistance between the active device gate terminal 10 and the active device source terminal 8. This function can protect the active gate terminal from overvoltage events.

[0217] Fig.12 A circuit schematic representation of a further embodiment of the proposed disclosure is shown in which a voltage limiting circuit including resistor 44, resistor 45 (forming a voltage divider) and an actively switched low voltage depletion mode transistor 46 is implemented. Many features of this embodiment are similar to Figure 6The features of the first auxiliary heterojunction transistor 46 are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, when the potential of the first additional terminal 16 (or drain (gate) terminal 16) of the first auxiliary heterojunction transistor increases, the resistance of the depletion mode transistor 46 can be reduced, thereby adjusting the resistance between the active device gate terminal 10 and the active device source terminal 8. The voltage divider formed by the two resistors (44, 45) determines the potential on the gate terminal of the depletion mode transistor 46. The described circuit can protect the active gate terminal from overvoltage events.

[0218] Fig.13 1 shows a circuit schematic representation of another embodiment of the proposed disclosure in which an overcurrent protection circuit consisting of a current sensing resistor 48 and an actively switched low voltage enhancement mode transistor 49 is implemented. Many features of this embodiment are similar to Figure 6 The features of the transistors are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the active region of the active (high voltage) transistor is divided into two regions, which form two parallel transistors. The drain and gate terminals of the two transistors are electrically connected. The two parallel transistors are a low resistance (main power) transistor 55 and a high resistance (current sensing) transistor 54. The first terminal of the current sensing resistor 48 is connected to the source terminal of the high resistance transistor 54. The potential at the gate terminal of the enhancement mode transistor 49 increases as the current through the current sensing resistor 48 increases. When the current through the resistive element 48 reaches a critical value, the enhancement mode transistor 49 turns on, providing a reduction in the resistance of the path between the gate 10 and the source 8 of the active (high voltage) device, thereby limiting the potential at the active gate terminal 10. The described circuit can protect the circuit from overcurrent events.

[0219] Fig.141 shows a circuit schematic representation of another embodiment of the proposed disclosure in which an overcurrent protection circuit consisting of a current sensing resistor 48 and an actively switched low voltage depletion mode transistor 47 is implemented. Many features of this embodiment are similar to Figure 6 The features of the transistor 40 are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the active region of the active (high voltage) transistor is divided into two isolation regions, which form two parallel transistors. The drain and gate terminals of the two transistors are electrically connected. The two parallel transistors are a low resistance (main power) transistor 55 and a high resistance (current sensing) transistor 54. The first terminal of the current sensing resistor 48 is connected to the source terminal of the high resistance transistor 54. The potential at the gate terminal of the depletion mode transistor 47 increases as the current through the resistor element 48 increases. As the current through the resistive element 48 increases, the resistance of the depletion mode transistor 49 decreases, providing a reduction in the resistance of the path between the gate 10 and the source 8 of the active (high voltage) device, thereby limiting the potential at the active gate terminal 10. The described circuit can protect the circuit from overcurrent events.

[0220] Fig.15 A circuit schematic representation of an additional embodiment of the proposed disclosure is shown in which an active Miller clamp circuit consisting of a resistor 52, an actively switched low voltage enhancement mode transistor 50, and an actively switched depletion mode transistor 51 is implemented. Many features of this embodiment are similar to Figure 6 The features of the transistor 100 are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, an active Miller clamp circuit is implemented to provide an additional pull-down network for the active device gate terminal 10 during the device turn-off transient.

[0221] Fig.16A circuit schematic representation of an additional embodiment of the proposed disclosure is shown in which an active Miller clamp circuit consisting of a resistor 52, an actively switched low voltage enhancement mode transistor 50, and an actively switched enhancement mode transistor 53 is implemented. Many features of this embodiment are similar to Figure 6 The features of the transistor 100 are similar and therefore have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, an active Miller clamp circuit is implemented to provide an additional pull-down network for the active device gate terminal 10 during the device turn-off transient.

[0222] Fig.17 Schematic representations of cross sections of active regions of depletion mode devices proposed in the prior art that can be used as actively switched transistors in locations 46, 47, 51, 58, 59, 60 are shown.

[0223] Fig.18 A three-dimensional schematic representation of the active region of a proposed depletion mode device with pGaN islands (not found in the prior art) in locations 46 , 47 , 51 , 58 , 59 that can be used as actively switched transistors is shown.

[0224] Fig.19 A diode operating in diode mode and used in positions 34, 58, 59 is shown. Fig.18 Three-dimensional schematic representation of the active region of a depletion mode device with pGaN islands shown.

[0225] Fig. 20 Shows Fig.18 The transfer characteristic of a depletion mode device is shown.

[0226] Fig.21 A cross section of an additional embodiment according to the second aspect of the proposed invention is shown. Fig.21 The features shown in Figure 2 In this embodiment, the first additional terminal 16 is not operatively connected to the auxiliary gate terminal 15 .

[0227] Fig. 22 Shows Fig.21, and the same reference numerals are used for corresponding features in the figure. In this embodiment, a series of components can be added between the auxiliary gate terminal 15 and the first additional terminal 16. By way of example only, these components can include, but are not limited to, any one or more of a resistive element, a passive element, and a current source. Additional illustrative examples of such embodiments are presented herein.

[0228] exist Fig.23 , a gallium nitride (GaN) chip 1000 (also referred to as a smart GaN power device or a GaN power or high-voltage integrated circuit) according to an embodiment of the second aspect of the present invention is shown. The GaN chip may include at least three terminals. The at least three terminals may include one or more of a high-voltage terminal, a low-voltage terminal, and a control terminal. The chip 1000 may also include one or more main power heterojunction transistors 500 with an internal gate. The source terminal and the drain terminal of the transistor 500 may be connected to the low-voltage terminal and the high-voltage terminal of the GaN chip, respectively. The chip 1000 may also include a current control circuit 530, a pull-down circuit 520 and / or an auxiliary gate circuit 510. The auxiliary gate circuit 510 may include at least one low-voltage heterojunction transistor (also referred to as an auxiliary transistor) with an internal gate.

[0229] The auxiliary gate circuit 510 can be operatively connected to at least one internal gate of the main power heterojunction transistor 500 through a first connection, and can also include a second connection operatively connecting the auxiliary gate 510 to a control terminal. A third connection of the auxiliary gate circuit 510 can operatively connect the internal gate of the low voltage heterojunction transistor of the auxiliary gate circuit 510 to the pull-down circuit 520.

[0230] In addition to at least one connection to the auxiliary gate circuit, the pull-down circuit 520 may also include at least one connection to the current control circuit and at least one connection to the source terminal of the main power heterojunction transistor 500 .

[0231] The current control circuit 530 may include at least one connection to each of the control terminal, the auxiliary gate circuit 510 , and the pull-down circuit 520 .

[0232] The auxiliary gate 510 may partially control the voltage and current level entering the internal gate of the main power heterojunction transistor 500. The current control circuit 530 may control the current level entering the pull-down circuit 520, and in conjunction with the pull-down circuit may further determine the voltage level of the internal gate of the low voltage heterojunction transistor applied to the auxiliary gate 510. The pull-down circuit may in turn actively pull down the gate voltage of the low voltage heterojunction transistor to clamp the voltage of the internal gate of the main power heterojunction transistor.

[0233] refer to Fig. 22 and Fig.23 In some embodiments, the auxiliary gate terminal 15 of the auxiliary gate block 510 may be connected to the first additional terminal 16 of the auxiliary gate block 510 through or via the current control block 530. The auxiliary gate terminal 15 may also be connected to the source terminal 8 of the active device block 500 through or via the pull-down circuit block 520.

[0234] When the auxiliary gate terminal 15 is at or close to 0V, the portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 may be depleted. As the first additional terminal bias is increased, the potential on both bias terminals 15, 16 may increase and a 2DEG may begin to form under the pGaN gate 14. The 2DEG formed under the pGaN gate 14 may connect with the (already formed) 2DEG layer under the first additional terminal 16 and the second additional terminal 12. By connecting these 2DEG layers, a 2DEG connection may be formed between the first additional terminal 16 and the second additional terminal 12.

[0235] When the second additional terminal 12 is connected to the active gate 10, the device can now be turned on. A positive shift in the device threshold voltage is observed using this structure because not all of the potential applied to the first additional terminal 16 is transferred to the active gate (internal gate) 10. A portion of this potential drops across the auxiliary gate 510, and only a portion is transferred to the second additional terminal 12 connected to the active gate (internal gate) 10. Advantageously, as described below, this enables the threshold voltage to be increased without compromising the on-state resistance of the device.

[0236] Fig.24 An example of the relationship between the external gate voltage bias (GaN chip control terminal bias) 2501 and the active gate voltage (internal gate voltage) 2502 according to one embodiment of the present invention is shown. When the external gate voltage signal initially rises (until the auxiliary gate transistor Vth), the auxiliary gate transistor has a high resistance. Most of the applied potential drops across the auxiliary gate transistor, and the potential of the active gate terminal remains close to 0V. When the external gate voltage signal reaches the auxiliary gate transistor Vth, the resistance of the auxiliary transistor becomes small, and the potential of the active gate terminal begins to rise.

[0237] Thus, an increase in threshold voltage is achieved in the GaN chip multi-block HEMT without affecting the on-state resistance of the device. A positive shift in the device threshold voltage is observed using this structure (as shown in Figure 2500) because not all of the potential applied to the external gate is transferred to the active gate (a portion of this potential is used to form an auxiliary 2DEG under the auxiliary gate), and only a portion is transferred to terminal 12 connected to the active gate 10.

[0238] When the external gate 16 bias voltage reaches a pre-designed level, the pull-down circuit block 520 starts to operate and pulls the gate 15 of the auxiliary transistor toward the potential of the active transistor source terminal 8. The auxiliary transistor has a high resistance in this case, so any additional external gate potential drops across the auxiliary transistor, and the active gate terminal potential remains approximately constant, for example, at least about 20V, as the external gate voltage signal rises.

[0239] The design of the current control block 530 and the pull-down circuit block 520 determines the potential to which the active gate terminal is clamped.

[0240] Several illustrative examples with different implementations of functional blocks 510, 520, 530 are included herein. Note that the list of examples described is not exhaustive, and any combination of different implementations of each block may be considered within the scope of the present invention. This includes the several examples described above for auxiliary gates. In addition, any or all of the protection circuits and control circuits described above (overvoltage, overcurrent, Miller clamp) may also be used with Fig.23 The functional blocks shown in are combined.

[0241] Fig.25 A schematic representation of one embodiment of the proposed invention GaN chip 1000a is shown. The auxiliary gate block 510a includes an enhancement mode low voltage HEMT, the current control block 530a includes a resistor, and the pull-down circuit 520a includes a HEMT in a threshold multiplier configuration. The threshold multiplier configuration in this embodiment includes a voltage divider and a pull-down enhancement mode HEMT, wherein the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT. In this embodiment, the top of the voltage divider is connected to the drain of the pull-down enhancement mode HEMT and the gate terminal of the auxiliary gate block HEMT.

[0242] Fig.26 A schematic representation of a further embodiment of the proposed invention GaN chip 1000b is shown, wherein the auxiliary gate block 510b comprises an enhancement mode low voltage HEMT. The current control block 530b comprises a resistor in parallel with an RC circuit. The parallel RC circuit can improve the dynamic characteristics of the device during turn-on and turn-off transients. The pull-down circuit 520b comprises a HEMT with parallel passive elements in a threshold multiplier configuration. The passive elements can improve the dynamic characteristics of the device during turn-on and turn-off transients.

[0243] Fig. 27A schematic representation of a further embodiment of the proposed invention GaN chip 1000c is shown. The auxiliary gate block 510c comprises an enhancement mode low voltage HEMT and a Schottky or pn diode in parallel. In this embodiment, a low on-state voltage diode is connected in parallel between the drain 16 and the source 12 of the auxiliary transistor. During the turn-off period of the entire configuration that connects the gate terminal 10 of the active GaN transistor to ground, the parallel diode acts as a pull-down network. When a positive bias is applied to the external gate terminal 16 (referred to as the on-state), the diode will be reverse biased and zero current will flow through it, thereby not affecting the electrical characteristics of the entire high voltage configuration. When zero bias (off-state) is applied to the auxiliary gate 15, the diode is forward biased and the off-current flowing through it will discharge the gate capacitance of the active transistor, thereby enabling the entire configuration to be turned off. In the off-state, the gate of the active device 10 will remain biased to a minimum voltage equal to the turn-on voltage of the diode. Therefore, the diode is designed to keep its turn-on voltage as low as possible, ideally a few millivolts. The current control block 530c includes a current source using a low voltage depletion mode HEMT and a resistor. The value of the resistor can be adjusted to set the maximum current level that can flow through the current source. The pull-down circuit 520c includes a HEMT in a threshold multiplier configuration.

[0244] Fig.28 A schematic representation of a further embodiment of the proposed invention GaN chip 1000d is shown, wherein the auxiliary gate block 510d comprises an enhancement mode low voltage HEMT. The current control block 530d comprises a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 520d comprises a HEMT in a threshold multiplier configuration.

[0245] Fig.29 A schematic representation of a further embodiment of the proposed invention GaN chip 1000e is shown, wherein the auxiliary gate block 510e comprises an enhancement mode low voltage HEMT. Furthermore, in this embodiment, a second auxiliary transistor (which may advantageously be low voltage) is connected in parallel with the first auxiliary transistor in the auxiliary gate block, wherein the drain terminal 16 of the first auxiliary transistor is connected to the drain terminal of the second auxiliary transistor, and the source terminal 12 of the first auxiliary transistor is connected to the source (gate) terminal of the second auxiliary transistor. In this embodiment, the pull-down network during the off period of the entire configuration is the second auxiliary transistor. This is similar to Fig. 27 , but using a second auxiliary transistor instead of a diode. The current control block 530e includes a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 520e includes a HEMT in a threshold multiplier configuration.

[0246] Fig.301 shows a schematic representation of another embodiment of the proposed invention GaN chip 1000f, wherein the auxiliary gate block 510f comprises an enhancement mode low voltage HEMT. Fig.29 In the embodiment described in the embodiment of the present invention, the second auxiliary transistor is connected in parallel with the first auxiliary transistor. The current control block 530f includes a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 520f includes a HEMT in a threshold multiplier configuration. In this embodiment, the threshold multiplier also includes a current source in parallel with one of the resistors in the voltage divider of the threshold multiplier circuit. The inclusion of the current source provides temperature stability in the clamping voltage value achieved on the active gate of the high voltage transistor 500 when the voltage signal on the external gate terminal is high.

[0247] Fig.31 A schematic representation of a further embodiment of the proposed invention GaN chip 1000j is shown, wherein the auxiliary gate block 510j comprises an enhancement mode low voltage HEMT. The current control block 530j comprises a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 520j comprises a HEMT in a threshold multiplier configuration, similar to the previous embodiment comprising a voltage divider and an enhancement mode pull-down HEMT. However, in this embodiment, the resistor on top of the voltage divider - connected to the drain terminal of the enhancement mode pull-down HEMT in the previous embodiment - is alternatively connected to the source terminal of the depletion mode HEMT used in the current source of the control block.

[0248] Fig.32 A block diagram schematically shows another embodiment of the proposed invention. In this embodiment, Fig.23 Compared with the embodiment shown in the figure, some additional functional blocks are included. In this embodiment, as in the previous embodiment, an auxiliary gate block, a current control block and a pull-down circuit block are included. An integrated active Miller clamp is also included.

[0249] An active Miller clamp circuit is implemented to provide an additional pull-down network for the active device gate terminal 10 during the device turn-off transient. The active Miller clamp circuit may include a monolithically integrated Miller clamp transistor 570, a logic inverter 560, an external gate signal to logic signal converter 540, and / or a DC to DC block 550 that generates a suitable inverter VDD rail.

[0250] As shown in this embodiment, transistor 570 may include a low voltage enhancement mode HEMT. Logic inverter 560 may include a low voltage enhancement mode HEMT and a resistor (similar to Fig.16). However, this is provided only as an example configuration, and other logic inverter designs may be used instead of or in addition to the p-GaN technology enhancement mode HEMT. The enhancement mode devices used in the inverter may be formed in the same process steps as the active high voltage transistors. Therefore, the upper limit of the voltage signal that may be applied to the gate of the inverting transistor may be lower than the external gate signal. The Vg to logic block 540 may be used to reduce the external gate voltage signal to a voltage signal suitable for use with a p-GaN technology enhancement mode HEMT.

[0251] When the output of the inverter is high, the integrated Miller clamp transistor can receive a signal close to VDD to its gate terminal. Therefore, if the available VDD rail is higher than the peak gate voltage that the integrated clamp resistor can withstand, the DC / DC step 550 can be integrated into the GaN chip multi-block power device to reduce the VDD rail to the desired level.

[0252] Fig.33 A schematic representation of another embodiment of the proposed invention is shown, wherein the auxiliary gate block 610a comprises a depletion mode low voltage HEMT. The current control block 630a comprises a resistor element. The pull-down circuit 620a comprises a HEMT in a threshold multiplier configuration. The operation of the GaN chip multi-block power device shown in this embodiment is similar to Fig.25 The following operation of the device shown is similar: when the external voltage signal exceeds a predetermined (by design) level, a clamping voltage signal is implemented on the active gate terminal (internal gate terminal) of the high voltage HEMT (main power heterojunction transistor) 500. Compared with the GaN chip power device 1000a, the use of depletion mode transistors in the auxiliary gate block in this embodiment may not be as effective in providing an increased threshold voltage for the GaN chip power device 3000a. When the potential on the active gate is high and the potential at the external gate terminal is low, the low voltage depletion mode HEMT can be more effective in providing a turn-off path as part of the turn-off network of the device due to the presence of a channel in the depletion mode transistor.

[0253] Fig.34A schematic representation of a further embodiment of the proposed invention GaN chip 3000b is shown, wherein the auxiliary gate block 610b comprises a depletion mode low voltage HEMT. In this embodiment, a second auxiliary transistor (which may advantageously be a low voltage transistor) is connected in parallel with the first auxiliary transistor in the auxiliary gate block, wherein the drain terminal 16 of the first auxiliary transistor is connected to the drain terminal of the second auxiliary transistor, and the source terminal 12 of the first auxiliary transistor is connected to the source (gate) terminal of the second auxiliary transistor. In this embodiment, during the turn-off of the high voltage transistor 500, the second auxiliary transistor is included as an additional pull-down network. The current control block 630e comprises a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 620e comprises a HEMT in a threshold multiplier configuration.

[0254] Fig.35 A schematic representation of a further embodiment of the proposed invention GaN chip 3000d is shown, wherein the auxiliary gate block 610d comprises a depletion mode low voltage HEMT. Furthermore, in this embodiment, a second depletion mode auxiliary transistor (which may advantageously be low voltage) is connected in parallel with the first auxiliary transistor in the auxiliary gate block, wherein the drain terminal 16 of the first auxiliary transistor is connected to the drain terminal of the auxiliary gate block, and the source terminal 12 of the first auxiliary transistor is connected to the source terminal of the second auxiliary transistor. The gate terminal of the second auxiliary transistor is connected to the source terminal of the high voltage transistor 500. In this embodiment, during the turn-on of the high voltage transistor 500, a second depletion mode auxiliary transistor is included as an additional current path. When the external gate signal goes high, the second depletion mode transistor is in saturation mode and provides an additional conduction path for charging the gate-source capacitance of the high voltage transistor 500. When the voltage of the active gate terminal rises above the threshold voltage of the second depletion mode transistor, the conduction path becomes very resistive. The current control block 630e comprises a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 620e includes a HEMT in a threshold multiplier configuration.

[0255] Fig.36 A schematic representation of a further embodiment of the proposed invention GaN chip 5000b is shown, wherein the auxiliary gate block 810b comprises an enhancement mode low voltage HEMT. The current control block 830b comprises a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 820b comprises a HEMT in a threshold multiplier configuration, which comprises a voltage divider and a pull-down enhancement mode HEMT, wherein the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT. In this embodiment, the top of the voltage divider is connected to the active gate terminal instead of the drain of the pull-down enhancement mode HEMT in the previous embodiment.

[0256] exist Fig.37In the embodiment shown in FIG. 1 , the top of the voltage divider is connected to the active gate terminal, and the voltage divider includes a plurality of E-HEMTs 821c connected in series with a resistor in the source-gate connection as shown in the previous embodiment. Fig.37 Two HEMTs in series are shown, but a different number may be used. These HEMTs are one possible approach for adjusting the voltage level that needs to be reached on the active gate terminal before the pull-down enhancement mode HEMT starts operating.

[0257] Fig.38 Another method for adjusting the voltage level that needs to be reached on the active gate terminal before the pull-down enhancement mode HEMT starts operating is shown. Fig.38 An additional HEMT in threshold multiplier configuration 821d is used.

[0258] Fig.39 A schematic representation of a further embodiment of the proposed invention GaN chip 6000a is shown, wherein the auxiliary gate block 910a comprises an enhancement mode low voltage HEMT. The current control block 930a comprises a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 920a comprises a HEMT in a threshold multiplier configuration, which comprises a voltage divider, wherein the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT (similar to the previous embodiment). However, in this embodiment, the voltage divider is connected to an external gate terminal instead of the gate terminal of the auxiliary transistor. In addition, an additional HEMT in a threshold multiplier configuration may be included between the gate and source terminals of the pull-down HEMT in enhancement mode. The additional threshold multiplier is used to limit the voltage on the gate terminal of the pull-down transistor. The additional threshold multiplier may alternatively be implemented using one or more diodes in series.

[0259] Fig.40 A schematic representation of a further embodiment of the proposed invention GaN chip 6000b is shown, wherein the auxiliary gate block 910b comprises an enhancement mode low voltage HEMT. The current control block 930b comprises a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 920b comprises a pull-down enhancement mode HEMT, whose gate is connected to the output of a voltage divider (similar to the other embodiments). In this embodiment, the voltage divider is connected to the external gate terminal and consists of a current source and a HEMT in a threshold multiplier configuration. The current source is implemented using a low voltage depletion mode HEMT and a resistor. The output of the voltage divider (divider) is the gate of the additional low voltage HEMT.

[0260] In further embodiments, the gate of the pull-down HEMT may be controlled by an additional external signal, preferably through a VG to Vlogic regulator as described above, or the gate of the pull-down HEMT may be controlled by the output of an additional circuit integrated on the GaN device that provides functions such as over-current protection, under-voltage lockout, supply voltage over-voltage protection, logic inverter, or others.

[0261] Fig.41 FIG. 1 shows a staggered device layout including an auxiliary gate structure of another embodiment of the present disclosure. Many features of this embodiment are similar to Fig.21 The features shown are similar and therefore have the same reference numerals, namely, active gate terminal 10, low voltage source terminal 8, high voltage drain terminal 9, first additional terminal 16 and second additional terminal 12. Also shown in this illustration are source pad metal 18, drain pad metal 19 and gate pad metal 20. However, in this embodiment, unlike the gate pad metal 20 that directly contacts the gate finger 10 in the prior art device, it is connected to the auxiliary gate terminal 16. The gate fingers in the staggered structure are directly connected to the second additional terminal 12. Note that in this layout, as in the cross-section in the previous embodiment, an isolation layer exists between the auxiliary gate and the 2DEG in the active device. Additional operating blocks in the device are also shown: auxiliary gate block 510, pull-down circuit block 520, current control block 530. The connection of the different blocks can be made using the interconnect metal layer 210.

[0262] Fig.42 1 shows an alternate device layout of another embodiment of the present disclosure, where the auxiliary gate and terminal regions are located below the source pad metal. Similarly, these circuits can be located below the gate pad or drain pad (not shown). Many features of this embodiment are similar to Fig.41 The features shown in are similar and therefore have the same reference numerals, namely, active gate terminal 10, low voltage source terminal 8, high voltage drain terminal 9, first additional terminal 16, second additional terminal 12, source pad metal 18, drain pad metal 19, gate pad metal 20, auxiliary gate block 510, pull-down circuit block 520, current control block 530, interconnect metal 210. However, in this embodiment, the auxiliary gate block, current control block and pull-down circuit block are located below the source pad metal 18. Intermetallic vias 220 can connect blocks at different metal layers in the process. Compared with prior art designs, less additional wafer area will be required to include additional blocks. Note that in this illustration, the additional block is located below the source pad metal, however, the present disclosure is intended to include designs in which the additional block can be located below other pads present in the integrated circuit layout.

[0263] Fig.43A block diagram of another embodiment of the proposed disclosure is shown, wherein any one embodiment of a GaN chip power device 35 is in a half-bridge configuration, wherein the external gates of the two power devices (high side and low side) are connected to a gate driver block, which in turn is connected to a logic block. The different components and blocks included in the figure can be discrete components or connected monolithically. This shows different examples of possible monolithic integration 36, 37, 38, while using the concept of auxiliary gates.

[0264] Fig.44 A circuit schematic representation of a further embodiment of the proposed disclosure is shown, wherein GaN chip power devices 35 according to the present disclosure are connected in a standard three-phase half-bridge configuration.

[0265] It should be understood that the auxiliary transistors in all embodiments may be low voltage transistors or high voltage transistors.

[0266] It should also be understood that terms such as "top" and "bottom", "above" and "below", "lateral" and "vertical", as well as "below" and "above", "front" and "back", "underlying", etc. may be used in this specification as conventionally described and do not imply a specific physical orientation of the device as a whole.

[0267] Although the present disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to these embodiments. In view of the present disclosure, those skilled in the art will be able to make modifications and substitutions, which are considered to fall within the scope of the appended claims. Each feature disclosed or shown in this specification, whether alone or in any suitable combination with any other feature disclosed or shown herein, may be included in the present disclosure.

[0268] References

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Claims

1. A heterojunction power device based on a group III nitride power semiconductor, the heterojunction power device comprising: An active heterojunction transistor is formed on a substrate, and the active heterojunction transistor comprises: a first Group III nitride semiconductor region including a first heterojunction including an active two-dimensional carrier gas of a second conductivity type; a first terminal operatively connected to the Group III nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the Group III-nitride semiconductor region; an active gate region formed on the Group III nitride semiconductor region, the active gate region being formed between the first terminal and the second terminal; An auxiliary heterojunction transistor is formed on the substrate or another substrate, and the auxiliary heterojunction transistor includes: a second Group III nitride semiconductor region including a second heterojunction including an auxiliary two-dimensional carrier gas of a second conductivity type; a first additional terminal operatively connected to the second Group III-nitride semiconductor region; a second additional terminal laterally spaced from the first additional terminal and operatively connected to the second Group III-nitride semiconductor region; an auxiliary gate region formed on the second group III nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal; wherein the first additional terminal is operatively connected to the auxiliary gate region, and wherein the second additional terminal is operatively connected to the active gate region; and wherein the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and wherein the heterojunction power device further comprises a second auxiliary heterojunction transistor operatively connected in parallel with the first auxiliary heterojunction transistor, and wherein the first additional terminal of the first auxiliary heterojunction transistor is operatively connected to a source terminal of the second auxiliary heterojunction transistor, and the second additional terminal of the first auxiliary heterojunction transistor is operatively connected to a drain terminal of the second auxiliary heterojunction transistor; and The heterojunction power device further comprises an active Miller clamp comprising a logic inverter and a transistor used as an active ground switch of a pull-down network, and wherein the logic inverter comprises a resistor or a resistive element and an enhancement mode transistor. 2 . The heterojunction power device according to claim 1 , further comprising a first resistor, the first resistor being connected in series with the second auxiliary heterojunction transistor, and the first resistor being located between a gate terminal and a drain terminal of the second auxiliary heterojunction transistor. 3 . The heterojunction power device of claim 2 , further comprising a second resistor operatively connected between a drain terminal of the second auxiliary heterojunction transistor and a second terminal of the active heterojunction transistor. 4 . 4 . The heterojunction power device according to claim 1 , further comprising a third auxiliary transistor, wherein the third auxiliary transistor is connected in series with the second auxiliary heterojunction transistor and the third auxiliary transistor is located between the gate and drain terminals of the second auxiliary heterojunction transistor.

5. The heterojunction power device according to claim 4, wherein: A gate terminal of the third auxiliary transistor is connected to a source terminal or a drain terminal of the third auxiliary transistor.

6. The heterojunction power device according to claim 4, wherein: The third auxiliary transistor is configured to reduce an active gate capacitance discharge time during turn-off of the heterojunction power device by increasing a potential of a gate terminal of the second auxiliary heterojunction transistor compared to a drain terminal of the second auxiliary heterojunction transistor.

7. The heterojunction power device according to claim 4, wherein: The third auxiliary transistor is a depletion mode transistor based on a heterojunction device of a depletion mode group III nitride semiconductor, comprising: substrate; a group III nitride semiconductor region formed on the substrate, wherein the group III nitride semiconductor region comprises a heterojunction, the heterojunction comprising at least one two-dimensional carrier gas of a second conductivity type; a first terminal operatively connected to the Group III nitride semiconductor region; a second terminal laterally spaced apart from the first terminal in a first dimension and operatively connected to the Group III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed on the Group III nitride semiconductor region, the at least two highly doped semiconductor regions formed between the first terminal and the second terminal; and an active gate region formed on the at least two highly doped semiconductor regions; Wherein, the at least two highly doped semiconductor regions are spaced apart from each other in a second dimension, and wherein the second dimension is perpendicular to the first dimension. 8 . The heterojunction power device of claim 4 , further comprising an additional resistor operatively connected between a drain terminal of the second auxiliary heterojunction transistor and a second terminal of the active heterojunction transistor. 9 . The heterojunction power device of claim 1 , further comprising a voltage limiting circuit comprising at least two resistors forming a voltage divider enhancement mode and an actively switched low voltage enhancement mode transistor.

10. The heterojunction power device according to claim 9, wherein: The drain terminal of the actively switched low voltage enhancement mode transistor is connected to the gate terminal of the active high voltage transistor, and the source terminal of the actively switched low voltage enhancement mode transistor is connected to the source terminal of the active heterojunction high voltage transistor.

11. The heterojunction power device according to claim 9, wherein: The voltage divider is operatively connected between a first additional terminal of the first auxiliary heterojunction transistor and a second terminal of the active heterojunction transistor.

12. The heterojunction power device according to claim 9, wherein: A midpoint of the voltage divider is operatively connected to a gate terminal of the actively switched low voltage enhancement mode transistor. 13 . The heterojunction power device of claim 1 , further comprising a voltage limiting circuit comprising at least two resistors forming a voltage divider and a low voltage depletion mode transistor.

14. The heterojunction power device of claim 1, further comprising an overcurrent protection circuit comprising a current sensing resistor and an actively switched low voltage enhancement mode transistor.

15. The heterojunction power device according to claim 14, wherein: The actively switched low voltage enhancement mode transistor is connected between a gate terminal of the active heterojunction transistor and a second terminal of the current sensing resistor, and wherein the actively switched low voltage enhancement mode transistor is connected to a first terminal of the current sensing resistor. 16 . The heterojunction power device of claim 1 , further comprising an overcurrent protection circuit comprising a current sensing resistor and a low voltage depletion mode transistor.

17. The heterojunction power device according to claim 1, wherein: The resistor is a 2DEG resistor monolithically integrated in the heterojunction power device.

18. A method for manufacturing a heterojunction power device based on a group III nitride semiconductor, the method comprising: An active heterojunction power transistor is formed on a substrate, wherein the active heterojunction power transistor comprises: a first Group III nitride semiconductor region including a first heterojunction including an active two-dimensional carrier gas of a second conductivity type; a first terminal operatively connected to the Group III nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the Group III-nitride semiconductor region; an active gate region formed on the Group III nitride semiconductor region, the active gate region being formed between the first terminal and the second terminal; A first auxiliary heterojunction transistor is formed on the substrate or on another substrate, wherein the first auxiliary heterojunction transistor comprises: a second Group III nitride semiconductor region including a second heterojunction including an auxiliary two-dimensional carrier gas of a second conductivity type; a first additional terminal operatively connected to the second Group III-nitride semiconductor region; a second additional terminal laterally spaced from the first additional terminal and operatively connected to the second Group III-nitride semiconductor region; an auxiliary gate region formed on the second group III nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal; forming a second auxiliary heterojunction transistor on the substrate or the further substrate, operatively connecting the first additional terminal to the auxiliary gate region, and operatively connecting the second additional terminal to the active gate region, connecting the second auxiliary heterojunction transistor in operative parallel connection with the first auxiliary heterojunction transistor, operatively connecting a first additional terminal of the first auxiliary heterojunction transistor to a source terminal of the second auxiliary heterojunction transistor, operatively connecting a second additional terminal of the first auxiliary heterojunction transistor to a drain terminal of the second auxiliary heterojunction transistor; and An active Miller clamp is provided, which includes a logic inverter and a transistor used as an active ground switch of a pull-down network, and wherein the logic inverter includes a resistor or a resistive element and an enhancement mode transistor.

19. A heterojunction chip having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal, wherein the heterojunction chip further comprises: at least one main power heterojunction transistor, wherein the at least one main power heterojunction transistor comprises an internal gate terminal, a source terminal, and a drain terminal, wherein the source terminal of the at least one main power heterojunction transistor is operatively connected to the low voltage terminal and the drain terminal of the at least one main power heterojunction transistor is operatively connected to the high voltage terminal; an auxiliary gate circuit, comprising at least one first low voltage heterojunction transistor, wherein the auxiliary gate circuit is operatively connected to an internal gate terminal of the at least one main power heterojunction transistor and the control terminal; a pull-down circuit comprising at least one non-linear element and at least one second low voltage heterojunction transistor, the non-linear element comprising a voltage divider for driving a gate terminal of the at least one second low voltage heterojunction transistor, wherein the pull-down circuit is operatively connected to an internal gate terminal of the at least one first low voltage heterojunction transistor and a source terminal of the at least one main power heterojunction transistor; a current control circuit comprising at least one resistor, wherein the current control circuit is operatively connected to the control terminal and the pull-down circuit; an active Miller clamp having a connection to an internal gate terminal of the main power heterojunction transistor and bypassing the pull-down circuit during a device off state or turn-off transient; the active Miller clamp comprising a logic inverter and at least one Miller clamp low voltage transistor; and wherein the logic inverter comprises a resistor or a resistive element and an enhancement mode transistor; and wherein the auxiliary gate and current control circuit at least partially controls the voltage and current entering the internal gate of the at least one main power heterojunction transistor; and Wherein, the current control circuit at least partially controls the current entering the pull-down circuit and at least partially determines the control terminal voltage level, at which the pull-down circuit actively pulls down the gate voltage of the at least one first low-voltage heterojunction transistor to clamp the internal gate voltage of the at least one main power heterojunction transistor.

20. The heterojunction chip according to claim 19, wherein: The voltage divider includes at least one of a resistor, a capacitor, a diode or a transistor element; and The voltage divider has at least one connection to an internal gate of the at least one second low voltage heterojunction transistor.

21. The heterojunction chip according to claim 19, wherein: The voltage divider is operatively connected to at least one of the current control circuit, an internal gate of the at least one main power heterojunction transistor, and the control terminal.

22. The heterojunction chip according to claim 19, wherein: The current control circuit includes at least one of the following: Resistors; at least one third low voltage heterojunction transistor; Wherein, each or both of the resistor and the at least one third low-voltage heterojunction transistor are used as a current source and control the action of the pull-down circuit.

23. The heterojunction chip according to claim 22, wherein: The current control circuit further includes at least one current mirror circuit.

24. The heterojunction chip according to claim 19, wherein: At least one of the auxiliary gate circuit, the pull-down circuit, and the current control circuit includes at least one low voltage depletion mode heterojunction transistor.

25. The heterojunction chip according to claim 19, wherein: At least one of the auxiliary gate circuit, the pull-down circuit, and the current control circuit includes at least one capacitor.

26. The heterojunction chip according to claim 19, wherein: The heterojunction chip also includes at least one monolithically integrated component, which is one or more of a DC to DC converter circuit, a voltage regulator, and a gate voltage to logic signal clamp circuit.

27. The heterojunction chip according to claim 19, wherein: At least one of the auxiliary gate circuit, the pull-down circuit, or the current control block is integrated under one or more of the internal gate, source terminal, and drain terminal of the at least one main power heterojunction transistor.

28. The heterojunction chip according to claim 19, wherein: The at least one main power heterojunction transistor comprises two main power heterojunction transistors connected in a half-bridge, and wherein at least one of the two main power heterojunction transistors comprises at least one of the auxiliary gate circuit, the pull-down circuit and the current control circuit.

29. The heterojunction chip according to claim 19, wherein: The at least one main power heterojunction transistor includes four main power heterojunction transistors connected in a full bridge, and wherein at least one of the four main power heterojunction transistors includes at least one of the auxiliary gate circuit, the pull-down circuit and the current control circuit.

30. The heterojunction chip according to claim 19, wherein: The at least one main power heterojunction transistor includes at least six main power heterojunction transistors connected in a three-phase half-bridge configuration, and wherein at least one of the six main power heterojunction transistors includes at least one of the auxiliary gate circuit, the pull-down circuit and the current control circuit.

31. The heterojunction chip according to claim 19, wherein: The active Miller clamp is a monolithically integrated Miller clamp circuit.

32. The heterojunction chip of claim 19, wherein a drain terminal of the at least one Miller clamped low voltage transistor is operatively connected to an internal gate of the at least one main power heterojunction transistor.

33. The heterojunction chip according to claim 32, wherein: The internal gate terminal of the Miller clamp low voltage transistor is operatively connected to an output of an additional circuit integrated on the heterojunction chip, wherein the additional circuit is at least one of the following: Overcurrent protection circuit; undervoltage lockout circuit; and Power supply voltage overvoltage protection circuit.

34. The heterojunction chip according to claim 19, wherein: The heterojunction chip further comprises a monolithically integrated additional circuit, and wherein the at least one second low voltage heterojunction transistor is operatively connected to an output of the monolithically integrated additional circuit, the monolithically integrated additional circuit being one of: Overcurrent protection circuit; Undervoltage lockout circuit; Power supply voltage overvoltage protection circuit; and Logic inversion circuit.

35. The heterojunction chip according to claim 19, wherein: The auxiliary gate circuit further includes at least one additional low voltage transistor, wherein an internal gate terminal of the at least one additional low voltage transistor is operatively connected to a source terminal to cause turn-off of the at least one main power heterojunction transistor.

36. The heterojunction chip according to claim 19, further comprising one or more monolithically integrated temperature compensation circuits, wherein: The one or more monolithic integrated temperature compensation circuits include: Low voltage heterojunction transistor; a first resistor connected in series with the low voltage heterojunction transistor; and a second resistor connected in parallel with the low voltage heterojunction transistor; and Wherein, the one or more monolithically integrated temperature compensation circuits each reduce the effects of temperature changes on the circuit behavior of the connected components.

37. The heterojunction chip according to claim 36, wherein: The one or more monolithically integrated temperature compensation circuits include a portion of at least one of the voltage divider, the auxiliary gate circuit, the pull-down circuit, and the current control circuit.

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