Multi-Jitter Profile Signal Generation

Abstract

At least some aspects of the present disclosure provide a system (104). In some examples, the system includes a pulse width modulation (PWM) generator (218) configured to generate a pulse width modulation (PWM) signal (PWM1). The PWM generator generates the PWM signal by: generating a first signal having a first dither profile and a first frequency bandwidth; generating a second signal having a second dither profile and a second frequency bandwidth greater than the first frequency bandwidth; modulating the second signal with the first signal to generate a double random spread spectrum signal; and generating the pulse width modulation signal according to the double random spread spectrum signal.

Description

Background Art

[0001] A switched mode power supply (SMPS) transfers power from an input power source to a load by switching one or more power transistors coupled via switch nodes / terminals to an energy storage element (such as an inductor / transformer and / or capacitor), which is capable of being coupled to the load. The power transistor may be included in a power converter, which includes or is capable of being coupled to the energy storage element. The SMPS may include an SMPS controller to provide one or more gate drive signals to the power transistor. The SMPS operates at a switching frequency that may generate noise, resulting in electromagnetic interference (EMI) at the switching frequency and its harmonic frequencies. Summary of the invention

[0002] At least some aspects of the present disclosure provide a circuit. In at least some instances, the circuit includes a linear feedback shift register (LFSR), a clock divider, a ramp generator, an adder, and an oscillator. The LFSR includes a clock input terminal configured to receive a clock signal, a first output terminal, and a second output terminal. The clock divider includes a clock input terminal configured to receive a clock signal, a first input terminal coupled to a first output terminal of the LFSR, a second input terminal coupled to a second output terminal of the LFSR, and an output terminal. The ramp generator includes an input terminal coupled to an output terminal of the clock divider and an output terminal. The adder includes a first input terminal coupled to an output terminal of the ramp generator and a second input terminal coupled to a first output terminal of the LFSR and an output terminal. The oscillator includes a first input terminal coupled to an output terminal of the adder and an output terminal.

[0003] Other aspects of the present disclosure provide a circuit. In at least some instances, the circuit includes an LFSR, a clock divider, a ramp generator, an adder, and an oscillator. The LFSR is timed by a clock signal and is configured to output a pseudo-random value in a digital data format. The clock divider is configured to receive a clock signal and divide the clock signal by a pseudo-random value to generate and output a divided clock signal. The ramp generator is configured to receive the divided clock signal, generate a ramp signal based on the divided clock signal, and output the ramp signal in a digital data format. The adder is configured to modulate the ramp signal with a pseudo-random value to generate a dual random spread spectrum signal. The oscillator is configured to receive the dual random spread spectrum signal and generate a pulse width modulated signal based on the dual random spread spectrum signal.

[0004] At least some aspects of the present disclosure provide a system. In some examples, the system includes a pulse width modulation (PWM) generator configured to generate a PWM signal. The PWM generator generates the PWM signal by: generating a first signal having a first jitter profile and a first frequency bandwidth; generating a second signal having a second jitter profile and a second frequency bandwidth greater than the first frequency bandwidth; modulating the second signal with the first signal to generate a double random spread spectrum signal; and generating a pulse width modulation signal according to the double random spread spectrum signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 showing block diagrams of illustrative systems according to various examples;

[0007] Figure 2 shows schematic diagrams of illustrative SMPSs according to various examples;

[0008] Figure 3 Schematic diagram showing an illustrative pulse width modulation (PWM) generator according to various examples;

[0009] Figure 4 diagrams showing illustrative signal waveforms according to various examples;

[0010] Figure 5 diagrams showing illustrative signal waveforms according to various examples;

[0011] Figure 6 diagrams showing illustrative signal waveforms according to various examples;

[0012] Figure 7 showing flowcharts of illustrative methods according to various examples; and

[0013] Figure 8 Table showing illustrative pseudo code according to various embodiments. DETAILED DESCRIPTION

[0014] In a switch mode power supply (SMPS), a power transistor is controlled (e.g., switched) to be turned on and off at a specific frequency called the switching frequency. The nature of the switching behavior of the power transistor causes and / or generates spectral frequency spurs of electromagnetic energy (e.g., conducted and / or radiated) at each of the switching frequency and its harmonic frequencies. These spectral frequency spurs are called electromagnetic interference (EMI) with a maximum amount of energy at the switching frequency. The generation of this sound may sometimes be undesirable. In at least some instances, the maximum amount of EMI energy permitted in a particular system at a specific frequency is limited. For example, various standards or government regulations limit the maximum amount of EMI energy permitted at a specific frequency in a system such as an automobile, audio equipment, or other application, in which excessive EMI at the specific frequency may be undesirable and / or inhibit the normal or intended operation of the system.

[0015] There are some techniques for reducing the peak energy of EMI at the switching frequency. For example, various jittering techniques spread the EMI energy over multiple frequencies (e.g., frequency bands). These jittering techniques are sometimes called spread spectrum jittering. Spread spectrum jittering changes the switching frequency between multiple values ​​over a predetermined bandwidth, thereby spreading the spectral energy of EMI over a predetermined bandwidth. This prevents the focusing of spectral energy at the switching frequency and reduces the peak spectral energy at the switching frequency. Some jittering techniques are more suitable for specific frequency ranges than other jittering techniques. For example, analog jittering techniques that generate triangular ramp signals can provide the best performance for jittering at low frequencies. Digital jittering techniques such as pseudo-random spread spectrum (PRSS) jittering can provide the best performance for jittering at high frequencies. However, a jittering technique that provides the best performance for one frequency range (e.g., high or low) may not provide the best performance for other frequency ranges, and in some instances may reduce system performance in other frequency ranges.

[0016] Aspects of the present disclosure provide for simultaneously using multiple jitter profiles (e.g., jitter signal shapes) or techniques to generate a dual random spread spectrum jitter (DRSS) signal. For example, a first signal is generated to represent an analog signal or a digital signal, and is a first modulated signal for modulating the output of an oscillator and is output as a plurality of digital bits. Alternatively, in some instances, the first signal is output in an analog format. In some instances, the first signal represents an analog triangular ramp, as discussed above. A second signal is generated to represent an analog signal or a digital signal, and the first signal is modulated by the second signal to generate a DRSS signal. In some instances, the second signal is a PRSS signal. In some instances, the first signal is modulated by the second signal by adding the first signal to the second signal. In some instances, the DRSS signal is output as a plurality of digital bits (e.g., data in a digital data format). In at least one instance, generating a DRSS signal by modulating the first signal with the second signal is referred to as DRSS jitter. In another instance, the result of modulating the first signal with the second signal is further modulated by another signal to generate a DRSS signal. In yet other examples, any number of signals, each optimized for varying frequencies, are modulated together or otherwise combined to form a DRSS signal. When a DRSS signal is generated by combining more than two signals, the DRSS signal may be renamed to reflect the multiple combined signals. An oscillator is controlled according to the DRSS signal to generate a pulse width modulated (PWM) clock signal for controlling another component (e.g., such as for controlling a power converter, setting a latch or other component that controls the power converter or another component, etc.). For consistency and clarity of description, in the present disclosure, the first signal includes digital bits representing a triangular wave form, and the second signal is a PRSS signal. However, the teachings of the present disclosure are not limited to this single example, and the first signal and the second signal may each be any signal suitable for use in modulation and / or dithering. For example, in various implementations, the first signal is in the form of a triangular wave and the second signal is in the form of a triangular wave, the first signal is in the form of a triangular wave and the second signal is a PRSS signal, the first signal and the second signal are each PRSS signals, the first signal is a PRSS signal and the second signal is a triangular waveform, either the first signal or the second signal is an adaptive random spread spectrum signal (ARSS), a periodic analog-type waveform, and the like. In at least some instances, an ARSS is defined as a modulation profile in the shape of a triangle with a modulation period (e.g., a triangle width) that is modulated over time. In some instances, the modulation period changes at the end of each ramp or at any other point in the cycle. Additionally, in some instances, the modulation period is a fixed value. In at least some instances, a periodic analog-type waveform is an analog or digital representation of an analog signal and can appear in a variety of shapes, including triangular, sinusoidal, exponential, and the like.

[0017] In some instances, the first signal is optimized for performing spread spectrum dithering in a low frequency band, such as a frequency band of about 150 kilohertz (kHz) to about 30 megahertz (MHz). Similarly, in some instances, the second signal is optimized for performing spread spectrum dithering in a high frequency band, such as a frequency band of about 30 MHz to about 108 MHz. Therefore, in at least some instances, modulating the first signal with the second signal to generate a DRSS signal causes the DRSS signal to be optimized for both the low frequency band and the high frequency band. For example, when the device is switched according to the PWM signal, generating the PWM signal according to the DRSS signal reduces the peak energy of EMI in the low frequency band (e.g., generated by the first signal) and the high frequency band (e.g., generated by modulating the first signal with the second signal).

[0018] Now turn to Figure 1 , showing a block diagram of an illustrative system 100. In at least some instances, the system 100 is an electronic device including a power supply 102, a SMPS 104, and a load 106. In at least some instances, the system 100 represents a consumer electronic device, such as a laptop computer, a smart phone, an audio device, a wearable device, etc. In other instances, the system 100 represents a system or subsystem in a transportation vehicle such as an automobile, an airplane, a ship, etc. In general, the system 100 represents any system that is expected and / or required to comply with a specific control specification or standard, which limits the peak energy of EMI at a specific frequency. One such standard is the International Special Committee on Radio Interference (Comité International Spécial des Perturbations Radioélectriques) (CISPR) 25, which specifies peak energy limits for various vehicles at specific frequencies. Other such standards or peak energy limits may be specified in emission standards established and / or published by the Federal Communications Commission (Federal Communications Commission) or other regulatory agencies.

[0019] In some examples, the power source 102 is a rechargeable or non-rechargeable battery or an exhaustible power source that outputs VIN. In other examples, the power source 102 is in the form of a mains power source, such as the output of a direct current (DC) transformer that receives an alternating current (AC) or other mains power source and generates a DC output signal as VIN. In some examples, the load 106 is any one or more electrical and / or mechanical components that receive VOUT from the SMPS 104 and operate at least in part according to VOUT. In at least one example, the SMPS 104 includes a controller 108 and a power converter 110. The power converter 110 is any suitable power converter, such as a buck power converter, a boost power converter, or a buck-boost power converter. The controller 108 generates a PWM that at least partially controls the operation of the power converter 110. In at least some examples, the controller 108 generates a PWM based on a DRSS signal to limit the EMI generated by the power converter 110 when generating VOUT, as described herein.

[0020] Now turn to Figure 2 , a schematic diagram of an illustrative SMPS 104 is shown. Although described as a component of system 100, in various examples, SMPS 104 is suitable for implementation in other systems or devices that receive VIN and generate VOUT by switching one or more components. In at least some examples, SMPS 104 includes a controller 108 and a power converter 110. In at least some examples, power converter 110 includes a field effect transistor (FET) 202, a FET 204, and an inductor 206. As shown in FIG. Figure 2 , power converter 110 is a current mode buck switching converter. However, the teachings of the present disclosure are equally applicable to boost switching converters and buck-boost switching converters, as well as voltage mode converters of buck, boost or buck-boost topologies or any other suitable power converter topology. In at least some examples, controller 108 includes resistor 208, resistor 210, amplifier 212, comparator 214, latch 216, PWM generator 218, and adder 220.

[0021] In the example architecture, FET 202 has a drain terminal coupled to node 224, a source terminal coupled to node 226, and a gate terminal. FET 204 has a drain terminal coupled to node 226, a source terminal coupled to ground node 230, and a gate terminal. Inductor 206 is coupled between node 226 and node 228. Resistor 208 is coupled between node 228 and node 232. Resistor 210 is coupled between node 232 and ground node 230. Amplifier 212 has a first input terminal (e.g., a negative or inverting input terminal) coupled to node 232, a second input terminal (e.g., a positive or non-inverting input terminal) coupled to node 234, and an output terminal. Comparator 214 has a first input terminal (e.g., a positive or non-inverting input terminal), a second input terminal (e.g., a negative or inverting input terminal) coupled to the output terminal of amplifier 212, and an output terminal. Latch 216 has a reset input terminal, a set input terminal, and an output terminal coupled to the output terminal of comparator 214. PWM generator 218 has an input terminal coupled to node 238, a first output terminal coupled to the set input terminal of latch 216, and a second output terminal coupled to the input terminal of adder 220. Adder 220 further has another input terminal configured to receive a signal (IL) indicating the current flowing through power converter 110. The output terminal of latch 216 is coupled to the gate terminal of FET 202. The output terminal of latch 216 is further coupled to the gate terminal of FET 204 through inverter 222. In other examples, inverter 222 is omitted, and an inverting output terminal (not shown) of latch 216 is coupled to the gate terminal of FET 204.

[0022] In an example of operation, the controller 108 controls the power converter to generate an output voltage (VOUT) at a node 228 based at least in part on an input voltage (VIN) received at a node 224. Based on the PWM output signal (PWM2) of the latch 216, the FET 202 and the FET 204 are controlled to be conductive or non-conductive, thereby generating VOUT from VIN. The resistor 208 and the resistor 210 together form a voltage divider having an output at a node 232. The signal present at the node 232 is a feedback signal (FB), which is a scaled representation of VOUT scaled based on the ratio of the resistances of the resistors 208 and 210. The amplifier 212 is an error amplifier that outputs a signal ERROR indicating the difference between FB and a reference voltage (VREF) received at a node 234 indicating a desired value of VOUT. The adder 220 receives IL and a slope compensation signal (COMP) and generates an output signal. Comparator 214 receives ERROR and the output signal of adder 220, and compares the received signals. When the output signal of adder 220 exceeds ERROR, comparator 214 outputs a signal (COMP2) with a logic high value. When the output signal of adder 220 is less than ERROR, comparator 214 outputs COMP2 with a logic low value. Latch 216 receives COMP2 at the reset input terminal and receives signal PWM1 at the set input terminal. When PWM1 is asserted, latch 216 outputs PWM2 with an asserted value. When COMP2 is asserted, latch 216 outputs PWM2 with a deasserted value. When PWM2 is asserted, FET 202 is controlled to be conductive, and FET 204 is controlled to be non-conductive. Similarly, when PWM2 is deasserted, FET 202 is controlled to be non-conductive, and FET 204 is controlled to be conductive.

[0023] PWM generator 218 is configured to receive a clock signal (CLK) at node 238 and generate PWM1 and COMP. For example, based on CLK, PWM generator 218 generates PWM1 as a modulation of at least two signals. CLK is generated according to any suitable circuit and according to any suitable process, the scope of which is not limited herein. Figure 2As described in , in at least some embodiments, PWM1 is a jitter clock signal, and COMP is a jitter compensation signal. In one example, the PWM generator 218 receives CLK and divides the frequency of CLK to generate a divided clock signal. In at least one embodiment, the PWM generator 218 generates a triangular ramp signal or a signal having any other suitable profile based on the divided clock signal. In some examples, the PWM generator 218 generates another triangular ramp signal or a signal having any other suitable profile based on CLK or based on a second divided clock signal. In other examples, the PWM generator 218 generates a PRSS signal, for example, output by a register (such as a linear feedback shift register (LFSR)). The PWM generator 218 then adds the generated signals (e.g., ramp signal+ramp signal, ramp signal+PRSS signal, etc.) to generate a DRSS signal. In some examples, the DRSS signal is output by the PWM generator 218 as COMP. The PWM generator 218 further generates PWM1 according to the DRSS signal, for example, fine-tuning an oscillator (not shown) that generates PWM1 according to the DRSS signal.

[0024] Now turn to Figure 3 , showing a schematic diagram of an illustrative PWM generator 300. In at least some instances, the PWM generator 300 is suitable for implementation in any device or system that receives a CLK and generates a jittered PWM signal. For example, the PWM generator 300 is suitable for implementation in some SMPS architectures, such as being implemented as the PWM generator 218 in the SMPS 104 of the present disclosure. In other instances, the PWM generator 300 is suitable for implementation in other systems that generate PWM signals based on the CLK but are not SMPSs. For example, in a device that includes an input pin for providing a clock signal (such as a clock synchronization or synchronization pin or input), the PWM generator 300 is suitable for coupling at an output terminal to the input pin for providing a PWM signal. In addition, at least some of the signals present in the PWM generator 300 are implemented in Figure 4 Therefore, by looking at Figure 4 The signal described in Figure 3 An understanding of the operation of the PWM generator 300 is illustrated in the schematic diagram. Figure 4 The signals described in correspond in name to signals described elsewhere herein with respect to generation and function.

[0025] In at least one example, the PWM generator 300 includes a clock divider 302, a ramp generator 304, a register 306, an adder 308, and an oscillator 310. In at least some examples, the register 306 is a linear feedback shift register that is clocked by CLK and has a plurality of output taps that each outputs one digital data bit. In at least some examples, the register 306 is not included in the PWM generator 300, but is a component of a system that implements the PWM generator 300 and the PWM generator 300 is configured to be coupled to it. In at least one example, the clock divider 302 is configured to receive CLK and generate CLK_DIV. The clock divider 302 is further configured to receive one or more data bits output by the register 306. In at least some examples, which specific data bits of the output register 306 (e.g., which positions in the register 306) are a matter of design choice. In at least some examples, the clock divider 302 generates CLK_DIV by dividing the CLK according to at least some of the data bits received from the register 306. Because clock divider 302 generates CLK_DIV based on the data bits received from register 306, the frequency of CLK_DIV varies as the value of the data bits output by register 306 changes. In this way, the frequency of CLK_DIV varies with the clock cycle.

[0026] The ramp generator 304 is coupled to the clock divider 302 and is configured to receive CLK_DIV. Based on CLK_DIV, the ramp generator 304 generates a ramp signal and outputs a plurality of data bits (e.g., RAMP_BIT0, RAMP_BIT1 ... RAMP_BITX) representing the value of the ramp signal for each clock cycle of CLK_DIV. In at least some instances, the data bits output by the ramp generator 304 include a digital representation of an analog signal (e.g., a digital representation of a triangular waveform). However, in other instances, the ramp generator 304 outputs the ramp signal in an analog format. The adder 308 receives at least some of the data bits output by the ramp generator 304 and the data bits output by the register 306, adds the data bits output by the register 306 to the data bits output by the ramp generator 304 to generate a DRSS signal, and outputs the DRSS signal as a plurality of data bits (DRSS_BIT0, DRSS_BIT1 ... DRSS_BITX). In at least some instances, the data bits (eg, PR_BIT0, PR_BIT1, etc.) output by register 306 include a PRSS signal.

[0027] Oscillator 310 is configured to receive a plurality of data bits output by adder 308. In at least some instances, oscillator 310 generates a PWM signal by charging and discharging a capacitor (not shown). In this way, in at least some instances, the output terminal of oscillator 310 is coupled to an output node of PWM generator 300, or is an output node of PWM generator 300. In at least some instances, oscillator 310 charges the capacitor by providing current to the capacitor via a programmable current source (not shown). The current output by the variable current source is determined according to the plurality of data bits output by adder 308, and thus the charging rate of the capacitor is determined. In this way, a PWM signal is generated according to the plurality of data bits output by adder 308, so that it varies according to the ramp signal generated by ramp generator 304 and the output bit of register 306.

[0028] Temporary turn Figure 5 , showing an illustrative diagram 500 of signal waveforms. Diagram 500 illustrates signal 505, signal 510, and signal 515. In at least one example, signal 505 is generated by Figure 3 The ramp signal generated by the ramp generator 304 is a signal 510 which is generated by Figure 3 The register 306 outputs the PRSS signal, and the signal 515 is Figure 3 310. In at least some instances, signal 515 further indicates the output of oscillator 310, such that signal 515 indicates a switching frequency (f_sw) that will control a power converter that receives the output of oscillator 310. The y-axis of graph 500 represents frequency, and the x-axis of graph 500 represents time. During the time period shown as t1 in graph 500, f_sw remains substantially constant. During this time period, jittering according to the present disclosure is disabled. During the time period shown as t2 in graph 500, jittering is enabled according to the present disclosure, and the value of the switching frequency f_sw during t2 varies within a bandwidth of approximately 0.156 times that of f_sw during t1. In addition, in at least some instances, signal 505 varies in frequency in a bandwidth of f_h, and signal 510 varies in frequency in a bandwidth of f_l, where f_l is less than f_h.

[0029] Back to Figure 3, in at least some examples, the PWM generator 300 includes one or more components (not shown) configured to bypass the adder 308. For example, in some cases, it may be preferred to bypass the adder 308 to characterize, monitor, or otherwise observe the data bits output by the ramp generator 304. In other examples, the components configured to bypass the adder 308 enable the PWM generator 300 to be selectively configured to operate in a DRSS mode or an ARSS mode. For example, in one implementation, a multiplexer is coupled between each output terminal of the register 306 and the adder 308. For example, each multiplexer receives a respective data bit output by the register 306 at a first input terminal, a second input terminal of the multiplexer is coupled to a ground node, and an output terminal of the multiplexer is coupled to the adder 308. Each multiplexer is configured to receive the same selection signal so that the PWM generator 300 can be configured by selecting the second input of each of the multiplexers to bypass the generation of the DRSS signal and instead generate a periodic analog-type waveform, as described above. In another example, the multiplexer is coupled between each output terminal of the ramp generator 304 and the oscillator 310. For example, each multiplexer receives a respective data bit output by the ramp generator 304 at a first input terminal, the second input terminal of the multiplexer is coupled to the corresponding output of the adder 308, and the output terminal of the multiplexer is coupled to the oscillator 310. Each multiplexer is configured to receive the same selection signal so that the PWM generator 300 can be configured by selecting the second input of each of the multiplexers to bypass the generation of the DRSS signal and instead generate a periodic analog-type waveform, as described above.

[0030] In some examples, such as current mode power converters, the slope compensation signal is generated by the controller to compensate for an error signal generated by the controller for controlling the power converter. In such examples, the slope compensation signal is generated based on the same input as the input received by the oscillator 310 (e.g., Figure 3 DRSS_BIT0, DRSS_BIT1...DRSS_BITX, in Figure 2 The slope compensation signal is fine-tuned by adjusting the slope compensation signal (collectively illustrated as signal COMP in FIG. 1 ). In at least some instances, fine-tuning the signal includes modifying and / or generating a value of the signal at a particular point in time based on the value of the signal on which the fine-tuning is based. Fine-tuning the slope compensation signal based on the same input as the input received by the oscillator 310 minimizes the ripple in the output voltage of the power converter. In other instances, such as a voltage mode power converter, the voltage ramp is instead fine-tuned based on the same input as the input received by the oscillator 310, thereby again minimizing the ripple in the output voltage of the power converter.

[0031] Additionally, in at least some instances, although not in Figure 3 304. However, PWM generator 300 includes a second ramp generator and may further include a second clock divider. The second ramp generator and / or the second clock divider together generate a second ramp signal in a manner substantially similar to clock divider 302 and ramp generator 304. In some examples, the output of the second ramp generator has a higher frequency than the output of ramp generator 304. In such examples, the output of the second ramp generator is provided to adder 308 in place of the output of register 306 (e.g., in place of PR_BIT0 and PR_BIT1).

[0032] Now turn to Figure 6 , showing an illustrative diagram 600 of a signal waveform. In at least some instances, diagram 600 illustrates a signal waveform present in Figure 3 Therefore, when describing the diagram 600, reference may be made to the multiple signals in the circuit 300. Figure 3 At least some components and / or signals of FIG. 600 illustrate signal 605, signal 610, and signal 615. In at least one example, signal 605 is generated by Figure 3 The ramp signal generated by the ramp generator 304 is , the signal 610 is another ramp signal, and the signal 615 is Figure 3 600 (e.g., when adder 308 receives signal 605 and signal 610 as inputs, signal 610 is received instead of the PRSS signal). In at least some examples, signal 615 further indicates the output of oscillator 310, such that signal 615 indicates f_sw of the power converter controlled at least in part according to the output of oscillator 310. The y-axis of graph 600 represents frequency, and the x-axis of graph 600 represents time. As illustrated in graph 600, in at least some examples, the bandwidth of signal 605 is greater than the bandwidth of signal 610, and the bandwidth of signal 615 is substantially equal to the bandwidth of signals 605 and 610 added together.

[0033] Now turn to Figure 7 , a flow chart of an illustrative method 700 is shown. In at least some examples, the method 700 is a method of PWM signal generation. In some examples, the frequency of the PWM signal changes with each clock cycle. For example, in at least some embodiments, the PWM signal is generated based on combining multiple spread spectrum schemes or modulated DRSS dithering when generating the PWM signal. In some examples, in Figure 3 The method 700 is implemented in the PWM generator of the PWM generator 300 .

[0034] At operation 705, a clock signal is received. In at least some instances, the clock signal is CLK, as described above. In some instances, the clock signal is the output of an oscillator, a PWM generator, or another circuit capable of generating a clock signal. At operation 710, the clock signal is divided to form a divided-frequency clock signal. In at least some instances, the divided-frequency clock signal is CLK_DIV, as described above. In at least some instances, the clock signal is divided according to the output of the linear feedback shift register. In other instances, the clock signal is divided by any other suitable value. In at least some instances, the value varies with the clock cycle to prevent the divided-frequency clock signal from remaining at the same frequency in multiple consecutive clock cycles.

[0035] At operation 715, a first signal is generated according to a jitter scheme. The first signal is, for example, an analog ramp, or a plurality of data bits representing an analog ramp. In other examples, the first signal is an ARSS signal or a periodic analog waveform, as described above. In yet other examples, the first signal is a PRSS signal. In at least one embodiment, the first signal is generated by a ramp generator. The first signal is generated according to the divided clock signal generated at operation 710, so that the frequency of the first signal changes with the clock period.

[0036] At operation 720, a second signal is generated according to a dithering scheme. The second signal is, for example, an analog ramp, or a plurality of data bits representing an analog ramp. In other examples, the second signal is an ARSS signal or a periodic analog waveform, as described above. In yet other examples, the second signal is a PRSS signal. In some examples, the dithering scheme at operation 720 is the same as the dithering scheme at operation 715. In other examples, the dithering scheme at operation 720 is different from the dithering scheme at operation 715. In at least one embodiment, the second signal is generated, for example, based on one or more bits output by a linear feedback shift register, such that the one or more bits form a PRSS signal.

[0037] At operation 725, the first signal is modulated by or with the second signal. In some instances, the first signal is modulated by the second signal by adding the second signal to the first signal. In some instances, the modulated first signal is a DRSS signal. In at least some instances, modulating the first signal with the second signal combines a dithering scheme of the first signal with a dithering scheme of the second signal. In some instances, combining the dithering scheme of the first signal with the dithering scheme of the second signal results in a greater variation in switching frequency between consecutive clock cycles than alternative methods using a single dithering scheme (e.g., ARSS, PRSS, or analog dithering).

[0038] At operation 730, the oscillator is fine-tuned according to the DRSS signal generated at operation 725 to generate a PWM signal. In at least some instances, fine-tuning the oscillator according to the DRSS signal causes the oscillator to generate a PWM signal having a frequency that changes as the value of the DRSS signal changes. The frequency changes according to the first signal generated at operation 715 and the second signal generated at operation 720. Changing the frequency of the PWM signal according to the first signal and the second signal enables the switch component controlled according to the PWM signal to improve EMI performance within a frequency range where the first signal is optimized and a frequency range where the second signal is optimized. For example, when the first signal is an analog ramp signal, the first signal is optimized for improving EMI performance at low frequencies. Similarly, when the second signal is a PRSS signal, the second signal is optimized for improving EMI performance at high frequencies. Therefore, by modulating the first signal with the second signal at operation 725 and generating a PWM signal according to this modulated signal at operation 730, the PWM signal becomes optimized for improving EMI performance at low and high frequencies.

[0039] At operation 735, the power converter is controlled according to the PWM signal to generate an output voltage from the input voltage. For example, the PWM signal drives a gate terminal of at least one power transistor of the power converter (or drives a gate driver, which in turn drives the gate terminal) to turn the power transistor on and off, thereby enabling or disabling current flowing through the power transistor to generate VOUT.

[0040] Now turn to Figure 8 , showing table 800 of illustrative pseudocode. In at least some examples, the present disclosure may be implemented at least in part via software. For example, Figure 7 At least some operations of method 700 may be performed by programming a processor to perform specific tasks. Table 800 illustrates an example of pseudo code for performing such programming. However, the pseudo code of Table 800 is only one method for programming a processor to perform the functions of the present disclosure, and other methods for achieving the same or similar results are also within the scope of the present disclosure.

[0041] As illustrated in Table 800, the variables clk_frequency, clk_divided_frequency, clk_divided_frequency_2, and pseudorandom are defined. A random number (rand) is generated. Subsequently, a first ramp signal (ramp) is generated and a second ramp signal (ramp_2) is generated. DRSS is then generated by adding ramp to rand (e.g., to modulate ramp according to rand, which is a PRSS signal in some examples) or by adding ramp to ramp_2. Based on the DRSS, the frequency of the clock signal is modified.

[0042] In the foregoing discussion, the terms "include" and "comprise" are used in an open manner and should therefore be interpreted to mean "including but not limited to". The term "coupled" is used throughout this specification. The term may encompass connections, communications, or signal paths that achieve a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B, or in a second instance, device A is coupled to device B via an intervening component C, where the intervening component C does not substantially change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A. A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof. Furthermore, a circuit or device said to include certain components may alternatively be configured to couple to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors), and / or one or more sources (such as voltage and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be configured to couple to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0043] Although certain components are described herein as belonging to a particular process technology (e.g., FET, metal oxide semiconductor FET (MOSFET), n-type, p-type, etc.), these components may be exchanged with components of other process technologies (e.g., replacing FETs and / or MOSFETs with BJTs, replacing n-type with p-type or vice versa, etc.) and the circuits including the replaced components reconfigured to provide desired functionality at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, components illustrated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistor. Furthermore, the use of the phrase "ground voltage potential" in the foregoing discussion is intended to include chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection applicable or suitable for the teachings of the present disclosure. Unless otherwise stated, "about," "substantially," or "substantially" preceding a value means + / - 10% of the stated value.

[0044] The above discussion is intended to illustrate the principles and various examples of the present disclosure. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. It is hoped that the present disclosure will be interpreted as including all such changes and modifications.

Claims

1. A circuit, wherein include: A pulse width modulation generator, configured to generate a pulse width modulation signal, the pulse width modulation generator comprising: A linear feedback shift register LFSR, comprising: A clock input terminal configured to receive a clock signal, The first output terminal, and A second output terminal; A clock divider comprising: a clock input terminal configured to receive the clock signal, a first input terminal coupled to the first output terminal of the LFSR, a second input terminal coupled to the second output terminal of the LFSR, and Output terminals; A ramp generator comprising: an input terminal coupled to the output terminal of the clock divider, and Output terminals; An adder comprising: a first input terminal coupled to the output terminal of the ramp generator, a second input terminal coupled to the first output terminal of the LFSR, and output terminals; and An oscillator comprising: a first input terminal coupled to the output terminal of the adder, and Output terminal.

2. The circuit of claim 1, wherein the LFSR further comprises a third output terminal, and wherein the clock divider further comprises a third input terminal coupled to the third output terminal of the LFSR.

3. The circuit of claim 1 , wherein the ramp generator further comprises a second output terminal, a third output terminal, and a fourth output terminal, and wherein the adder further comprises a third input terminal coupled to the second output terminal of the ramp generator, a fourth input terminal coupled to the third output terminal of the ramp generator, a fifth input terminal coupled to the fourth output terminal of the ramp generator, and a sixth input terminal coupled to the second output terminal of the LFSR.

4. The circuit of claim 3 , wherein the adder further comprises a second output terminal, a third output terminal, and a fourth output terminal, and wherein the oscillator further comprises the second output terminal coupled to the adder. A second input terminal coupled to an output terminal of the adder, a third input terminal coupled to the third output terminal of the adder, and a fourth input terminal coupled to the fourth output terminal of the adder. 5 . The circuit of claim 1 , further comprising a power converter comprising a power transistor having a gate terminal configured to be coupled to the output terminal of the oscillator.

6. The circuit of claim 1 , wherein the clock divider is configured to divide a received clock signal according to a value received by the clock divider from the LFSR as at least one digital data bit, and wherein the ramp generator is configured to generate a ramp signal that varies in frequency between successive cycles of the divided clock and output the ramp signal as a digital value.

7. The circuit of claim 6 , wherein the adder is configured to modulate the ramp signal according to at least one digital data bit received from the LFSR to generate a dual random spread spectrum DRSS signal including a jitter profile of the ramp signal and a jitter profile associated with the at least one digital data bit received from the LFSR.

8. The circuit of claim 7, wherein the oscillator is configured to generate a pulse width modulated signal based on the DRSS signal, wherein the pulse width modulated signal varies in frequency based on the ramp signal and the at least one digital data bit received by the adder from the LFSR.

9. A circuit, wherein include: A pulse width modulation generator, configured to generate a pulse width modulation signal, the pulse width modulation generator comprising: a linear feedback shift register LFSR clocked by the clock signal, the LFSR configured to output a pseudo-random value in a digital data format; a clock divider configured to receive the clock signal and divide the clock signal by the pseudo-random value to generate and output a divided clock signal; a ramp generator configured to receive the divided clock signal, generate a ramp signal according to the divided clock signal, and output the ramp signal in the digital data format; an adder configured to modulate the ramp signal with the pseudo-random value to generate a dual random spread spectrum signal; and An oscillator is configured to receive the dual random spread spectrum signal and generate the pulse width modulation signal according to the dual random spread spectrum signal.

10. The circuit according to claim 9, further comprising a power transistor configured to be controlled by the pulse width modulation signal, wherein a switching action of the power transistor under the control of the pulse width modulation signal generates electromagnetic interference with a smaller peak energy than a pulse width modulation signal generated only according to the ramp signal or only according to the pseudo-random value.

11. The circuit of claim 9, wherein the adder modulates the ramp signal with the pseudo-random value so that a frequency variation of the dual random spread spectrum signal in a single cycle of the clock signal is greater than a frequency variation of the ramp signal during the single cycle of the clock signal.

12. The circuit of claim 11, wherein the adder modulates the ramp signal with the pseudo-random value by adding the pseudo-random value to the ramp signal during each cycle of the clock signal, and wherein the adder outputs the dual random spread spectrum signal in the digital data format.

13. The circuit of claim 9, wherein a frequency of the pulse width modulated signal varies between successive cycles of the clock signal.

14. The circuit of claim 9, wherein the oscillator generates the pulse width modulated signal by programming a current source to charge a capacitor with a current determined at least in part by the dual random spread spectrum signal.

15. A system, wherein include: A pulse width modulation generator is configured to generate a pulse width modulation signal by: generating a first signal having a first jitter profile and a first frequency bandwidth; generating a second signal having a second jitter profile and a second frequency bandwidth greater than the first frequency bandwidth; modulating the second signal with the first signal to generate a dual random spread spectrum signal; as well as The pulse width modulation signal is generated according to the dual random spread spectrum signal.

16. The system of claim 15, wherein the first signal is a pseudo-random spread spectrum signal, and wherein the second signal is a periodic analog type waveform.

17. The system of claim 16, wherein the pulse width modulation generator include: a linear feedback shift register LFSR clocked by a clock signal and configured to output the pseudo-random spread spectrum signal; a clock divider configured to receive the clock signal and divide the clock signal by at least a portion of the pseudo-random spread spectrum signal to generate and output a divided clock signal; a ramp generator configured to receive the divided clock signal and generate the periodic analog waveform according to the divided clock signal; an adder configured to modulate the periodic analog waveform with the pseudo-random spread spectrum signal to generate the dual random spread spectrum signal; as well as An oscillator is configured to receive the dual random spread spectrum signal and generate the pulse width modulation signal according to the dual random spread spectrum signal.

18. The system of claim 17, wherein the dual random spread spectrum signal varies in frequency between successive cycles of the clock signal to a greater extent than the frequency of either the periodic analog-type waveform or the pseudo-random spread spectrum signal.

19. The system of claim 17, wherein the oscillator generates the pulse width modulated signal that varies in frequency between successive cycles of the clock signal by programming a current source to charge a capacitor with a current determined at least in part by the dual random spread spectrum signal.

20. The system of claim 15, wherein the pulse width modulated signal mitigates generation of electromagnetic interference in turning on and off of a power transistor in a high frequency band based on a component of the dual random spread spectrum signal attributable to the first signal and in a low frequency band based on a component of the dual random spread spectrum signal attributable to the second signal.

21. The system of claim 15, wherein the first signal is a periodic analog-type waveform, and wherein the second signal is a pseudo-random spread spectrum signal.

22. The system of claim 15, wherein the first signal is a periodic analog type waveform, and wherein the second signal is a second periodic analog type waveform.

23. The system of claim 15, wherein the first signal is a triangular ramp signal at a first frequency, and wherein the second signal is a triangular ramp signal at a second frequency.

24. The system of claim 15, further comprising: include: load; and A switch mode power supply is coupled to the load and the pulse width modulation generator, wherein the switch mode power supply includes a power transistor, and wherein the power transistor is switched on and off based at least in part on the pulse width modulation signal to generate an output voltage provided to the load.

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