Timing error detection and correction circuit

Abstract

This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register timed by a system clock and a second register. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. The timing correction circuitry coupled to the error detection circuitry outputs the system clock derived from the delayed reference clock.

Description

Technical Field

[0001] This disclosure relates to a timing error detection and correction circuit for an integrated circuit and a method for designing an integrated circuit including the timing error detection and correction circuit. Background Technology

[0002] Integrated circuits (ICs) that implement digital designs are designed to operate at specified frequencies under a range of power, voltage, and processing conditions. Timing error correction and detection schemes can be used to improve the robustness of such digital designs.

[0003] Examples of such systems use so-called Razor flip-flops (D. Ernst et al., "Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation," IEEE Micro, Vol. 24, No. 6, December 2004, pp. 10-20). Razor flip-flops utilize dynamic detection and correction of speed path faults in digital design. Razor flip-flops account for process variations, thus eliminating the need for unused margins. The flip-flops are augmented with an additional shadow latch using a delayed clock. If a timing violation exists in the master flip-flop, the shadow flip-flop will contain a different value after the clock edge of the delayed clock, which can be used to flag the error and / or potentially correct it. This concept is called double sampling. Razor has a data path metastability problem if a set-or-hold violation exists. Razor flip-flops also have relatively short delay paths and do not distinguish between delayed arrival of data and fast arrival of correct data. Therefore, Razor triggers require additional buffers for extra hold-up to ensure that only delayed arrivals are detected.

[0004] Another timing error detection and correction system is described in "Energy-Efficient and Metastability-Immune Timing-Error Detection and Recovery Circuits for Dynamic Variation Tolerance," IEEE International Conference on Integrated Circuit Design and Technology, Austin, TX, USA, June 2008, pp. 155-158. This circuit can detect timing errors in a manner similar to Razor, but it uses pulse latches and switching detectors to reduce area / energy overhead. Summary of the Invention

[0005] In a first aspect, a timing error detection and correction circuit for an integrated circuit including a data path is provided, the data path including at least one logic gate and disposed between the output of a first flip-flop and the input of a second flip-flop, the timing error detection and correction circuit comprising: a clock unit configured to receive a reference clock and provide a delayed reference clock; a transition detector coupled to a node on the data path and configured to detect a data value transition at the node; an error detection circuit coupled to the transition detector and the clock unit and configured to detect an error in response to detecting a data value transition during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock; and a timing correction circuit coupled to the error detection circuit and configured to output a system clock derived from the delayed reference clock and provide the system clock to the first flip-flop and the second flip-flop, wherein the timing correction circuit is further configured to adjust the system clock in response to detecting an error.

[0006] In some embodiments, the circuit further includes another transition detector coupled to another node on the data path and configured to detect signal transitions at the other node; wherein the error detection circuit is coupled to the other transition detector and is further configured to detect an error in response to a signal transition detected by at least one of the transition detectors, and the other transition detector, during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock.

[0007] In some embodiments, the data path is arranged between a first set of triggers including the first trigger node and a second set of triggers including the second trigger node, wherein the node and the other node have a path delay to at least one of the second set of triggers of less than 20% of a reference clock cycle.

[0008] In some embodiments, the clock unit includes: a delay unit having an input coupled to a reference clock input and an output coupled to a delayed reference clock output; and a logic circuit element having a first input coupled to the reference clock input and a second input coupled to the delayed reference clock output, and configured to generate a signal for enabling the error detection circuit when the reference clock and the delayed reference clock are different.

[0009] In some embodiments, the logic circuit element is configured to generate an enable signal when the reference clock is logic high and the delayed reference clock is logic low.

[0010] In some embodiments, the logic circuit elements implement the inversion of the delayed reference clock and the logical AND of the reference clock.

[0011] In some embodiments, the error detection circuit includes a dynamic logic circuit having an input coupled to the output of the transition detection circuit and an enable input coupled to the output of the logic circuit element.

[0012] In some embodiments, the dynamic logic circuit includes another input coupled to the output of another conversion detection circuit, and wherein the dynamic logic circuit implements a logic OR between the output of the conversion detection circuit and the output of the other conversion detection circuit.

[0013] In some embodiments, the transition detector includes: a transition detector input coupled to the input of a delay unit and a first input of an EXOR gate; the output of the delay unit coupled to a second input of the EXOR gate; and the output of the EXOR gate coupled to the transition detector output.

[0014] In some embodiments, the timing correction circuit further includes a clock gating circuit having an error detection input coupled to the output of the error detection circuit, a clock input coupled to the clock unit output and the system clock output, wherein the clock gating circuit is configured to couple the system clock output to the clock input when no error is detected and to disconnect the system clock output from the clock input when an error is detected.

[0015] In some embodiments, the timing correction circuit further includes a clock extension circuit having an error detection input coupled to the output of the error detection circuit, a clock input coupled to the clock unit output and the system clock output, wherein the clock gating circuit is configured to couple the system clock output to the clock input when no error is detected and to couple the system clock output to the time-shifted clock input when an error is detected.

[0016] In some embodiments, the clock extension circuit includes: a clock phase generator having an input coupled to the clock input and a plurality of outputs, and configured to generate a plurality of phase outputs of a clock received on the clock input; a clock switching circuit having a plurality of inputs, each input coupled to a corresponding output of the clock phase generator; and a clock switching controller having an input coupled to an output of an error detection circuit and a controller output coupled to a control input of the clock switching circuit; and wherein the clock switching controller is configured to control the clock switching circuit to couple one of the outputs to the system clock output based on a signal received on the error detection input.

[0017] In some embodiments, the clock extension circuit includes: a multiplexer having a first input coupled to the clock input, a second input, a control input coupled to the error detection input, and an output coupled to the system clock output; and another programmable delay having an input coupled to the clock input and an output coupled to the second input of the multiplexer; wherein the multiplexer is configured to couple the second input to the output in response to an error detection and to couple the first input to the output in response to no error detection.

[0018] In some embodiments, the timing correction circuit includes at least one of a power supply adjustment circuit and a body bias circuit adjustment, wherein the timing correction circuit is configured to adjust at least one of the power supply and the body bias in response to detecting an error.

[0019] In some embodiments, timing error detection and correction circuitry may be included in an integrated circuit including a data path comprising at least one logic gate, the data path being arranged between a first set of flip-flops including a first flip-flop and a second set of flip-flops including a second flip-flop.

[0020] In a second aspect, a method for designing an integrated circuit is provided, the integrated circuit comprising: a clock unit configured to receive a reference clock and provide a delayed reference clock; a data path including at least one logic gate, the data path being disposed between the output of a first flip-flop and the input of a second flip-flop; a plurality of transition detectors coupled to corresponding nodes on the data path and configured to detect data value transitions at the corresponding nodes; an error detection circuit coupled to the transition detectors and the clock unit and configured to detect an error in response to detecting a data value transition during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock; and a timing correction circuit coupled to the error detection circuit and configured to output a system clock derived from the delayed reference clock and provide the system clock to the first flip-flop and the second flip-flop, wherein the timing correction circuit is further configured to adjust the system clock in response to detecting an error, the method comprising: placing and routing the designed logic units; identifying units corresponding to data path nodes on a critical timing path; placing the plurality of transition detectors; identifying a cluster of transition detectors; placing circuit elements of the error detectors according to the cluster; and connecting the transition detectors to the data path nodes and the error detectors.

[0021] In a third aspect, an integrated circuit is provided, the integrated circuit comprising: a data path disposed between the output of a first set of flip-flops and the input of a second set of flip-flops; and a timing error detection and correction circuit, the timing error detection and correction circuit comprising: a clock unit configured to receive a reference clock and provide a delayed reference clock; a plurality of transition detectors, each transition detector coupled to a corresponding node on the data path and configured to detect a data value transition; an error detection circuit coupled to the transition detectors and the clock unit and configured to detect an error in response to one or more of the plurality of transition detectors detecting a data value transition during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock; and a timing correction circuit coupled to the error detection circuit and configured to output a system clock derived from the delayed reference clock and provide the system clock to the first and second flip-flops, wherein the timing correction circuit is further configured to adjust the system clock in response to detecting an error.

[0022] In some embodiments, the respective data path node has a path delay to at least one of the second set of triggers that is less than 20% of the reference clock cycle.

[0023] In some embodiments, the time interval between the transition of the reference clock and the corresponding transition of the delayed reference clock is the time interval between the rising edge of the reference clock and the next rising edge of the delayed reference clock.

[0024] In some embodiments, the time interval between the transition of the reference clock and the corresponding transition of the delayed reference clock is the time interval between the falling edge of the reference clock and the next falling edge of the delayed reference clock. Attached Figure Description

[0025] In the accompanying drawings and description, the same reference numerals denote the same features. Embodiments will now be described in detail only by way of examples shown in the accompanying drawings, in which:

[0026] Figure 1 An integrated circuit including timing error detection and correction circuitry is shown according to an embodiment.

[0027] Figure 2 An integrated circuit including timing error detection and correction circuitry is shown according to an embodiment.

[0028] Figure 3A A timing error detection and correction circuit for an integrated circuit according to an embodiment is shown.

[0029] Figure 3B Show Figure 3A Example waveforms of a timing error detection and correction circuit.

[0030] Figure 4A An example implementation of the conversion detection circuit is shown.

[0031] Figure 4B Show Figure 4A Example timing waveform of the conversion detection circuit.

[0032] Figure 5 An example implementation of a dynamic OR gate is shown.

[0033] Figure 6 An example programmable delay line is shown.

[0034] Figure 7 Examples of timing diagrams showing different timing correction strategies are shown.

[0035] Figure 8A An example waveform demonstrating timing correction behavior is shown.

[0036] Figure 8B Example behavior of a timing waveform error detection and correction circuit according to one or more embodiments is shown.

[0037] Figure 9 An example clock-gated circuit is shown.

[0038] Figure 10 A timing error detection and correction circuit according to an embodiment is shown.

[0039] Figure 11 An integrated circuit including timing error detection and correction circuitry is shown according to an embodiment.

[0040] Figure 12A Show Figure 11 The multiphase clock unit of the timing error detection and correction circuit.

[0041] Figure 12B Show Figure 12A Example waveform of a multiphase clock unit.

[0042] Figure 13 A method for designing an integrated circuit including timing error detection and correction circuitry according to an embodiment is shown.

[0043] Figure 14 An example plot showing the most critical probability density function (PDF) for a 50 ns clock cycle and a typical (TT) process-voltage-temperature (PVT) angle.

[0044] Figure 15 The diagram shows the relationship between the number of endpoints and cells at clock and slow PVT angles for a timing window at 12% of the clock cycle.

[0045] Figure 16A An example of a planar-level timing detection location of an integrated circuit including timing error detection and correction circuitry according to an embodiment is shown.

[0046] Figure 16B Show Figure 16A The plan view of the integrated circuit shown illustrates the dynamic OR gate location and timing detector connection. Detailed Implementation

[0047] Figure 1 An integrated circuit 100 including timing error detection and correction circuitry (EDaC) according to an embodiment is shown. The integrated circuit 100 includes a first flip-flop 102, a second flip-flop 104, and a data path 106, the data path 106 including one or more logic gates 108 disposed between the output of the first flip-flop 102 and the input of the second flip-flop 104. The first flip-flop 102 and the second flip-flop 104 are powered by a system clock (CLK) provided from the system clock output 144 of the timing corrector 118. sys )supply.

[0048] Integrated circuit 100 also includes a transition detector (TD) 110, which has an input coupled to a data path node 112 in the data path 106 and a transition detector output 124 connected to an input of an error detector 122. As used herein, the term data path can be considered to refer to a system of combinational logic circuits arranged between sequential logic circuits, such as flip-flops or latches.

[0049] A transition detector 110 is shown in integrated circuit 100, but in other examples, multiple transition detectors connected to corresponding data path nodes may be used. The error detector output 126 of error detector 122 may be connected to a control input of timing corrector 118. Clock unit 120 may include an enable generator 114 and a delay module 116. Clock reference input 130 may be connected to an input of delay module 116 and an input of enable generator 114. The delayed clock output 146 of delay module 116 may be connected to an input of timing corrector 118 and a second input of enable generator 114. Enable generator output 134 may be connected to an input of error detector 122. If needed, system clock output 144 may be connected to clock reference input 130 via delay unit 128.

[0050] During operation, the reference clock CLK ref A reference clock input 130 can be provided to clock unit 120. Delay module 116 can delay the reference clock signal and output a delayed version of the reference clock, CLK. del Provides a delayed clock output of 146. Delayed clock CLK del It can be received by timing corrector 118, which can provide a delay clock CLK. del Exported system clock CLK sys CLK can be used without the need for periodic calibration. sys Compatible with CLK del same.

[0051] Clock unit 120 can generate an enable signal on enable signal output 134 to enable error detector 122. The enable signal may have a value corresponding to reference CLK. ref Clock conversion and delay clock CLK del The pulse width of the enable signal corresponds to the delay of delay module 116 and defines an evaluation period close to the end of each clock cycle, just before the second flip-flop 104 captures data. The enable pulse should be as short as possible but sufficient to allow the transition pulse to propagate through the error detector. In some examples, the delay element can be tuned or programmable to adjust the amount of delay.

[0052] During normal operation of integrated circuit 100, based on the system clock CLKsys The edge-or transition of the system clock CLK is used to time the data received on the data input 132 of the first flip-flop 102. sys The timing corrector 118 provides the time T=0 at the beginning of the clock cycle, indicated by the dashed line 140. Any resulting output logic transitions can be propagated to the second flip-flop 104 via data path 106. This can be achieved at the system clock CLK. sys The subsequent transition captures the result of the logical operation on the data at the data input of the second trigger 104, and the subsequent transition corresponds to the time T shown by the dashed line 138. clk The clock cycle ends at this point. The transition detector 110 is connected between the first flip-flop 102 and the second flip-flop 104 at approximately time T. clk The timing window T at the end of the clock cycle. win A data path node 112 has a certain path delay. The selection of node 112 can be determined during the physical design phase of the integrated circuit, for example, based on static timing analysis of the path delay in the data path. Whenever a transition occurs at data path node 112, transition detector 110 can output a pulse. The transition can correspond to a logic 0 to logic 1 data transition, or a logic 1 to logic 0 data transition.

[0053] If the transition detector 110 outputs a transition during the active period of the enable signal corresponding to the evaluation period, this transition is captured by the error detector 122 and considered a delayed timing transition that causes a timing error. A timing error can cause data errors because the second flip-flop 104 may be causing the system clock CLK to fail. sys The next transformation T = T clk The system clock fails to capture the correct data value. Error detector 122 can output an error detection signal to timing corrector 118. In response, timing corrector can adjust the system clock CLKsys, for example, by clock gating or clock stretching, to delay the system clock transition and thus correct the timing error.

[0054] The inventors of this disclosure have learned that by detecting transitions in a timing window near the end of a clock cycle (e.g., within the last 20% of a clock cycle), an integrated circuit 100 including an error detection and correction (EDaC) system can enable an implemented digital design to operate at a superior level of power performance compared to designs with worst-case design margins.

[0055] Integrated circuit 100 can reduce the energy per operation at a constant rate. Compared to conventional designs with design margins, the proposed solution allows for further reduction of the digital supply voltage without compromising the operating frequency until the point of first failure. For example low-voltage designs under typical process and temperature conditions, nearly 30% energy savings have been observed.

[0056] Alternatively, the operating speed of integrated circuit 100 can be increased to a frequency higher than that of conventional designs with design margins. In some examples, integrated circuit 100 can operate with a frequency increase of up to 20% observed in example designs under typical PVT conditions. In other examples, the frequency can be approximately 100% to 200%, depending on the original design margin.

[0057] Dynamic power performance management is typically employed in many ICs. In most cases, a replica circuit, such as a ring oscillator or delay line, is used to obtain reference silicon speed performance for a given IC sample used for error detection, which may have a delay mismatch relative to the actual circuit.

[0058] In contrast, integrated circuit 100 does not require any replication circuitry; instead, one or more switching detectors monitor the actual critical path. Therefore, there is no mismatch between the performance of the replication circuitry and the actual critical path. This results in a reduced timing margin, which can be used to achieve lower power and higher speed.

[0059] Some error detection and correction methods require double sampling, which imposes a hold constraint equal to its timing window. Fixing this hold constraint requires hold-up, resulting in power overhead and potential area overhead. This reduces the maximum possible power savings. In practice, the power consumption of an integrated circuit with such an EDaC system using double sampling can be comparable to or higher than that of an integrated circuit without EDaC.

[0060] In contrast, because critical nodes are monitored near the end of the timing window, the error detection and correction circuitry in integrated circuit 100 does not require additional buffering to avoid hold-up violations, which reduces power consumption.

[0061] Furthermore, without additional hold-up overhead, the timing error detection window can be significantly larger compared to solutions based on existing double sampling techniques. This is because the detection range is broader, and the system does not depend on the propagation of critical activities toward endpoints, as the system can monitor all critical activities using numerous transition detectors. This makes the proposed EDaC tuning less activity-dependent, thereby improving the overall robustness of detection. The integrated circuit 100 can monitor all transitions within a predetermined timing error detection window, not just transitions at path endpoints. Therefore, the integrated circuit 100 can also have a relatively large timing error detection window.

[0062] Figure 2An integrated circuit 200 including timing error detection and correction circuitry (EDaC) according to an embodiment is shown. The integrated circuit 200 includes: a first set of flip-flops 202, 202'; a second set of flip-flops including flip-flop 204; and a data path 206 including one or more logic gates 208 disposed between the outputs of the first flip-flops 202, 202' and the input of the second flip-flop 204. The first flip-flops 202, 202' and the second flip-flop 204 are supplied with a system clock (CLKsys) provided from the system clock output 244 of a timing corrector (not shown).

[0063] Integrated circuit 200 also includes transition detectors 210a-c, each having a corresponding input coupled to a corresponding data path circuit node 212a-b in data path 206 and transition detector outputs 224a-b connected to a corresponding input of error detector 222. Error detection output 226 can be connected to a control input of a timing corrector (not shown). Enable input 234 of the error detector can be connected to an evaluation signal generator (not shown). The error detector may include one or more dynamic OR gates 223, with each input connected to a corresponding transition detector output 224a-b.

[0064] During normal operation of integrated circuit 200, based on the system clock CLK sys The system clock CLK is used to time the data received on the corresponding data input 232 of the first flip-flops 202 and 202'. sys The data is provided at time T=0, indicated by dashed line 240, at the start of the clock cycle. The captured data is propagated through data path 206 and can then be accessed at the data input of the second trigger 204 at time T, corresponding to time T indicated by dashed line 238. clk The system clock CLK at the end of the clock cycle. sys The transition detectors capture the results of the logical operations performed on the data by logic gate 208. Each transition detector 210a-c is connected between the first flip-flops 202, 202' and the second flip-flop 204 at an approach time T. clk The timing window T at the end of the clock cycle. win Data path nodes 212a-c contain a specific path delay. The system clock used to time flip-flops 202, 202', and 204 is derived from a delayed version of a reference clock. The selection of nodes 212a-d can be determined during the physical design phase of the integrated circuit, for example, based on static timing analysis of the path delay in the data path.

[0065] Transition detectors 210a-c monitor nodes 212a-d on the final gates of the critical path. The total propagation delay of the monitored gates determines the error detection window (T). win This is due to the ample processing time T.clk Starts at the worst-case input timing, which also includes the least critical gate (T). clk -T win Timing errors are detected only when the transition detectors 210a-c are active near the end of the clock cycle within the evaluation time determined by the enable signal provided to the error detector's enable input. This enable signal is generated from the difference between the transition of the reference clock and the corresponding transition of the delayed version of the reference clock. The transition detectors 210a-c may output a pulse whenever a transition corresponding to a logic 0 to logic 1 (or logic 1 to logic 0) occurs on the corresponding data path node 212a-c.

[0066] In response to an error detection, a timing corrector (not shown) can adjust the system clock CLK, for example, through clock gating or clock stretching. sys This delays the system clock transition and thus corrects timing errors.

[0067] Figure 3A A timing error detection and correction system 300 for an integrated circuit according to an embodiment is shown. The timing error detection and correction system 300 includes an error detector 322 having three levels of dynamic OR gates 323a-c, each OR gate 323a-c having a plurality of inputs 320a_0 to 320s_n, 320b_0 to 320b_n, and 320c_0 to 320c_n. Other example error detectors may have fewer or more levels. The timing error detection and correction system 300 includes a plurality of transition detectors 310_0 to 310_n having corresponding inputs coupled to corresponding data path nodes 324_0 to 324_n in a data path (not shown). The output of each transition detector can be connected to the corresponding OR gate inputs 320a_0 to 320a_n of the first-level dynamic OR gate 323a. The output of the first-level dynamic OR gate 323a can be connected to the first input 320b_0 of the second-level dynamic OR gate 320b. The remaining inputs of the second-stage dynamic OR gate 320B can be connected to another transition detector (not shown) or another first-stage dynamic OR gate (not shown). The output of the second-stage dynamic OR gate 323b can be connected to the first input 320c_0 of the third-stage dynamic OR gate 323c. The remaining inputs of the third-stage dynamic OR gate 323c can be connected to another transition detector (not shown) or the outputs of another first-stage and second-stage dynamic OR gates. The output of the third-stage dynamic OR gate 323c can be connected to the error detector output 326. Dynamic OR gates 323a, 323b, and 323c may have corresponding enable inputs 316a, 316b, and 316c. Enable inputs 316a-c can be connected to the evaluation signal output 312 of the clock unit 304 via corresponding buffers 314a, 314b, and 314c.

[0068] Clock unit 304 may include programmable delay unit 306 and, for example, an AND gate 308 having one non-inverting input and one inverting input. Reference clock input 302 may be connected to the non-inverting input of AND gate 308. The output of programmable delay unit 306 may be connected to delayed clock output 330 and the inverting input of AND gate 308.

[0069] The error detector output 326 of the error detector 322 can be connected to the control input of the timing corrector 318. The delay clock output 330 can be connected to the input of the timing corrector 318.

[0070] During operation, the reference clock CLK ref A reference clock input 302 can be provided to clock unit 304. Programmable delay unit 306 can delay the reference clock signal and output a delayed version of the reference clock, CLK. del Provided to the delayed clock output 330. Delayed clock CLK del It can be received by timing corrector 318, which can provide a delay clock CLK. del Exported system clock CLK sys CLK can be used without the need for periodic calibration. sys Compatible with CLK del same.

[0071] Clock unit 304 can generate an enable signal on evaluation signal output 312 to enable error detector 322. The enable signal may have a value corresponding to reference CLK. ref Clock conversion and delay clock CLK del The pulse width of the enable signal corresponds to the delay of the programmable delay unit 306. The enable signal pulse controls the error detector 322 to take a snapshot of the outputs of all transition detectors. If any transition detector output is active during the enable pulse, this is considered a timing error and the error detector output indicates an error condition.

[0072] If a timing error is detected, the error condition signal can be latched into the delayed clock CLK. del On the next conversion. The timing corrector 318 can gate the system clock output 328, causing the clock to be delayed by one cycle. This prevents timing errors from being caught by the receive trigger, thus acting as a single-cycle correction mechanism. For simplified and efficient design integration, the dynamic OR gate can be designed to fit into the digital standard cell template.

[0073] exist Figure 3A Example timing waveform 350 shows the operation of the timing error detection and correction system 300. CLK IN358 is from which the evaluation signal 362 (Edyn pulse) and the delayed clock 360 (CLK) of the OR gate are derived. DEL The input reference clock. System clock 372 (CLK) SYS ) and CLK DEL Synchronization. The width of the evaluation signal Edyn pulse 362 is equal to CLK as shown in regions 354 and 356. DEL and CLK IN The time difference between the rising edges, and corresponding to the time at which a possible timing error is evaluated, exactly during CLK. DEL The time before the next transition. When transition detectors 324_0 to 324_n detect a data switch while Edyn is high, an error signal 370 is generated by the error detector 322. This means that at least one of the transition detectors 324_0 to 324_n is exactly at CLK. DEL The activity is captured before the clock edge. An example output (TDout) is shown by waveform 368. This error condition is shown in time region 354, whereas in region 356, no transition was detected during the evaluation snapshot and therefore no error signal was output. The system clock 372 is gated after error detection by timing corrector 318. The pulse width 352 of the transition detector output pulse should be just large enough to be captured by the OR tree of error detector 322 if it occurs during the evaluation pulse Edyn. However, this does not mean that the transition detector output pulse should be greater than or equal to the Edyn pulse itself. A relatively short output pulse with a pulse width less than the propagation delay of the OR tree can still travel through the OR tree; therefore, the precise minimum width of this pulse depends on the actual implementation of the OR tree.

[0074] Figure 4A An example of a transition detector 400, which can be used as a transition detector in any of the error detectors described herein, is shown. The transition detector 400 includes a series arrangement of a buffer 404 between its input and a first input of an XOR gate 406. The second input of the XOR gate 406 is directly connected to input 402. The output of the XOR gate 406 is connected to the output of the transition detector 400.

[0075] In operation, input 402 is connected to a monitored data path circuit node (not shown). Output 408 provides a pulse in response to a data switch at the monitored circuit node (i.e., a data transition between logic 0 and logic 1, or a data transition between logic 1 and logic 0). Figure 4B The relevant signal waveform 410 is shown in Figure 412. Waveform 412 shows the data conversion and waveform at inputs 2-3. The width of pulse 414 is equal to the propagation delay of buffer 404 present in one of the input lines of the XOR gate.

[0076] Figure 5 A typical dynamic OR gate 420, which may be included in one or more detector circuits described herein, is illustrated. The dynamic OR gate 420 includes a parallel arrangement of a pre-charge PMOS transistor MP1 and a hold PMOS transistor MP2 between a power node 432 and a circuit node 430. The input of the pre-charge PMOS transistor MP1 is connected to an enable input 424. The input of an inverter INV1 may be connected to circuit node 430. The output of the inverter INV1 may be connected to the dynamic OR gate output 434. The OR output 434 may also be connected to the input of the hold transistor MP2. The dynamic OR gate has a parallel arrangement of NMOS transistors MN1, MN2, and MN11, which has a drain connection to circuit node 430 and a source connection to circuit node 428. The gate of each transistor MN1, MN2, and MN11 is connected to a corresponding input of dynamic OR gates 426_0, 426_1, and 426_10. A discharge transistor MN12 has a source connection to ground rail 422 and a drain connection to circuit node 428. The gate of the discharge transistor MN12 can be connected to the enable input 424. In operation, when used in an error detector, the dynamic OR gate can output logic 1 during the evaluation phase if either input is logic 1. In other examples, the dynamic OR gate may have fewer or more inputs than the 11 inputs shown in the dynamic OR gate 420.

[0077] Figure 6 An example of a programmable delay unit 450 is shown. The programmable delay unit input 452 can be connected to the first AND gate AI1 in a series arrangement of AND gates AI1, AI2, and AI16. One input of each of the first series AND gates is connected to the corresponding input of the NAND gates ND1, ND2, and ND16. The second input of each of the t AND gates AI1, AI2 is connected to... , , The output of a 1-bit programmable register (not shown) is inverted. The second input of each NAND gate is connected to the corresponding output of a 1-bit programmable register (not shown), denoted as S0, S1, S15. The output of each NAND gate is connected to the corresponding input of a second cascaded arrangement of AND gates AO16, AO22, AO11. The second input of AND gate AO16 is connected to logic 1. The output of AND gate AO1 is connected to the output 454 of a programmable delay unit. In operation, the delay between input 452 and output 454 can be determined by setting which value in the programmable registers S0...S15.

[0078] For example, if S0 is set to logic 1 ( If S0 is logic 0 and S1 is logic 1, then the delay from input 452 to output 454 is the delay via ND1 and AO1.

[0079] Figure 7 Waveform 500 is shown, illustrating the operation of a gated clock and an extended clock used for timing error correction in one or more embodiments. The "Error" signal 502 relates to the output of the dynamic OR gate tree of the error detector in the embodiments described herein. A timing error is detected when the "Error" signal 502 is at logic 1. In other examples, it should be understood that logic '0' can indicate an error condition, while logic '1' can indicate an error-free condition. As previously discussed, the "Uncorrected CLK" signal 506 is related to the delayed clock CLK. DEL The same applies. The "error" signal 502 is evaluated based on the time between the assertion reference CLK and the assertion delay clock, i.e., the delay time of the programmable delay line. The "delayed data" signal 504 indicates the switching of the gate monitored by the transition detector. When the switching occurs at the moment the dynamic OR gate is enabled, a timing error is marked by the assertion "error" signal. Waveform 508 shows the clock gating's response to the error signal, which sets CLK... sys The next clock cycle is delayed until the next cycle of the uncorrected clock. Waveform 510 shows the stretchable CLK. sys The extended clock response of the current clock cycle.

[0080] Figure 8A Waveform 550 is shown, and Figure 8B Figure 570 illustrates an example of the behavior of an embodiment of the error detection and correction system. Waveform 550 includes a reference clock 552, a system clock 554, an error detection enable signal 556, an OR operation output 558 of the conversion detector, and a detected error signal 560.

[0081] Go to Figure 8B At time t=0, the system clock frequency of the digital core application is equal to 20 MHz, a slow-corner scenario (SS) based on the process, voltage, and temperature frequencies. In the SS scenario, as expected, a timing error is not flagged. Subsequently, the frequency increases over time. At a given point, a timing error is flagged, indicating that the digital core has reached its critical frequency, i.e., the point of first failure (PoFF). The EDaC system responds to this error by applying clock gating, such as... Figure 8A The signal waveforms are visible, and the signal waveforms correspond to the detected error "Error_in" 558 and the processed error "Error_out" 560.

[0082] Figure 9 An example clock gating circuit 600, which can be used in a timing corrector in one or more embodiments described herein, is shown. The clock gating circuit includes a flip-flop 606 or latch and a gate 610. An enable signal is generated by the input clock clk_in (CLK) on input 602. DEL The timing trigger 606 captures the timer. When the enable signal is high, clk_out(CLK) is executed. SYS )612 Gating is low. When enabled low, clock gating is not active (transparent), i.e., clk_out = clk_in.

[0083] Figure 10 An example error detection and correction system 650 is shown, using clock extension for timing correction and configured as a ring oscillator. The error detection and correction system 650 includes a series arrangement of multiplexers 654, 658, and 660, each configured to select an output from one of a corresponding first series-connected inverter 654a, 656a, 661a and a second series-connected inverter 654b, 656b, and 661b. Each series of inverters may include a different number of inverters. In other examples, a combination of buffers and inverters may be used. The output of multiplexer 660 may be connected to a reference clock input 662 of clock unit 664. Multiplexers 654, 658, and 660 may have corresponding control inputs 653, 657, and 659 to independently select which input to use, thereby allowing adjustment of the ring oscillator's clock frequency.

[0084] Clock unit 664 may include a delay unit 668, which may be a programmable delay unit, and logic circuit elements such as an AND gate 666 having one non-inverting input and one inverting input. A reference clock input 662 may be connected to the non-inverting input of the AND gate 666. The output of delay unit 676 may be connected to a delayed clock output 670 and the inverting input of the AND gate 666. The output of the AND gate 666 is connected to an evaluation signal output 672, which may be connected to an error detector (not shown).

[0085] The delayed clock output 670 can be connected to the input of the timing corrector 674. The timing corrector 674 may include a programmable delay 676 disposed between the delayed clock output 670 and a first input of the timing corrector multiplexer 680. A second input of the timing corrector multiplexer 680 can be directly connected to the delayed clock output 670. The output of the timing corrector multiplexer can be connected to the system clock output 682. The system clock output can also be connected to the inputs of a first series inverter 654a and a second series inverter 654b. This feedback path can cause the error detection and correction system 650 to implement a ring oscillator function. The control input of the timing corrector multiplexer 680 can be connected to the output 656 of an error detector (not shown).

[0086] In operation, the error detection and correction system 650 can generate an enable signal on the enable output 672, the enable signal being used precisely at the delayed clock CLK. del An error detector is enabled during the evaluation cycle prior to clock transition. Detected error signals control the system clock multiplexer 680 of the timing corrector 674 to select the clock system CLK from the delayed path via a programmable delay unit 676. sys This extends the clock cycle. The system clock output is used to time triggers that have data paths as described herein with respect to other embodiments.

[0087] The error detection and correction system 650 implements a ring oscillator to prevent the clock cycle immediately following the corrected (extended) clock cycle from becoming too short, as this could lead to undesirable timing errors. Furthermore, clocking based on the ring oscillator can correct for global PVT variations, while the EDaC system corrects for local variations. In the case of the ring oscillator, the detection window should cover any mismatch between the monitored data path and the ring oscillator.

[0088] Figure 11 An integrated circuit 700 including an error detection and correction system is shown according to one or more embodiments. The error detection and correction system shown in the integrated circuit 700 uses clock extension in conjunction with a multiphase clock.

[0089] Integrated circuit 700 includes registers 702_1, 702_2, 702_3, and 702_4, each including a set of one or more flip-flops, the flip-flops being timed by a system clock. Logic data paths 704_1, 704_2, and 704_3 may be arranged between registers 702_1, 702_2, 702_3, and 702_4. A transition detector 710 may have inputs connected to critical nodes 708 within the respective logic data paths 704_1, 704_2, and 704_3. The transition detector 710 has outputs 712 connected to corresponding inputs of an error detector 714. The output 716 of the error detector 714 may be connected to an input of a clock switching controller 724. An error signal selection 729 output from the clock switching controller 724 may be connected to an input of a multiphase clock unit 722. The generated multiphase enable signal can output a system clock output 720, which is connected to each of the registers 702_1, 702_2, 702_3, and 702_4. The multiphase clock unit 722 may have an enable signal output connected to an error detector 714.

[0090] The master clock generator 728 may have outputs connected to the multiphase clock generator 727. As shown, the multiphase clock generator 727 generates four clock phases on corresponding outputs 726_0 (CLK-0%), 726_1 (CLK2-25%), 726_2 (CLK3-50% phase shift), and 726_3 (CLK4-75% phase shift) connected to the corresponding multiphase enable signal generator inputs.

[0091] Figure 12A An example implementation of a multiphase clock unit 722 is shown. The respective outputs from multiphase clock generators 726_0, 726_1, 726_2, and 726_3 are connected to single-phase clock units 730_0, 730_1, 730_2, and 730_3. Each single-phase clock unit outputs an enable signal for a corresponding clock phase on its respective enable signal outputs 732_0, 732_1, 732_2, and 732_3, and outputs a delayed version of the corresponding clock phase on outputs 734_0, 734_1, 734_2, and 734_3. The delayed clock outputs 734_0, 734_1, 734_2, and 734_3 can be connected to the respective inputs of a system clock multiplexer 738. The output of the system clock multiplexer 738 can be connected to a system clock output 720. Enable signal outputs 732_0, 732_1, 732_2, and 732_3 can be connected to the corresponding inputs of enable signal multiplexer 736. The output of the enable signal multiplexer can be connected to enable signal output 718. The control inputs of enable signal multiplexer 736 and system clock multiplexer 738 can be connected to error signal selector 729.

[0092] Figure 12B An example of the operation 750 of the error detection system in integrated circuit 700 is shown. Initially, a system clock is generated based on a first clock phase, denoted as CLK0. One or more transition detectors in transition detectors 710 can detect transitions within a predetermined time window near the end of the cycle of system clock phase CLK0, which are considered timing errors. After a timing error is detected, an enabled signal generator control selects the next clock phase, in this case CLK1, to correct the error. The system clock then continues to use CLK1 as a reference clock until a subsequent timing error is detected. If a subsequent timing error is detected, CLK2 is used.

[0093] Figure 13 A method for designing an error detection and correction system for an integrated circuit according to embodiment 800 is illustrated. In step 802, the circuit elements of the integrated circuit design are placed and routed. In step 804, key units in the design are selected to identify which part of the design will have a transition detector inserted.

[0094] After selecting the critical unit, the method moves to step 806, where the transition detectors are placed. In step 808, the transition detectors are then clustered to identify which detectors can be connected to which error detector, for example, a dynamic OR gate. In step 810, the dynamic OR gate is placed on the integrated circuit layout. Finally, in step 812, the routing of the transition detectors and error detectors is completed to connect to the relevant data path nodes. Steps 804 and 808 of the critical logic unit selection method are an extension of the digital design flow.

[0095] For the critical unit selection 804, a preferred approach is to use statistical static timing analysis for this purpose. This type of analysis provides the mean and sigma of the path delay under local variations. These values ​​are used to simulate a full-system Monte Carlo (MC) simulation for the critical timing path on different chip samples on the x-axis 822 in nanoseconds, which produces the probability density function (PDF) shown on the y-axis 824.

[0096] Figure 14 An example cell selection of 820 is shown for a design designed for worst-case 50 ns clock operation under typical process conditions. The PDF can be used to infer the applicable timing window (T). WIN This timing window should begin at the desired output rate, for example... Figure 14 The 4σ value is calculated and ends when the PDFs begin to fully overlap. Greater overlap between PDFs indicates less margin for recovery of timing errors per resolution.

[0097] In other examples, the cell selection step 804 can be performed using conventional static timing analysis. Figure 15 Example cell selection 830 is provided, showing the distribution of the number of endpoints / cells 832 for the same design under slow PVT conditions. Time window T WIN In the worst-case clock cycle toward a lower clock cycle (such as...) Figure 15 The critical path begins at 50 ns. The cells that are part of the critical path within this time window are candidates to be monitored with the corresponding Transition Detector (TD). The relevant critical path and cells are indicated by a darker shading 834.

[0098] The input / output of selected units is monitored via TD. However, trade-offs exist regarding recoverable margins, the number of required transition detectors, and the amount of timing errors that the EDaC system needs to resolve. To reduce the overhead of the EDaC system, it is advisable to monitor a subset of the total selected units based on signal propagation statistics in the critical path and / or other redundancy.

[0099] The number of TDs required depends on the amount of critical units that need to be monitored. For a given digital core, this amount can easily involve thousands of units. The TDs monitoring the critical units provide error signals, which are compressed into a single error signal by means of a dynamic OR gate.

[0100] The proposed hierarchical approach limits the number of TDs connected to a single dynamic OR gate in the example error detector. The first-level dynamic OR gate can connect to the next level of dynamic OR gate. This reduces overall wiring overhead and power consumption, allowing error signals from all TDs to be converged into a single error signal for timing error detection and correction purposes.

[0101] There is a trade-off between the number of inputs to a dynamic OR gate, its performance, and the total wire length of the EDaC system. In some embodiments, an error detector may use a 10-input dynamic OR gate, but in other cases, a dynamic OR gate with fewer or more than 10 inputs may be used. The K-means algorithm can be used to determine the placement of the dynamic OR gate while optimizing the minimum bus length. Figure 16A Examples of this type of design 840 are shown at the level of a floor plan of the TD. Figure 16B Examples of this type of design 850 are shown at the level of a floor plan diagram illustrating the TD location and the corresponding dynamic OR gate placement.

[0102] Embodiments of the described timing error correction and detection system can be included in low-power digital designs implemented on integrated circuits that utilize runtime dynamic power performance management. Specifically, battery-powered applications can benefit from this invention. Examples include ear devices, low-power connectivity solutions (e.g., wireless personal audio, IoT devices), low-power (general purpose) microcontrollers, and low-power secure access products such as car keys and building access.

[0103] Furthermore, because EDAC system implementations provide runtime performance indications, EDAC systems can also be used during IC at-speed testing and / or reliability qualification. For at-speed testing, EDAC systems can be used to support the verification of (critical) path performance at the IC sample level. For reliability testing, implementations of EDAC systems can be used to monitor circuit performance degradation during high-temperature operating life (HTOL) testing. This information can be used to reduce overall IC qualification time without affecting accuracy / ppm levels.

[0104] It should be understood that the logical transitions from 0 to 1 described in the detailed embodiments herein may be replaced by transitions from 1 to 0 in other embodiments with different detailed implementations.

[0105] This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register and the input of a second register, both timed by a system clock. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. Timing correction circuitry coupled to the error detection circuitry outputs a system clock derived from the delayed reference clock. The timing correction circuitry is also configured to adjust the system clock in response to the detection of an error.

[0106] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set, which is implemented on a computer or a machine programmed and controlled with said executable instructions. Such instructions are loaded to execute on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor may refer to a single component or multiple components.

[0107] In other examples, the instruction sets / methods illustrated herein, along with their associated data and instructions, are stored in appropriate storage devices, which are implemented as one or more non-transient machine-readable or computer-usable storage media. Such one or more computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture may refer to any single or multiple manufactured components. Non-transient machine-readable or computer-usable media as defined herein do not include signals, but such media are capable of receiving and processing information from signals and / or other transient media.

[0108] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via networks, computers, or data-based devices and / or services. These may include cloud, internet, intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. The following non-exclusive definitions are provided as may be used herein.

[0109] In one example, automating one or more instructions or steps discussed herein. The terms automation or automatic (and similar variations) mean controlling the operation of equipment, systems, and / or processes using computers and / or mechanical / electrical devices without human intervention, observation, effort, and / or decision-making.

[0110] Although the appended claims relate to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalized form thereof explicitly or implicitly disclosed herein, regardless of whether it relates to the same invention claimed in any claim or whether it alleviates any or all of the same technical problems as those alleviated by this invention.

[0111] Features described in the context of a single embodiment may be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination.

[0112] The applicant hereby reminds that new claims may be formulated based on such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0113] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a (a or an)" does not exclude that a plurality of, a single processor or other unit may perform the functions of the several components described in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0114] Appendix Label Table

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Claims

1. A timing error detection and correction circuit for an integrated circuit including a data path, characterized in that, The data path includes at least one logic gate and is arranged between the output of the first flip-flop and the input of the second flip-flop. The timing error detection and correction circuit includes: A clock unit configured to receive a reference clock and provide a delayed reference clock; A transformation detector, which is coupled to a node on the data path and configured to detect data value transformations on the node; An error detection circuit, coupled to the transition detector and the clock unit, is configured to detect an error in response to a data value transition detected during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock; a timing correction circuit, coupled to the error detection circuit, is configured to output a system clock derived from the delayed reference clock and provide the system clock to the first flip-flop and the second flip-flop, wherein the timing correction circuit is further configured to adjust the system clock in response to the detection of an error; Another transition detector, coupled to another node on the data path and configured to detect signal transitions on the other node; wherein the error detection circuit is coupled to the other transition detector and further configured to detect an error in response to a signal transition detected by at least one of the transition detectors, and the other transition detector, during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock; The clock unit includes: a delay module having an input coupled to a reference clock input and an output coupled to a delayed reference clock output; and a logic circuit element having a first input coupled to the reference clock input and a second input coupled to the delayed reference clock output, and configured to generate a signal for enabling the error detection circuit when the reference clock and the delayed reference clock are different; Furthermore, each of the transition detectors and the other transition detector includes: a transition detector input coupled to the input of a delay module and a first input of an EXOR gate; the output of the delay module coupled to a second input of an EXOR gate; and the output of the EXOR gate coupled to the output of the transition detector.

2. The circuit according to claim 1, characterized in that, The data path is arranged between a first set of flip-flops including the first flip-flop and a second set of flip-flops including the second flip-flop, wherein the node and the other node have a path delay to at least one of the second set of flip-flops of less than 20% of a reference clock cycle.

3. The circuit according to claim 1 or 2, characterized in that, The logic circuit element is configured to generate an enable signal when the reference clock is logic high and the delayed reference clock is logic low.

4. The circuit according to claim 1 or 2, characterized in that, The error detection circuit includes a dynamic logic circuit having an input coupled to the output of the conversion detection circuit and an enable input coupled to the output of the logic circuit element.

5. The circuit according to claim 4, characterized in that, The dynamic logic circuit includes another input coupled to the output of another conversion detection circuit, and wherein the dynamic logic circuit implements a logic OR between the output of the conversion detection circuit and the output of the other conversion detection circuit.

6. An integrated circuit, characterized in that, The circuit includes the timing error detection and correction circuit as described in any of the preceding claims and a data path including at least one logic gate, the data path being arranged between a first set of flip-flops including the first flip-flop and a second set of flip-flops including the second flip-flop.

7. A method for designing integrated circuits, characterized in that, The integrated circuit includes: A clock unit configured to receive a reference clock and provide a delayed reference clock; A data path, comprising at least one logic gate, is arranged between the output of a first flip-flop and the input of a second flip-flop; Multiple transformation detectors are coupled to corresponding nodes on the data path and configured to detect data value transformations on the corresponding nodes; An error detection circuit, coupled to the transition detector and the clock unit, is configured to detect an error in response to a data value transition detected during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock; A timing correction circuit, coupled to the error detection circuit, is configured to output a system clock derived from the delay reference clock and provide the system clock to the first and second flip-flops, wherein the timing correction circuit is further configured to adjust the system clock in response to detecting an error. Another transition detector, coupled to another node on the data path and configured to detect signal transitions on the other node; wherein the error detection circuit is coupled to the other transition detector and further configured to detect an error in response to a signal transition detected by at least one of the transition detectors, and the other transition detector, during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock; The clock unit includes: a delay module having an input coupled to a reference clock input and an output coupled to a delayed reference clock output; and a logic circuit element having a first input coupled to the reference clock input and a second input coupled to the delayed reference clock output, and configured to generate a signal for enabling the error detection circuit when the reference clock and the delayed reference clock are different; Furthermore, each of the transition detectors includes: a transition detector input coupled to the input of a delay module and a first input of an EXOR gate; the output of the delay module coupled to a second input of an EXOR gate; and the output of the EXOR gate coupled to the output of the transition detector. The method includes: Place and wire the logic units of the design; Identify the unit corresponding to the data path node on the critical timing path; Place the plurality of conversion detectors; Identity conversion detector cluster; The circuit elements of the error detection circuit are placed according to the cluster. Connect the conversion detector to the data path node and the error detection circuit.

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