4H-SiC electronic device with improved short-circuit performance and manufacturing method thereof

Abstract

Embodiments of the present disclosure relate to 4H-SiC electronic devices with improved short-circuit performance and methods of manufacturing the same. An electronic device includes a semiconductor body of silicon carbide and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly across the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has regions with different conduction threshold voltages and different saturation currents alternating with each other.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an electronic device and a method of manufacturing thereof. In particular, the present disclosure relates to an electronic device provided with selective areas having different conduction threshold voltages or, alternatively, different saturation currents. BACKGROUND

[0002] Figure 1 The basic structure of a vertical MOSFET device 1 is shown in a lateral view and in a three-axis reference system with orthogonal axes X, Y, Z. In a typical embodiment, the MOSFET device 1 comprises a plurality of such basic structures working together, the plurality of such basic structures sharing the same drain terminal (D), having all gate terminals (G) connected together by a deposited polysilicon grid (not shown), and all source terminals (S) electrically connected and linked by a top metal layer 10.

[0003] As shown in Figure 1 The MOSFET device 1 comprises a semiconductor body 2 of semiconductor material (including a substrate and, optionally, one or more epitaxial layers) having a top surface 2a and a bottom surface 2b. The semiconductor body 2 is, for example, N-doped. At the bottom surface 2b, a drain region 4 is formed, for example by implantation of N-type (N+ doped) dopants. At the top surface 2a, a body region 5 (P-doped) surrounds a source region 8 (N+ doped). A gate structure 6, including a stack of a gate conductive layer 6a and a gate dielectric layer 6b, extends over the top surface 2a, partially overlapping the source region 8. A respective insulating layer 9 covers the gate structure 6.

[0004] The top metal layer 10 electrically contacts the source region 8 and the body region 5 at surface portions 16 and 17, respectively, so as to bias the source region 8 and the body region 5 with the same bias voltage during use.

[0005] In order to improve the electrical contact between the top metal layer 10 and the body region 5, a P-well region (P+ doped) 14 is formed in some body regions 5 and faces the top surface 2a in the area corresponding to the surface portion 17. Typically, a silicide interface layer (not shown) is formed at the surface portion 17, forming an ohmic contact between the metal 10 and the implanted P-well region 14. The P-well region 14 is formed only at the locations where the metal layer 10 is designed to contact the body region 5. In the respective body region 5, the P-well region 14 is arranged between the source regions 8.

[0006] Where, by design, it has been decided to form a contact between the top metal layer 10 and the source region 8 (i.e. at the surface region 16), the respective source region 8 extending continuously within the body region 5 that hosts it, facing the top surface 2a at the surface region 16. In order to enhance the electrical contact between the metal 10 and the source 8, additional layers can be formed in a manner known per se (not shown).

[0007] During the ON state of the MOSFET device 1, the gate-source voltage V GS above the threshold, the conduction current is confined in the region of the semiconductor body 2 (current 18) under the gate structure 6 and the drain region 4. During the OFF state of the MOSFET device 1, the voltage drop across the drain D and the source S is maintained at the reverse bias by the PN junction, and a very small current (leakage) flows through the PN junction. If the voltage is increased too much and the electric field reaches a critical value, the PN junction breaks down and the current starts to flow through the body region 5. If an overvoltage is applied to the PN junction, the current flows through the PN junction while the MOSFET device 1 limits the actual drain-source breakdown voltage (BV DS ) to a value that is much lower than the breakdown voltage of the PN junction. The breakdown mechanism itself is not destructive to the PN junction. However, the overheating caused by the high breakdown current and voltage can damage the PN junction unless sufficient heat dissipation is provided.

[0008] Considering the MOSFET structure in more detail, it can be seen that the PN junction is not a "perfect diode". The diode is the collector-base junction of a bipolar junction transistor (BJT), also known as a parasitic transistor, made of the N+ source 8, the P / P+ body 5 and the N+ drain 4, with the base shorted to the emitter by the metal layer 10.

[0009] When designing a device, the behavior of the device in a fault mode in a short-circuit event should be considered, in which the simultaneous presence of high current and high voltage leads to thermal runaway, causing the device to be damaged (a usual event that occurs when an electric motor stops).

[0010] It is known that some semiconductor materials are ideal for the production of electronic components such as diodes or transistors, in particular for power applications. These materials have a wide bandgap, in particular with an energy value of the bandgap Eg greater than 1.1 eV, a low on-state resistance (R ON ), high thermal conductivity, high operating frequency and high speed saturation of the charge carriers. A material with the above characteristics and designed for the manufacture of electronic components is silicon carbide (SiC). In particular, with regard to the characteristics listed earlier, silicon carbide is more preferable than silicon in its different polytypes (for example 3C-SiC, 4H-SiC, 6H-SiC).

[0011] Electronic devices provided on silicon carbide substrates exhibit many advantageous characteristics, such as low output resistance in conduction, low leakage current, high operating temperature and high operating frequency, compared to similar devices provided on silicon substrates.

[0012] However, the above problems are not completely overcome by using SiC, and to improve the avalanche capability of MOSFET devices, the usual solution foresees edge structures with a higher breakdown threshold with respect to the active region. However, this goal is not always feasible due to the limitations of the device edge efficiency.

[0013] Since the source resistance depends on the doping value of the source region 8, the resistance in the ON state is further affected. SUMMARY

[0014] In various embodiments, the present disclosure provides electronic devices and methods of manufacturing the same that overcome the drawbacks of the prior art. In one or more embodiments of the present disclosure, the following advantageous technical effects are provided: a method of limiting thermal runaway, and limiting the saturation current and the local dissipated power, with minimal impact on the output resistance of the device.

[0015] According to the present disclosure, an electronic device and a method of manufacturing the same are provided.

[0016] In at least one embodiment, an electronic device comprising a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite each other along a direction is provided. A body region having a first conductivity extends in the semiconductor body at the first surface. A source region having a second conductivity opposite the first conductivity extends in the body region at the first surface of the semiconductor body. A doped region having the second conductivity extends continuously at the entire first surface of the semiconductor body and comprises one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration.

[0017] In at least one embodiment, a method for manufacturing an electronic device is provided, the method comprising: forming a body region having a first conductivity at a first surface in a silicon carbide (SiC) semiconductor body having a second surface opposite the first surface along a direction; forming a source region having a second conductivity opposite the first conductivity in the body region at the first surface of the semiconductor body; forming a drain region having the second conductivity at the second surface; and forming a doped region having the second conductivity, the doped region extending seamlessly at the entire first surface of the semiconductor body, forming the doped region comprising: forming one or more first sub-regions having a first doping concentration; and forming one or more second sub-regions having a second doping concentration lower than the first doping concentration.

[0018] In at least one embodiment, a device is provided, comprising a semiconductor body having a first surface and a second surface opposite to the first surface in a direction. A body region having a first conductivity extends in the semiconductor body at the first surface. A source region having a second conductivity opposite to the first conductivity extends in the body region at the first surface of the semiconductor body. A drain region having a second conductivity extends in the semiconductor body at the second surface. A doped region having the second conductivity extends continuously over the entire first surface of the semiconductor body. The doped region comprises a first subregion having a first doping concentration and a second subregion having a second doping concentration lower than the first doping concentration. A first gate structure is located on the first doped region, and a second gate structure is located on the second doped region. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order that the present disclosure may be better understood, preferred embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0020] Figure 1 A MOSFET device of a known type is shown;

[0021] Figure 2 shows a MOSFET device according to an embodiment of the present disclosure;

[0022] Figure 3A and Figure 3B Shows the manufacturing Figure 2 MOSFET device process steps; and

[0023] Figures 4A to 4D The corresponding embodiment according to the present disclosure is shown Figure 2 A plan view of the corresponding layout of the implanted regions of a MOSFET device. DETAILED DESCRIPTION

[0024] Figure 2 A portion of a MOSFET device 100 is shown according to an embodiment of the present disclosure. Figure 2 Is with Figure 1 The three-axis reference system of the orthogonal axes X, Y, and Z is a cross-sectional view in the same three-axis reference system.

[0025] If you have already referred Figure 1 discussed, Figure 2 The portion shown in may be a basic structure or "cell" that may be used to develop a MOSFET device 100 by replicating the basic structure a desired number of times; such basic structures working together, sharing a common drain terminal (D), a common gate terminal (G), and a common source terminal (S).

[0026] It is clear that, when copying Figure 2 parts of the figures, variations in the basic structure can be introduced, which will be clear to the person skilled in the art, for example in order to comply with one or more of design requirements, area occupation, electrical requirements, manufacturing requirements, etc.

[0027] The MOSFET device 100 comprises a semiconductor body 102 of semiconductor material (which comprises, for example, a substrate and, optionally, one or more epitaxial layers), the semiconductor body 102 having a top surface 102a and a bottom surface 102b opposite each other along a Z-axis.

[0028] In particular, the semiconductor body 102 is made of silicon carbide (SiC), more in particular of 4H-SiC. In one embodiment, the semiconductor body 102 is N-doped.

[0029] Facing the bottom surface 102b is a drain region 104, which is formed, for example, of an N-type (N+ doped) implantation of dopant type. A body region 105 (P doped) is arranged at the top surface 102a.

[0030] A source region 108 (N+ doped) is formed by implantation in the semiconductor body 102, the source region 108 facing the top surface 102a within the body region 105. The body region 105 thus surrounds the respective source region 108 formed therein.

[0031] A gate structure 106 extends over the top surface 102a and comprises a stack of a gate conductive layer 106a (for example, a metallic material) and a gate dielectric layer 106b (insulating or dielectric material). A respective insulating layer 109 covers each gate structure 106 to electrically insulate the gate structure 106 from a metal layer 110. The gate structure 106 partially overlaps the source region 8; during use, a respective channel region 118 is formed between the body region 105 / source region 108 in the region of the semiconductor body 102 under the gate structure 106 in a manner known per se. A current path is drawn in dashed lines 118 in Figure 2 and runs from the source region 108 towards the drain region 104 (vertical conduction).

[0032] The active region of the MOSFET device 100 is the region in which current conduction takes place, and in particular the channel-forming region. Typically, the active region is completely or partially surrounded by an edge termination region, which is not shown and is known per se. The edge termination region is, for example, an implantation region of P conductivity type.

[0033] In a manner not shown in detail and known per se, all gate structures 106 are electrically connected together (eg, by a polysilicon mesh), and all source regions 108 are electrically connected together.

[0034] The top metal layer 110 makes electrical contact with the source region 108 and the body region 105 at respective contact regions so that the source region 108 and the body region 105 are biased at the same bias voltage during use.

[0035] In order to improve the electrical contact between the top metal layer 110 and the body region 105, an electrical contact interface (P+ doping) 114 is formed in one or more body regions 105 at the top surface 2 a. Typically, each electrical contact interface 114 includes a silicide interface layer (not shown) to form an ohmic contact between the top metal layer 110 and the corresponding electrical contact interface 114. The electrical contact interface 114 is formed where the metal layer 110 reaches the top surface 102 a to contact the body region 105.

[0036] According to one aspect of the present disclosure, by design, at locations where contacts are to be formed between the top metal layer 110 and the source regions 108 , there are also electrical contact interfaces 116 between the top metal layer 110 and regions of the semiconductor body.

[0037] According to one aspect of the present disclosure, the device 100 presents an implanted region 120 adjacent to or directly facing the top surface 102a, extending along the entire extension of the device 100. The implanted region 120 is of N-type and has the function of modulating the saturation current of the device 100. In this context, the saturation current is the maximum current that the device can sustain at a given gate voltage Vg, and once the linear region (where the on-state resistance R is identified) is exceeded, the saturation current is reduced to zero. ON ) exceeds a certain drain-source voltage V DS The saturation current is limited by the device's turn-on voltage (Vth): a higher Vth corresponds to a lower saturation current.

[0038] The implantation region 120 is designed to present at least a first subregion 121 having a first N-type dopant value and at least a second subregion 123 having a second N-type dopant value lower than the first value of the first subregion 121 .

[0039] The implanted region 120 extends towards the top surface 102 a in the region for accommodating the conductive channel and the drain region 104 below the body region 105 , the source region 108 and the gate dielectric 106 b.

[0040] Therefore, the implantation region 120 is in electrical contact with the body region 105 , the source region 108 and the electrical contact interface 114 .

[0041] The depth of the implanted region 120 in the semiconductor body 102, measured in the Z direction from the top surface 102a, ranges between 10 nm and 0.1 μιη, in particular from 20 nm to 50 nm.

[0042] In case of an increased implantation dose (first sub-region 121), the threshold voltage Vth decreases, i.e. the gate-source voltage value V GS required for generating or turning on a conductive channel with respect to the second sub-region 123 decreases. DS The threshold voltage Vth is defined as the gate-source voltage V 2 at which the drain-source current I GS equals 250 μΑ / mm .

[0043] By confining the implant to a position adjacent to the top surface 102a, in particular at the interface between the semiconductor body 102 and the gate dielectric layer 106b, it is possible to influence the threshold voltage Vth in this particular range of the device 100, as a result of saturation of interface defects typically present in SiC (as demonstrated, for example, by I. Pintilie et al., "Analysis of electron traps at the 4H - SiC / SiO2 interface; influence by nitrogen implantation prior to wet oxidation", Journal of Applied Physics 108, 024503, 2010).

[0044] In this way, during operation, the sub-region 121, having a higher doping concentration, turns on at a lower voltage V GS than the voltage V GS required for turning on the sub-region 123. As a result, as the voltage V GS increases, a conduction channel is first formed in the sub-region 121, and subsequently, in the sub-region 123. Furthermore, however, when the voltage V GS is such that the channels in both the sub-region 121 and the sub-region 123 are turned on, a higher current density is observed in the sub-region 121.

[0045] The N-type dopant concentration in the first sub-region 121 is such that it exceeds the surface concentration of the body region 105 by a factor of 5 to 20 times the concentration of the body region 105; the N-type dopant concentration in the second sub-region 123 is such that it exceeds the surface concentration of the body region 105 by a factor of 2 to 10 times the concentration of the body region 105.

[0046] The ratio Vth2 / Vthi between the threshold voltage Vth2 of the sub-region 123 and the threshold voltage Vthi of the sub-region 121 varies from 1.1 to 2.5 and is defined by the ratio of the dopant concentrations present in the two sub-regions.

[0047] It is thus possible, by suitable layout of the implantation region 120, to define zones of the device 100 designed to carry greater current with respect to other zones of the device 100, or in other words, to design zones of the device 100 in which the current is limited, as a result of which the saturation current in that range is limited. On the basis of design considerations, the zones for transporting the highest current are selected, either in the most robust range of the device or the current is distributed uniformly so as not to be concentrated in some ranges with respect to others.

[0048] With reference to the manufacturing process of the implantation region 120, reference is made to Figure 3A and Figure 3B , Figure 3A and Figure 3B a portion of a semiconductor wafer is shown, which is limited to the same features useful for understanding the present disclosure. Figure 3A and Figure 3B The manufacturing steps for forming the implantation region 120 are specifically illustrated, while the remaining process steps for starting and completing the manufacturing of the device 100 are not described or illustrated, as they are not part of the present disclosure.

[0049] With reference to Figure 3A , after the formation of the body region 105 by implantation of P dopants and of the source region 108 by implantation of N dopants, a first unmasked implant of N-type (for example, nitrogen or phosphorus) is performed in order to form a first implantation region 130 in the interface 102a. This first implant (as indicated by the arrow in Figure 3A ) is performed with an implantation energy ranging from 10 to 100 keV. A protective layer 134 can be formed on the surface 102a in order to avoid any surface damage of the semiconductor body 102 caused by the implantation.

[0050] Figure 3A The implantation step of the first sub-region 121 is particularly described with reference to Figure 2 and contributes to the formation of the second sub-region 123.

[0051] Then, Figure 3B , a second masked implant of N-type (for example, nitrogen or phosphorus) is performed in order to complete the formation of the first sub-region 121.

[0052] This second implant (as indicated by the arrow in Figure 3BThe second implantation is performed (as indicated by the middle arrow 136) with an implantation energy ranging from 10 to 100 keV. The mask 137 used for the second implantation leaves exposed surface portions of the semiconductor body 102 corresponding to the regions where only the first sub-regions 121 are to be formed. In one embodiment, the mask 137 can be formed as a hard mask, a mask layer of, for example, silicon oxide is deposited on the surface 102a of the semiconductor body 102, and the mask layer is shaped to expose surface regions of the semiconductor body 102 where implantation of sub-regions 121 is desired.

[0053] Then, an annealing step is performed to facilitate activation of all implants in the sub-regions 121, 123. The annealing step is performed at a temperature ranging from 1600 to 1800 °C. The annealing step can be dedicated to the formation of the implanted regions 120, or shared with the implantation of regions 120 and the body and / or source and / or drain regions.

[0054] Figure 4A A top view of a portion of the device 100 is illustrated by way of example only, which is limited to the body regions 105 and the implants of the first sub-regions 121 (as mentioned, the sub-regions 123 are considered to be uniformly present at the surface 102a of the device 100, excluding portions not belonging to the surface 102a of the device 100). It is noted that, in the present embodiment, the plurality of body regions 105 extends in the form of a strip parallel to each other along the Y-axis direction; the plurality of first sub-regions 121 extends in the form of a strip parallel to each other along the X-axis direction and overlaps the plurality of body regions 105. According to the designer’s choice, the first sub-regions 121 can cover a variable percentage of the body regions 105, i.e. the percentage of coverage of the body regions 105 varies from 50% to 80%.

[0055] Figures 4B to 4D It is shown that, according to alternative and Figure 4A corresponding embodiments of the alternative and Figure 4A ; the plurality of first sub-regions 121 extends in the form of a strip parallel to each other along the same Y-axis direction, partially overlapping the plurality of body regions 105.

[0056] As Figure 4B illustrated, the strips of first sub-regions 121 can extend to completely overlap the corresponding strips of body regions 105, or as Figure 4C and Figure 4D illustrated, only partially overlap them.

[0057] Figure 4B (and similar Figure 4C) illustrates first sub-regions 121 (one for every two regions, ie, the total area of ​​the first sub-regions 121 is equal to 50% of the total area of ​​the body region) extending alternately with each other to cover the body region 105.

[0058] Figure 4C A first sub-region 121 is shown which extends between strips of body regions 105 arranged side by side and directly facing each other, partially overlapping these body regions 105 arranged side by side. Figure 4B , the total extension (or area) of the first sub-region 121 is equal to 50% of the total area of ​​the body region 105 .

[0059] Figure 4D An implementation of a first “checkerboard” sub-region 121 is illustrated, wherein the first sub-region 121 extends discontinuously along the body region 105 .

[0060] The advantages of the present disclosure are apparent from what has been described.

[0061] It has been found that embodiments of the present disclosure increase durability during short circuit testing. In fact, Figure 2 The structure of (in the various described embodiments) allows the saturation current of the MOSFET device 100 to be modulated at selected portions of the device 100 with minimal impact on the output resistance of the device 100.

[0062] The layout is designed to eliminate areas of high current density, for example at wires or clips, so that the saturation current is limited to even out the total current circulating in the device and avoid damage to the device in the event of a short circuit.

[0063] Finally, it is clear that modifications and variations can be made to what has been described and illustrated herein without departing from the scope of the present disclosure.

[0064] For example, the previously disclosed embodiments relate to N-channel MOSFETs. However, it is obvious to those skilled in the art that the present disclosure can also be applied to P-channel MOSFETs.

[0065] In some embodiments, an electronic device (100) can be summarized as comprising a semiconductor body (102) of silicon carbide, SiC, having a first surface (102a) and a second surface (102b) opposite each other along a direction (Z). A body region (105) has a first conductivity (P) and extends at the first surface (102a) of the semiconductor body (102). A source region (108) has a second conductivity (N) opposite the first conductivity (P) and extends in the body region (105) at the first surface (102a) of the semiconductor body (102). A drain region (104) has the second conductivity (N) and extends at the second surface (102b) of the semiconductor body (102). A doped region (120) having the second conductivity (N) extends continuously at the entire first surface (102a) of the semiconductor body (102) and the doped region (120) comprises one or more first sub-regions (121) having a first doping concentration and one or more second sub-regions (123) having a second doping concentration lower than the first doping concentration.

[0066] In some embodiments, the first sub-regions (121) alternate with the second sub-regions (123) to form zones having different conduction threshold voltages (Vth1, Vth2) or, alternatively, different saturation currents.

[0067] In some embodiments, each first sub-region (121) and each second sub-region (123) are designed so that the ratio (Vth2 / Vth1) between the conduction threshold voltage (Vth2) of each second sub-region (123) and the conduction threshold voltage (Vth1) of each first sub-region (121) is in the range 1.1 to 2.5.

[0068] In some embodiments, the first and second sub-regions (121, 123) have a depth in the semiconductor body ranging between 10 nm and 0.1 pm from the surface (102a).

[0069] In some embodiments, the value of the first doping concentration is in the range 5 to 20 times the value of the respective doping concentration of the body region (105) and the value of the second doping concentration is in the range 2 to 10 times the value of the respective doping concentration of the body region (105).

[0070] In some embodiments, the first sub-regions (121) are adjacent and electrically connected to the respective second sub-regions (123).

[0071] In some embodiments, the second sub-regions (123) occupy a volume of the doped region (120) in the range 50% to 80%.

[0072] In some embodiments, the gate structure (106) is disposed on the first surface (102a) of the semiconductor body. The gate structure comprises a gate dielectric layer (106b), a metal gate layer (106a) on the gate dielectric layer (106b) and an insulating layer surrounding the metal gate layer (106a). The doped region (120) can extend within the source region, the body region and under the gate structure (106).

[0073] In some embodiments, the semiconductor body (102) is a semiconductor body of 4H-SiC.

[0074] In some embodiments, the method for manufacturing an electronic device (100) can be summarized as comprising the steps of: arranging a semiconductor body (102) of silicon carbide, SiC, having a first surface (102a) and a second surface (102b) opposite each other along a direction (Z); forming a body region (105) having a first conductivity (P) at the first surface (102a) of the semiconductor body (102); forming a source region (108) having a second conductivity (N) opposite the first conductivity (P) in the body region (105) at the first surface (102a) of the semiconductor body (102); and forming a drain region (104) having the second conductivity (N) at the second surface (102b), characterized in that the steps further comprise forming a doped region (120) having the second conductivity (N) extending seamlessly across the first surface (102a) of the semiconductor body (102), comprising the sub-steps of: forming one or more first sub-regions (121) having a first doping concentration; and forming one or more second sub-regions (123) having a second doping concentration lower than the first doping concentration.

[0075] In some embodiments, the first sub-regions (121) alternate with the second sub-regions (123) so as to form zones having different conduction threshold voltages (Vth1, Vth2) or, alternatively, different saturation currents.

[0076] In some embodiments, each first sub-region (121) and each second sub-region (123) are designed so that the ratio (Vth2 / Vth1) between the conduction threshold voltage (Vth2) of each second sub-region (123) and the conduction threshold voltage (Vth1) of each first sub-region (121) is in the range 1.1 to 2.5.

[0077] In some embodiments, the first and second sub-regions (121, 123) have a depth in the semiconductor body ranging between 10 nm and 0.1 pm from the surface (102a).

[0078] In some embodiments, forming the doped region (120) comprises the steps of: performing a maskless implant over the entire first surface (102a) to form a uniformly doped region having a second doping concentration; arranging an implantation mask (137) on the first surface (102a), the implantation mask (137) exposing a surface region of the semiconductor body (102) at which the first sub-region (121) is desired to be formed; performing a masked implant using the implantation mask (137) to form a selectively doped region having a first doping concentration.

[0079] In some embodiments, the first doping concentration has a value in the range of 5 to 20 times the value of the respective doping concentration of the body region (105), and the second doping concentration has a value in the range of 2 to 10 times the value of the respective doping concentration of the body region (105).

[0080] In some embodiments, the first sub-region (121) is adjacent to and electrically connected with the respective second sub-region (123).

[0081] In some embodiments, the second sub-region (123) occupies a volume of the doped region (120) in the range of 50% to 80%.

[0082] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the detailed description. In general, the selected terms are used in the following claims as limiting terms in the manner used by those skilled in the art in their own patent claims. Accordingly, the claims are not to be construed as limited to the embodiments and examples disclosed in the specification and drawings.

Claims

1. An electronic device comprising: A semiconductor body having a first surface and a second surface opposite to each other along a direction; a body region having a first conductivity and extending in the semiconductor body at the first surface; a source region having a second conductivity opposite to the first conductivity, extending in the body region at the first surface of the semiconductor body; a drain region having the second conductivity and extending at the second surface of the semiconductor body; a doped region having the second conductivity, extending continuously over the entire first surface of the semiconductor body and comprising one or more first subregions having a first doping concentration and one or more second subregions having a second doping concentration lower than the first doping concentration; a first gate structure on the one or more first sub-regions; and A second gate structure is on the one or more second sub-regions. 2 . The device according to claim 1 , wherein the first sub-regions alternate with the second sub-regions, the first sub-regions and the second sub-regions forming alternating regions having different conduction threshold voltages or different saturation currents. 3 . The device according to claim 1 , wherein a ratio between a conduction threshold voltage of each second sub-region and a conduction threshold voltage of each first sub-region is in a range of 1.1 to 2.

5. 4 . The device according to claim 1 , wherein the first subregion and the second subregion have a depth in the semiconductor body from the first surface in the range of 10 nm to 0.1 μm.

5. The device of claim 1 , wherein the first doping concentration has a value in the range of 5 to 20 times a corresponding doping concentration value of the body region, and the second doping concentration has a corresponding value in the range of 2 to 10 times the doping concentration value of the body region. The device according to claim 1 , wherein the first sub-region is continuous with and electrically connected to the corresponding second sub-region. The device according to claim 1 , wherein the second sub-region occupies a volume of the doped region in a range of 50% to 80%.

8. The device of claim 1 , further comprising a gate structure on the first surface of the semiconductor body, the gate structure comprising: gate dielectric layer, a metal gate layer on the gate dielectric layer, and an insulating layer surrounding the metal gate layer, The doped region extends in the source region, the body region, and below the gate structure. 9 . The device according to claim 1 , wherein the semiconductor body is a semiconductor body of 4H—SiC. 10 . The device of claim 1 , wherein each of the first subregion and the second subregion extends from the first surface to the same depth in the semiconductor body. The device according to claim 1 , wherein the semiconductor body is a semiconductor body of silicon carbide (SiC).

12. A method for manufacturing an electronic device, comprising: forming a body region having a first conductivity at a first surface in a semiconductor body, the semiconductor body having a second surface opposite to the first surface in a direction; forming a source region having a second conductivity opposite to the first conductivity in the body region at the first surface of the semiconductor body; forming a drain region having the second conductivity at the second surface; forming a doped region having the second conductivity, wherein the doped region seamlessly extends over the entire first surface of the semiconductor body, wherein forming the doped region comprises: forming one or more first sub-regions having a first doping concentration; and forming one or more second sub-regions having a second doping concentration lower than the first doping concentration; and forming a first gate structure on the one or more first sub-regions; and A second gate structure is formed on the one or more second sub-regions. 13 . The method according to claim 12 , wherein the first sub-regions and the second sub-regions alternate with each other and form regions having different conduction threshold voltages or different saturation currents that alternate with each other. 14 . The method according to claim 12 , wherein each first subregion and each second subregion are formed such that a ratio between a conduction threshold voltage of each second subregion and a conduction threshold voltage of each first subregion is in a range of 1.1 to 2.

5. The method according to claim 12 , wherein the first subregion and the second subregion have a depth in the semiconductor body from the first surface in the range of 10 nm to 0.1 μm.

16. The method of claim 12, wherein forming the doped region comprises: forming a uniformly doped region having the second doping concentration by performing maskless implantation on the entire first surface; arranging an implantation mask on the first surface, the implantation mask exposing a surface region of the semiconductor body at which the first sub-region is desired to be formed; as well as By performing mask implantation using the implantation mask, a selective doping region having the first doping concentration is formed.

17. The method according to claim 12, wherein the first doping concentration has a value in the range of 5 to 20 times the corresponding doping concentration value of the body region, and the second doping concentration has a corresponding value in the range of 2 to 10 times the doping concentration value of the body region. The method according to claim 12 , wherein the first sub-region is continuous with and electrically connected to the corresponding second sub-region. 19 . The method of claim 12 , wherein the second sub-region occupies a volume of the doped region in a range of 50% to 80%.

20. The method of claim 12, wherein the semiconductor body is a semiconductor body of silicon carbide (SiC).

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