Memory device, memory device structure and manufacturing method thereof

Abstract

The present disclosure relates to a memory device, a memory device structure and a method for forming the same. A magnetic tunnel junction (MTJ) memory cell includes a connecting via structure, a bottom electrode disposed on the connecting via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, wherein the bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack.

Description

Technical Field

[0001] The disclosed embodiments relate to a memory device, a memory device structure and a manufacturing method thereof. Background Art

[0002] Magnetoresistive random-access memory (MRAM) is a type of non-volatile random access memory (NV RAM) that stores data in magnetic domains. These elements are formed by two ferromagnetic plates separated by a thin insulating layer, each of which can maintain magnetization. One of the two ferromagnetic plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of the external field to store memory contents. If the insulating layer is thin enough (usually a few nanometers), electrons can tunnel from one ferromagnet to the other. This configuration is called a magnetic tunnel junction (MTJ) and is the simplest structure of an MRAM bit. Summary of the invention

[0003] An embodiment of the present invention provides a memory device including a connecting through-hole structure, a bottom electrode memory material stack, and a conductive contact structure. The bottom electrode is arranged on the connecting through-hole structure. The memory material stack is arranged on the bottom electrode. The conductive contact structure is arranged on the memory material stack, wherein the bottom surface of the conductive contact structure is in direct contact with the memory material layer of the memory material stack, and wherein the sidewall of the conductive contact structure is in direct contact with the sidewall of the etch stop layer.

[0004] An embodiment of the present invention provides a memory device structure including a connecting via structure, a magnetic tunnel junction memory cell, an etch stop layer, a conductive contact structure, and a dielectric layer. The magnetic tunnel junction memory cell includes: a bottom electrode disposed on the connecting via structure; a memory material stack disposed on the bottom electrode; and a top electrode disposed on the memory material stack. The etch stop layer is disposed above the top electrode, wherein the sidewalls of the etch stop layer surround the conductive contact structure disposed on the memory material stack. The dielectric layer is disposed above the top electrode, wherein the sidewalls of the dielectric layer surround the conductive contact structure disposed on the memory material stack, wherein the sidewalls of the etch stop layer and the sidewalls of the dielectric layer are coplanar and tapered inwardly toward the top electrode.

[0005] An embodiment of the present invention provides a method for manufacturing a memory device, comprising: forming a bottom electrode material layer, a magnetic tunnel junction material layer and a top electrode layer; patterning the bottom electrode material layer, the magnetic tunnel junction material layer and the top electrode layer to form a bottom electrode, a memory material stack and a top electrode, respectively; forming an etch stop layer and a dielectric layer above the top electrode; and performing a first etching process to partially remove the dielectric layer and the etch stop layer, thereby forming side walls in the dielectric layer and the etch stop layer, wherein the side walls of the etch stop layer and the side walls of the dielectric layer are coplanar and tapered inwardly at an angle toward the top electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A vertical cross-sectional view of a magnetic tunnel junction (MTJ) structure is shown after etching through exposed portions of a first etch stop layer and a second etch stop layer to expose a top electrode.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a complementary metal-oxide-semiconductor (CMOS) transistor and a metal interconnect structure formed in an interconnect-level dielectric layer according to an embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of connected via structures according to an embodiment of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a bottom electrode material layer, a nonmagnetic metallic buffer layer, a synthetic antiferromagnetic layer (SAF), a nonmagnetic tunnel barrier layer, a free magnetization layer, and a top electrode material layer according to an embodiment of the present disclosure.

[0011] Figure 5is a vertical cross-sectional view of an exemplary structure after depositing and patterning a photoresist layer according to an embodiment of the present disclosure.

[0012] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of memory cells according to an embodiment of the present disclosure.

[0013] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of first dielectric spacer portions according to an embodiment of the present disclosure.

[0014] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of second dielectric spacer portions according to an embodiment of the present disclosure.

[0015] Fig. 9 is a vertical cross-sectional view of an exemplary structure after forming a memory-level dielectric layer according to an embodiment of the present disclosure.

[0016] Fig.10 is a vertical cross-sectional view of an exemplary structure after forming first and second etch stop layers and an upper connection-level dielectric layer according to an embodiment of the present disclosure.

[0017] Fig.11 is a vertical cross-sectional view of an exemplary structure after depositing and patterning a mask layer according to an embodiment of the present disclosure.

[0018] Fig.12 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of through-via cavities according to an embodiment of the present disclosure.

[0019] Fig.13 is a vertical cross-sectional view of an exemplary structure after etching through a plurality of exposed portions of a second etch stop layer according to an embodiment of the present disclosure.

[0020] Fig.14 is a vertical cross-sectional view of an exemplary structure after etching through a plurality of exposed portions of the first etch stop layer and the top electrode according to an embodiment of the present disclosure.

[0021] Fig.15 is a vertical cross-sectional view of an exemplary structure after depositing a layer of metal fill material in a plurality of via cavities according to an embodiment of the present disclosure.

[0022] Fig.16is a vertical cross-sectional view of a first alternative embodiment of an exemplary structure after exposing top surfaces of a plurality of memory cells beneath an array having a plurality of through-via cavities according to an embodiment of the present disclosure.

[0023] Fig.17 is a vertical cross-sectional view of a second alternative embodiment of the exemplary structure after exposing a top surface of a plurality of top electrodes beneath an array of a plurality of through-via cavities according to an embodiment of the present disclosure.

[0024] Fig.18 is a vertical cross-sectional view of a second alternative embodiment of the exemplary structure after depositing a layer of metal fill material in a plurality of via cavities according to an embodiment of the present disclosure.

[0025] Fig.19 is a vertical cross-sectional view of another alternative embodiment of the exemplary structure after depositing and patterning a photoresist layer.

[0026] Fig. 20 is a vertical cross-sectional view of another alternative embodiment of the exemplary structure after etching the top electrode to expose at least a portion of the underlying free magnetization material layer.

[0027] Fig.21 is a vertical cross-sectional view of another alternative embodiment of the exemplary structure after the photoresist layer may be removed.

[0028] Fig. 22 is a vertical cross-sectional view of another alternative embodiment of the exemplary structure after depositing a layer of metal fill material in a plurality of via cavities according to an embodiment of the present disclosure.

[0029] Fig.23 is a vertical cross-sectional view of another alternative embodiment of the exemplary structure after depositing a conductive contact structure for forming an MTJ memory cell.

[0030] Fig.24 is a vertical cross-sectional view of another alternative embodiment of the exemplary structure after depositing a conductive contact structure for forming an MTJ memory cell.

[0031] Fig.25 is a flow chart showing the general processing steps of the method of the present disclosure.

[0032] [Explanation of Symbols]

[0033] 9: Substrate

[0034] 177: Photoresist layer

[0035] 100: Memory array area

[0036] 108: Top cover

[0037] 110: Lower connection level dielectric layer

[0038] 122: Metal barrier layer

[0039] 124: Metal via filling material section

[0040] 126: Bottom electrode

[0041] 126L: Bottom electrode material layer

[0042] 130: Non-magnetic metal buffer layer

[0043] 130L: Non-magnetic metal buffer material layer

[0044] 140: Synthetic antiferromagnetic structures

[0045] 140L: Synthetic antiferromagnetic layer

[0046] 141: Ferromagnetic hard layer

[0047] 142: Antiferromagnetic coupling layer

[0048] 143: Reference magnetic layer

[0049] 146: Non-magnetic tunnel barrier

[0050] 146L: Non-magnetic tunnel barrier material layer

[0051] 148: Free magnetic layer

[0052] 148L: Free magnetic material layer

[0053] 158: Top electrode

[0054] 158L: Top electrode material layer

[0055] 162: First spacer portion / spacer / dielectric spacer

[0056] 164: Second spacer portion / spacer / dielectric spacer

[0057] 170: Memory level dielectric layer / dielectric layer

[0058] 172: First etch stop layer / dielectric etch stop layer / etch stop layer

[0059] 174: Second etch stop layer / dielectric etch stop layer / etch stop layer

[0060] 176: Upper connection level dielectric layer / dielectric layer

[0061] 178: Mask layer

[0062] 179: First through hole cavity / through hole cavity

[0063] 180: Conductive contact structure

[0064] 200: Logical area

[0065] 279: Second through hole cavity / through hole cavity

[0066] 280: Conductive contact structure

[0067] 601: First dielectric material layer / contact level dielectric material layer

[0068] 610: First interconnect level dielectric material layer

[0069] 612: Device contact through-hole structure

[0070] 618: First Line Structure

[0071] 620: Second interconnect level dielectric material layer

[0072] 622: First through-hole structure

[0073] 628: Second Line Structure

[0074] 630: Third interconnect level dielectric material layer

[0075] 632: Second through hole structure

[0076] 638: Third Line Structure

[0077] 640: Fourth interconnect level dielectric material layer

[0078] 642: The third through hole structure

[0079] 648: Fourth Line Structure

[0080] 700: Complementary Metal Oxide Semiconductor (CMOS) Circuit System

[0081] 720: Shallow Trench Isolation Structure

[0082] 732: Source region

[0083] 735: Semiconductor Channel

[0084] 738: Drain region

[0085] 742: Source-side metal semiconductor alloy region

[0086] 748: Drain side metal semiconductor alloy region

[0087] 750: Gate structure

[0088] 752: Gate Dielectric

[0089] 754: Gate electrode

[0090] 756: Dielectric Gate Spacer

[0091] 758: Gate Cap Dielectric

[0092] 2510, 2520, 2530, 2540: Steps DETAILED DESCRIPTION

[0093] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0094] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0095] In general, the structures and methods of the present disclosure may be used to form a memory cell and / or an array having a plurality of memory cells. Specifically, the structures and methods of the present disclosure may be used to form a magnetic tunnel junction memory cell and / or an array having a plurality of magnetic tunnel junction memory cells. Although the present disclosure is described using an exemplary structure including a magnetic tunnel junction memory cell, the methods of the present disclosure may be used to form any memory cell or any array having a plurality of memory cells including a vertical stack of a plurality of patterned material portions constituting the memory cell and including a top electrode.

[0096] It should be understood that a memory device according to an embodiment of the present disclosure may include a single separate memory cell, a one-dimensional array having a plurality of memory cells, or a two-dimensional array having a plurality of memory cells. It should also be understood that the one-dimensional array having a plurality of memory cells of the present disclosure may be implemented as a periodic one-dimensional array having a plurality of memory cells, and the two-dimensional array having a plurality of memory cells of the present disclosure may be implemented as a periodic two-dimensional array having a plurality of memory cells. In addition, although the present disclosure is described using an embodiment in which a two-dimensional array having a plurality of memory cells is formed within a particular metal interconnect level, embodiments in which a two-dimensional array having a plurality of memory cells is formed within a different metal interconnect level are explicitly contemplated herein.

[0097] Resistance reduction is a key development in the design and manufacturing process of embedded magnetoresistive random access memory (MRAM). The top electrode of the MTJ memory cell within the MTJ structure can serve as an important hard mask for MTJ patterning and a connection to the upper trench (i.e., a contact formed by a metal filling material layer, such as a bit line). However, this manufacturing process contributes additional resistance to the MTJ functional path, causing the copper (Cu) material filled in the bottom shrink trench connected to the top electrode composed of TiN to induce high resistance. In addition, due to the small size of the bottom shrink trench, the filling of the bottom shrink trench portion may lead to the risk of Cu filling pits. In other words, the lateral size difference between the bottom shrink trench and the upper trench portion above the top electrode may cause defects or pockets to form during the Cu filling process. Embodiments of the present disclosure provide a method for forming a top electrode of an MTJ memory cell, which reduces the resistance of the MTJ memory cell and the contact.

[0098] Various embodiments of the present disclosure allow for reductions in Figure 1 The resistance caused by the bottom shrinkage trench and the top electrode is shown. Various embodiments include apparatus and methods for performing low-selectivity etching to facilitate the formation of a cavity above the top electrode and avoid the formation of a bottom shrinkage portion. Various embodiments include apparatus and methods for performing self-aligned and isotropic etching landed on the MTJ so that the top electrode with TiN can be completely removed and replaced with lower resistance Cu and the mask layer with TiN can be completely removed.

[0099] Figure 1A vertical cross-sectional view of a typical MTJ structure is shown after etching through multiple exposed portions of the first etch stop layer 172 (also known as a dielectric etch stop layer, etch stop layer) and multiple exposed portions of the second etch stop layer 174 (also known as a dielectric etch stop layer, etch stop layer) to expose multiple top electrodes 158. The MTJ memory cell structure may include a memory array region 100 in which an array having a plurality of memory elements is formed and a logic region 200 in which a plurality of logic devices supporting the operation of the array having the plurality of memory elements are formed.

[0100] Reference Figure 1 In a typical process, a plurality of first via cavities 179 may be vertically extended by etching a portion of the first etch stop layer 172 to expose the top electrode 158 of the MTJ memory cell. For example, an anisotropic etching process may be performed using the mask layer 178 to remove a portion of the first etch stop layer 172. The mask layer 178 may be a via-level (i.e., a cavity for forming a via) etching mask layer. In one embodiment, the mask layer 178 may be a metal etching mask layer. The chemistry of the anisotropic etching process may be selective to the material of the plurality of second spacer portions 164. For example, the first etch stop layer 172 may include silicon nitride, and the anisotropic etching process may include a reactive ion etching process that selectively etches the silicon nitride over the dielectric material of the second spacer portions 164.

[0101] The first via cavities 179 extend vertically through the first etch stop layer 172 and the second etch stop layer 174 so that the sidewalls of the first etch stop layer 172 and the sidewalls of the second etch stop layer 174 may be exposed around each first via cavity 179. The top surface of the top electrode 158 may be exposed below the array of first via cavities 179. Each first via cavity 179 may include an upper portion laterally surrounded by the upper connection level dielectric layer 176 (also referred to as a dielectric layer) and a downward-protruding portion or bottom contraction trench laterally surrounded by the first etch stop layer 172 and the second etch stop layer 174. The downward-protruding portion may have a smaller lateral dimension than the upper portion of each first via cavity 179.

[0102] A metal filling material layer (not shown) may be used to fill the plurality of via cavities 179 and the plurality of via cavities 279 to form contacts with the top electrode 158 of the MTJ memory cell structure in the memory array region 100 and the underlying fourth line structure 648 and the third via structure 642 in the logic region 200. The metal filling material layer may be composed of copper (Cu), and the mask layer 178 and the top electrode 158 may be composed of titanium nitride (TiN). After the metal filling material layer is deposited and contacts are formed in each via cavity 179, the mask layer 178 and the top electrode 158 may remain in the MTJ structure. Since the shape of the via cavity 179 is such that its downwardly protruding portion (i.e., the bottom shrinkage trench) has a smaller lateral dimension than the upper portion of each first via cavity 179, the metal filling material layer used to fill the via cavity 179 may exhibit the size of both the upper portion and the downwardly protruding portion. Due to the bottom shrinkage trench of the downwardly protruding portion, the contact of the top electrode 158 has a high resistance. In other words, depending on the size of the bottom shrinkage trench, the width of the resulting contact formed by the metal fill material layer causes the contact to have a bottom portion with a small lateral width in contact with the top electrode 158, thereby inducing a high resistance value and thus limiting the total current flow.

[0103] Reference Figure 2 , showing an exemplary structure according to an embodiment of the present disclosure. Figure 2is a vertical cross-sectional view of an exemplary structure after forming a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of metal interconnect structures formed in a plurality of dielectric material layers according to an embodiment of the present disclosure. The exemplary structure includes a substrate 9, which may be a semiconductor substrate, such as a commercially available silicon substrate. A plurality of shallow trench isolation structures 720 including a dielectric material such as silicon oxide may be formed in an upper portion of the substrate 9. A suitable doped semiconductor well, such as a p-type well and an n-type well, may be formed in each region laterally enclosed by a portion of the shallow trench isolation structure 720. A plurality of field effect transistors may be formed above the top surface of the substrate 9. For example, each field effect transistor may include a source region 732, a drain region 738, a semiconductor channel 735 including a surface portion of the substrate 9 extending between the source region 732 and the drain region 738, and a gate structure 750. Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal semiconductor alloy region 742 may be formed on each source region 732, and a drain-side metal semiconductor alloy region 748 may be formed on each drain region 738.

[0104] An exemplary structure may include a memory array region 100 in which an array having a plurality of memory elements may be subsequently formed, and a logic region 200 in which a plurality of logic devices supporting the operation of the array of memory elements may be formed. In one embodiment, the devices (e.g., field effect transistors) in the memory array region 100 may include a bottom electrode access transistor that provides access to the bottom electrode of the memory cell to be subsequently formed. At this processing step, a top electrode access transistor may be formed in the logic region 200 that provides access to the top electrode of the memory cell to be subsequently formed. The devices (e.g., field effect transistors) in the logic region 200 may provide the functions required to operate the array having a plurality of memory cells to be subsequently formed. Specifically, the devices in the logic region 200 may be configured to control programming operations, erasing operations, and sensing (read) operations of the array having a plurality of memory cells. For example, the devices in logic region 200 may include sensing circuitry and / or top electrode bias circuitry. The devices formed on the top surface of substrate 9 may include complementary metal oxide semiconductor (CMOS) transistors and optionally additional semiconductor devices such as resistors, diodes, capacitors, etc., and are collectively referred to as CMOS circuitry 700.

[0105] Various metal interconnect structures formed in multiple dielectric material layers may then be formed over the substrate 9 and the device (e.g., field effect transistor). The dielectric material layers may include, for example: a first dielectric material layer 601, which may be a layer surrounding the contact structure connected to the source and drain (sometimes referred to as a contact-level dielectric material layer 601); a first interconnect-level dielectric material layer 610; a second interconnect-level dielectric material layer 620; a third interconnect-level dielectric material layer 630; and a fourth interconnect-level dielectric material layer 640. The metal interconnect structures may include a device contact via structure 612 formed in the first dielectric material layer 601 and contacting a corresponding component of the CMOS circuit system 700, a first line structure 618 formed in the first interconnect level dielectric material layer 610, a first via structure 622 formed in a lower portion of the second interconnect level dielectric material layer 620, a second line structure 628 formed in an upper portion of the second interconnect level dielectric material layer 620, a second via structure 632 formed in a lower portion of the third interconnect level dielectric material layer 630, a third line structure 638 formed in an upper portion of the third interconnect level dielectric material layer 630, a third via structure 642 formed in a lower portion of the fourth interconnect level dielectric material layer 640, and a fourth line structure 648 formed in an upper portion of the fourth interconnect level dielectric material layer 640. In one embodiment, the second line structure 628 may include a source line connected to a source side power supply for an array having a plurality of memory cells. A voltage provided by the source line may be applied to the bottom electrode through an access transistor provided in the memory array region 100 .

[0106] Each of the first dielectric material layer 601 and the interconnect level dielectric material layers 610, 620, 630, 640 may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (e.g., 612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner layer (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the contemplated scope of the present disclosure may also be used. In one embodiment, the first via structure 622 and the second line structure 628 may be formed as an integrated line and via structure by a dual damascene process, the second via structure 632 and the third line structure 638 may be formed as an integrated line and via structure, and / or the third via structure 642 and the fourth line structure 648 may be formed as an integrated line and via structure. Although the present disclosure is described using an embodiment in which an array having a plurality of memory cells is formed above the fourth interconnect level dielectric material layer 640, embodiments in which an array having a plurality of memory cells may be formed at a different metal interconnect level are expressly contemplated herein.

[0107] A top cap layer 108 and a bottom connection-level dielectric layer 110 may be formed over the metal interconnect structure and the interconnect-level dielectric material layer. For example, the top cap layer 108 may be formed on the top surface of the fourth line structure 648 and on the top surface of the fourth interconnect-level dielectric material layer 640. The top cap layer 108 may include a dielectric cap material that may protect the underlying metal interconnect structure (e.g., the fourth line structure 648). In one embodiment, the top cap layer 108 may include a material (i.e., a dielectric material) that may provide high etch resistance and may also be used as an etch stop material during a subsequent anisotropic etching process for etching the bottom connection-level dielectric layer 110. For example, the top cap layer 108 may include silicon carbide or silicon nitride and may have a thickness in the range of 5 nm to 30 nm, although lesser and greater thicknesses may also be used.

[0108] The lower connection level dielectric layer 110 may include any material that may be used for the first dielectric material layer 601 and the interconnect level dielectric material layers 601, 610, 620, 630, 640. For example, the lower connection level dielectric layer 110 may include undoped silicate glass or doped silicate glass deposited by decomposition of tetraethylorthosilicate (TEOS). The thickness of the lower connection level dielectric layer 110 may be in the range of 50 nm to 200 nm, but lesser and greater thicknesses may also be used. The cap layer 108 and the lower connection level dielectric layer 110 may be formed as flat blanket (unpatterned) layers having respective flat top surfaces and respective flat bottom surfaces extending throughout the memory array region 100 and the logic region 200.

[0109] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of connecting via structures according to an embodiment of the present disclosure. Figure 3 , a plurality of through-hole cavities may be formed through the lower connection level dielectric layer 110 and the cap layer 108. For example, a photoresist layer (not shown) may be applied over the lower connection level dielectric layer 110, and the photoresist layer may be patterned to form an opening in a region of the memory array region 100 overlying a corresponding one of the fourth line structures 648. Anisotropic etching may be performed to transfer the pattern in the photoresist layer through the lower connection level dielectric layer 110 and the cap layer 108. The through-hole cavities formed by the anisotropic etching process are referred to herein as lower electrode contact through-hole cavities because a bottom electrode connection through-hole structure is subsequently formed in the lower electrode contact through-hole cavities. The lower electrode contact through-hole cavities may have tapered sidewalls having a tapered angle (relative to the vertical direction) in the range of 1 degree to 10 degrees. The top surface of the fourth line structure 648 may be exposed at the bottom of each lower electrode contact through-hole cavity. The photoresist layer may then be removed, for example, by ashing.

[0110] The metal barrier layer may be formed as a material layer. The metal barrier layer may cover the exposed top surface of the fourth line structure 648, the tapered sidewalls of the lower electrode contact via cavity, and the top surface of the lower connection level dielectric layer 110 without any holes passing therethrough. The metal barrier layer may include a conductive metal nitride, such as TiN, TaN, and / or WN. Other suitable materials within the contemplated scope of the present disclosure may also be used. The thickness of the metal barrier layer may be in the range of 3 nm to 20 nm, but lesser and greater thicknesses may also be used.

[0111] A metal fill material such as tungsten (W), Cu, or tantalum nitride (TaN) may be deposited in the remaining volume of the lower electrode contact via cavity. Other suitable metal fill materials for deposition in the lower electrode contact via cavity are also within the contemplated scope of the present disclosure. The metal fill material and the portion of the metal barrier layer overlying the horizontal plane including the topmost surface of the lower connection level dielectric layer 110 may be removed by a planarization process such as chemical mechanical planarization. Each remaining portion of the metal fill material located in the corresponding via cavity constitutes a metal via fill material portion 124. Each remaining portion of the metal barrier layer located in the corresponding via cavity constitutes a metal barrier layer 122. Each combination of the metal barrier layer 122 and the metal via fill material portion 124 that fills the via cavity constitutes a connecting via structure (including 122, 124). The connecting via structure (including 122, 124) may be referred to as a bottom electrode via (BEVA). An array of multiple connecting via structures (including 122 , 124 ) may be formed on the underlying metal interconnect structure in the lower connecting level dielectric layer 110 .

[0112] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a bottom electrode material layer, a nonmagnetic metal buffer layer, a synthetic antiferromagnetic layer, a nonmagnetic tunnel barrier layer, a free magnetization layer, and a top electrode material layer according to an embodiment of the present disclosure. Figure 4 A layer stack including a bottom electrode material layer 126L, a non-magnetic metal buffer material layer 130L, a synthetic antiferromagnetic layer 140L, a non-magnetic tunnel barrier material layer 146L, a free magnetization material layer 148L, and a top electrode material layer 158L may be formed on the metal barrier layer 122 and the metal via filling material portion 124. The layers in the layer stack may be deposited by a corresponding chemical vapor deposition process or a corresponding physical vapor deposition process. Each layer in the layer stack may be deposited as a flat blanket material layer having a corresponding uniform thickness as a whole. The non-magnetic metal buffer material layer 130L, the synthetic antiferromagnetic layer 140L, the non-magnetic tunnel barrier material layer 146L, and the free magnetization material layer 148L are collectively referred to as a memory material layer. In other words, the memory material layer is formed between the bottom electrode material layer 126L and the top electrode material layer 158L.

[0113] Although the present disclosure is described using an embodiment in which the memory material layer includes a nonmagnetic metal buffer material layer 130L, a synthetic antiferromagnetic layer 140L, a nonmagnetic tunnel barrier material layer 146L, and a free magnetization material layer 148L, the methods and structures of the present disclosure may be applied to any structure in which the memory material layer includes a different layer stack disposed between the bottom electrode material layer 126L and the top electrode material layer 158L and includes a material layer that can store information in any manner. Modifications to the present disclosure in which the memory material layer includes a phase change memory material, a ferroelectric memory material, or a vacancy-modulated conductive oxide material are expressly contemplated herein.

[0114] The bottom electrode material layer 126L includes at least one non-magnetic metal material, such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, alloys thereof, and / or combinations thereof. Other suitable materials within the contemplated scope of the present disclosure may also be used. For example, the bottom electrode material layer 126L may include elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt, and / or may be substantially composed of elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt. The thickness of the bottom electrode material layer 126L may be in the range of 10 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0115] The non-magnetic metal buffer material layer 130L includes a non-magnetic material that can be used as a seed layer. Specifically, the non-magnetic metal buffer material layer 130L can provide a template crystal structure that aligns the polycrystalline grains of the material of the synthetic antiferromagnetic layer 140L along a direction that maximizes the magnetization of the reference layer within the synthetic antiferromagnetic layer 140L. The non-magnetic metal buffer material layer 130L can include Ti, CoFeB alloy, NiFe alloy, ruthenium, or a combination thereof. The thickness of the non-magnetic metal buffer material layer 130L can be in the range of 3nm to 30nm, but smaller and larger thicknesses can also be used.

[0116] The synthetic antiferromagnetic layer 140L may include a layer stack of a ferromagnetic hard layer 141, an antiferromagnetic coupling layer 142, and a reference ferromagnetic layer 143. Each of the ferromagnetic hard layer 141 and the reference ferromagnetic layer 143 may have a corresponding fixed magnetization direction. The antiferromagnetic coupling layer 142 provides an antiferromagnetic coupling between the magnetization of the ferromagnetic hard layer 141 and the magnetization of the reference ferromagnetic layer 143, so that the magnetization direction of the ferromagnetic hard layer 141 and the magnetization direction of the reference ferromagnetic layer 143 remain fixed during the operation of the memory cell to be formed later. The ferromagnetic hard layer 141 may include a hard ferromagnetic material, such as PtMn, IrMn, RhMn, FeMn, OsMn, etc. The reference magnetic layer 143 may include a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the contemplated scope of the present disclosure may also be used. The antiferromagnetic coupling layer 142 may include ruthenium or iridium. The thickness of the antiferromagnetic coupling layer 142 may be selected so that the exchange interaction induced by the antiferromagnetic coupling layer 142 stabilizes the relative magnetization directions of the ferromagnetic hard layer 141 and the reference magnetic layer 143 in opposite directions, i.e., antiparallel alignment. In one embodiment, the net magnetization of the synthetic antiferromagnetic layer 140L is achieved by matching the magnetization magnitude of the ferromagnetic hard layer 141L with the magnetization magnitude of the reference magnetic layer 143. The thickness of the synthetic antiferromagnetic layer 140L may be in the range of 5 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0117] The non-magnetic tunnel barrier material layer 146L may include a tunnel barrier material, which may be an electrically insulating material having a thickness that allows electrons to tunnel. For example, the non-magnetic tunnel barrier material layer 146L may include magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), or zirconium oxide (ZrO2). Other suitable materials within the scope of the present disclosure may also be used. The thickness of the non-magnetic tunnel barrier material layer 146L may be 0.7nm to 1.3nm, but smaller and larger thicknesses may also be used.

[0118] The free magnetization material layer 148L includes a ferromagnetic material having two stable magnetization directions that are parallel or antiparallel to the magnetization direction of the reference magnetization layer 143. The free magnetization material layer 148L includes a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the scope of the present disclosure may also be used. The thickness of the free magnetization material layer 148L may be in the range of 1 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0119] The top electrode material layer 158L includes a top electrode material, which may include any non-magnetic material that can be used for the bottom electrode material layer 126L. Exemplary metal materials that can be used for the top electrode material layer 158L include, but are not limited to, TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, alloys thereof, and / or combinations thereof. Other suitable materials within the scope of the present disclosure may also be used. For example, the bottom electrode material layer 126L may include elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt, and / or may be substantially composed of elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt. The thickness of the top electrode material layer 158L may be in the range of 10nm to 100nm, but smaller and larger thicknesses may also be used.

[0120] Figure 5 is a vertical cross-sectional view of an exemplary structure after deposition and patterning of a photoresist layer according to an embodiment of the present disclosure. Figure 5 , a photoresist layer 177 may be applied over the top electrode material layer 158L, and the photoresist layer 177 may be lithographically patterned to form an array having a plurality of separated photoresist material portions. Each separated photoresist material portion in the array having a plurality of separated photoresist material portions may overlie a corresponding one of the connecting via structures (including 122, 124). In one embodiment, the connecting via structures (including 122, 124) may be arranged as a two-dimensional periodic array having a first pitch along a first horizontal direction and a second pitch along a second horizontal direction. The separated photoresist material portions may be arranged as a two-dimensional periodic array having the same periodicity as the two-dimensional periodic array of the connecting via structures (including 122, 124).

[0121] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of memory cells according to an embodiment of the present disclosure. Figure 6, an anisotropic etching process may be performed to transfer the pattern of the photoresist layer 177 through the layer stack including the top electrode material layer 158L, the free magnetization material layer 148L, the nonmagnetic tunnel barrier material layer 146L, the synthetic antiferromagnetic layer 140L, the nonmagnetic metal buffer material layer 130L, and the bottom electrode material layer 126L. During the anisotropic etching process, portions of the layer stack (including 158L, 148L, 146L, 140L, 130L, 126L) that are not masked by the photoresist layer 177 are etched.

[0122] The anisotropic etching process may include a series of anisotropic etching steps that sequentially etch various material layers of the underlying layer stack. In one embodiment, the patterned portion of the layer stack may include sidewalls having a non-zero taper angle (i.e., having a non-vertical surface). The taper angle may vary from layer to layer and may typically be in the range of 3 degrees to 30 degrees, such as 6 degrees to 20 degrees, although smaller and larger taper angles may also be used. The unmasked portion of the lower connection level dielectric layer 110 may be vertically recessed by the anisotropic etching process.

[0123] The layer stack (including 158L, 148L, 146L, 140L, 130L, 126L) formed by the top electrode material layer 158L, the free magnetization material layer 148L, the non-magnetic tunnel barrier material layer 146L, the synthetic antiferromagnetic layer 140L, the non-magnetic metal buffer material layer 130L and the bottom electrode material layer 126L can be patterned into an array having a plurality of memory cells (including 126, 130, 140, 146, 158). Each of the memory cells (including 126, 130, 140, 146, 158) includes a bottom electrode 126, a memory material stack (including 130, 140, 146, 148) and a top electrode 158. For ease of describing the present disclosure, the top electrode material layer 158L may be referred to as a barrier layer (eg, a second barrier material layer), and the top electrode 158 may be referred to as a barrier, which may be removed during various etching processes in some embodiments.

[0124] In one embodiment, each memory cell (including 126, 130, 140, 146, 148, 158) may be an MTJ memory cell. Each MTJ memory cell (including 126, 130, 140, 146, 148, 158) may include a bottom electrode 126, a magnetic tunnel junction structure (including 140, 146, 148) and a top electrode 158. Each magnetic tunnel junction (MTJ) structure (including 140, 146, 148) may include a synthetic antiferromagnetic (SAF) structure 140, a nonmagnetic tunnel barrier layer 146 and a free magnetization layer 148. A nonmagnetic metal buffer layer 130 may be disposed between the bottom electrode 126 and the magnetic tunnel junction structure (including 140, 146, 148). Each bottom electrode 126 is a patterned portion of a bottom electrode material layer 126L. Each antiferromagnetic structure 140 is a patterned portion of a synthetic antiferromagnetic layer 140L. Each nonmagnetic tunnel barrier layer 146 is a patterned portion of a nonmagnetic tunnel barrier material layer 146L. Each free magnetic layer 148 is a patterned portion of a free magnetic material layer 148L. Each top electrode 158 is a patterned portion of a top electrode material layer 158L. In one embodiment, each of the memory cells (including 126, 130, 140, 146, 148, 158) includes a vertical stack having a synthetic antiferromagnetic structure 140, a nonmagnetic tunnel barrier layer 146, and a free magnetic layer 148.

[0125] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of first spacer portions (eg, inner dielectric spacers) according to an embodiment of the present disclosure. Figure 7A first dielectric material, such as silicon nitride, may be conformally deposited over an array having a plurality of memory cells, including 126, 130, 140, 146, 148, 158. For example, the first dielectric material may be deposited by a chemical vapor deposition process. Above a horizontal surface, the thickness of the first dielectric material may be in a range of 2 nm to 20 nm, such as 4 nm to 10 nm, although lesser and greater thicknesses may also be used. An anisotropic etching process may be performed to remove horizontal portions of the first dielectric material. The remaining portions of the first dielectric material constitute an array having a plurality of first spacer portions 162, which laterally surrounds the array having a plurality of memory cells, including 126, 130, 140, 146, 148, 158. In one embodiment, the duration of the anisotropic etching process may be selected such that the sidewalls of the array having a plurality of top electrodes 158 are partially or completely exposed. The maximum thickness of each first spacer portion 162 (also referred to as spacer, dielectric spacer) can be in the range of 2 nm to 20 nm, such as 4 nm to 10 nm, although smaller and larger thicknesses can also be used.

[0126] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of second spacer portions (eg, outer dielectric spacers) according to an embodiment of the present disclosure. Figure 8 , a second dielectric material such as a dielectric metal oxide may be conformally deposited over the array having a plurality of first spacer portions 162. For example, the second dielectric material may include aluminum oxide (AlOx), aluminum nitride (AlN), hafnium oxide, lanthanum oxide, or yttrium oxide, and may be deposited by a chemical vapor deposition process. Above the horizontal surface, the thickness of the second dielectric material may be in the range of 2nm to 20nm, such as 4nm to 10nm, but lesser and greater thicknesses may also be used. An anisotropic etching process may be performed to remove horizontal portions of the second dielectric material. The remaining portions of the second dielectric material constitute an array having a plurality of second spacer portions 164, which laterally surrounds the array having a plurality of first spacer portions 162. In one embodiment, the second spacer portions 164 may be deposited directly on the sidewalls of the top electrode 158. In one embodiment, the entirety of each sidewall of the top electrode 158 may contact a corresponding second spacer portion 164. The maximum thickness of each second spacer portion 164 (also referred to as spacer, dielectric spacer) can be in the range of 2 nm to 20 nm, such as 4 nm to 10 nm, although smaller and larger thicknesses can also be used.

[0127] Each combination of the first spacer portion 162 and the second spacer portion 164 constitutes a spacer (including 162, 164). An array having a plurality of spacers (including 162, 164) laterally surrounds an array having a plurality of memory cells (including 126, 130, 140, 146, 148, 158). Although the present disclosure is described using embodiments in which the spacers (including 162, 164) include the first spacer portion 162 and the second spacer portion 164, embodiments in which the dielectric spacer consists of the first spacer portion 162 or the second spacer portion 164 are expressly contemplated herein. In general, the spacers (including 162, 164) can be formed to surround each top electrode 158 within an array having a plurality of top electrodes 158. Each spacer (including 162, 164) can be formed directly on and around the sidewalls of a corresponding top electrode 158 portion.

[0128] Fig. 9 is a vertical cross-sectional view of an exemplary structure after forming a dielectric layer according to an embodiment of the present disclosure. Fig. 9 , a memory level dielectric layer 170 (also referred to as a dielectric layer) may be formed to surround an array of multiple spacers (including 162, 164) in the memory array region 100 and above the lower connection level dielectric layer 110 in the logic region 200. The memory level dielectric layer 170 includes a planarizable dielectric material, such as undoped silicate glass or doped silicate glass. The dielectric material of the memory level dielectric layer 170 may be deposited by a conformal deposition process (e.g., a chemical vapor deposition process) or a self-planarizing deposition process (e.g., spin coating). A chemical mechanical planarization process may be performed to remove a portion of the deposited dielectric material from above a horizontal plane including the top surface of the top electrode 158. Various planarization assist structures (not shown) (e.g., an electrically isolated patterned portion of the top electrode material layer 158L and an electrically isolated patterned portion of the underlying material layer) may be used in the logic region 200 to assist in planarizing the deposited dielectric material. The remaining portion of the deposited dielectric material after the planarization process constitutes the memory level dielectric layer 170. The top surface of the memory level dielectric layer 170 can be in the same horizontal plane as the top surface of the top electrode 158. In one embodiment, the top surface of the spacer (including 162, 164) (e.g., the top surface of the second spacer portion 164) can be in the same horizontal plane as the top surface of the memory level dielectric layer 170. For example, the top surface of the spacer (including 162, 164) can completely surround the top electrode 158 so that the top electrode 158 does not contact the memory level dielectric layer 170.

[0129] Fig.10 is a vertical cross-sectional view of an exemplary structure after forming a first etch stop layer and a second etch stop layer and an upper connection level dielectric layer according to an embodiment of the present disclosure. Fig.10 , a first etch stop layer 172 and a second etch stop layer 174 may be sequentially deposited over the memory-level dielectric layer 170 and over the top surface of the top electrode 158. The first etch stop layer 172 may include a dielectric material different from the dielectric material of the memory-level dielectric layer 170. In one embodiment, the memory-level dielectric layer 170 may include a silicon oxide-based dielectric material, such as undoped silicate glass or doped silicate glass, and the first etch stop layer 172 may include a silicon-containing dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, or silicon carbide nitride. The first etch stop layer 172 may be deposited by a conformal deposition process or a non-conformal deposition process. In one embodiment, the first etch stop layer 172 may be formed by chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The thickness of the first etch stop layer 172 may be in the range of 2 nm to 20 nm, such as 3 nm to 12 nm, although lesser and greater thicknesses may also be used.

[0130] The second etch stop layer 174 comprises a dielectric material that is different from the dielectric material of the first etch stop layer 172. In one embodiment, the second etch stop layer 174 may comprise a dielectric metal oxide material, such as aluminum oxide, aluminum nitride, hafnium oxide, titanium oxide, tantalum oxide, yttrium oxide, and / or lanthanum oxide. Other suitable etch stop layer materials are also within the contemplated scope of the present disclosure. The second etch stop layer 174 may be deposited by a conformal deposition process or a non-conformal deposition process. In one embodiment, the second etch stop layer 174 may be formed by chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The thickness of the second etch stop layer 174 may be in the range of 2 nm to 20 nm, for example 3 nm to 12 nm, although lesser and greater thicknesses may also be used.

[0131] The first etch stop layer 172 and the second etch stop layer 174 may then be patterned so that the first etch stop layer 172 and the second etch stop layer 174 remain in the memory array region 100 and are removed from the logic region 200. For example, a photoresist layer (not shown) may be applied over the second etch stop layer 174, and the photoresist layer may be photolithographically patterned to cover the memory array region 100 but not the logic region 200. An etching process (e.g., a wet etching process) may be performed to etch the unmasked portion of the first etch stop layer 172 and the unmasked portion of the second etch stop layer 174. The photoresist layer may then be removed, for example, by ashing.

[0132] An upper connection level dielectric layer 176 may be formed over the first etch stop layer 172 and the second etch stop layer 174. The upper connection level dielectric layer 176 includes a dielectric material, such as undoped silicate glass, doped silicate glass, or organosilicate glass. The dielectric material of the upper connection level dielectric layer 176 may be deposited by a conformal deposition process, such as a chemical vapor deposition process, or a self-planarization deposition process, such as spin coating. In the memory array region 100, the thickness of the upper connection level dielectric layer 176 may be in the range of 50 nm to 300 nm, such as 80 nm to 200 nm, although lesser and greater thicknesses may also be used.

[0133] A mask layer 178 may be formed over the upper connection level dielectric layer 176. The mask layer 178 includes a metal material that may be used as an etch mask in a subsequent anisotropic etching process. For example, the mask layer 178 may include a conductive metal nitride material such as TiN, TaN, W, or WN or a conductive metal carbide material such as TiC, TaC, or WC. In one embodiment, the mask layer 178 includes the same material as the top electrode 158. In one embodiment, the mask layer 178 and the top electrode 158 include and / or consist essentially of titanium nitride. The mask layer 178 may be formed by chemical vapor deposition or physical vapor deposition. The mask layer 178 may have a thickness in the range of 2 nm to 20 nm, such as 3 nm to 10 nm, although lesser and greater thicknesses may also be used.

[0134] Fig.11 is a vertical cross-sectional view of an exemplary structure after depositing and patterning a mask layer according to an embodiment of the present disclosure. Fig.11, a photoresist layer 77 may be applied over the mask layer 178, and the photoresist layer 77 may be photolithographically patterned to form an array of a plurality of openings in an area overlying the array having a plurality of top electrodes 158. The area of ​​each opening in the photoresist layer 77 may be greater than, less than, or the same as the area of ​​the underlying top electrode 158. In a plan view (i.e., a view along a vertical direction), the perimeter of each opening in the photoresist layer 77 may be located outside the sidewall of the underlying top electrode 158, may be located inside the sidewall of the underlying top electrode 158, or may coincide with the sidewall of the underlying top electrode 158. Additional plurality of openings may be formed in the photoresist layer 77 within the logic region 200. The region with openings in the photoresist layer 77 within the logic region 200 may overlie an area of ​​an underlying metal interconnect structure such as the fourth line structure 648.

[0135] An etching process may be performed to transfer the pattern in the photoresist layer 77 through the mask layer 178. The etching process may include an anisotropic etching process or an isotropic etching process. In one embodiment, an anisotropic etching process such as a reactive ion etching process may be performed to transfer the pattern in the photoresist layer 77 through the mask layer 178. The photoresist layer 77 may then be removed, for example, by ashing.

[0136] Fig.12 is a vertical cross-sectional view of an exemplary structure after forming an array having a plurality of through-hole cavities according to an embodiment of the present disclosure. Fig.12 , a first anisotropic etching process may be performed using the mask layer 178 as an etching mask. The first anisotropic etching process may include a reactive ion etching process that selectively etches the upper connection level dielectric layer 176, the memory level dielectric layer 170, and the lower connection level dielectric layer 110 compared to the materials of the second etch stop layer 174 and the cap layer 108. In one embodiment, the upper connection level dielectric layer 176, the memory level dielectric layer 170, and the lower connection level dielectric layer 110 may include a silicon oxide-based dielectric material, such as undoped silicate glass, doped silicate glass, or organic silicate glass, and the first anisotropic etching process may include a reactive ion etching process that selectively etches the silicon oxide-based dielectric material compared to the dielectric material of the second etch stop layer 174 and the cap layer 108.

[0137] A plurality of through-hole cavities 179 (also referred to as first through-hole cavities) and a plurality of through-hole cavities 279 (also referred to as second through-hole cavities) may be formed below the openings through the mask layer 178. Specifically, a plurality of first through-hole cavities 179 extending vertically through the upper connection level dielectric layer 176 may be formed in the memory array region 100. The top surface of the second etch stop layer 174 may be exposed at the bottom of each first through-hole cavity 179. An array having a plurality of first through-hole cavities 179 may be formed above an array having a plurality of memory cells (including 126, 130, 140, 146, 148, 158). A plurality of second through-hole cavities 279 extending vertically through the upper connection level dielectric layer 176, the memory level dielectric layer 170, and the lower connection level dielectric layer 110 may be formed in the logic region 200. The top surface of the cap layer 108 may be exposed at the bottom of each second through-hole cavity 279.

[0138] In one embodiment, each first via cavity 179 formed through the upper connection level dielectric layer 176 may have a lateral extent greater than the lateral extent of each top electrode 158. In one embodiment, each top electrode 158 may have a circular horizontal cross-sectional shape, an elliptical horizontal cross-sectional shape, a rectangular horizontal cross-sectional shape, or a rounded rectangular horizontal cross-sectional shape. In this embodiment, the horizontal cross-sectional shape of each first via cavity 179 may be an enlargement of the horizontal cross-sectional shape of one of the top electrodes 158. In an illustrative example, the maximum lateral dimension of each first via cavity 179 may be in the range of 100.1% to 150% of the maximum lateral dimension of one of the top electrodes 158.

[0139] Fig.13 is a vertical cross-sectional view of an exemplary structure after etching through a plurality of exposed portions of the second etch stop layer according to an embodiment of the present disclosure. Fig.13 , the first via cavity 179 may be vertically extended by etching the exposed portion of the second etch stop layer 174. For example, a first dry etching process may be performed to remove the exposed portion of the second etch stop layer 174. For example, if the second etch stop layer 174 includes a dielectric metal oxide material, a dry etching process may be used to selectively etch the dielectric metal oxide material compared to the dielectric materials of the upper connection level dielectric layer 176, the memory level dielectric layer 170, the lower connection level dielectric layer 110, the first etch stop layer 172, and the cap layer 108. Fig.12 and Fig.13 The dry etching process described in the embodiment is used to partially remove the upper connection level dielectric layer 176 and the second etch stop layer 174, thereby forming a plurality of first openings.

[0140] In some embodiments, the dry etching process may include implementing tetrafluoride (CF4), fluoroform (CHF3) or other fluorinated gases to etch until the end point. In some embodiments, the dry etching process may additionally or separately include plasma etching using argon (Ar), oxygen (O2) or other plasma bombardment techniques to reduce the bottom footing / bottom shrink at the exposed top surface of the first etch stop layer 172. The dry etching process may align the sidewalls of the second etch stop layer 174 with the sidewalls of the upper connection level dielectric layer 176 so that the width of the first through hole cavity 179 continuously and gradually decreases along the vertical length from the exposed portion of the mask layer 178 toward the exposed top surface of the first etch stop layer 172. For example, the bottom footing / bottom constriction of the first etch stop layer 172 may be reduced or otherwise removed by a dry etching process so that the walls (e.g., sidewalls) of the first etch stop layer 172 do not extend outwardly relative to the walls (e.g., sidewalls) of the upper connection level dielectric layer 176 to form a flat ledge or bottom footing / bottom constriction (e.g., Figure 1 In some embodiments, the etching process may cause the sidewalls of the second etch stop layer 174 to be coplanar with the sidewalls of the upper connection level dielectric layer 176 and to be tapered inwardly toward the memory material stack (including 130, 140, 146, 148).

[0141] Fig.14 is a vertical cross-sectional view of an exemplary structure after etching through multiple exposed portions of the first etch stop layer and multiple exposed portions of the top electrode according to an embodiment of the present disclosure. Fig.14 , the first and second via cavities 179 and 279 may be vertically extended by etching the exposed portions of the first etch stop layer 172, the exposed portions of the cap layer 108, and the exposed portions of the memory level dielectric layer 170. For example, an anisotropic etching process may be performed using a mask layer 178 (not shown) to remove the exposed portions of the first etch stop layer 172, the exposed portions of the memory level dielectric layer 170, and the exposed portions of the cap layer 108. The chemistry of the anisotropic etching process may be selective to the material of the top electrode 158 and the material of the second spacer portion 164. For example, the first etch stop layer 172 and the cap layer 108 may include silicon nitride, and the memory level dielectric layer 170 may include oxide, and the anisotropic etching process may include a reactive ion etching process that selectively etches the silicon nitride and the oxide compared to the dielectric material of the second spacer portion 164. In an illustrative example, the anisotropic etching process may include using HBr, CH2H2, CHF3, CF4, O2, N2, CH x F y, Ar, He and / or other fluorinated gases as process gases.

[0142] In some embodiments, an anisotropic etching process may be performed to remove the exposed portion of the top electrode 158 and the exposed portion of the mask layer 178. The chemistry of the anisotropic etching process may be selective to the material of the second spacer portion 164 and the memory level dielectric layer 170. For example, the top electrode 158 and the mask layer 178 may include TiN, and the anisotropic etching process may include a reactive ion etching process that selectively etches the TiN as compared to the dielectric material of the second spacer portion 164 and the dielectric material of the memory level dielectric layer 170. In an illustrative example, the anisotropic etching process may include a reactive ion etching process using chlorine (Cl2) or other halogen gas as a process gas. The anisotropic etching process may be performed Fig.14 The etching process described in is performed to partially remove the first etch stop layer 172 , the top electrode 158 , and the memory level dielectric layer 170 , thereby forming a second opening that extends the size of the first via cavity 179 .

[0143] The etching process performed to remove the exposed portions of the first etch stop layer 172 and the exposed portions of the cap layer 108 and to remove the remnants of the top electrode 158 and the mask layer 178 can form a larger first through-hole cavity 179, so that the first through-hole cavity 179 extends downward toward the top layer (i.e., the free magnetization layer 148) of the exposed MTJ structure in the array having multiple memory cells (including 126, 130, 140, 146, 148). The etching process can align the sidewalls of the first etch stop layer 172 and the memory level dielectric layer 170 with the sidewalls of the second etch stop layer 174 and the upper connection level dielectric layer 176, so that the width of the first through-hole cavity 179 continuously and gradually decreases along the vertical length from the top of the upper connection level dielectric layer 176 toward the exposed top surface (for example, the top layer of the MTJ structure (i.e., the free magnetization layer 148)) in the array having multiple memory cells (including 126, 130, 140, 146, 148).

[0144] In some embodiments, the etching process may cause the sidewalls of the first etch stop layer 172, the sidewalls of the memory level dielectric layer 170, the sidewalls of the second etch stop layer 174, and the sidewalls of the upper connection level dielectric layer 176 to be coplanar and tapered inwardly toward the memory material stack (including 130, 140, 146, 148). In embodiments in which the memory-level dielectric layer 170 is not in contact with the top electrode 158 (i.e., the spacers (including 162, 164) extend vertically to the surface of the memory-level dielectric layer 170 to separate the top electrode 158 from the memory-level dielectric layer 170), the etching process can cause the sidewalls of the first etch stop layer 172, the sidewalls of the second etch stop layer 174, and the sidewalls of the upper connection level dielectric layer 176 to be coplanar and tapered at an angle inward toward the memory material stack (including 130, 140, 146, 148) (i.e., the memory-level dielectric layer 170 is not affected by the same etching process).

[0145] The aligned walls (e.g., sidewalls) of the first etch stop layer 172, the memory level dielectric layer 170, the second etch stop layer 174, and the upper connection level dielectric layer 176 may form a perimeter of the first via cavity 179. In some embodiments, the etching process may expose corresponding portions of the spacers (including 162, 164) such that the perimeter of the first via cavity 179 may be partially defined by the exposed portions of the spacers (including 162, 164). For example, the size of the first via cavity 179 may be defined by the aligned walls (e.g., sidewalls) of the first etch stop layer 172, the memory level dielectric layer 170, the second etch stop layer 174, and the upper connection level dielectric layer 176, and the exposed portions of the spacers (including 162, 164) that protrude outwardly into the first via cavity 179 under the memory level dielectric layer 170. After removing the top electrode 158, the perimeter of the first via cavity 179 can overlie the top layer (e.g., free magnetization layer 148) in the array having a plurality of memory cells (including 126, 130, 140, 146, 148). The perimeter of the first via cavity 179 can be larger, smaller, or the same as the area of ​​the underlying top layer (e.g., free magnetization layer 148) in the array having a plurality of memory cells (including 126, 130, 140, 146, 148). In a plan view (i.e., a view along the vertical direction), the perimeter of each of the first via cavities 179 can be located outside the sidewalls of the spacers (including 162, 164), can be located inside the sidewalls of the spacers (including 162, 164), or can coincide with the sidewalls of the spacers (including 162, 164).

[0146] In one embodiment, each first via cavity 179 may have an upper portion laterally surrounded by the dielectric etch stop layer (including 172, 174) and the upper connection level dielectric layer 176, and a downwardly protruding portion laterally surrounded by the corresponding spacer (including 162, 164). In one embodiment, the downwardly protruding portion may have a smaller lateral dimension than the upper portion of each first via cavity 179. In this embodiment, the horizontal top surface of the spacer (including 162, 164) and the horizontal top surface of the memory level dielectric layer 170, which may be present, may be exposed in each first via cavity 179.

[0147] Fig.15 is a vertical cross-sectional view of an exemplary structure after depositing a metal filling material layer in a plurality of via cavities according to an embodiment of the present disclosure. Fig.15 , a metal filling material layer may be sequentially deposited in and on each of the through hole cavities (including 179, 279) to form a plurality of metal filling material portions. The metal filling material layer (not shown) may include a metal material that provides high electrical conductivity. For example, the metal filling material layer may include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the metal filling material layer may include W, Cu, Co, Ru, Mo, Al, alloys thereof, and / or layer stacks thereof. Other suitable materials within the contemplated scope of the present disclosure may also be used. The metal filling material layer may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, and / or electroless plating.

[0148] A chemical mechanical planarization (CMP) process may be performed to remove portions of the metal fill material layer overlying a horizontal plane including a top surface of the upper connection level dielectric layer 176. Each remaining portion of the metal fill material layer filling the first via cavity 179 forms a conductive contact structure 180. Each remaining portion of the metal fill material layer filling the second via cavity 279 forms a conductive contact structure 280. The top surface of the conductive contact structures (including 180, 280) may be in the same horizontal plane as the top surface of the upper connection level dielectric layer 176.

[0149] In some embodiments, the metal filling material layer used to form each conductive contact structure 180 may be deposited / disposed on a previously deposited metal barrier layer (not shown). Each metal barrier layer may be formed in the same manner as described above. Fig.15 The process steps shown are similar to the metal fill material layer deposited on the patterned portions of the metal barrier layer.

[0150] In general, the conductive contact structure 180 may be formed by depositing at least one conductive material in the first via cavity 179, and the conductive contact structure 280 may be formed by depositing the at least one conductive material in the second via cavity 279. Each conductive contact structure 180 may be formed directly on a top surface of a top layer (e.g., free magnetization layer 148) of a corresponding MTJ structure of an array having a plurality of memory cells (including 126, 130, 140, 146, 148) and within a corresponding first via cavity 179. An array having a plurality of conductive contact structures 180 may be formed in an array having a plurality of first via cavities 179 and on a corresponding top surface of a top layer (e.g., free magnetization layer 148) of a corresponding MTJ structure in an array having a plurality of memory cells (including 126, 130, 140, 146, 148). The conductive contact structure 180 may be formed to serve as a plurality of top electrodes of a corresponding array having a plurality of memory cells (including 126, 130, 140, 146, 148). For example, each MTJ memory cell (including 126, 130, 140, 146, 148, 180) may include a bottom electrode 126, a magnetic tunnel junction structure (including 140, 146, 148), and a conductive contact structure 180 that operates as a top electrode of the MTJ memory cell, such that the conductive contact structure 180 replaces the top electrode 158 that was removed as described above and extends further than it.

[0151] Fig.16 1 is a vertical cross-sectional view of a first alternative embodiment of an exemplary structure after exposing the top surface of the memory cells (including 126, 130, 140, 146, 148) below the array having a plurality of through-hole cavities 179 according to an embodiment of the present disclosure. Fig.16 , available from Fig.13 and Fig.14 The illustrated exemplary structure is obtained by performing one or more dry etching processes to obtain the exemplary structure of the first alternative embodiment, which removes the first etch stop layer 172 and the top electrode 158 while retaining at least a portion of the mask layer 178. The chemistry of the anisotropic etching process can be selective to the material of the mask layer 178. For example, the anisotropic etching process can include a reactive ion etching process that selectively etches the material of the first etch stop layer 172 and the material of the top electrode 158 compared to the material of the mask layer 178. In some embodiments where the top electrode 158 and the mask layer 178 are composed of the same material (e.g., TiN), the etching process can be controlled to retain part or all of the mask layer 178 while etching away part or all of the top electrode 158.

[0152] The etching process performed to remove the exposed portion of the first etch stop layer 172 and the exposed portion of the top electrode 158 may result in the formation of a larger first via cavity 179, such that the first via cavity 179 extends downward toward the exposed top layer (i.e., the free magnetic layer 148) of the array having a plurality of memory cells (including 126, 130, 140, 146, 148). The etching process may align the sidewalls of the first etch stop layer 172 and the memory level dielectric layer 170 with the sidewalls of the second etch stop layer 174 and the upper connection level dielectric layer 176, such that the width of the first via cavity 179 continuously and gradually decreases along the vertical length from the top of the upper connection level dielectric layer 176 toward the exposed top surface (e.g., the top layer (i.e., the free magnetic layer 148) of the MTJ structure) of the array having a plurality of memory cells (including 126, 130, 140, 146, 148).

[0153] In some embodiments, the etching process may cause the sidewalls of the first etch stop layer 172, the sidewalls of the memory level dielectric layer 170, the sidewalls of the second etch stop layer 174, and the sidewalls of the upper connection level dielectric layer 176 to be coplanar and tapered inwardly toward the memory material stack (including 130, 140, 146, 148). In embodiments in which the memory-level dielectric layer 170 is not in contact with the top electrode 158 (i.e., the spacers (including 162, 164) extend vertically to the surface of the memory-level dielectric layer 170 to separate the top electrode 158 from the memory-level dielectric layer 170), the etching process can cause the sidewalls of the first etch stop layer 172, the sidewalls of the second etch stop layer 174, and the sidewalls of the upper connection level dielectric layer 176 to be coplanar and tapered at an angle inward toward the memory material stack (including 130, 140, 146, 148) (i.e., the memory-level dielectric layer 170 is not affected by the same etching process).

[0154] Fig.17 is a vertical cross-sectional view of a second alternative embodiment of an exemplary structure after exposing the top surface of the top electrode 158 below the array of the plurality of via cavities 179 according to an embodiment of the present disclosure. Fig.17 , available from Fig.13 and Fig.14The exemplary structure shown is obtained by performing one or more dry etching processes to obtain the exemplary structure of the second alternative embodiment, which removes the first etch stop layer 172 and the mask layer 178 while retaining the top electrode 158. The chemistry of the anisotropic etching process can be selective to the material of the top electrode 158. For example, the anisotropic etching process can include a reactive ion etching process that selectively etches the material of the first etch stop layer 172 and the material of the mask layer 178 compared to the material of the top electrode 158. In some embodiments where the top electrode 158 and the mask layer 178 are composed of the same material (e.g., TiN), the etching process can be controlled to retain part or all of the top electrode 158 while etching away part or all of the mask layer 178. A conductive contact structure 180 can be formed on the top electrode 158 to directly contact the top electrode 158.

[0155] The etching process performed to remove the exposed portions of the first etch stop layer 172 and the exposed portions of the mask layer 178 may result in the formation of a larger first via cavity 179 such that the first via cavity 179 extends downward toward the exposed surface of the top electrode 158. The etching process may align the sidewalls of the first etch stop layer 172 and the memory level dielectric layer 170 with the sidewalls of the second etch stop layer 174 and the upper connection level dielectric layer 176 such that the width of the first via cavity 179 continuously and gradually decreases along the vertical length from the top of the upper connection level dielectric layer 176 toward the exposed top surface of the top electrode 158.

[0156] In some embodiments, the etching process may cause the sidewalls of the first etch stop layer 172, the sidewalls of the memory level dielectric layer 170, the sidewalls of the second etch stop layer 174, and the sidewalls of the upper connection level dielectric layer 176 to be coplanar and to be tapered inwardly at an angle toward the top electrode 158. In embodiments where the memory level dielectric layer 170 is not in contact with the top electrode 158 (i.e., the spacers (including 162, 164) extend vertically to the surface of the memory level dielectric layer 170 to separate the top electrode 158 from the memory level dielectric layer 170), the etching process may cause the sidewalls of the first etch stop layer 172, the sidewalls of the second etch stop layer 174, and the sidewalls of the upper connection level dielectric layer 176 to be coplanar and to be tapered inwardly at an angle toward the top electrode 158 (i.e., the memory level dielectric layer 170 is not affected by the same etching process).

[0157] In conjunction with the conductive contact structure 180, various methods may be used to accomplish Figures 2 to 17The manufacturing process of the MTJ structure shown. The gradually decreasing width (i.e., from the top surface to the bottom surface) of the conductive contact structure (e.g., 180) formed within the perimeter of the first through-hole cavity (e.g., 179), combined with etching away the bottom constriction / bottom footing above the top layer (e.g., 148) of the corresponding array having multiple memory cells (including 126, 130, 140, 146, 148), allows the resistance within the MRAM loop (MRAM loop) to be reduced. For example, increasing the width of the perimeter of the conductive contact structure by removing the bottom constriction / bottom footing allows the current to be increased. Replacing the top electrode (e.g., 158) containing TiN of the MTJ memory cell with a single structure (e.g., conductive contact structure 180) containing Cu that vertically extends beyond the size of the replaced top electrode can enable the MRAM loop to have a lower resistance path.

[0158] Fig.18 is a vertical cross-sectional view of a second alternative embodiment of an exemplary structure after depositing a layer of metal fill material in a plurality of via cavities according to an embodiment of the present disclosure. Fig.18 , a metal filling material layer may be sequentially deposited in and on each of the through hole cavities (including 179, 279) to form a plurality of metal filling material portions. The metal filling material layer (not shown) may include a metal material that provides high electrical conductivity. For example, the metal filling material layer may include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the metal filling material layer may include W, Cu, Co, Ru, Mo, Al, alloys thereof, and / or layer stacks thereof. Other suitable materials within the contemplated scope of the present disclosure may also be used. The metal filling material layer may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, and / or electroless plating.

[0159] A CMP process may be performed to remove portions of the metal fill material layer overlying a horizontal plane including a top surface of the upper connection level dielectric layer 176. Each remaining portion of the metal fill material layer filling the first via cavity 179 forms a conductive contact structure 180. Each remaining portion of the metal fill material layer filling the second via cavity 279 forms a conductive contact structure 280. The top surface of the conductive contact structures (including 180, 280) may be in the same horizontal plane as the top surface of the upper connection level dielectric layer 176.

[0160] In some embodiments, the metal filling material layer used to form each conductive contact structure 180 may be deposited / disposed on a previously deposited metal barrier layer (not shown). Each metal barrier layer may be formed in the same manner as described above. Fig.18 The process steps shown are similar to the metal fill material layer deposited on the patterned portions of the metal barrier layer.

[0161] Typically, the conductive contact structure 180 may be formed by depositing at least one conductive material in the first via cavity 179, and the conductive contact structure 280 may be formed by depositing the at least one conductive material in the second via cavity 279. Each conductive contact structure 180 may be formed directly on the top surface of the corresponding top electrode 158 and within the corresponding first via cavity 179. An array having a plurality of conductive contact structures 180 may be formed in the array having a plurality of first via cavities 179 and on the corresponding top surfaces of the corresponding top electrodes 158. The conductive contact structure 180 may be formed such that the first etch stop layer 172, the memory level dielectric layer 170, the second etch stop layer 174, and the upper connection level dielectric layer 176 surround the conductive contact structure 180 in a manner that is all coplanar and angled tapered inwardly toward the top electrode 158.

[0162] Fig.19 is a vertical cross-sectional view of another alternative embodiment of the exemplary structure after deposition and patterning of a photoresist layer 177. Fig.19 , available in Fig.17 A photoresist layer 177 is deposited over the intermediate structure shown. Specifically, the photoresist layer 177 can be deposited over the upper connection level dielectric layer 176, in the first via cavity 179, and in the second via cavity 279. The photoresist layer 177 can be photolithographically patterned within the first via cavity 179 to expose portions of the top electrode 158 while retaining other portions to mask the upper connection level dielectric layer 176 and the second via cavity 279.

[0163] Fig. 20 1 is a vertical cross-sectional view of another alternative embodiment of an exemplary structure after etching the top electrode 158 to expose at least a portion of the underlying free magnetic material layer 148. The top electrode 158 may have a thickness in the range of 0 nm to 30 nm, although greater thicknesses may also be used. An annular ring of top electrode 158 material may remain, with its sidewalls exposed. In some embodiments, etching of the top electrode 158 may be stopped before at least a portion of the underlying free magnetic material layer 148 is exposed. In such an embodiment, the recessed top surface of the top electrode 158 and the sidewalls of the top electrode 158 may be exposed. In such an embodiment, additional surface area of ​​the top electrode 158 may be provided to contact a subsequently deposited conductive contact structure 180. For example, the recess in the top electrode 158 may be 0 nm to 30 nm. Thus, the sidewalls of the top electrode 158 may have a depth between 0 nm and 30 nm.

[0164] Fig.21 is a vertical cross-sectional view of another alternative embodiment of the exemplary structure after the photoresist layer 177 may be removed, such as by ashing. Fig. 22is a vertical cross-sectional view of another alternative embodiment of an exemplary structure after depositing a metal fill material layer in a plurality of via cavities according to an embodiment of the present disclosure. Fig. 22 , a metal filling material layer may be sequentially deposited in and on each of the through hole cavities (including 179, 279) to form a plurality of metal filling material portions. The metal filling material layer (not shown) may include a metal material that provides high electrical conductivity. For example, the metal filling material layer may include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the metal filling material layer may include W, Cu, Co, Ru, Mo, Al, alloys thereof, and / or layer stacks thereof. Other suitable materials within the contemplated scope of the present disclosure may also be used. The metal filling material layer may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, and / or electroless plating.

[0165] A CMP process may be performed to remove portions of the metal fill material layer overlying a horizontal plane including the top surface of the upper connection level dielectric layer 176. Each remaining portion of the metal fill material layer filling the first via cavity 179 forms a conductive contact structure 180. Each of the conductive contact structures 180 may be surrounded by an annular ring of top electrode 158 material. In some embodiments, the metal fill material may contact the top electrode 158 material in the bottom of the first via cavity 179 such that the metal fill material contacts the top electrode 158 material along the sidewalls and bottom surfaces of the conductive contact structures 180. Each remaining portion of the metal fill material layer filling the second via cavity 279 forms a conductive contact structure 280. The top surface of the conductive contact structures (including 180, 280) may be in the same horizontal plane as the top surface of the upper connection level dielectric layer 176.

[0166] In some embodiments, the metal filling material layer used to form each conductive contact structure 180 may be deposited / disposed on a previously deposited metal barrier layer (not shown). Each metal barrier layer may be formed in the same manner as described above. Fig. 22 The process steps shown are similar to the metal fill material layer deposited on the patterned portions of the metal barrier layer.

[0167] Typically, the conductive contact structure 180 may be formed by depositing at least one conductive material in the first via cavity 179, and the conductive contact structure 280 may be formed by depositing the at least one conductive material in the second via cavity 279. Each conductive contact structure 180 may be formed directly on the top surface of the corresponding top electrode 158 and within the corresponding first via cavity 179. An array having a plurality of conductive contact structures 180 may be formed in the array having a plurality of first via cavities 179 and on the corresponding top surfaces of the corresponding top electrodes 158. The conductive contact structure 180 may be formed such that the first etch stop layer 172, the memory level dielectric layer 170, the second etch stop layer 174, and the upper connection level dielectric layer 176 surround the conductive contact structure 180 in a manner that is all coplanar and angled tapered inwardly toward the top electrode 158.

[0168] Fig.23 1 is a vertical cross-sectional view of another alternative embodiment of an exemplary structure after depositing a conductive contact structure 180 for forming an MTJ memory cell (including 126, 130, 140, 146, 148, 180). In this embodiment, the dielectric spacers (including 162, 164) can be at the same vertical height as the top layer of the memory material stack (including 130, 140, 146, 148), so that the topmost portion of the dielectric spacers (including 162, 164) can be at the same horizontal height as the top surface of the free magnetization layer 148 that is in direct contact with the conductive contact structure 180. In some embodiments, before depositing the conductive contact structure 180 material, a CMP process can be performed to align the top surface of the top layer of the memory material stack (including 130, 140, 146, 148) with the topmost portion of the dielectric spacers (including 162, 164).

[0169] Fig.24 1 is a vertical cross-sectional view of another alternative embodiment of an exemplary structure after depositing a conductive contact structure 180 for forming an MTJ memory cell (including 126, 130, 140, 146, 148, 180). In this embodiment, the conductive contact structure 180 can be deposited on the top layer of the memory material stack (including 130, 140, 146, 148) and on the exposed portions of the dielectric spacers (including 162, 164). For example, the bottom surface of the conductive contact structure 180 can be wider than the top layer of the memory material stack (including 130, 140, 146, 148) and in addition to being deposited on the top layer of the memory material stack (including 130, 140, 146, 148), it can also be deposited on the topmost exposed portions of the dielectric spacers (including 162, 164).

[0170] Reference Fig.25, a flowchart showing the general processing steps of the disclosed method for forming a single memory device including a magnetic tunnel junction memory cell (e.g., including 126, 130, 140, 146, 148) and its conductive contact structure (e.g., 180). A memory device can be formed by this method. Referring to steps 2510 and Figure 4 , a bottom electrode material layer (e.g., 126L), a magnetic tunnel junction (MTJ) material layer (e.g., 130L, 140L, 146L, 148L) and a top electrode material layer (e.g., 158L) may be sequentially formed on the connecting via structure (e.g., including 122, 124). Referring to step 2520 and Figure 5 and Figure 6 , the bottom electrode material layer (e.g., 126L), the magnetic tunnel junction material layer (e.g., including 130L, 140L, 146L, 148L) and the top electrode material layer (e.g., 158L) may be patterned to form a bottom electrode (e.g., 126), a memory material stack (e.g., including 130, 140, 146, 148) and a top electrode (e.g., 158), respectively. Referring to steps 2530 and Fig.10 , an etch stop layer (e.g., including 172 and / or 174) and an upper connection level dielectric layer (e.g., 176) may be sequentially formed on the top electrode (e.g., 158). Referring to steps 2540 and Figures 11 to 13 , a first etching process may be performed to partially remove the dielectric layer (e.g., 176) and the etch stop layer (e.g., including 172 and / or 174), thereby forming sidewalls in the dielectric layer (e.g., 176) and the etch stop layer (e.g., including 172 and / or 174). In some embodiments, the sidewalls of the etch stop layer (e.g., including 172 and / or 174) and the sidewalls of the dielectric layer (e.g., 176) may be coplanar and tapered inwardly toward the top electrode (e.g., 158).

[0171] In one embodiment, referring to Fig.14 , a second etching process may be performed to remove the top electrode (eg, 158). In one embodiment, the second etching process may be performed using at least one of Cl2, CHF3, or Ar.

[0172] In one embodiment, referring to Fig.15 , conductive materials may be deposited in a plurality of via cavities formed in the etch stop layer (e.g., including 172 and / or 174) and the upper connection level dielectric layer (e.g., 176) to form a plurality of conductive contact structures (e.g., 180). In one embodiment, the conductive contact structures (e.g., 180) may be composed of Cu.

[0173] In one embodiment, the method may also include forming a dielectric spacer (e.g., including 162, 164) surrounding the walls (e.g., sidewalls) of the bottom electrode (e.g., 126), the memory material stack (e.g., including 130, 140, 146, 148), and the top electrode (e.g., 158), wherein the inner sidewalls of the dielectric spacer (e.g., including 162, 164) may be exposed during the second etching process, and wherein the conductive contact structure (e.g., 180) may contact the inner sidewalls of the dielectric spacer (e.g., including 162, 164).

[0174] In one embodiment, the method may also include performing a chemical mechanical planarization (CMP) process to form a flat surface, wherein the flat surface includes an exposed top surface of the conductive contact structure (e.g., 180) and an exposed top surface of the upper connection level dielectric layer (e.g., 176), wherein the exposed top surface of the conductive contact structure (e.g., 180) and the exposed top surface of the dielectric layer (e.g., 176) are in the same horizontal plane.

[0175] In one embodiment, the method may further include depositing a mask layer (e.g., 178) over the upper connection level dielectric layer (e.g., 176), wherein the sidewalls of the etch stop layer (e.g., including 172 and / or 174) and the sidewalls of the dielectric layer (e.g., 176) are formed in the first etching process based on the width of the mask layer (e.g., 178). In one embodiment, a second etching process may be performed to remove the mask layer (e.g., 178). In one embodiment, the mask layer (e.g., 178) may be composed of TiN. In one embodiment, the second etching process may be performed using at least one of Cl2, CHF3, or Ar.

[0176] In one embodiment, the top electrode (eg, 158) may be composed of TiN. In one embodiment, the first etching process may be performed using at least one of CF4, CHF3, Ar, or O2.

[0177] With reference to all the drawings and in accordance with various embodiments of the present disclosure, a memory device is provided, which includes a connecting via structure (e.g., including 122, 124), a bottom electrode (e.g., 126) disposed on the connecting via structure (e.g., including 122, 124), a memory material stack (e.g., including 130, 140, 146, 148) disposed on the bottom electrode (e.g., 126), and a conductive contact structure (e.g., 180) disposed on the memory material stack (e.g., including 130, 140, 146, 148), wherein a bottom surface of the conductive contact structure (e.g., 180) is in direct contact with a memory material layer (e.g., 148) of the memory material stack (e.g., including 130, 140, 146, 148), and wherein a sidewall of the conductive contact structure (e.g., 180) is in direct contact with a sidewall of an etch stop layer (e.g., including 172 and / or 174). In one embodiment, the conductive contact structure (e.g., 180) may be composed of Cu. In one embodiment, the sidewalls of the conductive contact structure (e.g., 180) may contact the sidewalls of the etch stop layer (e.g., including 172 and / or 174) and the dielectric layer (e.g., including 170 and / or 176). In one embodiment, the sidewalls of the etch stop layer (e.g., including 172 and / or 174) and the dielectric layer (e.g., including 170 and / or 176) may be coplanar and angled inwardly tapered toward the memory material stack (e.g., including 130, 140, 146, 148). In one embodiment, the top surface of the conductive contact structure (e.g., 180) may be in the same horizontal plane as the top surface of the upper connection level dielectric layer (e.g., 176). In one embodiment, the bottom surface of the conductive contact structure (e.g., 180) may be disposed within a dielectric spacer (e.g., including 162, 164) that surrounds a wall (e.g., sidewall) of a memory material stack (e.g., including 130, 140, 146, 148). In one embodiment, the bottom surface of the top electrode may contact a top layer (e.g., 148) of the MTJ memory material stack (e.g., including 130, 140, 146, 148). In one embodiment, the width of the conductive contact structure (e.g., 180) may be continuous and gradually reduced from its top surface toward the memory material stack (e.g., including 130, 140, 146, 148).

[0178] With reference to all the drawings and according to various embodiments of the present disclosure, a memory device structure is provided, which includes a connecting via structure (e.g., including 122, 124) and an MTJ memory cell (e.g., including 126, 130, 140, 146, 148, 158), wherein the MTJ memory cell (e.g., including 126, 130, 140, 146, 148, 158) includes a bottom electrode (e.g., 126) disposed on the connecting via structure (e.g., including 122, 124), a memory material stack (e.g., including 130, 140, 146, 148) disposed on the bottom electrode (e.g., 126), and a top electrode (e.g., 158) disposed on the memory material stack (e.g., including 130, 140, 146, 148). The memory device structure may also include an etch stop layer (e.g., including 172 and / or 174) disposed above the top electrode (e.g., 158), wherein sidewalls of the etch stop layer (e.g., including 172 and / or 174) surround a conductive contact structure (e.g., 180) disposed on the memory material stack (e.g., including 130, 140, 146, 148). The memory device structure may also include a dielectric layer (e.g., including 170 and / or 176) disposed above the top electrode (e.g., 158), wherein sidewalls of the dielectric layer (e.g., 170 and / or 176) wrap around a conductive contact structure (e.g., 180) disposed on the memory material stack (e.g., including 130, 140, 146, 148), and wherein sidewalls of the etch stop layer (e.g., including 172 and / or 174) and sidewalls of the dielectric layer (e.g., including 170 and / or 176) are coplanar and tapered inwardly at an angle toward the top electrode (e.g., 158). In one embodiment, the memory device structure may further include a conductive contact structure (e.g., 180) disposed on the top electrode (e.g., 158), wherein a bottom surface of the conductive contact structure (e.g., 180) contacts a top surface of the top electrode (e.g., 158), and wherein a sidewall of the conductive contact structure (e.g., 180) is surrounded by sidewalls of the etch stop layer (e.g., including 172 and / or 174) and the dielectric layer (e.g., including 170 and / or 176). In one embodiment, the width of the conductive contact structure (e.g., 180) may be continuous and gradually reduced from its top surface toward the top electrode (e.g., 158). In one embodiment, the top surface of the conductive contact structure (e.g., 180) may be in the same horizontal plane as a top surface of an upper connection level dielectric layer (e.g., 176).

[0179] According to some embodiments, a memory device includes: a connecting through-hole structure; a bottom electrode disposed on the connecting through-hole structure; a memory material stack disposed on the bottom electrode; and a conductive contact structure disposed on the memory material stack, wherein the bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack, and wherein the sidewall of the conductive contact structure is in direct contact with the sidewall of an etch stop layer.

[0180] According to some embodiments, in the memory device, the conductive contact structure is composed of copper. According to some embodiments, in the memory device, the sidewalls of the conductive contact structure are in contact with the sidewalls of the dielectric layer. According to some embodiments, in the memory device, the sidewalls of the etch stop layer and the sidewalls of the dielectric layer are coplanar and tapered inwardly at an angle toward the memory material stack. According to some embodiments, in the memory device, the top surface of the conductive contact structure is in the same horizontal plane as the top surface of the dielectric layer. According to some embodiments, in the memory device, the bottom surface of the conductive contact structure is disposed within a dielectric spacer, and the dielectric spacer surrounds the wall (e.g., sidewall) of the memory material stack. According to some embodiments, in the memory device, the width of the conductive contact structure continuously and gradually decreases from its top surface toward the memory material stack.

[0181] According to some embodiments, a memory device structure includes: a connecting via structure; a magnetic tunnel junction memory cell including a bottom electrode disposed on the connecting via structure, a memory material stack disposed on the bottom electrode, and a top electrode disposed on the memory material stack; an etch stop layer disposed above the top electrode, wherein the sidewalls of the etch stop layer surround a conductive contact structure disposed on the memory material stack; and a dielectric layer disposed above the top electrode, wherein the sidewalls of the dielectric layer surround the conductive contact structure disposed on the memory material stack, wherein the sidewalls of the etch stop layer and the sidewalls of the dielectric layer are coplanar and tapered inwardly at an angle toward the top electrode.

[0182] According to some embodiments, in the memory device structure, the conductive contact structure is disposed on the top electrode, wherein the bottom surface of the conductive contact structure contacts the top surface of the top electrode, and wherein the sidewalls of the conductive contact structure are surrounded by the sidewalls of the etch stop layer and the sidewalls of the dielectric layer. According to some embodiments, in the memory device structure, the width of the conductive contact structure continuously and gradually decreases from the top surface thereof toward the top electrode. According to some embodiments, in the memory device structure, the top surface of the conductive contact structure is in the same horizontal plane as the top surface of the dielectric layer.

[0183] According to some embodiments, a method for manufacturing a memory device includes the following steps: forming a bottom electrode material layer, a magnetic tunnel junction material layer and a top electrode layer; patterning the bottom electrode material layer, the magnetic tunnel junction material layer and the top electrode layer to form a bottom electrode, a memory material stack and a top electrode, respectively; forming an etch stop layer and a dielectric layer above the top electrode; and performing a first etching process to partially remove the dielectric layer and the etch stop layer, thereby forming sidewalls in the dielectric layer and the etch stop layer, wherein the sidewalls of the etch stop layer and the sidewalls of the dielectric layer are coplanar and tapered at an angle inward toward the top electrode.

[0184] According to some embodiments, in the manufacturing method, the top electrode is composed of titanium nitride. According to some embodiments, in the manufacturing method, the first etching process is performed using at least one of carbon tetrafluoride, fluoroform, argon or oxygen. According to some embodiments, the manufacturing method further includes: performing a second etching process to remove the top electrode. According to some embodiments, the manufacturing method further includes: depositing a mask layer on the dielectric layer, wherein the sidewalls of the etch stop layer and the sidewalls of the dielectric layer are formed in the first etching process based on the width of the mask layer, and wherein the mask layer is composed of titanium nitride. According to some embodiments, the manufacturing method further includes: performing a second etching process to remove the mask layer. According to some embodiments, in the manufacturing method, the second etching process is performed using at least one of chlorine, fluoroform or argon. According to some embodiments, the manufacturing method further includes: depositing a conductive material in the through-hole cavity formed in the etch stop layer and the dielectric layer to form a conductive contact structure. According to some embodiments, in the manufacturing method, the conductive contact structure is composed of copper.

[0185] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: connecting through-hole structures; A bottom electrode, disposed on the connecting through-hole structure; a memory material stack disposed on the bottom electrode and including a magnetic tunnel junction having a free magnetization layer; a dielectric layer overlying the memory material stack; as well as A conductive contact structure extending vertically through the dielectric layer and comprising: A metal filling material layer; a bottom surface directly contacting the top surface of the free magnetic layer; a top surface, in the same horizontal plane as the top surface of the dielectric layer, the bottom surface of the conductive contact structure is the bottom surface of the metal filling material layer, and the top surface of the conductive contact structure is the top surface of the metal filling material layer, wherein the conductive contact structure comprises an upper portion having a first sidewall and a lower portion having a second sidewall, and wherein a top edge of the second sidewall is laterally offset inwardly relative to a bottom edge of the first sidewall by a connecting surface segment, so that a vertical cross-section of the conductive contact structure has a stepped vertical cross-sectional profile, wherein The width of the conductive contact structure increases gradually along the vertical direction at the connection surface section.

2. The memory device of claim 1, wherein the conductive contact structure is composed of copper. 3 . The memory device of claim 1 , wherein the first sidewall of the conductive contact structure contacts a sidewall of the dielectric layer.

4. The memory device of claim 3, further comprising an etch stop layer disposed between the dielectric layer and the memory material stack, wherein sidewalls of the etch stop layer and the sidewalls of the dielectric layer are coplanar and tapered inwardly toward the memory material stack.

5. The memory device of claim 3, further comprising an additional dielectric layer laterally surrounding the memory material stack and underlying the dielectric layer, wherein the first sidewall is in contact with a sidewall of the additional dielectric layer.

6. The memory device of claim 1, wherein the bottom surface of the conductive contact structure is disposed within a dielectric spacer that surrounds a wall of the memory material stack.

7. The memory device of claim 1, wherein a width of the upper portion of the conductive contact structure continuously and gradually decreases from the top surface of the conductive contact structure toward the memory material stack.

8. The memory device of claim 1 , further comprising a top electrode including an opening therethrough and contacting a peripheral portion of the top surface of the free magnetization layer, The second sidewall of the lower portion of the conductive contact structure contacts a sidewall of the opening that passes through the top electrode.

9. A memory device structure, comprising: connecting through-hole structures; A magnetic tunnel junction memory cell including a magnetic tunnel junction having a free magnetization layer; An etch stop layer, disposed above the magnetic tunnel junction memory cell; a dielectric layer disposed above the etch stop layer; as well as A conductive contact structure vertically extends through the dielectric layer and the etch stop layer and comprises: A metal filling material layer; a bottom surface directly contacting the top surface of the free magnetic layer; a top surface, in the same horizontal plane as the top surface of the dielectric layer, the bottom surface of the conductive contact structure is the bottom surface of the metal filling material layer, and the top surface of the conductive contact structure is the top surface of the metal filling material layer, wherein the conductive contact structure comprises an upper portion having a first sidewall and a lower portion having a second sidewall, and wherein a top edge of the second sidewall is laterally offset inwardly relative to a bottom edge of the first sidewall by a connecting surface segment, so that a vertical cross-section of the conductive contact structure has a stepped vertical cross-sectional profile, wherein The width of the conductive contact structure increases gradually along the vertical direction at the connection surface section.

10. The memory device structure of claim 9, wherein: The first sidewall of the upper portion of the conductive contact structure is surrounded by and contacts sidewalls of the etch stop layer and the dielectric layer.

11. The memory device structure of claim 9, wherein a width of the upper portion of the conductive contact structure continuously and gradually decreases from the top surface of the conductive contact structure toward the magnetic tunnel junction.

12. A method for manufacturing a memory device, comprising: forming a bottom electrode material layer, a magnetic tunnel junction material layer and a top electrode layer; patterning the bottom electrode material layer, the magnetic tunnel junction material layer, and the top electrode layer to form a bottom electrode, a memory material stack including a magnetic tunnel junction with a free magnetization layer, and a top electrode, respectively; forming an etch stop layer and a dielectric layer on the top electrode; as well as forming a conductive contact structure passing through the dielectric layer and the etch stop layer, wherein the conductive contact structure comprises: A metal filling material layer; a bottom surface formed directly on a top surface of the free magnetization layer; a top surface formed directly in the same horizontal plane as the top surface of the dielectric layer, the bottom surface of the conductive contact structure being the bottom surface of the metal filling material layer, and the top surface of the conductive contact structure being the top surface of the metal filling material layer, wherein the conductive contact structure comprises an upper portion having a first sidewall and a lower portion having a second sidewall, and wherein a top edge of the second sidewall is laterally offset inwardly relative to a bottom edge of the first sidewall by a connecting surface segment, so that a vertical cross-section of the conductive contact structure has a stepped vertical cross-sectional profile, wherein The width of the conductive contact structure increases gradually along the vertical direction at the connection surface section.

13. The manufacturing method of claim 12, wherein the top electrode is composed of titanium nitride.

14. The manufacturing method according to claim 12 further includes performing a first etching process to partially remove the dielectric layer and the etch stop layer, thereby forming sidewalls in the dielectric layer and the etch stop layer, wherein the first etching process is performed using at least one of carbon tetrafluoride, fluoroform, argon or oxygen.

15. The manufacturing method according to claim 14, wherein: The first etching process forms a through-hole cavity; and The manufacturing method further includes depositing a conductive material in the through hole cavity formed in the etch stop layer and the dielectric layer to form the conductive contact structure.

16. The manufacturing method according to claim 12, further comprising: A second etching process is performed to remove at least a portion of the top electrode. The manufacturing method according to claim 16 , wherein the electrically conductive contact structure is composed of copper.

18. The manufacturing method according to claim 12, further comprising: A mask layer is deposited over the dielectric layer, wherein the sidewall of the etch stop layer and the sidewall of the dielectric layer are formed in a first etching process based on a width of the mask layer, and wherein the mask layer is composed of titanium nitride.

19. The manufacturing method according to claim 18, further comprising: A second etching process is performed to remove the mask layer.

20. The manufacturing method according to claim 19, wherein the second etching process is performed using at least one of chlorine, fluoroform, or argon.

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