Semiconductor devices

Abstract

The present invention provides a semiconductor device, comprising: a substrate; a circuit region having a power wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and the first wiring. The first wiring is one of the power wiring and the ground wiring. The first diode has a first impurity region of a first conductivity type electrically connected to the signal line and a second impurity region of a second conductivity type different from the first conductivity type electrically connected to the first wiring. The signal line, or the first wiring, or both the signal line and the first wiring are formed on the substrate.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] A semiconductor device includes various circuit regions, and examples of circuit regions include an internal circuit region and an input / output (I / O) unit region. In order to suppress the damage to the internal circuit region caused by static electricity, an ESD (Electro-Static Discharge: ESD) protection circuit is provided in the I / O unit region. Power supply wiring is provided in various circuit regions.

[0003] Power supply wiring is mainly provided on the substrate, but in recent years, a semiconductor device in which the power supply wiring is buried in the substrate has been proposed. The power supply wiring of such a structure is sometimes called a BPR (Buried Power Rail).

[0004] Patent Document 1: U.S. Patent No. 9224725

[0005] Patent Document 2: U.S. Patent Application Publication No. 2018 / 0374791

[0006] Patent Document 3: U.S. Patent Application Publication No. 2018 / 0190670

[0007] Patent Document 4: U.S. Patent Application Publication No. 2018 / 0294267

[0008] Patent Document 5: U.S. Patent Application Publication No. 2017 / 0294448

[0009] Patent Document 6: U.S. Patent No. 9570395

[0010] Until now, no detailed studies have been conducted on the specific structure of a semiconductor device including an ESD protection circuit when a buried wiring such as a BPR is used. Summary of the invention

[0011] An object of the present invention is to provide a semiconductor device capable of realizing an ESD protection circuit including a buried wiring.

[0012] The semiconductor device of the disclosed technology comprises: a substrate; a circuit region having a power wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and the first wiring. The first wiring is one of the power wiring or the ground wiring. The first diode comprises: a first impurity region of a first conductivity type electrically connected to the signal line; and a second impurity region of a second conductivity type, the second conductivity type being different from the first conductivity type, the second impurity region electrically connected to the first wiring. The signal line, or the first wiring, or both the signal line and the first wiring are formed on the substrate.

[0013] According to the disclosed technology, an ESD protection circuit including buried wiring can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a diagram showing the layout of the semiconductor device according to the first embodiment.

[0015] Figure 2 This is a circuit diagram showing the structure of an input / output cell region included in the semiconductor device according to the first embodiment.

[0016] Figure 3 FIG. 1 is a schematic diagram showing a planar structure of one diode in the first embodiment.

[0017] Figure 4 is a cross-sectional view showing one diode in the first embodiment.

[0018] Figure 5 FIG. 1 is a schematic diagram showing a planar structure of another diode in the first embodiment.

[0019] Figure 6 is a cross-sectional view showing another diode in the first embodiment.

[0020] Figure 7 FIG. 1 is a schematic diagram showing a planar structure of a diode in the second embodiment.

[0021] Figure 8 FIG. 1 is a schematic diagram showing a planar structure of another diode in the second embodiment.

[0022] Fig. 9 Schematic diagram showing a planar structure of two diodes in the third embodiment.

[0023] Fig.10 It is a cross-sectional view showing a portion between two diodes in the third embodiment.

[0024] Fig.11 It is a schematic diagram showing a planar structure of two diodes in a first modified example of the third embodiment.

[0025] Fig.12 It is a schematic diagram showing a planar structure of two diodes in the second modification example of the third embodiment.

[0026] Fig.13 It is a schematic diagram showing a planar structure of two diodes in a third modification example of the third embodiment.

[0027] Fig.14 It is a schematic diagram showing a planar structure of two diodes in a fourth modification example of the third embodiment.

[0028] Fig.15 This is a schematic diagram showing an outline of two diodes in a fifth modification example of the third embodiment.

[0029] Fig.16 It is a schematic diagram showing an enlarged view of the main part of the fifth modification example of the third embodiment.

[0030] Fig.17 Schematic diagram showing a planar structure of two diodes in the fourth embodiment.

[0031] Fig.18 is a cross-sectional view showing a diode in the fourth embodiment.

[0032] Fig.19 is a cross-sectional view showing another diode in the fourth embodiment.

[0033] Fig. 20 It is a schematic diagram showing a planar structure of two diodes in a first modification example of the fourth embodiment.

[0034] Fig.21 It is a schematic diagram showing a supply unit of a power supply potential to a power supply wiring in a second modification of the fourth embodiment.

[0035] Fig. 22 It is a cross-sectional view showing a supply portion of a power supply potential to a power supply wiring in a second modification of the fourth embodiment.

[0036] Fig.23 This is a schematic diagram showing a supply unit of a power supply potential to a power supply wiring in a third modification of the fourth embodiment.

[0037] Fig.24 It is a cross-sectional view showing a supply portion of a power supply potential to a power supply wiring in a third modification of the fourth embodiment.

[0038] Fig.25 It is a schematic diagram showing a planar structure of a diode in the fifth embodiment.

[0039] Fig.26 This is a cross-sectional view showing a diode in the fifth embodiment (Part 1).

[0040] Fig. 27 This is a cross-sectional view showing a diode in the fifth embodiment (part 2).

[0041] Fig.28 FIG. 1 is a schematic diagram showing a planar structure of another diode in the fifth embodiment.

[0042] Fig.29 It is a cross-sectional view (Part 1) showing another diode in the fifth embodiment.

[0043] Fig.30 This is a cross-sectional view showing another diode in the fifth embodiment (part 2).

[0044] Fig.31 Schematic diagram showing a planar structure of two diodes in the sixth embodiment. DETAILED DESCRIPTION

[0045] Hereinafter, the implementation mode will be described in detail with reference to the accompanying drawings. In addition, in this specification and the accompanying drawings, there is a case where repeated description is omitted by marking the components having the same functional structure with the same reference numerals. In addition, in the following description, two directions parallel to the surface of the substrate and orthogonal to each other are set as the X direction and the Y direction, and the direction perpendicular to the surface of the substrate is set as the Z direction. In addition, the so-called configuration consistency in the present disclosure strictly does not exclude the situation that it is inconsistent due to manufacturing deviations. Even if the configuration is offset due to manufacturing deviations, it can be regarded as a consistent configuration.

[0046] (First Embodiment)

[0047] First, the first embodiment will be described. Figure 1 It is a diagram showing the layout of the semiconductor device according to the first embodiment. Figure 2 This is a circuit diagram showing the structure of an input / output cell region included in the semiconductor device according to the first embodiment.

[0048] like Figure 1 As shown, the semiconductor device 1 of the first embodiment includes a plurality of internal circuit regions 10 and an input / output (I / O) cell region 20 disposed around the internal circuit regions 10. The number of internal circuit regions 10 may be one or three or more.

[0049] like Figure 2As shown, the I / O cell region 20 has a VSS pad 31, a VDD pad 32, and an I / O pad 33. The VSS pad 31 is connected to a VSS wiring, which supplies a power supply potential of VSS to the internal circuit region 10. The power supply potential of VSS is, for example, a ground potential. The VDD pad 32 is connected to a VDD wiring, which supplies a power supply potential of VDD to the internal circuit region 10. The I / O pad 33 is connected to a signal line of the internal circuit region 10. The I / O cell region 20 has, for example, an inverter including an N-channel MOS transistor 401 and a P-channel MOS transistor 402. For example, the gate of the N-channel MOS transistor 401 and the gate of the P-channel MOS transistor 402 are connected to the I / O pad 33. For example, the source of the N-channel MOS transistor 401 is connected to the VSS pad 31, and the source of the P-channel MOS transistor 402 is connected to the VDD pad 32. The VSS wiring may be called a ground wiring, and the VDD wiring may be called a power supply wiring.

[0050] like Figure 2 As shown, the I / O cell region 20 has an ESD protection circuit 400 including a diode 200 and a diode 300. The anode of the diode 200 is connected to the VSS pad 31, and the cathode is connected to the I / O pad 33. The anode of the diode 300 is connected to the I / O pad 33, and the cathode is connected to the VDD pad 32.

[0051] Next, the structure of the diode 200 will be described. Figure 3 2 is a schematic diagram showing a planar structure of the diode 200 in the first embodiment. Figure 4 2 is a cross-sectional view showing the diode 200 according to the first embodiment. Figure 4 Equivalent to following Figure 3 Cross-sectional view of the Y11-Y21 line.

[0052] like Figure 3 and Figure 4As shown, a P-well 101P is formed on the surface of the substrate 101, and an element separation film 102 is formed on the surface of the P-well 101P. The element separation film 102 is formed, for example, by the STI (Shallow Trench Isolation) method. A groove extending in the X direction is formed in the P-well 101P and the element separation film 102, and a signal line 93 is formed in the groove via an insulating film 104. For example, the surface of the signal line 93 is covered by the insulating film 103. For example, the surface of the element separation film 102 and the surface of the insulating film 103 may be in the same plane as the surface of the P-well 101P, or may not be in the same plane. For example, the signal line 93 is connected to the I / O pad 33. The conductivity type of the substrate 101 may also be P-type. In this case, the P-well 101P can be replaced by a P-type substrate 101P. The same is true in other embodiments and modified examples.

[0053] A plurality of N-type fins 211 and a plurality of P-type fins 221 extending in the X direction and standing in the Z direction are formed on the P-well 101P exposed from the element separation film 102. Here, four N-type fins 211 and four P-type fins 221 are formed. For example, in the Y direction, the N-type fin 211 is located between the signal line 93 and the P-type fin 221. The P-type fin 221 functions as an anode of the diode 200, and the N-type fin 211 functions as a cathode of the diode 200.

[0054] A plurality of local wirings 212 extending in the Y direction and connected to each N-type fin 211 are formed on the element separation film 102. Here, four local wirings 212 are formed. A plurality of dummy gate electrodes 210, such as gate electrodes of so-called fin transistors, are arranged in the X direction so as to sandwich the local wirings 212. The dummy gate electrode 210 extends in the Y direction. A dummy gate insulating film (not shown) is formed between the dummy gate electrode 210 and the N-type fin 211.

[0055] A plurality of local wirings 222 extending in the Y direction and connected to each P-type fin 221 are formed on the element separation film 102. Here, four local wirings 222 are formed. A plurality of dummy gate electrodes 220, such as gate electrodes of so-called fin transistors, are arranged in the X direction so as to sandwich the local wirings 222. The dummy gate electrode 220 extends in the Y direction. A dummy gate insulating film (not shown) is formed between the dummy gate electrode 220 and the P-type fin 221.

[0056] like Figure 4As shown, an insulating film 151 is formed above the P well 101P and the element isolation film 102. Local wirings 212 and 222, and dummy gate electrodes 210 and 220 are buried in the insulating film 151. The insulating film 152 is formed on the insulating film 151, the local wirings 212 and 222, and the dummy gate electrodes 210 and 220, and an insulating film 153 is formed on the insulating film 152.

[0057] A contact hole 193 is formed in the insulating film 103 between the local wiring 212 and the signal line 93 , and the local wiring 212 is connected to the signal line 93 via a conductor in the contact hole 193 .

[0058] The insulating film 152 is provided with a contact hole 181 that reaches the local wiring 222. The insulating film 153 is provided with a power wiring 81 that extends in the X direction and is connected to the local wiring 222 via a conductor in the contact hole 181. For example, the power wiring 81 is connected to the VSS pad 31.

[0059] Next, the structure of the diode 300 will be described. Figure 5 1 is a schematic diagram showing a planar structure of the diode 300 in the first embodiment. Figure 6 1 is a cross-sectional view showing the diode 300 according to the first embodiment. Figure 6 Equivalent to following Figure 5 Cross-sectional view of the Y12-Y22 line.

[0060] like Figure 5 and Figure 6 As shown, an N-well 101N is formed on the surface of the substrate 101, and an element separation film 102 is formed on the surface of the N-well 101N. A groove extending in the X direction is formed in the N-well 101N and the element separation film 102, and a signal line 93 is formed in the groove via an insulating film 104. For example, the surface of the signal line 93 is covered by the insulating film 103. For example, the surface of the element separation film 102 and the surface of the insulating film 103 may be in the same plane as the surface of the N-well 101N, or may not be in the same plane.

[0061] A plurality of P-type fins 311 and a plurality of N-type fins 321 extending in the X direction and standing in the Z direction are formed on the N-well 101N exposed from the element isolation film 102. Here, four P-type fins 311 and four N-type fins 321 are formed. For example, in the Y direction, the P-type fin 311 is located between the signal line 93 and the N-type fin 321. The P-type fin 311 functions as an anode of the diode 300, and the N-type fin 321 functions as a cathode of the diode 300.

[0062] A plurality of local wirings 312 extending in the Y direction and connected to each P-type fin 311 are formed on the element separation film 102. Here, four local wirings 312 are formed. A plurality of dummy gate electrodes 310, such as gate electrodes of so-called fin transistors, are arranged in the X direction so as to sandwich the local wirings 312. The dummy gate electrode 310 extends in the Y direction. A dummy gate insulating film (not shown) is formed between the dummy gate electrode 310 and the P-type fin 311.

[0063] A plurality of local wirings 322 extending in the Y direction and connected to each N-type fin 321 are formed on the element separation film 102. Here, four local wirings 322 are formed. A plurality of dummy gate electrodes 320, such as gate electrodes of so-called fin transistors, are arranged in the X direction so as to sandwich the local wirings 322. The dummy gate electrode 320 extends in the Y direction. A dummy gate insulating film (not shown) is formed between the dummy gate electrode 320 and the N-type fin 321.

[0064] like Figure 6 As shown, an insulating film 151 is formed above the N well 101N and the element isolation film 102. The local wirings 312 and 322, and the dummy gate electrodes 310 and 320 are buried in the insulating film 151. The insulating film 152 is formed on the insulating film 151, the local wirings 312 and 322, and the dummy gate electrodes 310 and 320, and the insulating film 153 is formed on the insulating film 152.

[0065] A contact hole 193 is formed in the insulating film 103 between the local wiring 312 and the signal line 93 , and the local wiring 312 is connected to the signal line 93 via a conductor in the contact hole 193 .

[0066] The insulating film 152 has a contact hole 182 that reaches the local wiring 322. The insulating film 153 has a power wiring 82 that extends in the X direction and is connected to the local wiring 322 via a conductor in the contact hole 182. For example, the power wiring 82 is connected to the VDD pad 32.

[0067] In the first embodiment, the diode 200 includes the signal line 93 as a buried wiring, and the diode 300 includes the signal line 93 as a buried wiring. Thus, according to the first embodiment, an ESD protection circuit including a buried wiring can be realized. Therefore, it is suitable for further miniaturization of semiconductor devices.

[0068] In addition, in the diode 200, a power supply wiring connected to the local wiring 222 may be formed as a buried wiring in the P well 101P instead of the power supply wiring 81. Similarly, in the diode 300, a power supply wiring connected to the local wiring 322 may be formed as a buried wiring in the N well 101N instead of the power supply wiring 82. In these cases, in the diodes 200 and 300, a signal line connected to the local wiring 212 and a signal line connected to the local wiring 312 may be formed in the insulating film 153 instead of the signal line 93. In addition, in the diodes 200 and 300, the number of fins, dummy gate electrodes, and local wirings may be appropriately changed.

[0069] (Second Embodiment)

[0070] Next, a second embodiment will be described. The second embodiment is different from the first embodiment mainly in the extending directions of the signal lines and the power supply wiring. Figure 7 2 is a schematic diagram showing a planar structure of a diode 200 according to the second embodiment. Figure 8 1 is a schematic diagram showing a planar structure of a diode 300 according to the second embodiment.

[0071] like Figure 7 As shown in the diode 200, a groove extending in the Y direction is formed in the P well 101P and the element isolation film 102, and an insulating film 104 (see FIG. 104 ) is provided in the groove. Figure 4 ) is formed with a signal line 93. Figure 4 ) is formed with a contact hole 183 that reaches the local wiring 212. A signal line 83 is formed in the insulating film 153. The signal line 83 extends in the X direction and is connected to the local wiring 212 via a conductor in the contact hole 183. Between the signal line 83 and the signal line 93, there is a gap between the insulating film 152 and the insulating film 151 (see Figure 4 ) is formed on the surface, and the signal line 83 is connected to the signal line 93 through the conductor in the contact hole 2193.

[0072] In the diode 200, another groove extending in the Y direction is formed in the P well 101P and the element isolation film 102, and the insulating film 104 (see FIG. Figure 4 ) is formed with a power supply wiring 91. Figure 4 ) is formed with a contact hole 181 that reaches the local wiring 222. Figure 4 ) is formed in the contact hole 181, and the power supply wiring 81 extends in the X direction and is connected to the local wiring 222 through the conductor in the contact hole 181. The insulating film 152 and the insulating film 151 (see Figure 4) is formed with a contact hole 2191, and the power wiring 81 is connected to the power wiring 91 through the conductor in the contact hole 2191. In addition, a local wiring and a contact hole connected to the local wiring, the power wiring 81 and the power wiring 91 may be formed at the position where the contact hole 2191 is formed.

[0073] In the second embodiment, two groups including four N-type fins 211, four local wirings 212, four contact holes 183, five dummy gate electrodes 210, and one signal line 83 are provided in the diode 200. In addition, two groups including four P-type fins 221, four local wirings 222, four contact holes 181, five dummy gate electrodes 220, and one power supply wiring 81 are provided in the diode 200.

[0074] like Figure 8 As shown in the diode 300, a groove extending in the Y direction is formed in the N well 101N and the element isolation film 102, and an insulating film 104 (see FIG. 104 ) is provided in the groove. Figure 4 ) is formed with a signal line 93. Figure 4 ) is formed with a contact hole 183 that reaches the local wiring 312. A signal line 83 is formed in the insulating film 153. The signal line 83 extends in the X direction and is connected to the local wiring 312 through a conductor in the contact hole 183. Between the signal line 83 and the signal line 93, there is a gap between the insulating film 152 and the insulating film 151 (see Figure 4 ) is formed with a contact hole 2193, and the signal line 83 is connected to the signal line 93 through the conductor in the contact hole 2193. In addition, a local wiring and a contact hole connected to the local wiring, the signal line 83 and the signal line 93 may be formed at the position where the contact hole 2193 is formed.

[0075] In the diode 300, another groove extending in the Y direction is formed in the N well 101N and the element isolation film 102, and the insulating film 104 (see FIG. Figure 4 ) is formed with a power supply wiring 92. Figure 4 ) is formed with a contact hole 182 that reaches the local wiring 322. Figure 4 ) is formed in the contact hole 182, and the power supply wiring 82 extends in the X direction and is connected to the local wiring 322 through the conductor in the contact hole 182. Between the power supply wiring 82 and the power supply wiring 92, an insulating film 152 and an insulating film 151 (see Figure 4 ) is formed with a contact hole 2192, and the power wiring 82 is connected to the power wiring 92 through the conductor in the contact hole 2192. In addition, a local wiring and a contact hole connected to the local wiring, the power wiring 92 and the power wiring 82 may be formed at the position where the contact hole 2192 is formed.

[0076] In the second embodiment, two groups including four P-type fins 311, four local wirings 312, four contact holes 183, five dummy gate electrodes 310, and one signal line 83 are provided in the diode 300. In addition, two groups including four N-type fins 321, four local wirings 322, four contact holes 182, five dummy gate electrodes 320, and one power supply wiring 82 are provided in the diode 300.

[0077] The other structures are the same as those of the first embodiment.

[0078] In the second embodiment, the diode 200 includes the power supply wiring 91 and the signal line 93 as buried wiring, and the diode 300 includes the power supply wiring 92 and the signal line 93 as buried wiring. In this way, according to the second embodiment, an ESD protection circuit including buried wiring can be realized. Therefore, it is suitable for further miniaturization of semiconductor devices.

[0079] Furthermore, a power supply network is formed by a power supply wiring 91 extending in the Y direction and a plurality of power supply wirings 81 extending in the X direction. A power supply network is formed by a power supply wiring 92 extending in the Y direction and a plurality of power supply wirings 82 extending in the X direction. A power supply network is formed by a signal line 93 extending in the Y direction and a plurality of signal lines 83 extending in the X direction. Therefore, the current flowing in each diode can be further made uniform. In addition, compared with a structure in which the power supply wiring or signal line constituting the power supply network is formed only above the fin, the uniformity of the current can be further improved.

[0080] Furthermore, at least a portion of the power wiring or signal line extending in the Y direction and at least a portion of the power wiring or signal line extending in the X direction may be formed on the substrate 101 within a range where wirings of different potentials or signals are not connected to each other. In addition, the number of configurations of each fin, dummy gate electrode, local wiring, and group of these components may be appropriately changed in the diodes 200 and 300. In other embodiments and modified examples, such a change in the number of configurations may also be performed in the same manner.

[0081] In other embodiments and modifications, at least a portion of the power supply wiring or the signal line may be formed on the substrate 101 so as to extend in the Y direction.

[0082] (Third Embodiment)

[0083] Next, a third embodiment will be described. The third embodiment is different from the first embodiment mainly in the scale of the diode. Fig. 9 1 is a schematic diagram showing a planar structure of a diode 200 and a diode 300 in the third embodiment. Fig.10It is a cross-sectional view showing a portion between the diode 200 and the diode 300 in the third embodiment. Fig.10 is equivalent to following Fig. 9 Cross-sectional view of line Y13-Y23 in the figure.

[0084] like Fig. 9 As shown in FIG. 1 , in the third embodiment, the diode 200 and the diode 300 are arranged side by side in the X direction. A plurality of (three in this case) signal lines 93 are provided so as to be shared by the diode 200 and the diode 300. Fig.10 As shown, a contact hole 193 reaching the signal line 93 is formed in the insulating film 103 between the diode 200 and the diode 300. A local wiring 122 connected to the signal line 93 via a conductor in the contact hole 193 is formed in the element isolation film 102. A contact hole 183 reaching the local wiring 122 is formed in the insulating film 152. A signal line 83 is formed in the insulating film 153, and the signal line 83 extends in the X direction and is connected to the local wiring 122 via a conductor in the contact hole 183.

[0085] The diode 200 includes a main portion 201 and a guard ring portion 202 . The guard ring portion 202 surrounds the main portion 201 in a plan view.

[0086] In the main part 201, four N-type fins 211, four P-type fins 221, and four N-type fins 211 are sequentially arranged between two adjacent signal lines 83 in the Y direction. As described above, three signal lines 83 are arranged. Therefore, the main part 201 has two groups including four N-type fins 211, four P-type fins 221, and four N-type fins 211. In addition, similar to the first embodiment, local wirings 212 and local wirings 222, dummy gate electrodes 210 and dummy gate electrodes 220, contact holes 193 and contact holes 181, and power wiring 81 are arranged.

[0087] A plurality of P-type fins 221 are arranged in a ring shape in the guard ring portion 202. In addition, the guard ring portion 202 has a local wiring 222 connected to the P-type fins 221 and a power wiring 81 connected to the local wiring 222. A portion of the power wiring 81 in the guard ring portion 202 may also be shared with a portion of the power wiring 81 in the main portion 201.

[0088] The diode 300 includes a main portion 301 and a guard ring portion 302 . The guard ring portion 302 surrounds the main portion 301 in a plan view.

[0089] In the main part 301, four P-type fins 311, four N-type fins 321, and four P-type fins 311 are sequentially arranged between two adjacent signal lines 83 in the Y direction. As described above, three signal lines 83 are provided. Therefore, the main part 301 has two groups including four P-type fins 311, four N-type fins 321, and four P-type fins 311. In addition, similar to the first embodiment, local wirings 312 and local wirings 322, dummy gate electrodes 310 and dummy gate electrodes 320, contact holes 193 and contact holes 182, and power wiring 82 are provided.

[0090] In the guard ring portion 302, a plurality of N-type fins 321 are arranged in a ring shape. In addition, the guard ring portion 302 has a local wiring 322 connected to the N-type fins 321 and a power wiring 82 connected to the local wiring 322. A portion of the power wiring 82 in the guard ring portion 302 may also be shared with a portion of the power wiring 82 in the main portion 301.

[0091] In the third embodiment, for example, the signal line 83 connected to the local wiring 122 is connected to the I / O pad 33. In addition, the diode 200 and the diode 300 include a common signal line 93 electrically connected to the signal line 83 as an embedded wiring. In this way, according to the third embodiment, an ESD protection circuit including embedded wiring can be realized. In addition, since the diode 200 includes the guard ring portion 202 and the diode 300 includes the guard ring portion 302, it is possible to suppress current leakage from the main portion 201 and the main portion 301 to the outside.

[0092] The power supply wiring connected to the VSS pad 31 or the power supply wiring connected to the VDD pad 32 may be embedded wiring. In addition, both the power supply wiring connected to the VSS pad 31 and the power supply wiring connected to the VDD pad 32 may be embedded wiring.

[0093] (First Modification of the Third Embodiment)

[0094] Next, a first modification of the third embodiment will be described. The first modification is different from the third embodiment mainly in that a signal line 83 is provided in parallel with a signal line 93 . Fig.11 1 is a schematic diagram showing a planar structure of a diode 200 and a diode 300 in a first modification example of the third embodiment.

[0095] like Fig.11 As shown, in the first modification, in the main portion 201 of the diode 200, the insulating film 152 (see Figure 4) A contact hole 183 is formed to reach the local wiring 212. A signal line 83 is formed in the insulating film 153. The signal line 83 extends in the X direction and is connected to the local wiring 212 through a conductor in the contact hole 183.

[0096] In addition, in the main portion 301 of the diode 300, the insulating film 152 (see Figure 4 ) A contact hole 183 is formed to reach the local wiring 312. A signal line 83 is formed in the insulating film 153. The signal line 83 extends in the X direction and is connected to the local wiring 312 through a conductor in the contact hole 183.

[0097] The other structures are the same as those of the third embodiment.

[0098] The first modification example can also achieve the same effects as those of the third embodiment. In addition, the diode 200 is provided with the signal line 83 connected to the local wiring 212 connected to the signal line 93, and the diode 300 is provided with the signal line 83 connected to the local wiring 312 connected to the signal line 93. Therefore, the resistance of the signal path in which the signal input to the I / O pad 33 propagates can be reduced.

[0099] In addition, the signal line 83 in the diode 200 and the signal line 83 in the diode 300 may be connected to each other above the substrate 101 .

[0100] When a part of the power wiring connected to the VSS pad 31 is embedded, in order to reduce resistance, the power wiring connected to the local wiring connected to the embedded wiring may be arranged above the substrate 101. Similarly, when a part of the power wiring connected to the VDD pad 32 is embedded, in order to reduce resistance, the power wiring connected to the local wiring connected to the embedded wiring may be arranged above the substrate 101.

[0101] (Second Modification of the Third Embodiment)

[0102] Next, a second modification of the third embodiment will be described. The second modification is different from the third embodiment mainly in that a signal line is provided in an upper layer in parallel with the signal line 93 . Fig.12 1 is a schematic diagram showing a planar structure of a diode 200 and a diode 300 in a second modification of the third embodiment.

[0103] like Fig.12As shown, in the second modification, four signal lines 84 are provided, for example, in a layer above the insulating film 153, so as to be shared by the diode 200 and the diode 300. The signal line 84 extends, for example, in the X direction. The signal line 84 is connected to the local wiring 212 in the main part 201 of the diode 200 and the local wiring 312 in the main part 301 of the diode 300.

[0104] The other structures are the same as those of the third embodiment.

[0105] The second modification can also achieve the same effects as those of the third embodiment. In addition, a signal line 84 is provided, and the signal line 84 is connected to the local wiring 212 connected to the signal line 93 in the diode 200, and is connected to the local wiring 312 connected to the signal line 93 in the diode 300. Therefore, the resistance of the signal path in which the signal input to the I / O pad 33 propagates can be reduced.

[0106] In addition, the signal line 84 in the diode 200 and the signal line 84 in the diode 300 may be separated from each other above the substrate 101. The signal line 84 may be formed on a layer different from the power wiring 81 and the power wiring 82, or may be formed on the same layer as the power wiring 81 and the power wiring 82 to be insulated from the power wiring 81 and the power wiring 82.

[0107] In other embodiments and modifications, the embedded wiring and the power supply wiring or signal line provided above the substrate may be connected in the local wiring.

[0108] (Third Modification of Third Embodiment)

[0109] Next, a third modification of the third embodiment will be described. The third modification is different from the third embodiment mainly in the number of fins. Fig.13 1 is a schematic diagram showing a planar structure of a diode 200 and a diode 300 in a third modification of the third embodiment.

[0110] like Fig.13 As shown in the third modification, the main part 201 of the diode 200 has two groups including two N-type fins 211, four P-type fins 221, and two N-type fins 211. In addition, the signal line 93 is formed below the other end of the local wiring 212 extending from the signal line 93 shared by the diode 200 and the diode 300 in the Y direction. Moreover, the other end is formed on the insulating film 103 (see Figure 4 ) is connected to the conductor in the contact hole 193 of the signal line 93.

[0111] The main part 301 of the diode 300 has two groups including two P-type fins 311, four N-type fins 321, and two P-type fins 311. In addition, the signal line 93 is formed below the other end of the local wiring 312 extending from the signal line 93 shared by the diode 200 and the diode 300 in the Y direction. And, the other end is formed on the insulating film 103 (see Figure 4 ) is connected to the conductor in the contact hole 193 of the signal line 93.

[0112] The other structures are the same as those of the third embodiment.

[0113] The third modification can also achieve the same effects as those of the third embodiment. In addition, the local wiring 212 is connected to two signal lines 93 in the diode 200, and the local wiring 312 is connected to two signal lines 93 in the diode 300. Therefore, the resistance of the signal path in which the signal input to the I / O pad 33 propagates can be reduced.

[0114] As in the third variant, the number of multiple fins of the same conductivity type arranged near the embedded wiring (here, signal line 93) may be different from the number of fins of different conductivity type arranged next to it. For example, the former may be less than the latter. In addition, the embedded wiring may be provided on the side with fewer fins.

[0115] In addition, the number of fins in the guard ring portion 202 or the guard ring portion 302 may correspond to the number of fins in the main portion 201 or the main portion 301. For example, the number of fins in the guard ring portion 202 or the guard ring portion 302 may be reduced to correspond to a portion in which the number of fins in the main portion 201 or the main portion 301 is smaller. In this case, the circuit scale is reduced, and the semiconductor device can be miniaturized easily.

[0116] (Fourth Modification of Third Embodiment)

[0117] Next, a fourth modification of the third embodiment will be described. The fourth modification is different from the third embodiment mainly in that dummy wirings are provided outside the guard ring portion 202 and the guard ring portion 302 . Fig.14 1 is a schematic diagram showing a planar structure of a diode 200 and a diode 300 in a fourth modification of the third embodiment.

[0118] like Fig.14 As shown, in the fourth modification, in the Y direction, outside the guard ring portion 202 and the guard ring portion 302, on the substrate 101 and the element separation film 102 (see Figure 4 , Figure 6 ) is formed with a groove extending in the X direction, and an insulating film 104 (see Figure 4 , Figure 6) is formed with a dummy wiring 94. For example, the surface of the dummy wiring 94 is covered by the insulating film 103. For example, the surface of the element separation film 102 and the surface of the insulating film 103 may be in the same plane as the surface of the substrate 101, or may not be in the same plane. For example, the dummy wiring 94 is in an electrically floating state.

[0119] The other structures are the same as those of the third embodiment.

[0120] The fourth modification can also achieve the same effects as those of the third embodiment. Furthermore, in the manufacturing process, the density variation of the embedded wiring can be reduced, and the dimensional variation is less likely to occur.

[0121] Furthermore, the dummy wiring 94 may also be provided inside the guard ring portion 202 and inside the guard ring portion 302 .

[0122] In other embodiments and modified examples, dummy wiring 94 may be provided.

[0123] (Fifth Modification of the Third Embodiment)

[0124] Next, a fifth modification of the third embodiment will be described. The fifth modification is different from the third embodiment mainly in that the guard ring portion is provided in multiple layers. Fig.15 It is a schematic diagram showing the outline of the diode 200 and the diode 300 in the fifth modification of the third embodiment. Fig.16 It is a schematic diagram showing, in an enlarged manner, a main part of a fifth modification example of the third embodiment. Fig.16 Corresponds to Fig.15 The area R1 is shown by the double-dashed line in FIG.

[0125] like Fig.15 As shown, in the fifth modification, the diode 200 includes a main portion 201 and a guard ring portion 202 provided in the P well 101P, and a guard ring portion 203 of the N well 102N provided around the guard ring portion 202. In addition, the diode 300 includes a main portion 301 and a guard ring portion 302 provided in the N well 101N, and a guard ring portion 303 of the P well 102P provided around the guard ring portion 302.

[0126] like Fig.16 As shown, in the guard ring portion 203, a plurality of N-type fins 211 are arranged in a ring shape. In addition, the guard ring portion 203 has a local wiring 212 connected to the N-type fins 211 and a power wiring 82 connected to the local wiring 212. In the guard ring portion 303, a plurality of P-type fins 311 are arranged in a ring shape. In addition, the guard ring portion 303 has a local wiring 312 connected to the P-type fins 311 and a power wiring 81 connected to the local wiring 312.

[0127] The other structures are the same as those of the third embodiment.

[0128] The fifth modification can also achieve the same effects as those of the third embodiment. Furthermore, since the guard rings 203 and 303 are provided, leakage of current from the main parts 201 and 301 to the outside can be further suppressed. The guard rings may be formed in three or more layers.

[0129] The dummy wiring 94 of the fourth modified example may be provided between the guard ring portion 202 and the guard ring portion 203. In addition, another dummy wiring 94 may be provided outside the guard ring portion 203. Similarly, the dummy wiring 94 may be provided between the guard ring portion 302 and the guard ring portion 303. In addition, another dummy wiring 94 may be provided outside the guard ring portion 303.

[0130] In other embodiments and modified examples, multiple guard ring portions may be provided, and dummy wirings 94 may be provided between or outside multiple guard ring portions.

[0131] (Fourth Embodiment)

[0132] Next, a fourth embodiment will be described. The fourth embodiment is different from the third embodiment mainly in that the power supply wiring is a buried wiring. Fig.17 1 is a schematic diagram showing a planar structure of a diode 200 and a diode 300 in the fourth embodiment. Fig.18 2 is a cross-sectional view showing a diode 200 according to a fourth embodiment. Fig.19 1 is a cross-sectional view showing a diode 300 according to a fourth embodiment. Fig.18 Equivalent to following Fig.17 Cross-sectional view of line Y14-Y24 in the figure. Fig.19 Equivalent to following Fig.17 Cross-sectional view of the Y15-Y25 line.

[0133] like Figure 17 to Figure 19 As shown, in the fourth embodiment, six signal lines 83 are provided to be shared by the diodes 200 and 300. The signal line 83 is connected to the local wiring 212 in the main part 201 and the local wiring 312 in the main part 301 through the conductor in the contact hole 183.

[0134] like Fig.17 as well as Fig.18As shown in FIG. 1 , in the diode 200, in the Y direction, a power supply wiring 81 is provided between the first signal line 83 and the second signal line 83, between the third signal line 83 and the fourth signal line 83, and between the fifth signal line 83 and the sixth signal line 83 among the six signal lines 83 from one side. The power supply wiring 81 is connected to the local wiring 222 through the conductor in the contact hole 181. In the Y direction, a power supply wiring 91 is provided between the second signal line 83 and the third signal line 83, and between the fourth signal line 83 and the fifth signal line 83 among the six signal lines 83 from one side. The power supply wiring 91 is connected to the local wiring 222 through the insulating film 104 (see FIG. 1 ). Figure 4 ) is formed in a groove formed in the P well 101P and the element isolation film 102. In the guard ring portion 202, the local wiring 222 is connected to the power supply wiring 91 through a conductor formed in the contact hole 191 of the insulating film 103.

[0135] In the Y direction, the ends of the second to fifth signal lines 83 from one side of the six signal lines 83 on the opposite side to the diode 300 are located in the main part 201, and the power supply wiring 81 is provided on the extension lines of the second to fifth signal lines 83 in the guard ring part 202. The power supply wiring 81 is connected to the power supply wiring 91.

[0136] like Fig.17 as well as Fig.19 As shown in FIG. 1 , in the diode 300, in the Y direction, power supply wiring 82 is provided between the first signal line 83 and the second signal line 83, between the third signal line 83 and the fourth signal line 83, and between the fifth signal line 83 and the sixth signal line 83 among the six signal lines 83 from one side. The power supply wiring 82 is connected to the local wiring 322 through the conductor in the contact hole 182. In the Y direction, power supply wiring 92 is provided between the second signal line 83 and the third signal line 83, and between the fourth signal line 83 and the fifth signal line 83 among the six signal lines 83 from one side. The power supply wiring 92 is connected to the local wiring 322 through the insulating film 104 (see FIG. 1 ). Figure 4 ) is formed in a groove formed in the N well 101N and the element isolation film 102. In the guard ring portion 302, the local wiring 322 is connected to the power supply wiring 92 through a conductor formed in the contact hole 192 of the insulating film 103.

[0137] In the Y direction, the ends of the second to fifth signal lines 83 from one side of the six signal lines 83 on the opposite side to the diode 200 are located in the main part 301, and the power supply wiring 82 is provided on the extension lines of the second to fifth signal lines 83 in the guard ring part 302. The power supply wiring 82 is connected to the power supply wiring 92.

[0138] In the fourth embodiment, the diode 200 includes the power supply wiring 91 as a buried wiring, and the diode 300 includes the power supply wiring 92 as a buried wiring. As described above, according to the fourth embodiment, an ESD protection circuit including a buried wiring can be realized.

[0139] In addition, the power supply wiring 91 is formed in the P well 101P, and the power supply potential of VSS is supplied to both the power supply wiring 91 and the P well 101P. Therefore, the parasitic capacitance between the power supply wiring 91 and the P well 101P can be reduced. Similarly, the power supply wiring 92 is formed in the N well 101N, and the power supply potential of VDD is supplied to both the power supply wiring 92 and the N well 101N. Therefore, the parasitic capacitance between the power supply wiring 92 and the N well 101N can be reduced.

[0140] In the fourth embodiment, for example, the power supply potential of VSS is supplied to the power supply wiring 81 provided above the guard ring portion 202. Fig.17 As shown by the arrow in , the power supply potential of VSS can be supplied to a part of the guard ring portion 202 via the power supply wiring 91. Therefore, the wiring arranged above the P-type fin 221 in order to supply the power supply potential to the guard ring portion 202 can be reduced. Similarly, the power supply potential of VDD can be supplied to a part of the guard ring portion 302 via the power supply wiring 92. Therefore, the wiring arranged above the N-type fin 321 in order to supply the power supply potential to the guard ring portion 302 can be reduced. Therefore, the degree of freedom of the layout of the wiring layer can be improved. For example, as in the present embodiment, the signal line 83 can be configured to be shared by the diode 200 and the diode 300. Such a structure can also be applied to other embodiments and modified examples.

[0141] In addition, in a portion of the guard ring portion 202, a local wiring 222 is shared between adjacent groups of four P-type fins 221. Fig.17 As shown by the arrow in , the power supply potential of VSS supplied from the power supply wiring 81 to the local wiring 222 can be applied to both groups. Therefore, even if the P-type fin 221 overlaps with the signal line 83 in the thickness direction, the power supply potential of VSS can be supplied to the P-type fin 221. Similarly, in a portion of the guard ring portion 302, the local wiring 322 is shared between the groups of four adjacent N-type fins 321. Therefore, as Fig.17 As shown by the arrows in , the power supply potential of VDD supplied from the power supply wiring 82 to the local wiring 322 can be applied to the two groups. Therefore, even if the N-type fin 321 and the signal line 83 overlap in the thickness direction, the power supply potential of VDD can be supplied to the N-type fin 321. Such a structure can also be applied to other embodiments and modified examples.

[0142] (First Modification of Fourth Embodiment)

[0143] Next, a first modification of the fourth embodiment will be described. The first modification is different from the fourth embodiment mainly in a configuration for supplying a power supply potential to a power supply wiring. Fig. 20 1 is a schematic diagram showing a planar structure of a diode 200 and a diode 300 in a first modification example of the fourth embodiment.

[0144] like Fig. 20 As shown in the first modification, in the diode 200, in the Y direction, the ends of the second to fifth signal lines 83 from one side among the six signal lines 83 on the opposite side to the diode 300 are located in the guard ring portion 202. The local wiring 123 provided outside the guard ring portion 202 is connected to the power wiring 91 through the conductor in the contact hole 191. In addition, the power wiring 81 is connected to the local wiring 123 through the conductor in the contact hole 181.

[0145] In the diode 300, the ends of the second to fifth signal lines 83 from one side in the Y direction on the opposite side to the diode 200 are located in the guard ring portion 302. The local wiring 124 provided outside the guard ring portion 302 is connected to the power wiring 92 via the conductor in the contact hole 192. In addition, the power wiring 82 is connected to the local wiring 124 via the conductor in the contact hole 182.

[0146] The other structures are the same as those of the fourth embodiment.

[0147] In the fourth embodiment, for example, the power supply wiring 81 connected to the local wiring 123 is connected to the VSS pad 31, and the power supply wiring 82 connected to the local wiring 124 is connected to the VDD pad 32. Also, similar to the fourth embodiment, the power supply potential VSS or VDD is supplied to the main portion 201 and the main portion 301, and the guard ring portion 202 and the guard ring portion 302.

[0148] The first modification example can also provide the same effects as those of the fourth embodiment.

[0149] In other embodiments and modifications, as in the first modification, the power supply potential may be supplied from the outside of the guard ring portion 202 and the guard ring portion 302 .

[0150] (Second Modification of Fourth Embodiment)

[0151] Next, a second modification of the fourth embodiment will be described. The second modification is different from the fourth embodiment mainly in the configuration for supplying a power supply potential to the power supply wiring. Fig.21 1 is a schematic diagram showing a supply unit of a power supply potential to the power supply wiring 91 in a second modification of the fourth embodiment. Fig. 221 is a cross-sectional view showing a portion for supplying a power supply potential to the power supply wiring 91 in a second modification of the fourth embodiment. Fig. 22 is equivalent to following Fig.21 Cross-sectional view of line Y16-Y26 in the figure.

[0152] like Fig.21 as well as Fig. 22 As shown, in the second modification, outside the guard ring portion 202 of the diode 200, a contact hole 191A that reaches the power wiring 91 is formed in the insulating film 151 and the insulating film 103. A conductive plug 91A is formed in the contact hole 191A. Furthermore, the power wiring 81 is connected to the conductive plug 91A through the conductor in the contact hole 181.

[0153] The diode 300 is similarly configured. In other words, although not shown in the figure, a contact hole that reaches the power wiring 92 is formed in the insulating film 151 and the insulating film 103 outside the guard ring portion 302, and a conductive plug is formed in the contact hole. The power wiring 82 is connected to the conductive plug via a conductor in the contact hole 182.

[0154] The other structures are the same as those of the fourth embodiment.

[0155] The second modification example can also provide the same effects as those of the first modification example of the fourth embodiment.

[0156] (Third Modification of Fourth Embodiment)

[0157] Next, a third modification of the fourth embodiment will be described. The third modification is different from the fourth embodiment mainly in the configuration for supplying a power supply potential to the power supply wiring. Fig.23 1 is a schematic diagram showing a supply unit of a power supply potential to the power supply wiring 91 in a third modification of the fourth embodiment. Fig.24 It is a cross-sectional view showing a portion for supplying a power supply potential to the power supply wiring 91 in a third modification of the fourth embodiment. Fig.24 is equivalent to following Fig.23 Cross-sectional view of line X11-X21 in .

[0158] like Fig.23 as well as Fig.24 As shown, the third modification example includes a first semiconductor chip 510 and a second semiconductor chip 520 .

[0159] The first semiconductor chip 510 has the same structure as the second variant of the fourth embodiment except for the following points. In the first semiconductor chip 510, a via hole 511 is formed on the substrate 101 outside the guard ring portion 202 to reach the power wiring 91 from the back side, and a through hole 512 is embedded in the via hole 511. In addition, outside the guard ring portion 202, the power wiring 91 is covered by the insulating film 103 and the insulating films 151 to 153. The first semiconductor chip 510 has the same structure as the second variant of the fourth embodiment except for these points.

[0160] The second semiconductor chip 520 includes an insulating film 521 and a power supply wiring 522 provided on the surface of the insulating film 521. A power supply potential of VSS is supplied to the power supply wiring 522. The insulating film 521 is formed, for example, on a substrate (not shown).

[0161] The diode 300 is similarly configured. In other words, although not shown in the figure, a via hole is formed in the substrate 101 outside the guard ring portion 302 so as to reach the power supply wiring 92 from the back surface, and a through hole is buried in the via hole.

[0162] In addition, the second semiconductor chip 520 has a power supply wiring for supplying a power supply potential of VDD on the surface of the insulating film 521 .

[0163] The first semiconductor chip 510 and the second semiconductor chip 520 are bonded to each other so that the power wiring 522 is connected to the through hole 512 in the diode 200 and the power wiring for supplying the power supply potential of VDD is connected to the through hole in the diode 300 .

[0164] In the third modification, power supply line 522 of second semiconductor chip 520 can supply power supply line 91 of diode 200 with power supply potential VSS through via 512. Similarly, power supply line 92 of diode 300 can be supplied with power supply potential VDD from power supply line 522 of second semiconductor chip 520 through via.

[0165] The third modification can also achieve the same effects as those of the fourth embodiment. In addition, the number of power supply wirings 81 and 82 provided in the diode 200 and the diode 300 of the first semiconductor chip 510 can be reduced, thereby increasing the degree of freedom in the layout of the wiring layer.

[0166] In other embodiments and modifications, the second semiconductor chip 520 may be used to route power supply wiring and signal lines. For example, in a structure where the first semiconductor chip 510 includes the signal line 93 as a buried wiring, the second semiconductor chip 520 may have a signal line on the surface of the insulating film 521 .

[0167] Furthermore, the connection destination of the through hole such as the through hole 512 may not be the embedded wiring but a wiring formed in the insulating film 153 or the like. For example, it may be connected to the power supply wiring 81 in the guard ring portion 202 or to the power supply wiring 82 in the guard ring portion 302.

[0168] (Fifth Embodiment)

[0169] Next, a fifth embodiment will be described. The fifth embodiment is different from the first embodiment mainly in the arrangement structure of the fins.

[0170] First, the structure of the diode 200 in the fifth embodiment will be described. Fig.25 1 is a schematic diagram showing a planar structure of a diode 200 according to the fifth embodiment. Fig.26 as well as Fig. 27 2 is a cross-sectional view showing a diode 200 according to the fifth embodiment. Fig.26 is equivalent to following Fig.25 Cross-sectional view of line Y17-Y27 in the figure. Fig. 27 is equivalent to following Fig.25 Cross-sectional view of line Y18-Y28 in the figure.

[0171] like Figure 25 to Figure 27 As shown, similar to the first embodiment, a signal line 93 extending in the X direction is formed. On the P well 101P exposed from the element separation film 102, a plurality of fins 280 are formed on both sides of the signal line 93 in the Y direction, wherein the fins 280 extend in the X direction and stand upright in the Z direction. Here, every four fins 280 are formed on both sides of the signal line 93. Each fin 280 has a plurality of (two each in this case) N-type regions 261 and P-type regions 271 alternately arranged. The N-type regions 261 of each fin 280 are arranged in the Y direction, and the P-type regions 271 of each fin 280 are arranged in the Y direction.

[0172] A plurality of local wirings 232 extending in the Y direction and connected to each N-type region 261 are formed on the element separation film 102. Here, two local wirings 232 are formed. A plurality of local wirings 242 extending in the Y direction and connected to each P-type region 271 are formed on the element separation film 102. Here, two local wirings 242 are formed. A plurality of dummy gate electrodes 230 such as gate electrodes of so-called fin transistors are arranged in the X direction in a manner that sandwiches the local wirings 232 or the local wirings 242. The dummy gate electrode 230 extends in the Y direction. A dummy gate insulating film (not shown) is formed between the dummy gate electrode 230 and the fin 280.

[0173] like Fig.25 as well as Fig.26As shown, a contact hole 193 is formed in the insulating film 103 between the local wiring 232 and the signal line 93 , and the local wiring 232 is connected to the signal line 93 via a conductor in the contact hole 193 .

[0174] like Fig.25 as well as Fig. 27 As shown, a contact hole 181 reaching the local wiring 242 is formed in the insulating film 152. A power wiring 81 is formed in the insulating film 153. The power wiring 81 extends in the X direction and is connected to the local wiring 242 through a conductor in the contact hole 181. For example, the power wiring 81 is connected to the VSS pad 31.

[0175] Next, the structure of the diode 300 in the fifth embodiment will be described. Fig.28 It is a schematic diagram showing a planar structure of a diode 300 in the fifth embodiment. Fig.29 as well as Fig.30 1 is a cross-sectional view showing a diode 300 according to the fifth embodiment. Fig.29 is equivalent to following Fig.28 Cross-sectional view of the Y19-Y29 line. Fig.30 is equivalent to following Fig.28 Cross-sectional view of the Y20-Y30 line.

[0176] like Figures 28 to 30 As shown, similar to the first embodiment, a signal line 93 extending in the X direction is formed. On the N well 101N exposed from the element separation film 102, each plurality of fins 380 is formed on both sides of the signal line 93 in the Y direction, wherein the fins 380 extend in the X direction and stand upright in the Z direction. Here, every four fins 380 are formed on both sides of the signal line 93. Each fin 380 has a plurality of (here two) P-type regions 361 and N-type regions 371 alternately arranged. The P-type regions 361 of each fin 380 are arranged in the Y direction, and the N-type regions 371 of each fin 380 are arranged in the Y direction.

[0177] A plurality of local wirings 332 extending in the Y direction and connected to each P-type region 361 are formed on the element separation film 102. Here, two local wirings 332 are formed. A plurality of local wirings 342 extending in the Y direction and connected to each N-type region 371 are formed on the element separation film 102. Here, two local wirings 342 are formed. A plurality of dummy gate electrodes 330 such as gate electrodes of so-called fin transistors are arranged in the X direction in a manner that the local wirings 332 or the local wirings 342 are sandwiched in the middle. The dummy gate electrode 330 extends in the Y direction. A dummy gate insulating film (not shown) is formed between the dummy gate electrode 330 and the fin 380.

[0178] like Fig.28 as well as Fig.29 As shown, a contact hole 193 is formed in the insulating film 103 between the local wiring 332 and the signal line 93 , and the local wiring 332 is connected to the signal line 93 via a conductor in the contact hole 193 .

[0179] like Fig.28 as well as Fig.30 As shown, a contact hole 182 reaching the local wiring 342 is formed in the insulating film 152. A power wiring 82 is formed in the insulating film 153. The power wiring 82 extends in the X direction and is connected to the local wiring 342 through a conductor in the contact hole 182. For example, the power wiring 82 is connected to the VDD pad 32.

[0180] In the fifth embodiment, the diode 200 includes the signal line 93 as a buried wiring, and the diode 300 includes the signal line 93 as a buried wiring. Thus, according to the fifth embodiment, an ESD protection circuit including buried wiring can be realized. Therefore, it is suitable for further miniaturization of semiconductor devices.

[0181] In addition, in the diode 200, a power supply wiring connected to the local wiring 242 may be formed as a buried wiring in the P well 101P instead of the power supply wiring 81. Similarly, in the diode 300, a power supply wiring connected to the local wiring 342 may be formed as a buried wiring in the N well 101N instead of the power supply wiring 82. In these cases, in the diodes 200 and 300, a signal line connected to the local wiring 232 and a signal line connected to the local wiring 332 may be formed in the insulating film 153 instead of the signal line 93.

[0182] (Sixth Embodiment)

[0183] Next, the sixth embodiment will be described. The sixth embodiment is different from the fifth embodiment mainly in the scale of the diode. Fig.31 1 is a schematic diagram showing a planar structure of a diode 200 and a diode 300 in the sixth embodiment.

[0184] like Fig.31 As shown in FIG. 1 , in the sixth embodiment, the diode 200 and the diode 300 are arranged side by side in the X direction. Three signal lines 93 are provided so as to be shared by the diode 200 and the diode 300 .

[0185] In the main part 201 of the diode 200, a power supply wiring 91 extending in the X direction is provided between two signal lines 93 adjacent in the Y direction. In the Y direction, a plurality of fins 280 are provided so as to sandwich the signal line 93 or the power supply wiring 91. As in the fifth embodiment, each fin 280 has a plurality of N-type regions 261 and a plurality of P-type regions 271 arranged alternately. As in the fifth embodiment, a local wiring 232 connected to the N-type region 261 and a plurality of local wirings 242 connected to the P-type region 271 are formed on the element separation film 102. The local wiring 232 is connected to the signal line 93 through the conductor in the contact hole 193. In other words, the signal line 93 is connected to the N-type region 261 via the local wiring 232. The local wiring 242 is connected to the power supply wiring 91 through the conductor in the contact hole 191. In other words, the power supply wiring 91 is connected to the P-type region 271 via the local wiring 242.

[0186] Furthermore, in the insulating film 153 (see Fig.26 , Fig. 27 ) are formed in the contact hole 181, and a power supply wiring 81 connected to the local wiring 242 through a conductor in the contact hole 181, and a signal line 83 connected to the local wiring 232 through a conductor in the contact hole 183.

[0187] In the main part 301 of the diode 300, a power supply wiring 92 extending in the X direction is provided between two signal lines 93 adjacent in the Y direction. In the Y direction, a plurality of fins 380 are provided so as to sandwich the signal line 93 or the power supply wiring 92. As in the fifth embodiment, each fin 380 has a plurality of P-type regions 361 and N-type regions 371 arranged alternately. As in the fifth embodiment, a local wiring 332 connected to the P-type region 361 and a plurality of local wirings 342 connected to the N-type region 371 are formed on the element separation film 102. The local wiring 332 is connected to the signal line 93 through the conductor in the contact hole 193. In other words, the signal line 93 is connected to the P-type region 361 via the local wiring 332. The local wiring 342 is connected to the power supply wiring 91 via the conductor in the contact hole 191. In other words, the power supply wiring 91 is connected to the N-type region 371 via the local wiring 342.

[0188] Furthermore, in the insulating film 153 (see Fig.26 , Fig. 27 ) are formed in the contact hole 182, and a power supply wiring 82 connected to the local wiring 342 through a conductor in the contact hole 182, and a signal line 83 connected to the local wiring 332 through a conductor in the contact hole 183.

[0189] In the sixth embodiment, the diode 200 includes the power wiring 91 and the signal line 93 as buried wiring, and the diode 300 includes the power wiring 92 and the signal line 93 as buried wiring. In this way, according to the sixth embodiment, an ESD protection circuit including buried wiring can be realized. Therefore, it is suitable for further miniaturization of semiconductor devices. In addition, according to the sixth embodiment, since the buried wiring is provided, it is possible to make the current flow easily through the diode 200 and the diode 300.

[0190] Furthermore, similarly to the third embodiment, the parasitic capacitance between the power supply wiring 91 and the P-well 101P can be reduced, and the parasitic capacitance between the power supply wiring 92 and the N-well 101N can be reduced.

[0191] In addition, it is not necessary to provide embedded wiring at all positions between the four fin groups arranged in the Y direction, but it is possible to provide embedded wiring at a portion. In addition, in the diode 200, only one of the signal line 93 or the power supply wiring 91 may be provided as the embedded wiring, and in the diode 300, only one of the signal line 93 or the power supply wiring 92 may be provided as the embedded wiring.

[0192] For example, the material of the embedded wiring (power wiring 91, power wiring 92, signal line 93, pseudo wiring 94) can use ruthenium (Ru), cobalt (Co), tungsten (W), etc. For example, the material of the wiring (power wiring 81, power wiring 82, signal line 83, signal line 84) provided above the fin can use copper (Cu), ruthenium (Ru), cobalt (Co), etc. When copper or cobalt is used, it is preferred to form a conductive base film (barrier metal film), such as a tantalum (Ta) film or a tantalum nitride (TaN) film, but when ruthenium is used, the base film may not be formed.

[0193] For example, the material of the local wiring can use copper (Cu), ruthenium (Ru), cobalt (Co), or tungsten (W). In the case of using copper, cobalt, or tungsten, it is preferred to form a conductive base film (barrier metal film), such as a titanium (Ti) film or a titanium nitride (TiN) film, but in the case of using ruthenium, the base film may not be formed. For example, the conductor (through hole) in the contact hole can use the same material as the material of the local wiring, or the same material as the material of the wiring provided above the fin.

[0194] For example, the substrate can use a semiconductor such as silicon (Si). For example, the fin can be formed by patterning the substrate. A silicide of a high melting point metal such as nickel (Ni) or cobalt (Co) can also be provided in the portion of the fin that contacts the local wiring.

[0195] For example, the dummy gate electrode can be made of a conductive material such as titanium (Ti), titanium nitride (TiN), polysilicon (Poly Si), etc. For example, the dummy gate insulating film can be made of a high dielectric material such as hafnium oxide, aluminum oxide, or an oxide of hafnium and aluminum.

[0196] For example, the wiring (power wiring 81, power wiring 82, signal line 83, signal line 84) disposed above the fin is formed by dual damascene together with the contact hole disposed below the wiring. Alternatively, the wiring disposed above the fin may be formed independently of the contact hole disposed below the wiring by single damascene.

[0197] As mentioned above, the present invention has been described based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiment. These points can be changed within the scope that does not impair the gist of the present invention and can be appropriately determined according to the application mode.

[0198] Description of Reference Numerals

[0199] 1…semiconductor device, 10…internal circuit region, 20…I / O cell region, 31…VSS pad, 32…VDD pad, 33…I / O pad, 81, 82, 91, 92, 522…power supply wiring, 83, 84, 93…signal line, 94…pseudo wiring, 200, 300…diode, 201, 301…main part, 202, 203, 302, 303…guard ring part, 211, 321…N-type fin, 221, 311…P-type fin, 280, 380…fin, 261, 371…N-type region, 271, 361…P-type region, 400…ESD protection circuit

Claims

1. A semiconductor device, characterized in that: have: substrate; The circuit area has power wiring, ground wiring and signal lines; A first diode connected between the signal line and the first wiring; as well as a second diode connected between the signal line and the second wiring, The first wiring is one of the power wiring and the ground wiring. The first diode has: A first impurity region of a first conductivity type electrically connected to the signal line; and a second impurity region of a second conductivity type, the second conductivity type being different from the first conductivity type, the second impurity region being electrically connected to the first wiring, The second diode has: The third impurity region of the second conductivity type is electrically connected to the signal line; and The fourth impurity region of the first conductivity type is electrically connected to the second wiring. The signal line, or the first wiring, or both the signal line and the first wiring are formed on the substrate. The signal line, or the second wiring, or both the signal line and the second wiring are formed on the substrate. In a plan view, the signal line or the first wiring or both the signal line and the first wiring formed on the substrate extend in a direction parallel to a direction in which the first impurity region and the second impurity region are arranged. In a plan view, the signal line or the second wiring or both the signal line and the second wiring formed on the substrate extend in a direction parallel to a direction in which the third impurity region and the fourth impurity region are arranged.

2. The semiconductor device according to claim 1, wherein: The second wiring is the other of the power wiring and the ground wiring.

3. The semiconductor device according to claim 1, wherein: The signal line is formed on the substrate. A portion of the signal line connected to the first impurity region and a portion of the signal line connected to the third impurity region are connected to each other.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The first wiring and the second wiring are formed on the substrate.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that The first diode includes a fifth impurity region of the first conductivity type formed in the substrate. The second diode includes a sixth impurity region of the second conductivity type formed in the substrate, The first impurity region and the second impurity region are arranged separately from each other on the fifth impurity region. The third impurity region and the fourth impurity region are arranged to be separated from each other on the sixth impurity region.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that The first impurity region and the second impurity region are arranged adjacent to each other on the substrate. The third impurity region and the fourth impurity region are arranged adjacent to each other on the substrate.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that have: A first guard ring portion surrounds the first diode when viewed from above; and The second guard ring portion surrounds the second diode in a plan view.

8. The semiconductor device according to claim 7, wherein: supplying a power supply potential to the first wiring formed on the substrate from above the first guard ring portion, A power supply potential is supplied to the second wiring formed on the substrate from above the second guard ring portion.

9. The semiconductor device according to claim 7, wherein: supplying a power supply potential to the first wiring formed on the substrate from the outside of the first guard ring portion in a plan view, A power supply potential is supplied to the second wiring formed on the substrate from the outside of the second guard ring portion in a plan view.

10. The semiconductor device according to any one of claims 1 to 3, wherein: supplying a power supply potential to the first wiring formed on the substrate from the back side of the substrate, A power supply potential is supplied to the second wiring formed on the substrate from the back surface of the substrate.

11. The semiconductor device according to any one of claims 1 to 3, wherein: A pseudo wiring is provided, wherein the pseudo wiring is formed on the substrate, and the pseudo wiring is insulated from the signal line or the first wiring or both the signal line and the first wiring formed on the substrate, and the signal line or the second wiring or both the signal line and the second wiring formed on the substrate.

12. A semiconductor device, characterized in that: have: substrate; The circuit area has power wiring, ground wiring and signal lines; A first diode connected between the signal line and the first wiring; as well as a second diode connected between the signal line and the second wiring, The first wiring is one of the power wiring and the ground wiring. The second wiring is the other of the power wiring and the ground wiring. The first diode has: A first impurity region of a first conductivity type electrically connected to the signal line; and a second impurity region of a second conductivity type, the second conductivity type being different from the first conductivity type, the second impurity region being electrically connected to the first wiring, The second diode has: The third impurity region of the second conductivity type is electrically connected to the signal line; and The fourth impurity region of the first conductivity type is electrically connected to the second wiring. The signal line, or the first wiring, or both the signal line and the first wiring are formed on the substrate. The signal line, or the second wiring, or both the signal line and the second wiring are formed on the substrate. The first impurity region, the second impurity region, the third impurity region, and the fourth impurity region are formed in any one of a plurality of fins formed on the substrate. The number of first fins connected to the signal line or the first wiring or both the signal line and the first wiring formed on the substrate is less than the number of second fins adjacent to the first fins. The number of third fins among the plurality of fins connected to the signal line or the second wiring or both the signal line and the second wiring formed on the substrate is less than the number of fourth fins adjacent to the third fins.

13. The semiconductor device according to claim 12, wherein: The signal line is formed on the substrate. A portion of the signal line connected to the first impurity region and a portion of the signal line connected to the third impurity region are connected to each other.

14. The semiconductor device according to claim 12 or 13, characterized in that: The first wiring and the second wiring are formed on the substrate.

15. The semiconductor device according to claim 12 or 13, characterized in that: The first diode includes a fifth impurity region of the first conductivity type formed in the substrate. The second diode includes a sixth impurity region of the second conductivity type formed in the substrate, The first impurity region and the second impurity region are arranged separately from each other on the fifth impurity region. The third impurity region and the fourth impurity region are arranged to be separated from each other on the sixth impurity region.

16. The semiconductor device according to claim 12 or 13, characterized in that: The first impurity region and the second impurity region are arranged adjacent to each other on the substrate. The third impurity region and the fourth impurity region are arranged adjacent to each other on the substrate.

17. The semiconductor device according to claim 12 or 13, characterized in that: have: A first guard ring portion surrounds the first diode when viewed from above; and The second guard ring portion surrounds the second diode in a plan view.

18. The semiconductor device according to claim 17, wherein: supplying a power supply potential to the first wiring formed on the substrate from above the first guard ring portion, A power supply potential is supplied to the second wiring formed on the substrate from above the second guard ring portion.

19. The semiconductor device according to claim 17, wherein: supplying a power supply potential to the first wiring formed on the substrate from the outside of the first guard ring portion in a plan view, A power supply potential is supplied to the second wiring formed on the substrate from the outside of the second guard ring portion in a plan view.

20. The semiconductor device according to claim 12 or 13, characterized in that supplying a power supply potential to the first wiring formed on the substrate from the back side of the substrate, A power supply potential is supplied to the second wiring formed on the substrate from the back surface of the substrate.

21. The semiconductor device according to claim 12 or 13, characterized in that A pseudo wiring is provided, wherein the pseudo wiring is formed on the substrate, and the pseudo wiring is insulated from the signal line or the first wiring or both the signal line and the first wiring formed on the substrate, and the signal line or the second wiring or both the signal line and the second wiring formed on the substrate.

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