Self-aligned contacts for 3D logic and memory

Abstract

A semiconductor device includes dielectric layers and local interconnects that are alternately stacked over a substrate and laterally extend along a top surface of the substrate. Sidewalls of the dielectric layers and sidewalls of the local interconnects have a stepped configuration. The local interconnects are spaced apart from one another by dielectric layers and have portions that are not covered by the dielectric layers. The semiconductor device also includes conductive layers that are selectively located over the exposed portions of the local interconnects, wherein sidewalls of the conductive layers and sidewalls of the local interconnects are coplanar. The semiconductor device further includes isolation caps that extend from the dielectric layers. The isolation caps are positioned along the sidewalls of the conductive layers and the sidewalls of the local interconnects so as to isolate the conductive layers from one another.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefits of U.S. Provisional Application No. 62 / 852,434, filed May 24, 2019, and U.S. Application No. 16 / 721,583, filed December 19, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to microfabrication methods, including the manufacture of semiconductor devices. Background Technology

[0004] In the fabrication of semiconductor devices (especially at the microscale), various processing techniques are performed, such as film deposition, etch mask creation, patterning, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device elements on a substrate. Historically, microfabrication has been used to create transistors on a single plane, with wiring / metallization layers formed above the active device plane; this is therefore characterized as two-dimensional (2D) circuitry or 2D fabrication. While miniaturization has significantly increased the number of transistors per unit area in 2D circuits, it will face even greater challenges as it moves into the nanoscale semiconductor device fabrication node. Semiconductor device manufacturers have expressed a desire for three-dimensional (3D) semiconductor circuits with transistors stacked on top of each other. Summary of the Invention

[0005] While saturation in critical dimension miniaturization is inevitable, 3D integration has been considered the most viable option for continuing semiconductor miniaturization. Two-dimensional transistor density miniaturization halts when the contact gate pitch reaches its miniaturization limit due to fabrication variability and limitations of electrostatic devices. Even experimental new transistor designs that one day overcome these contact gate pitch miniaturization limitations (such as vertical channel gate-around transistors) cannot guarantee a return to normal semiconductor miniaturization, as resistance, capacitance, and reliability issues hinder line pitch miniaturization, thus limiting the density at which transistors can be wired into circuits.

[0006] 3D integration (i.e., vertical stacking of multiple devices) aims to overcome these miniaturization limitations by increasing transistor density in terms of volume rather than area. The flash memory industry has successfully demonstrated and implemented this idea with the adoption of 3D NAND. However, 3D integration of logic devices presents considerable challenges. One challenge in achieving miniaturization density in 3D integrated devices is minimizing the pitch from the wiring level above to the subsequent device level.

[0007] The techniques described in this paper provide a self-aligned process flow for forming contacts on stepped devices at dimensions independent of lithographic resolution or overlay control. Accordingly, monolithically integrated transistor stacks are used to provide vertical connections on stepped devices in 3D integrated logic or memory.

[0008] Of course, the order of the production steps disclosed herein is presented for clarity. Generally, these production steps can be performed in any suitable order. Furthermore, although each of the different features, techniques, configurations, etc., described herein may be discussed in different places within this disclosure, it should be noted that each concept can be performed independently or in combination with each other. Accordingly, this disclosure can be implemented and viewed in many different ways.

[0009] It should be noted that the Summary of this Scope does not specify every embodiment and / or additional novel aspects of this disclosure or the claimed invention. Rather, the Summary provides only a preliminary discussion of different embodiments and points of novelty compared to conventional techniques. For additional details and / or possible perspectives on the invention and embodiments, the reader should refer to the Detailed Description section of this disclosure and the corresponding drawings, as discussed further below.

[0010] According to one aspect of this disclosure, a semiconductor device is provided. The device includes a plurality of dielectric layers stacked over a substrate and extending laterally along a top surface of the substrate in a stepped configuration. The device also includes a plurality of local interconnects. These local interconnects are alternately stacked over the dielectric layers and extend laterally along the top surface of the substrate in a stepped configuration. The local interconnects are spaced apart from each other by the dielectric layers and have portions not covered by the dielectric layers. The device further includes a plurality of conductive layers selectively located over the exposed portions of the local interconnects, wherein the sidewalls of the conductive layers are flush with the sidewalls of the local interconnects. The semiconductor device also includes a plurality of isolation caps extending from the dielectric layers. These isolation caps are further positioned along the sidewalls of the conductive layers and the local interconnects to space the conductive layers apart from each other.

[0011] In some embodiments, the device includes a plurality of transistor pairs stacked above the substrate, and each of these transistor pairs includes an n-type transistor and a p-type transistor stacked on top of each other. The n-type transistor may have a source region and a drain region located at both ends of an n-type channel region. Each of the source and drain regions of the n-type transistor is coupled to a corresponding local interconnect, and the n-type channel region is surrounded by an n-type gate structure. The p-type transistor has a source region and a drain region located at both ends of a p-type channel region. Each of the source and drain regions of the p-type transistor is coupled to a corresponding local interconnect, and the p-type channel region is surrounded by a p-type gate structure.

[0012] The semiconductor device may include a plurality of gate electrodes stacked in a stepped configuration on the substrate, wherein each of these gate electrodes is electrically coupled to a corresponding gate structure of the transistor pairs. Further, each of these local interconnects is located on one side of the respective gate electrode.

[0013] In this semiconductor device, the top surfaces of these isolation caps may be flush with the top surfaces of these conductive layers. Furthermore, each of these isolation caps has a first sidewall and a second sidewall. The first sidewall of each of these isolation caps is in direct contact with a corresponding local interconnect, and the second sidewall of each of these isolation caps is flush with the sidewall of a corresponding dielectric layer.

[0014] In this semiconductor device, the sidewalls of each of these dielectric layers protrude beyond the sidewalls of the overlying local interconnects to form a gap, in which a corresponding isolation cap is located.

[0015] According to another aspect of this disclosure, a method for forming a semiconductor device is provided. In the disclosed method, a plurality of transistor pairs are formed. These transistor pairs are stacked over a substrate, and each of these transistor pairs includes an n-type transistor and a p-type transistor stacked on top of each other. Furthermore, a plurality of local interconnects are stacked on the substrate in a stepped configuration, electrically coupled to the source and drain regions of these transistor pairs, and spaced apart from each other by a dielectric layer having a stepped configuration. A plurality of isolation caps are then formed. These isolation caps are selectively located on the sidewalls of these local interconnects and the dielectric layer. Further, a portion of these dielectric layers is removed along the sidewalls of these isolation caps to expose a portion of these local interconnects. A plurality of conductive layers are then formed over the exposed portions of these local interconnects, such that these conductive layers are spaced apart from each other by the isolation caps.

[0016] In some embodiments, the isolation caps may be selectively grown vertically along the sidewalls of the local interconnects and dielectric layers before a portion of these dielectric layers is removed.

[0017] In some embodiments, the isolation caps and the conductive layers can be grown alternately to achieve a predetermined height. When the predetermined height is reached, a surface planarization process can be performed so that the top surfaces of the isolation caps are flush with the top surfaces of the conductive layers.

[0018] According to another aspect of this disclosure, a semiconductor device is provided. The device includes a plurality of transistor pairs stacked over a substrate, wherein each of the transistor pairs includes an n-type transistor and a p-type transistor stacked over each other. The device also includes a plurality of local interconnects stacked over the substrate and extending horizontally along the top surface of the substrate in a stepped configuration, wherein the local interconnects are electrically coupled to source and drain regions of the transistor pairs and spaced apart from each other by dielectric layers. The dielectric layers have a stepped configuration such that the local interconnects have portions not covered by the dielectric layers. The device also includes a plurality of conductive layers selectively located over the exposed portions of the local interconnects, wherein the sidewalls of the conductive layers are flush with the sidewalls of the local interconnects. The device further includes a plurality of isolation caps. These isolation caps extend from the dielectric layers and are positioned along the conductive layers and the sidewalls of the local interconnects to space the conductive layers apart from each other. Attached Figure Description

[0019] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0020] Figure 1A This is a schematic diagram of a semiconductor device formed based on a 3D integrated CFET stack with stepped local interconnects, according to some embodiments.

[0021] Figure 1B This is a schematic diagram of a semiconductor device formed based on a 3D integrated CFET stack with stepped local interconnects, according to some embodiments.

[0022] Figure 2 This is a schematic diagram of a semiconductor device formed based on a 3D integrated CFET stack with self-aligned contacts, according to some embodiments.

[0023] Figures 3A to 3M These are schematic diagrams illustrating various exemplary intermediate steps in the fabrication of a semiconductor device based on a 3D integrated CFET stack with self-aligned contacts, according to some embodiments.

[0024] Figure 4 This is a schematic diagram of a first semiconductor device configured to form self-aligned contacts according to some embodiments.

[0025] Figure 5 This is a schematic diagram of a second semiconductor device configured to form self-aligned contacts according to some embodiments. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Additionally, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between an element or feature illustrated in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the accompanying drawings, the spatially related terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0028] Throughout this specification, references to "an embodiment" or "embodiment" mean that a particular feature, structure, material, or characteristic described in conjunction with an embodiment is included in at least one embodiment, but does not imply that they are present in every embodiment. Therefore, the phrase "in an embodiment" appearing throughout this specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0029] Figure 1A This is a schematic diagram of a semiconductor device formed based on a 3D integrated CFET stack 100 (also referred to as a transistor stack 100 or CFET transistor stack 100) with stepped local interconnects. Complementary field-effect transistor (CFET) devices are three-dimensionally stacked logic standard cells, where NMOS or PMOS transistors are located on top of their complementary devices (vertically above). This configuration enables area reduction and improved routing congestion for both logic standard cells and SRAM memory cells. The schematic diagram of transistor stack 100 illustrates the challenges addressed by the techniques presented in this paper. Figure 1A The diagram illustrates a stepped stack of p-type and n-type transistors. Specifically, Figure 1A Four complementary transistor pairs are shown stacked in a stepped pyramid. The staggered arrangement allows access to each device level from a specific wiring level above.

[0030] like Figure 1AAs shown, a transistor stack 100 with stepped or pyramidal local interconnects has vertical direct contacts 110 extending from the steps of the transistor stack 100. The transistor stack 100 may include four CFET devices 102 to 108 stacked above a substrate (not shown). Each CFET device may include an n-type transistor and a p-type transistor coupled to a corresponding input (e.g., inputs A to D). For example, CFET 102 may include an n-type transistor N3 and a p-type transistor P3. The transistor stack 100 may have a plurality of local interconnects 112 to 126 having a stepped configuration. Each local interconnect is coupled to a corresponding transistor. The transistor stack 100 may further include an array of vertical direct contacts 110 coupled to and extending from the local interconnects 112 to 126. This array of vertical direct contacts 110 may have a top surface that is coplanar with each other, and the length of each vertical direct contact or vertical post varies depending on the height and position of the landing step.

[0031] Figure 1B This is a diagram of the contacts that fall on each local interconnect, used to contact subsequent source / drain regions from a given wiring level above. In other words, Figure 1B An array of contacts resting on a stepped device stack is shown. The minimum achievable size of the entire stacked device arrangement is ultimately limited by the minimum landing area required on each device level.

[0032] like Figure 1BAs shown, semiconductor devices can be formed based on a 3D integrated CFET stack 200 (also referred to as a transistor stack 200 or CFET transistor stack 200) with stepped local interconnects. The CFET transistor stack 200 may include four CFET devices 202 to 208 stacked on a substrate (not shown). Each of these four CFET devices may include a transistor pair formed by an n-type transistor and a p-type transistor. For example, CFET device 202 may include a transistor pair formed by an n-type transistor N3 and a p-type transistor P3. The n-type transistor may be located above the p-type transistor. In some embodiments, the n-type transistor and the p-type transistor may have a shared gate structure. The gate structure may surround the n-type channel region of the n-type transistor and the p-type channel region of the p-type transistor. The channel region may have a sheet, line, or strip configuration. The n-type transistor may have a source region and a drain region located at opposite ends of the n-type channel region, wherein the gate structure surrounds the n-type channel region and is located between the source and drain regions of the n-type transistor. A p-type transistor may have a source region and a drain region located at opposite ends of a p-type channel region, wherein a gate structure surrounds the p-type channel region and is located between the source and drain regions of the p-type transistor. Furthermore, the gate structure may be electrically coupled to the gate electrode. The source and drain regions may each have a source local interconnect and a drain local interconnect, respectively.

[0033] For example, n-type transistor N3 and p-type transistor P3 share a gate structure 212. The n-type transistor N3 has a source region 218 and a drain region 216 located at both ends of the n-type channel region. The n-channel region is surrounded by the gate structure 212, which is located between the source region 218 and the drain region 216. The p-type transistor P3 has a source region 222 and a drain region located behind the gate structure 212. The source region 222 and the drain region are located at both ends of the p-type channel region. Similarly, the p-type channel region is surrounded by the gate structure 212, which is located between the source region 222 and the drain region of the p-type transistor P3.

[0034] The gate structure 212 may have one or more gate electrodes 214. The gate electrodes 214 may be located at both ends of the gate structure 212. The source region 218 and drain region 216 of the n-type transistor N3 may have source local interconnects 226 and drain local interconnects 224, respectively. Similarly, the source region 222 of the p-type transistor P3 may have source local interconnects 220, and the drain region of the p-type transistor P3 may have drain local interconnects located behind the gate structure 212. Figure 1B The diagram also illustrates multiple local interconnects 228 to 232 that are respectively coupled to n-type transistors N4, N2, and N1.

[0035] It should be noted that the transistor stack 200 may further include multiple dielectric layers that space the transistor pairs apart from each other. Figure 1B (Not shown in the diagram). The dielectric layer can also separate n-type transistors from p-type transistors in a transistor pair. The dielectric layer can further provide local interconnects (e.g., Figure 1B 220, 224 to 232 are separated from each other.

[0036] In the transistor stack 200, the gate electrode and source / drain (S / D) local interconnects can have a stepped configuration. Furthermore, multiple vertical direct contacts 210 are coupled to and extend from the S / D local interconnects or the gate electrode. Therefore, the stepped configuration of the gate electrode and the S / D local interconnects facilitates easy access to each transistor in the transistor stack 200 and avoids complex interconnect connections.

[0037] although Figure 1A and Figure 1B The provided configuration can improve the area reduction and routing congestion of logic standard cells and SRAM memory cells, but the minimum achievable size of the entire stacked device arrangement is ultimately limited by the minimum landing area required on each device level. Figure 1A and Figure 1B The minimum landing area of ​​the local interconnects illustrated in the diagram is primarily driven by two process constraints: lithographic resolution and lithographic location. Lithographic resolution refers to the minimum pitch that can be patterned. Specifically, lithographic resolution is the contact array (e.g., Figure 1B The minimum pitch that a 210 can land on, or the minimum pitch that each contact within the array can land on. The minimum pitch is typically limited by the resolution of a given lithography system (e.g., a scanner or stepper) used to expose the pattern. Lithography position limitations refer to the additional space or tolerance required to compensate for pattern position errors. Misaligned patterns can cause short circuits in contacts of local interconnect structures belonging to devices on adjacent device levels. In other words, although very small patterns can be printed, the pattern itself may be misaligned due to a combination of tooling and wafer factors.

[0038] To achieve higher levels of device integration, it is desirable to minimize the size of the stepped extension at each device level by making the landing size of each step independent of lithographic resolution and pattern placement constraints. Accordingly, the techniques presented in this paper provide a self-aligned process for contact placement. Figure 2 The diagram illustrates an exemplary structure, and... Figures 3A to 3M The diagram illustrates an exemplary process flow.

[0039] Figure 2 A schematic diagram of a semiconductor device based on a 3D integrated CFET stack 300 (also referred to as a transistor stack 300) is shown, which has self-aligned contacts (or self-aligned vertical direct contacts) coupled to local interconnects. A comparison of transistor stack 300 and... Figure 1B The transistor stack 200, stack 300 may have multiple self-aligned vertical direct contacts (or conductive layers) 246 to 252 located above local interconnects (e.g., 226 to 232) instead of multiple vertical direct contacts 210. Figure 2 As shown, a plurality of dielectric layers 236 to 242 are stacked over a substrate and extend laterally along the top surface of the substrate (not shown), wherein the sidewalls 236a to 242a of the plurality of dielectric layers 236 to 242 may have a stepped configuration. Local interconnects 226 to 232 are alternately stacked over the dielectric layers 236 to 242 and extend laterally along the top surface of the substrate, wherein the sidewalls 226b to 232b of the plurality of local interconnects 226 to 232 may have a stepped configuration. The local interconnects 226 to 232 are spaced apart from each other by the dielectric layers 236 to 242 and have portions 226a to 232a not covered by the dielectric layers 236 to 242.

[0040] Still referencing Figure 2 Multiple conductive layers (or self-aligned vertical direct contacts) 246 to 252 are selectively located above the exposed portions 226a to 232a of the local interconnects 226 to 232. In some embodiments, the first sidewalls 246a to 252a of the conductive layers 246 to 252 are flush with the sidewalls 226b to 232b of the local interconnects 226 to 232. For example, the first sidewall 246a of the conductive layer 246 and the sidewall 226b of the local interconnect 226 are coplanar. In some embodiments, the second sidewalls 246b to 252b of the conductive layers 246 to 252 may be in direct contact with the dielectric layer or the source / drain region. For example, the second sidewall 246b of the conductive layer 246 may be in direct contact with the source region 218 ( Figure 2 (Not shown in the image) directly contact, and the second sidewall 248b of the conductive layer 248 can directly contact the dielectric layer 236.

[0041] The transistor stack 300 may include a plurality of isolation caps 254 to 260 extending from dielectric layers 236 to 242, respectively. The isolation caps 254 to 260 are further positioned along first sidewalls 246a to 252a of conductive layers 246 to 252 and sidewalls 226b to 232b of local interconnects 226 to 232 to space the conductive layers 246 to 252 apart from each other. Still referring to... Figure 2Each of the plurality of isolation covers may have a first sidewall and a second sidewall. The first sidewall of each of these isolation covers is in direct contact with a corresponding local interconnect, and the second sidewall of each of these isolation covers is flush with the sidewall of a corresponding dielectric layer. For example, isolation covers 254 to 260 may have first sidewalls 254a to 260a and second sidewalls 254b to 260b. The first sidewall 254a of isolation cover 254 is in direct contact with local interconnect 226, and the second sidewall 254b of isolation cover 254 is flush with the sidewall 236a of dielectric layer 236.

[0042] In some embodiments, the top surfaces of the plurality of isolation caps 254 to 260 are flush with the top surfaces of the plurality of conductive layers 246 to 252.

[0043] It should be noted that Figure 2 This is just an example. The transistor stack 300 may include any number of local interconnects, dielectric layers, and insulating caps.

[0044] Figures 3A to 3M This is a schematic diagram of various exemplary intermediate steps in the fabrication of a semiconductor device based on a 3D integrated CFET stack 300 with self-aligned contacts, according to some embodiments.

[0045] Figure 3A The illustration shows two sets of stacked devices 400A to 400B, each with four pairs of complementary transistors. For ease of description, the embodiments have been simplified. Figure 3A The example structure shown can have the same characteristics as... Figure 1B The illustrated 3D integrated CFET stack 200 has a similar configuration, except that no contacts (i.e., 210) are formed to couple to local interconnects. As mentioned above, logic devices or memory devices of integrated circuits can be designed as these stepped device stacks with many rows and columns. It should also be noted that the geometry illustrated is not limiting, and the stepped structure can also be implemented using L-shaped and stacked structures or other routing geometries. The stacked devices 400A to 400B can be formed based on a variety of fabrication processes, which can include film deposition (e.g., CVD, PVD, diffusion, ALD), etching processes, photolithography processes, ion implantation processes, wet cleaning processes, surface planarization processes (e.g., CMP), metrology processes, etc.

[0046] To provide electrical isolation between each device level or layer, a dielectric film (or dielectric layer, insulator, isolation layer) (e.g., dielectric layer 242) is deposited between device levels, such as... Figure 3AAs shown. Both the conductive layer (metal) and the insulating layer (insulator) are deposited as continuous films, while a given device stack is built prior to a sequence of vertical and lateral etching operations (which form a staircase). For simplicity and clarity, the dielectric film is not shown. Figure 3A As shown in, and in Figures 3B to 3M It was provided in China.

[0047] Figure 3B The illustration shows a close-up (or magnified) view of the space 400 between two sets of stepped device stacks (also known as CFET transistor stacks) 400A and 400B with a stepped configuration. For simplicity and clarity, the subsequent fabrication steps for forming self-aligned contacts (also known as self-aligned vertical direct contacts) are described based on the stepped device stack 400A. During the formation of the self-aligned contacts in the stepped device stack 400A, similar self-aligned contacts can be formed simultaneously in the stepped device stack 400B.

[0048] like Figure 3B As shown, multiple dielectric layers (or insulators or isolation layers) 225 and 236 to 242 and multiple local interconnects 226 to 232 are arranged alternately, such that the local interconnects 226 to 232 are spaced apart from each other by the dielectric layers 225 and 236 to 242. In some embodiments, the sidewalls 226b to 232b of the local interconnects and the sidewalls of the dielectric layers (e.g., 225a, 236a to 240a) may be coplanar.

[0049] exist Figure 3CIn this embodiment, multiple electrically insulating caps 254 to 260 are selectively deposited on the ends (or sidewalls) of local interconnect structures (or local interconnects) 226 to 232. This selective deposition of insulating caps provides advantages. By selectively depositing only on the material used to form the local interconnect structure (e.g., tungsten, cobalt, ruthenium), a relatively thin insulating layer is added to the end face (vertical surface) of each step or step. In other words, the insulating caps are grown horizontally on the exposed sidewalls of the local interconnect. This end-face cap insulator (or insulating cap) itself provides protection against electrical faults caused by misaligned contacts shorting adjacent local interconnect stages together. This end-face insulating cap also improves resilience or tolerance to pattern placement errors. The insulating caps can be made of metal oxides, including Al2O3, HfO2, ZrO2, TiO2, or combinations thereof, or other suitable metal oxides. The insulating caps can also be made of dielectric materials such as SiN, SiO, SiCN, SiCON, SiC, etc. For example, the insulating cap may include at least one of Al2O3, HfO2, ZrO2, TiO2, or SiO2. Any suitable film deposition technique can be applied to form the insulating cap. For example, film deposition techniques may include chemical vapor deposition (CVD), physical vapor deposition (PVD), diffusion and atomic layer deposition (ALD), or other suitable film deposition processes.

[0050] Now for reference Figure 3D After forming the end-face insulating cap (selectively depositing insulator-on-metal), the end-face insulating cap is extended by selectively depositing insulator-on-insulator. For example... Figure 3D As shown, isolation caps 254 to 260 grow along the sidewalls of local interconnects 226 to 232 and dielectric layers 225 and 236 to 242.

[0051] After extending the insulating cap, the dielectric layers separating the lateral conductive layers (i.e., local interconnects) are selectively etched away to expose the individual conductive metal layers (i.e., local interconnects), such as... Figure 3E As depicted. (e.g.) Figure 3E As shown, selective etching can remove a portion of the plurality of dielectric layers along the sidewalls of the isolation caps 254 to 260 (e.g., first sidewalls 254a to 260a and second sidewalls 254b to 258b) to expose portions of local interconnects 226 to 232. When the selective etching is complete, a plurality of exposed portions 226a to 232a of the local interconnects are formed. Further, as Figure 3E As shown, the dielectric layer 225 can be completely removed, thus fully exposing the local interconnect 226. Furthermore, due to selective etching, the sidewalls 236a to 240a of the dielectric layers 236 to 240 can be removed from... Figure 3D The original position in the space is reduced. Accordingly, the second sidewalls 254b to 258b of the isolation caps 254 to 258 can be flush with the sidewalls 236a to 240a of the dielectric layers 236 to 240. It should be noted that after selective etching, the sidewalls 236a to 240a of the dielectric layers protrude beyond the sidewalls 226b to 232b of the overlying local interconnects 226 to 232 to form a plurality of gaps 236b to 240b, and a plurality of isolation caps 254 to 260 are respectively located in these gaps. For example, the sidewall 236a of the dielectric layer 236 extends beyond the sidewall 226b of the overlying local interconnect 226 to form gaps 236b. Isolation caps 254 are located in gaps 236b.

[0052] exist Figure 3F In this process, selective metal-on-metal deposition can be applied to induce the growth of multiple conductive layers 246 to 252 on exposed metal regions. Conductive layers 246 to 252 can be selectively formed over exposed portions 226a to 232a of local interconnects 226 to 232 and positioned along the first sidewalls 254a to 260a of isolation caps 254 to 260. In some embodiments, the conductive layer can be disposed between the sidewall of the dielectric layer and the first sidewall of the isolation cap. For example, conductive layer 248 is located between the sidewall 236a of the dielectric layer 236 and the first sidewall 256a of the isolation cap 256. In some embodiments, the conductive layer can be in direct contact with the source / drain regions. For example, conductive layer 246 and source region 218 (… Figure 3F (Not shown) Direct contact. The conductive layer can be made of tungsten (W), cobalt (Co), ruthenium (Ru), nickel (Ni), or other suitable conductive materials. For example, the conductive layer may include at least one of Ru, Co, W, Ni, or Cu. Any suitable film deposition technique can be applied to form the insulating cap. For example, film deposition techniques may include chemical vapor deposition (CVD), physical vapor deposition (PVD), diffusion, and atomic layer deposition (ALD).

[0053] exist Figures 3G to 3L In this process, substrate processing continues through alternating cycles of selectively depositing insulator-on-insulator (e.g., isolation caps 254 to 260) and metal-on-metal (e.g., conductive layers 246 to 252). This alternating deposition and growth maintains electrical isolation between contacts (e.g., conductive layers 246 to 252) and with adjacent local interconnect structures (e.g., local interconnects 226 to 232). The isolation caps and conductive layers can be grown alternately to achieve a predetermined height. When the predetermined height is met, a surface planarization process (e.g., chemical mechanical polishing (CMP)) can be applied to flatten the top surfaces of the insulation caps and conductive layers. Figure 3MMultiple final self-aligned vertical direct contacts formed after the CMP process are shown. Therefore, self-aligned vertical direct contacts can be formed by alternating between growing dielectric material only on the insulating cap and growing conductive material only on the conductive layer. Figure 3M As shown, the self-aligned vertical direct contact formed in the transistor stack 600 can have the same characteristics as those formed in the stack. Figure 1B The transistor stack 300 shown exhibits a similar configuration to the self-aligned vertical interconnects. Growing these vertical interconnect features in this manner, using selective deposition to differentiate the growth of insulators (e.g., insulating caps) and conductors (e.g., conductive layers), produces self-aligned contact features that are insensitive to yield losses due to patterning variations. This self-alignment enables increased dimensional miniaturization.

[0054] In this disclosure, one embodiment includes a microfabrication method, such as on a semiconductor wafer. A stepped stack of transistor device layers is formed on a substrate, wherein local interconnect structures of a given layer extend horizontally beyond the edge of an overlay layer. This can be repeated for each layer to form a stepped or stepped geometry. A dielectric layer is formed between each transistor device layer, and a conductive layer (e.g., local interconnects) is formed on the top surface of each transistor device layer. During fabrication, each layer can initially be formed as a continuous layer, and then various etching and patterning techniques can be used to form a pyramidal or stepped structure. Each layer then has a conductive top surface and an insulating bottom surface, and a portion of each layer protrudes substantially from the overlay layer or the layer above it.

[0055] A first insulating material (e.g., an insulating cap) is selectively formed or deposited on the exposed sidewalls of the local interconnect structure or layer. Then, a first conductive material (e.g., a conductive layer) is selectively formed or grown on the exposed horizontal surface of the local interconnect structure. Accordingly, the horizontal surface of the local interconnect structure or layer step may have a conductive layer. After the formation of these initial two materials, materials are then grown upwards by alternating material formation. An additional first insulating material is formed on the exposed surface of the first insulating material in a vertical direction. And then, an additional first conductive material (or a different conductive material) is formed on the exposed first conductive material in a vertical direction until a predetermined vertical height of the first insulating material and the first conductive material is reached. Note that the final structure of the vertical conductive structure can have a relative height very similar to that of a stepped structure. The substrate can then be planarized, for example, by chemical mechanical polishing, to produce a flat surface.

[0056] Figure 4 and Figure 5 Semiconductor devices configured to deposit metal and metal oxide insulators are provided, which can be selectively deposited to implement the methods herein.

[0057] Figure 4 This is a schematic diagram of a first semiconductor device 700, configured to deposit metal and dielectric material (e.g., metal oxide) to selectively form a conductive layer or an insulating cap, respectively. Figure 4 As shown, apparatus 700 can provide a chemical vapor deposition (CVD) process. Apparatus 700 may include a plurality of wafer loading ports 702 configured to receive wafers, and a wafer processor 704 configured to transport wafers from the wafer loading ports to a loading lock 706. The loading lock 706 acts as an auxiliary vacuum chamber to accommodate the wafers and further transfer the wafers to processing chambers. Apparatus 700 also includes a plurality of processing chambers 710 to 716 and a wafer transfer mechanism 708 configured to transfer wafers between processing chambers.

[0058] The apparatus 700 may include a first processing chamber 710 configured to deposit a metal (such as Ru, Co, W, Ni, or other suitable metal) to form a conductive layer. The apparatus 700 may have a treatment chamber 712 configured to remove surface oxides on the conductive structure by a plasma process or an H2O vapor process. The treatment chamber 712 may also provide an annealing process and deposition of a self-aligned monolayer (SAM) that facilitates the selective growth of the conductive or dielectric layer. The apparatus 700 further includes a second deposition chamber 714 configured to form a first dielectric material (such as SiO) and a third deposition chamber 716 configured to form a second dielectric material (such as a metal oxide). The metal oxide may include Al2O3, HfO2, ZrO2, TiO2, or other suitable metal oxides.

[0059] An exemplary deposition process for forming ruthenium based on apparatus 700 may involve introducing a Ru CVD precursor into a first processing chamber 710 and introducing a processing temperature between 400°C and 600°C. The Ru CVD precursor includes Ru(acac)3 (acac is also known as acetylacetonate), Ru(EtCp)2 (EtCp is also known as ethylcyclopentadienyl), and Ru3(CO). 12 wait.

[0060] Figure 5 This is a schematic diagram of a second semiconductor device 800 configured to form an insulating cap or conductive layer. (See diagram below.) Figure 5As shown, semiconductor device 800 may include multiple wafer loading ports 802, a wafer processor 804, one or more loading locks 806, multiple processing chambers 810 to 814, and a wafer transfer mechanism 808. The processing chambers include a first processing chamber 810, which is configured to deposit metal (e.g., a layer, such as Ru, Co, W, Ni, or other suitable metal) to form a conductive layer. Device 800 may have a processing chamber 812 and a second processing chamber 814, which have similar functions to the processing chamber 712 described above. Compared to device 700, the second processing chamber 814 may sequentially produce a first dielectric material (e.g., SiO) and a second dielectric material (e.g., a metal oxide). For example, the second processing chamber 814 may first form the first dielectric material and then form the second dielectric material. Alternatively, the second processing chamber 814 may form the second dielectric material first, and then form the first dielectric material, depending on the fabrication requirements.

[0061] The various embodiments described herein offer several advantages over related examples. For example, the techniques described herein provide a self-aligned process flow for forming contacts on stepped devices at dimensions independent of lithographic resolution or overlay control. Accordingly, monolithically integrated transistor stacks are used to provide vertical connections on stepped devices in 3D integrated logic or memory.

[0062] In the foregoing description, specific details, such as the particular geometry of the machining system and the description of the various components and processes used therein, have been set forth. However, it should be understood that the techniques described herein can be practiced in other embodiments departing from these specific details, and that these details are for illustrative purposes and not for limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been presented for illustrative purposes to provide a thorough understanding. However, embodiments can be practiced without these specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and therefore any redundant description may be omitted.

[0063] Various techniques have been described as multiple independent operations to aid in understanding the various embodiments. The order of description should not be construed as meaning that these operations are necessarily order-dependent. In fact, these operations do not need to be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0064] As used herein, "substrate" or "target substrate" generally refers to the object being processed according to the present invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device) and may be, for example, a base substrate structure (such as a semiconductor wafer, a photomask) or a layer (such as a thin film) on or overlaid on a base substrate structure. Therefore, the substrate is not limited to any particular base structure, underlayer, or overlayer, whether patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0065] Those skilled in the art will also understand that many changes can be made to the operation of the above-described techniques while still achieving the same objectives of the invention. The scope of this disclosure is intended to encompass these changes. Therefore, the foregoing description of embodiments of the invention is not intended to be limiting. Rather, any limitations on embodiments of the invention are set forth in the appended claims.

Claims

1. A semiconductor device, comprising: A dielectric layer, which is stacked on top of a substrate and extends laterally along the top surface of the substrate, wherein the sidewalls of the dielectric layer have a stepped configuration; Local interconnects are alternately stacked over the dielectric layer and extend laterally along the top surface of the substrate. The sidewalls of the local interconnects have a stepped configuration, wherein each of the local interconnects is located over a corresponding dielectric layer and extends along the top surface of the corresponding dielectric layer, such that the local interconnects are spaced apart from each other by the dielectric layer and have portions not covered by the dielectric layer. A conductive layer, selectively located on and extending vertically from the exposed portions of the local interconnects, wherein the sidewalls of the conductive layer and the sidewalls of the local interconnects are coplanar; and An isolation cap extending from the dielectric layer, the isolation cap being further positioned along the sidewalls of the conductive layer and the local interconnection, so as to space the conductive layers apart from each other, wherein, Each dielectric layer in the dielectric layer has a sidewall that protrudes beyond the sidewall of the overlying local interconnect from the local interconnect, so as to form a gap between the sidewall of the respective dielectric layer and the sidewall of the overlying local interconnect, with a corresponding isolation cap from the isolation cap located in the gap.

2. The semiconductor device according to claim 1, further comprising: A pair of transistors stacked on the substrate, each pair comprising an n-type transistor and a p-type transistor stacked on top of each other, wherein: The n-type transistor has a source region and a drain region located at both ends of an n-type channel region, each of the source and drain regions being coupled to a corresponding local interconnect from the local interconnect, the n-type channel region being surrounded by an n-type gate structure; and The p-type transistor has a source region and a drain region located at both ends of the p-type channel region of the p-type transistor, each of the source region and the drain region of the p-type transistor being coupled to a corresponding local interconnect from the local interconnect, the p-type channel region being surrounded by a p-type gate structure.

3. The semiconductor device according to claim 2, further comprising: Gate electrodes are stacked on the substrate in a stepped configuration, each of which is electrically coupled to a corresponding gate structure from the transistor pair.

4. The semiconductor device according to claim 3, wherein, Each of the local interconnects is located on one side of the corresponding gate electrode from the gate electrode.

5. The semiconductor device according to claim 1, wherein, The top surface of the isolation cover and the top surface of the conductive layer are coplanar.

6. The semiconductor device according to claim 1, wherein, Each of the isolation covers has a first sidewall and a second sidewall.

7. The semiconductor device according to claim 6, wherein, The first sidewall of each of the isolation covers is in direct contact with the corresponding local interconnect from the local interconnect.

8. The semiconductor device according to claim 6, wherein, The second sidewall of each of the isolation covers is flush with the sidewall of the underlying dielectric layer from the dielectric layer.

9. The semiconductor device according to claim 6, wherein, The first local interconnect in the local interconnect and the first isolation cap in the isolation cap are located above the first dielectric layer of the dielectric layer. The first conductive layer in the conductive layer is located above the first local interconnect and is in contact with the first isolation cap. The sidewalls of the first local interconnect and the sidewalls of the first conductive layer are coplanar. The first sidewall of the first isolation cover contacts the sidewall of the first partial interconnection and the sidewall of the first conductive layer, and The second sidewall of the first isolation cover is flush with the sidewall of the first dielectric layer.

10. A method for forming a semiconductor device, the method comprising: Forming transistor pairs stacked on a substrate, each pair of transistors including an n-type transistor and a p-type transistor stacked on top of each other; A dielectric layer and local interconnects are formed over the substrate. The dielectric layer is stacked over the substrate and extends laterally along the top surface of the substrate. The local interconnects are alternately stacked over the dielectric layer such that the local interconnects are spaced apart from each other by the dielectric layer. The sidewalls of the dielectric layer and the sidewalls of the local interconnects are coplanar and have a stepped configuration such that the sidewall of each local interconnect is flush with the sidewall of the overlying dielectric layer from the dielectric layer. Each local interconnect is electrically coupled to one of the corresponding source region and the corresponding drain region from the transistor pair. Forming an isolation cover that is selectively positioned along the sidewalls of the locally interconnected structures; A portion of the dielectric layer is removed along the sidewall of the isolation cover to form the exposed portion of the local interconnect; as well as A conductive layer is formed over the exposed portion of the local interconnect, such that the conductive layers are spaced apart from each other by the isolation cap.

11. The method of claim 10, further comprising, before removing the portion of the dielectric layer: The isolation cap is selectively grown vertically along the sidewalls of the local interconnects and the sidewalls of the dielectric layer.

12. The method of claim 10, further comprising, after forming the conductive layer: The isolation cap and the conductive layer are grown alternately to achieve a predetermined height.

13. The method of claim 12, further comprising: A surface planarization process is performed to make the top surface of the isolation cover and the top surface of the conductive layer coplanar.

14. The method of claim 10, wherein, The isolation cover includes at least one of Al2O3, HfO2, ZrO2, TiO2, or SiO2.

15. The method according to claim 10, wherein, The conductive layer includes at least one of Ru, Co, W, Ni, or Cu.

16. The method of claim 10, wherein, Forming the transistor pair further includes: Gate electrodes are formed in a stepped configuration stacked above the substrate, each of the gate electrodes being electrically coupled to a corresponding gate structure from the transistor pair.

17. A semiconductor device, comprising: A pair of transistors stacked on a substrate, each pair of transistors comprising an n-type transistor and a p-type transistor stacked on top of each other; A dielectric layer, which is stacked over the substrate and extends laterally along the top surface of the substrate, wherein the sidewalls of the dielectric layer have a stepped configuration; Local interconnects are alternately stacked over the dielectric layer and extend laterally along the top surface of the substrate. The sidewalls of the local interconnects have a stepped configuration. Each of the local interconnects is electrically coupled to one of a corresponding source region and a corresponding drain region from the transistor pair. Each of the local interconnects is located over the corresponding dielectric layer and extends along the top surface of the corresponding dielectric layer, such that the local interconnects are spaced apart from each other by the dielectric layer and further have portions not covered by the dielectric layer. A conductive layer, situated on and extending vertically from the exposed portions of the local interconnects, wherein the sidewalls of the conductive layer and the sidewalls of the local interconnects are coplanar; and An isolation cap extending from the dielectric layer, the isolation cap being further positioned along the sidewalls of the conductive layer and the sidewalls of the locally interconnected layers, in order to space the conductive layers apart from each other, wherein, Each dielectric layer in the dielectric layer has a sidewall that protrudes beyond the sidewall of the overlying local interconnect from the local interconnect, so as to form a gap between the sidewall of the respective dielectric layer and the sidewall of the overlying local interconnect, with a corresponding isolation cap from the isolation cap located in the gap.

18. The semiconductor device of claim 17, further comprising: Gate electrodes are stacked on the substrate in a stepped configuration, each of which is electrically coupled to a corresponding gate structure from the transistor pair.

19. The semiconductor device according to claim 17, wherein, The first sidewall of each of the isolation covers is in direct contact with the corresponding local interconnect from the local interconnect.

20. The semiconductor device according to claim 17, wherein, The second sidewall of each of the isolation covers is flush with the sidewall of the underlying dielectric layer from the dielectric layer.

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