A silicon-based nanowire piezoresistive pressure sensor and a method for preparing the same

Abstract

The present invention discloses a silicon-based nanowire piezoresistive pressure sensor and a preparation method thereof, belonging to the field of microelectromechanical system sensor design. The present invention proposes a silicon strain film with a suspended silicon piezoresistive nanowire structure, and the piezoresistors are respectively arranged in a suspended manner between the edge of the strain film and the beam boss, and between the central boss and the beam boss, greatly improving the sensitivity of the piezoresistive pressure sensor; a coated SiO2 layer is formed by thermal oxidation on the surface of the silicon piezoresistive nanowire. On the one hand, it can effectively reduce the generation of leakage current. On the other hand, thermal oxidation can make the concentration distribution of the piezoresistance more uniform; SiO2 / Si3N4 has good blocking characteristics for K in the KOH etching process as a mask for the KOH etching process, and the processed device has high reliability; the silicon-glass anodic bonding process is adopted, in which the glass plays a role of stress buffering for the pressure sensing film, improving the stability of the sensor in subsequent packaging and testing. + The blocking property of is better, and the processed device has high reliability; the silicon-glass anodic bonding process is adopted, in which the glass plays a role of stress buffering for the pressure sensing film, improving the stability of the sensor in subsequent packaging and testing.

Description

Technical Field

[0001] The invention belongs to the field of micro-electromechanical system (MEMS) sensor design, and relates to a MEMS piezoresistive pressure sensor and a method for manufacturing a silicon chip-level pressure sensor by adopting a MEMS processing method. Background Art

[0002] MEMS (Micro Electro Mechanical System) is an emerging interdisciplinary high-tech research field. Piezoresistive pressure sensors manufactured based on MEMS technology are gradually replacing traditional pressure detection devices and becoming the mainstream product in the field of pressure sensing due to their small size, easy integration, reliable performance, and ability to convert non-electrical signals to electrical signals. They are often used in the fields of automobiles, aerospace, petrochemicals, and biomedicine.

[0003] The working principle of a typical piezoresistive pressure sensor is to deform the strain film of the sensor under the action of external pressure, thereby deforming the piezoresistors on the strain film. Due to the piezoresistive effect, the resistance of the piezoresistors will change, which is converted into changes in the corresponding output voltage, thereby measuring the pressure. Usually, the piezoresistors are distributed in the stress concentration area of ​​the strain film in the form of a Wheatstone bridge to maximize the pressure-sensitive effect.

[0004] The high linearity, temperature coefficient, zero drift and other undesirable factors of pressure sensors can be solved by integrated circuits, while the sensitivity of pressure sensors, a performance indicator, can be improved mainly through device structure or processing technology. At present, micro-pressure sensors mainly improve their sensitivity by creating a stress concentration area on the strain film and embedding the piezoresistor into this area, which requires the strain film to be thin and large. However, due to the limitations of the strain film, this method cannot maximize the stress concentration in the piezoresistive area. At the same time, the piezoresistors embedded in the strain film are in contact with the surrounding bulk silicon substrate, and the leakage and noise they bring also have a great impact on high-sensitivity piezoresistive pressure sensors. Summary of the invention

[0005] The present invention aims to solve the above problems and propose a new silicon-based nanowire piezoresistive pressure sensor and its preparation method. Compared with the pressure sensor of the typical structure, the sensor of this structure has extremely high sensitivity and low nonlinearity; the sensor preparation method is compatible with the processing method of the standard bulk silicon piezoresistive pressure sensor, and has a broad application prospect in the field of micro-pressure.

[0006] To achieve the above object, the present invention adopts the following technical solution:

[0007] A silicon-based nanowire piezoresistive pressure sensor comprises a silicon strain film, a varistor, a heavily doped connecting wire, a metal lead and a glass base; the silicon strain film is made of a silicon substrate, and its front side contains a central boss located in the center, four beam boss structures located outside the central boss and symmetrical about the center, and a silicon strain film edge surrounding the outside of the beam boss; the varistor is a suspended silicon piezoresistive nanowire, suspended between the edge of the silicon strain film and each beam boss and between the central boss and each beam boss; the heavily doped connecting wire is a suspended silicon heavily doped connecting wire, suspended between the edge of the strain film and the beam boss; the metal lead and the heavily doped connecting wire form an ohmic contact on the front side of the silicon strain film; the glass base is a porous glass bonded to the back side of the silicon strain film.

[0008] Furthermore, the silicon substrate is a single crystal silicon wafer with an N-type (100) crystal plane.

[0009] Furthermore, the silicon strain film is square, the central boss is square, circular or other centrally symmetrical shapes, and the beam boss is rectangular, trapezoidal or other mirror-symmetrical shapes.

[0010] Furthermore, there are one or more varistors suspended between the central boss and each beam boss, one or more varistors suspended between the edge of the strain membrane and each beam boss, and one or more heavily-doped connecting lines suspended between the edge of the strain membrane and each beam boss; the varistors and heavily-doped connecting lines suspended between the edge of the strain membrane and each beam boss are arranged symmetrically.

[0011] A method for preparing a silicon-based nanowire piezoresistive pressure sensor comprises the following steps:

[0012] 1) A first photolithography pattern is formed on the front side of the silicon substrate to expose a varistor region, in which a varistor is fabricated; and a second photolithography pattern is formed to expose a heavily doped contact region, in which a heavily doped connecting wire is fabricated;

[0013] 2) SiO2 and Si3N4 are fabricated on the front and back sides of the silicon substrate in sequence, and then the pattern is patterned for the third time on the front side, Si3N4 is etched, and a hard mask of silicon nanowires is fabricated in the varistor and heavily doped connecting wire regions, and the varistor and heavily doped connecting wire regions are etched using the hard mask to form silicon nanowires and grooves on both sides thereof;

[0014] 3) SiO2 and Si3N4 are sequentially fabricated on the front and back sides of the silicon substrate, and then a fourth photolithography pattern is formed on the back side to form an etching window, and then a back cavity etching is performed in the etching window area to form a back cavity, thereby obtaining a silicon strain film;

[0015] 4) performing a fifth photolithography pattern on the front side of the silicon strain film, removing SiO2 and Si3N4 at the bottom of the groove by anisotropic etching, retaining SiO2 and Si3N4 on the sidewalls of the silicon nanowires, then anisotropically etching the Si at the bottom of the groove, and finally isotropically etching the silicon at the bottom of the nanowires to form suspended silicon nanowires and beam bosses and a central boss structure;

[0016] 5) removing SiO2 and Si3N4 on the front and back sides of the silicon strain film, and then performing thermal oxidation to form SiO2 to cover the silicon nanowires and form a dielectric isolation layer between the metal and the silicon substrate;

[0017] 6) The sixth photolithography image is formed on the front side of the silicon strain film to form a lead hole area, and SiO2 through holes are etched in the lead hole area to make lead holes; the seventh photolithography image is formed to form a metal lead area, and metal is made on the front side of the silicon strain film, and then stripping is performed to make metal leads;

[0018] 7) Bonding the back side of the silicon strain film obtained in step 6) to a glass with holes, and then dicing the film to obtain a silicon-based nanowire piezoresistive pressure sensor.

[0019] Furthermore, in step 1), the varistor is manufactured by ion implantation; and the heavily doped region connecting wire is manufactured by ion implantation or diffusion.

[0020] Furthermore, in steps 2) and 3), SiO2 is made by thermal oxidation, APCVD, LPCVD or PECVD, and Si3N4 is made by APCVD, LPCVD or PECVD. SiO2 is preferably made by LPCVD, and Si3N4 is preferably made by PECVD. The SiO2 film made by LPCVD has better quality and is more suitable for K + The barrier properties are good, which is beneficial to improve the stability of the device. The Si3N4 film produced by PECVD has less stress.

[0021] Furthermore, in step 3), the back cavity etching adopts HNA, TMAH or KOH anisotropic etching process.

[0022] Furthermore, in step 4), the anisotropic etching is preferably performed by RIE etching process, and the isotropic etching is performed by HNA process or XeF2 gaseous etching process, preferably XeF2 gaseous etching process.

[0023] Furthermore, in step 5), SiO2 and Si3N4 on the front and back sides of the silicon strain film are removed by wet etching. The wet etching process for SiO2 is preferably a BHF process, and the wet etching process for Si3N4 is preferably 85% phosphoric acid at 150°C.

[0024] Furthermore, in step 6), the through hole is etched by a dry etching process or a wet etching process, preferably an RIE etching process; when making the metal lead, the metal lead area is first photolithographically formed, then PVD metal is formed, and finally the metal lead is formed by stripping.

[0025] Furthermore, in step 7), the bonding method is preferably an anodic bonding process.

[0026] Compared with the prior art, the advantages of the present invention are:

[0027] 1) The introduction of silicon piezoresistive nanowire structure improves the stress concentration in the piezoresistive region, which enables the sensor to obtain extremely high sensitivity.

[0028] 2) The surface of silicon piezoresistive nanowires is thermally oxidized to form a coated SiO2 layer. On the one hand, it can effectively reduce the generation of leakage current. On the other hand, thermal oxidation can make the concentration distribution of the piezoresistor more uniform.

[0029] 3) SiO2 / Si3N4 as a mask for KOH etching process + The barrier properties are good, and the processed devices have high reliability;

[0030] 4) The silicon glass anodic bonding process is adopted, in which the glass plays a stress buffering role for the pressure sensing film, improving the stability of the sensor in subsequent packaging and testing, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A Schematic diagram of making a varistor on a silicon wafer;

[0032] Figure 1B A schematic diagram of making heavily doped contact regions on a silicon wafer;

[0033] Figure 1C Schematic diagram of etching Si3N4 on the front side of a silicon wafer to form a hard mask for silicon nanowires;

[0034] Figure 1D Schematic diagram of etching silicon on the front side of a silicon wafer to form silicon nanowires;

[0035] Figure 1E Schematic diagram of etching a cavity on the back side of a silicon wafer to form a silicon strain film;

[0036] Figure 1F Schematic diagram of removing SiO2 / Si3N4 at the bottom of the silicon groove and etching the boss structure;

[0037] Figure 1G Schematic diagram of removing silicon at the bottom of a silicon nanowire to form a suspended silicon nanowire;

[0038] Figure 1H Schematic diagram of thermal oxidation of silicon wafers;

[0039] Fig. 1I A schematic diagram of making lead holes and metal leads on the front side of a silicon wafer;

[0040] Figure 1J Schematic diagram of anodic bonding on the back side of silicon wafer with holes;

[0041] Figure 2 Schematic diagram of a piezoresistive pressure sensor with suspended silicon nanowire structure;

[0042] Figure 3A This is a schematic diagram of the front view of the silicon strained film with suspended silicon nanowire structure;

[0043] Figure 3B Schematic diagram of the piezoresistive arrangement circuit of the suspended silicon nanowire structure.

[0044] In the figure: 1—silicon substrate; 2—SiO2; 3—varistor; 4—heavily doped connecting wire; 5—hard mask; 6—groove; 7—SiO2-coated silicon nanowire; 8—metal lead; 9—perforated glass; 10—center boss; 11—beam boss. Specific implementation methods

[0045] The present invention is described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0046] This embodiment discloses a method for preparing a silicon-based nanowire piezoresistive pressure sensor. There is a great stress concentration in the suspended silicon piezoresistive nanowire region arranged along the <1 1 0> crystal direction. Four groups of silicon piezoresistive nanowires and silicon heavily doped connecting wires are suspended between the edge of the square strain film made by the back cavity etching process and the beam boss. Each group of silicon piezoresistive nanowires and silicon heavily doped connecting wires are symmetrically arranged. The number of each group of silicon piezoresistive nanowires and silicon heavily doped connecting wires can be arbitrary (generally 1-5), and the number in this embodiment is 2. Four groups of silicon piezoresistive nanowires are suspended symmetrically between the central boss and the beam boss. The number of each group of silicon piezoresistive nanowires can be arbitrary (generally 1-5), and the number in this embodiment is 1. Specifically, the steps of the method include:

[0047] 1) The varistor and the heavily doped contact region are fabricated on the front side of a single crystal silicon wafer (i.e., silicon substrate) with a (100) crystal plane by ion implantation;

[0048] 2) Fabricating a SiO2 / Si3N4 hard mask on the front side of the silicon substrate and etching silicon to form silicon nanowires;

[0049] 3) SiO2 is fabricated on both sides, and then Si3N4 is fabricated on both sides as a back cavity etching mask. The back side of the silicon wafer is photolithographically processed to form a back cavity etching window, and then the back cavity etching is performed to fabricate a silicon strain film;

[0050] 4) Firstly, Si3N4, SiO2 and Si are anisotropically etched on the front side of the silicon substrate, and then silicon is isotropically etched to form suspended silicon nanowires and boss structures;

[0051] 5) Etching and removing SiO2 and Si3N4 on the front and back sides of the silicon substrate, and then thermally oxidizing to form SiO2, which covers the silicon nanowires and forms a dielectric isolation layer between the metal and the silicon substrate;

[0052] 6) Making lead holes and metal leads on the front side of the silicon strain film;

[0053] 7) bonding the back side of the silicon strain film with silicon nanowires to the glass with holes;

[0054] 8) Slice and package into pressure sensors.

[0055] A specific embodiment is given below. Figures 1A-1J The process flow chart of the preparation method of silicon-based nanowire piezoresistive pressure sensor is as follows:

[0056] a) Preparation and production of varistor 3: N-type (100) single crystal silicon wafer is used as silicon substrate 1 of the chip, the thickness of the silicon wafer is 400 μm, and the front and back surfaces of the silicon wafer are thermally oxidized and grown SiO2 2; The first photolithography pattern on the front of the silicon wafer reveals the varistor area, and the RIESiO2 remaining Ion implantation B + , boron pushes, and obtains the varistor 3, such as Figure 1A As shown;

[0057] b) Making heavily doped connecting wire 4: The second photolithography pattern on the front of the silicon wafer reveals the heavily doped contact area, and the RIE SiO2 residue Ion implantation B + , boron is pushed forward to obtain a heavily doped connecting line 4, such as Figure 1B As shown;

[0058] c) Making a hard mask for silicon nanowires 5: Double-sided LPCVD SiO2 Then double-sided PECVD Si3N4 The front side of the silicon wafer is patterned for the third time, and then Si3N4 is etched by RIE to form a hard mask 5 of silicon nanowires in the varistor and heavily doped connecting line area. The line width of the hard mask is 1μm. Figure 1C As shown;

[0059] d) Fabrication of silicon nanowires: Using SiO2 / Si3N4 hard mask RIE to etch Si 1 μm around the varistor and heavily doped connecting wire area to form a groove 6, and fabricate silicon nanowires, such as Figure 1D As shown;

[0060] e) Fabrication of silicon strain film: double-sided LPCVD SiO2 and double-sided PECVD Si3N4 Silicon nanowires used to protect the front side of the strain film; SiO2 and Si3N4 as back cavity etching masks, fourth photolithography KOH etching window on the back side of the silicon wafer; two RIE Si3N4 / SiO2 Remove the glue; KOH solution corrodes Si, the corrosion depth is 385μm, and the KOH corrosion back cavity is obtained to obtain the silicon strain film, such as Figure 1E As shown;

[0061] f) Fabrication of the boss structure: The fifth photolithography pattern on the front of the silicon strain film reveals the Si3N4 and SiO2 at the bottom of the groove 6; RIESi3N4 / SiO2 RIE Si 3μm, making boss structures, such as Figure 1F As shown;

[0062] g) Fabrication of suspended silicon nanowires: isotropic XeF2 gaseous etching of Si at the bottom of the silicon nanowires to form suspended silicon nanowires. Figure 1G As shown;

[0063] h) Fabrication of SiO2-coated silicon nanowires 7 and dielectric isolation layers: wet etching to remove SiO2 and Si3N4; thermal oxidation growth SiO2, covers the silicon nanowires and forms a dielectric isolation layer between the metal and the silicon substrate. The diameter of the silicon nanowires is about 820nm. Figure 1H As shown;

[0064] i) Make lead holes and metal leads 8: Sixth photolithography of the lead hole area on the front side, RIE SiO2 BHF bleaching of natural oxide layer; seventh photolithography of metal lead area on the front side, PVD sputtering of Al 0.8-1μm; removal of photoresist, stripping to form metal lead 8; Al alloying; Fig. 1I As shown;

[0065] j) The back side of the silicon substrate is anode-bonded to the porous glass 9 to complete the manufacture of the piezoresistive pressure sensor chip with a suspended silicon nanowire structure, such as Figure 1J As shown;

[0066] After the chip is manufactured, it is diced. Figure 2 As shown, this step splits the entire silicon wafer into a large number of individual pressure sensor chips, and each silicon wafer can obtain a different number of pressure sensor chips according to the designed silicon wafer area size.

[0067] In the above-mentioned preparation process, Si3N4 is used as a hard mask for preparing silicon nanowires, which reduces the number of photomasks and has a very good etching selectivity for Si; SiO2 and Si3N4 masks have a good selectivity for K + The barrier ability is strong, which can avoid KOH corrosion during + diffusion, thereby improving the reliability of the pressure gauge chip; PECVD Si3N4 can reduce the residual stress caused by Si3N4 and ensure that the silicon nanowires will not be damaged during the preparation process; thermal oxidation and coating of SiO2 on the surface of silicon nanowires can effectively reduce the leakage of the device.

[0068] Figure 3A The figure is a schematic diagram of a silicon strain film of a piezoresistive pressure sensor with a suspended silicon nanowire structure. The figure mainly highlights the arrangement of the varistor 3, the heavily doped connecting wire 4 and the metal lead 8, as well as the shape of the bosses 10 and 11. The other parts of the silicon strain film are not fully shown. One of the two suspended silicon nanowires near the edge of the strain film is a varistor 3, and the other is a heavily doped connecting wire 4; the suspended silicon nanowire near the central boss 10 is a varistor 3. The number of varistors 3 and heavily doped connecting wires 4 is not limited to two or one. The connection method of the varistor 3 can also be diversified. The central boss 10 is for suspending the silicon nanowire and improving the linearity of the pressure sensor, but it is not limited to being a rectangular boss, and its geometric shape can also be other shapes, such as a circle or other centrally symmetrical shapes; the beam boss 11 is for suspending the silicon nanowire and improving the sensitivity of the pressure sensor, but it is not limited to being a rectangular boss, and its geometric shape can also be other shapes, such as a trapezoid or other mirror-symmetrical shapes. Figure 3B Schematic diagram of the piezoresistive arrangement circuit of the suspended silicon nanowire structure.

[0069] The outstanding feature of the present invention is that it proposes a silicon-based nanowire piezoresistive pressure sensor design for the first time, and the silicon nanowire piezoresistors are suspended and distributed at both ends of the beam boss, which can maximize the sensitivity. At the same time, the surface of the nanowire piezoresistor is wrapped with oxide, which can effectively reduce the leakage of the device. Table 1 below is a simulated performance comparison of the silicon-based nanowire piezoresistive pressure sensor of the present invention and the traditional flat membrane structure piezoresistive pressure sensor. It can be seen that the pressure sensor of the present invention has extremely high sensitivity.

[0070] Table 1. Performance data comparison between the pressure sensor of the present invention and the traditional typical flat membrane structure pressure sensor

[0071]

[0072] The pressure sensor preparation method in the above embodiment is only a preferred implementation method and is not intended to be limiting. Those skilled in the art should understand that without departing from the essence of the present invention, slight modifications or equivalent substitutions may be made to the technical solution of the present invention. The scope of protection of the present invention shall be subject to the claims.

Claims

1. A silicon-based nanowire piezoresistive pressure sensor, characterized in that: The invention comprises a silicon strain film, a varistor, a heavily doped connecting wire, a metal lead and a glass base; the silicon strain film is made of a silicon substrate, and the front side thereof comprises a central boss located in the center, four beam boss structures located outside the central boss and symmetrical about the center, and the edge of the silicon strain film surrounding the outside of the beam boss; the varistor is a suspended silicon piezoresistive nanowire, which is suspended between the edge of the silicon strain film and each beam boss and between the central boss and each beam boss; the varistor R1 is suspended between the edge of the silicon strain film and each beam boss, and the varistor R2 is suspended between the edge of the silicon strain film and each beam boss, and the varistor R3 is suspended between the central boss. Between each beam boss is a varistor R2; the heavily doped connecting wire is a suspended silicon heavily doped connecting wire, suspended between the edge of the strain film and the beam boss; the metal lead is arranged on the front of the central boss, each beam boss and the edge of the silicon strain film, and forms an ohmic contact with the heavily doped connecting wire on the front of the silicon strain film; the glass base is a perforated glass bonded to the back of the silicon strain film; wherein, one end of the varistor R1 close to the beam boss is connected to one end of the varistor R2 close to the beam boss through the metal lead on the beam boss; the varistor R The end of the varistor R1 close to the beam boss and the end of the varistor R2 close to the beam boss are connected to the voltage input terminal Vin, the zero voltage input terminal 0, the high voltage output terminal Vout+, and the low voltage output terminal Vout- through the metal lead on the beam boss, the heavily doped connecting wire, and the metal lead on the edge of the silicon strained film respectively; the two varistor R1s connecting the voltage input terminal Vin and the low voltage output terminal Vout-, the ends of which close to the edge of the silicon strained film are connected to each other through the metal lead on the edge of the silicon strained film; the two varistor R1s connecting the zero voltage input terminal 0 and the high voltage output terminal Vout+, the ends of which close to the edge of the silicon strained film are connected to each other through the metal lead on the edge of the silicon strained film; the two varistor R2s connecting the voltage input terminal Vin and the high voltage output terminal Vout+, the ends of which close to the center boss are connected to each other through the metal lead located on the center boss; the two varistor R2s connecting the zero voltage input terminal 0 and the low voltage output terminal Vout-, the ends of which close to the center boss are connected to each other through the metal lead located on the center boss.

2. The silicon-based nanowire piezoresistive pressure sensor according to claim 1, characterized in that: The silicon substrate is a single crystal silicon wafer with an N-type (100) crystal plane; the silicon strain film is square, the central boss is square, circular or other centrally symmetrical shapes, and the beam boss is rectangular, trapezoidal or other mirror-symmetrical shapes.

3. A method for preparing a silicon-based nanowire piezoresistive pressure sensor according to claim 1 or 2, characterized in that: The following steps are involved: 1) The first photolithography pattern is performed on the front side of the silicon substrate to expose the varistor area, and the varistor is manufactured in the varistor area; and then the second photolithography pattern is performed to expose the heavily doped contact area, and the heavily doped connecting wire is manufactured in the heavily doped contact area; 2) SiO2 and Si3N4 are fabricated on the front and back sides of the silicon substrate in sequence, and then the pattern is patterned for the third time on the front side, Si3N4 is etched, and a hard mask of silicon nanowires is fabricated in the varistor and heavily doped connecting wire regions. The varistor and heavily doped connecting wire regions are etched using the hard mask to form silicon nanowires and grooves on both sides thereof; 3) SiO2 and Si3N4 are fabricated on the front and back sides of the silicon substrate in sequence, and then a fourth photolithography pattern is formed on the back side to form an etching window, and then a back cavity is formed by back cavity etching in the etching window area to obtain a silicon strain film; 4) performing a fifth photolithography pattern on the front side of the silicon strain film, removing SiO2 and Si3N4 at the bottom of the groove by anisotropic etching, retaining SiO2 and Si3N4 on the sidewall of the silicon nanowire, then anisotropically etching the Si at the bottom of the groove, and finally isotropically etching the silicon at the bottom of the nanowire to form a suspended silicon nanowire and a boss structure; 5) Removing SiO2 and Si3N4 on the front and back sides of the silicon strain film, and then performing thermal oxidation to form SiO2 to cover the silicon nanowires and form a dielectric isolation layer between the metal and the silicon substrate; 6) The sixth photolithography image is formed on the front side of the silicon strain film to form a lead hole area, and SiO2 through holes are etched in the lead hole area to make lead holes; the seventh photolithography image is formed to form a metal lead area, and metal is made on the front side of the silicon strain film, and then stripping is performed to make metal leads; 7) Bonding the back side of the silicon strain film obtained in step 6) to a glass with holes, and then dicing the film to obtain a silicon-based nanowire piezoresistive pressure sensor.

4. The method according to claim 3, characterized in that In step 1), the varistor is manufactured by ion implantation, and the heavily doped region connecting wire is manufactured by ion implantation or diffusion.

5. The method according to claim 3, characterized in that In steps 2) and 3), SiO2 is produced by thermal oxidation, APCVD, LPCVD or PECVD, and Si3N4 is produced by APCVD, LPCVD or PECVD. In step 3), back cavity etching is performed by HNA, TMAH or KOH anisotropic etching.

6. The method according to claim 3, characterized in that In step 4), anisotropic etching adopts RIE etching process, and isotropic etching adopts HNA process or XeF2 gaseous etching process.

7. The method according to claim 3, characterized in that Step 5) Remove SiO2 and Si3N4 on the front and back sides of the silicon strain film by wet etching. The wet etching process of SiO2 adopts BHF process, and the wet etching process of Si3N4 adopts 85% phosphoric acid at 150°C.

8. The method according to claim 3, characterized in that Step 6) Etching through holes by dry etching or wet etching; when making metal leads, first photolithography is performed to form metal lead areas, then PVD metal is applied, and finally stripping is performed to form metal leads.

9. The method according to claim 3, characterized in that In step 7), the bonding method adopts an anodic bonding process.

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