Sense amplifier architecture for low supply voltage operation

Abstract

The present invention is entitled "Sense Amplifier Architecture for Low Supply Voltage Operation". The present invention describes systems and methods for reducing the energy per bit of memory cell sensing operations (such as memory read operations) by dynamically adjusting the body effect of data latch transistors during the sensing operation. A significant component of the energy required to perform a memory cell sensing operation may correspond to parasitic currents through low threshold voltage (VT) transistors of a data latch within a sense amplifier circuit. In order to reduce the energy per bit of a memory cell sensing operation while using a reduced supply voltage for the data latch, the body effect of a selected number of low VT transistors within the data latch may be dynamically adjusted so that the body effect is minimized or absent during latching of new data into the data latch and then increased after the new data is latched into the data latch.

Description

Background Art

[0001] The growth of demand for portable consumer electronic devices has driven the demand for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, have been widely used to meet the growing demand for digital information storage and exchange. Their portability, versatility and rugged design as well as their high reliability and large capacity make such memory devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs, cellular phones and solid-state drives (SSDs). Semiconductor memory devices may include non-volatile memory or volatile memory. Even when the non-volatile memory is not connected to a power source (e.g., a battery), the non-volatile memory allows information to be stored and retained. Examples of non-volatile memory include flash memory (e.g., NAND flash memory and NOR flash memory) and electrically erasable programmable read-only memory (EEPROM).

[0002] Semiconductor memory tube core is usually placed in the package for easier handling and assembly, and to protect the tube core from damage. Although the plural form of the English word "die" of the tube core is "dice", it is a common industry practice to use "die" as a plural form as well as a singular form. In one example, one or more semiconductor memory tube cores and other integrated circuits (such as processors) can be wrapped in a package, where the tube core can be stacked on top of another tube core in the package. The package may include a surface mount package, such as a BGA package or a TSOP package. One benefit of vertically stacking multiple tube cores (for example, stacking eight tube cores in a single package) in the package is that the overall form factor and package size can be reduced. In some cases, the package may include a stacked multi-chip package, a system-level package (SiP) or a chip stacked multi-chip module (MCM). Vertical connectors between stacked tube cores (including direct vertical connectors passing through the substrate of the tube core (for example, through a silicon substrate)) can be formed in each tube core before or after the tube core is bonded. The vertical connector may include a through silicon via (TSV). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Like numbered elements refer to common parts in different figures.

[0004] Figure 1 is a block diagram depicting one embodiment of a memory system.

[0005] Figure 2A One embodiment of two separate dies is depicted.

[0006] Figure 2B One embodiment of a plurality of stacked dies including a memory array die and a CMOS die is depicted.

[0007] FIG. 3A to FIG. 3B Various embodiments of integrated memory components are depicted.

[0008] Figure 4 is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

[0009] Figure 5 The threshold voltage distribution is depicted.

[0010] Fig. 6A is a table that describes one example of assigning data values ​​to data states.

[0011] Figure 6B One embodiment of a series of program and verify pulses applied to a selected word line during a programming operation is depicted.

[0012] Figure 7 One embodiment of a plurality of stacked dies is depicted.

[0013] Fig. 8A One implementation of a portion of a sense amplifier is depicted.

[0014] Figure 8B Depicted with Fig. 8A One embodiment of voltage waveforms corresponding to the operation of a portion of the sense amplifier is depicted.

[0015] Figure 8C One implementation of a data latch is depicted.

[0016] FIG. 8D to FIG. 8I Depicted Figure 8C Various embodiments of cross-sectional views of low VT NMOS transistors are depicted in FIG.

[0017] Figure 8J An alternative implementation of a data latch is shown.

[0018] FIG. 9A to FIG. 9B A flow chart describing one embodiment of a process for dynamically adjusting the body effect of a data latch transistor within a sense amplifier circuit during a sensing operation is depicted.

[0019] FIG. 9C to FIG. 9D A flow chart describing an alternative embodiment of a process for dynamically adjusting the body effect of a data latch transistor within a sense amplifier circuit during a sensing operation is depicted. DETAILED DESCRIPTION

[0020] The present invention describes a technique for improving the performance and energy efficiency of memory cell sensing operations by dynamically adjusting the body effect of a data latch transistor within a sense amplifier circuit during a sensing operation. The memory cell sensing operation may include a read operation or a program verification operation. Multiple sense amplifier circuits may be used to determine the data states of multiple memory cells, and multiple data latches may be used to store data corresponding to the data states of the multiple memory cells. In one example, the sense amplifier circuit may determine a data state associated with a specific threshold voltage of a memory cell transistor, and two data latches may be used to store two bits corresponding to the data state. In some cases, the total number of data latches on a die (e.g., a CMOS die or a memory die) may exceed one million. A significant component of the energy per bit of the memory cell sensing operation may correspond to a parasitic current through a transistor of the data latch. When a low VT transistor is set to a non-conducting state, the parasitic current may include a leakage current through a low threshold voltage (VT) transistor. One technical benefit of using low VT transistors within a data latch to store memory cell data is that the supply voltage (e.g., VDD_SA) of the data latch can be reduced (e.g., from 1.8V to 1.5V), which can reduce the energy per bit of the memory cell sensing operation. However, a technical problem with using low VT transistors within a data latch is that parasitic currents can increase, which can increase the energy per bit of the memory cell sensing operation. In order to reduce the energy per bit of the memory cell sensing operation while using a reduced data latch supply voltage, the body effect of a selected number of low VT transistors within the data latch can be dynamically adjusted so that the body effect is minimized or absent during latching of new data into the data latch, and then the body effect is increased after the new data is latched into the data latch.

[0021] In some cases, as the bulk voltage (bulk voltage or body voltage) of the NMOS transistor drops below the source voltage of the NMOS transistor and the voltage difference between the bulk voltage and the source voltage becomes more negative, the width of the depletion region formed under the gate will increase, thereby causing the threshold voltage of the NMOS transistor to increase. This effect that the increase in the source-to-bulk voltage of the NMOS transistor causes the threshold voltage of the NMOS transistor to increase can be referred to as the "body effect." PMOS transistors can also experience the body effect when the body-to-source voltage of the PMOS transistor increases.

[0022] A sense amplifier circuit for sensing current through a memory cell and determining a data state of the memory cell may utilize a local data latch to store or temporarily buffer data associated with the determined data state. When receiving new data to be latched, the data latch may be set to a higher speed, higher power configuration, and then set to a lower speed, lower power configuration after the data has been latched. During a memory read operation, the sense amplifier circuit may dynamically adjust the body effect of the low VT NMOS transistor to balance circuit performance for circuit power. In some embodiments, in order to increase the threshold voltage of the low VT NMOS transistor used in the data latch after the new data has been latched to reduce the subthreshold leakage current through the low VT NMOS transistor when the low VT NMOS transistor is cut off or placed in a non-conducting state, the source-to-body voltage of the low VT NMOS transistor may be set to at least a first voltage difference (e.g., 0.7V). In one example, the source-to-body voltage of the low VT NMOS transistor may be set to the first voltage difference by applying 0.7V to the source of the low VT NMOS transistor and applying 0V to the PWELL body of the low VT NMOS transistor. In another example, the source-to-body voltage of the low VT NMOS transistor may be set to the first voltage difference by applying 0 V to the source of the low VT NMOS transistor and applying -0.7 V to the PWELL body of the low VT NMOS transistor. In another example, the source-to-body voltage of the low VTNMOS transistor may be set to the first voltage difference by applying positive 350 mV to the source of the low VTNMOS transistor and negative 350 mV to the PWELL body of the low VT NMOS transistor.

[0023] Determining whether to adjust the source voltage or the body voltage applied to the low VT NMOS transistor within the data latch may depend on the chip temperature and the number of data latches that are enabled. The amount of current loss due to parasitic currents through the data latches may increase with increasing chip temperature and with the number of data latches that are set to an enabled state that does not prevent parasitic currents. In one example, if the chip temperature is greater than a threshold temperature (e.g., greater than 55 degrees Celsius), the minimum source voltage applied to the low VT NMOS transistor may be set to 0.7V; however, if the chip temperature is not greater than the threshold temperature, the minimum source voltage applied to the low VT NMOS transistor may be set to 0V. In another example, if the chip temperature is less than a threshold temperature (e.g., less than 55 degrees Celsius), the PWELL body voltage applied to the low VT NMOS transistor may be set to 0V; however, if the chip temperature is not less than the threshold temperature, the PWELL body voltage applied to the low VT NMOS transistor may be set to -1V. In another example, if the number of data latches is greater than a threshold number of data latches (e.g., greater than 8 thousand data latches), the minimum source voltage applied to the low VT NMOS transistor may be set to 0.7V; however, if the number of data latches is not greater than the threshold number of data latches, the minimum source voltage applied to the low VT NMOS transistor may be set to 0V.

[0024] In order to reduce the cost and energy consumption of the memory system, one or more memory array dies and one or more CMOS dies can be stacked vertically and electrically connected together. Each CMOS die may include a memory array support circuit, such as a voltage regulator, a charge pump, a sense amplifier, a page register, and / or a state machine. Each CMOS die may include a peripheral I / O circuit for supporting one or more memory dies, a dedicated core for accelerating a specific application domain (e.g., ECC, compression, filtering, reconfigurable logic, etc.), and a lightweight CPU for supporting a general application domain. The peripheral I / O circuit may include a sense amplifier, a decoder, a charge pump, etc. The memory array die may include various memory structures, including a planar NAND structure, a vertical NAND structure, a bit cost scalable (BiCS) NAND structure, a 3D NAND structure, or a 3D ReRAM structure.

[0025] In some cases, a plurality of stacked dies may include a first group of CMOS dies and a second group of memory array dies. A CMOS die may be physically smaller or have a smaller die area than a memory array die and utilize a cheaper manufacturing process than a memory array die. A plurality of stacked dies may include a first memory array die arranged on a first layer and two or more different CMOS dies arranged on a second layer positioned above the first layer. The second memory array die may then be arranged on a third layer above the second layer. In this case, a combination of horizontal busbars and vertical busbars together with a crossbar switch transistor may allow each CMOS die within a plurality of stacked dies to be electrically connected to a first memory array die or a second memory array die. Vertical and horizontal crossbar structures may be used to allow each CMOS die to be connected to any memory array die in a memory array die within a plurality of stacked dies. TSVs may be used to make vertical connections through the substrate of the die. In one example, a crossbar structure using one or more TSVs may connect an internal node (e.g., a bit line node) within a first memory array die of a plurality of stacked dies to an internal node (e.g., a sense amplifier node) within a second die of a plurality of stacked dies.

[0026] In one embodiment, the nonvolatile memory system may include one or more two-dimensional arrays of nonvolatile memory cells. The memory cells within the two-dimensional memory array may form a single layer of memory cells and may be selected in the X and Y directions via control lines (e.g., word lines and bit lines). In another embodiment, the nonvolatile memory system may include one or more monolithic three-dimensional memory arrays, in which two or more layers of memory cells may be formed on a single substrate without any intermediate substrate. In some cases, the three-dimensional memory array may include one or more vertical columns of memory cells that are located above the substrate and are orthogonal to the substrate, or substantially orthogonal to the substrate (e.g., within 1-2 degrees of a normal vector orthogonal to the substrate). In one example, the nonvolatile memory system may include a memory array with vertical bit lines or bit lines arranged orthogonally to the semiconductor substrate. The substrate may include a silicon substrate.

[0027] Figure 11 is a block diagram of an embodiment of a memory system 100 that implements the technology of the present invention, which includes countermeasures to avoid unrecoverable errors caused by over-programming. In one embodiment, the memory system 100 is a solid state drive ("SSD"). The memory system 100 can also be a memory card, a USB drive, or other types of storage systems. The technology of the present invention is not limited to any one type of memory system. The memory system 100 is connected to a host 102, which can be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses a memory and has data processing capabilities. In some embodiments, the host 102 is separated from the memory system 100 but connected thereto. In other embodiments, the memory system 100 is embedded in the host 102.

[0028] Figure 1 The components of the memory system 100 depicted in FIG. 1 are electronic circuits. The memory system 100 includes a controller 120 connected to one or more memory dies 130 and a local high-speed volatile memory 140 (e.g., DRAM). The one or more memory dies 130 each include a plurality of non-volatile memory cells. More information about the structure of each memory die 130 is provided below. The controller 120 uses the local high-speed volatile memory 140 to perform certain functions. For example, the local high-speed volatile memory 140 stores a logical to physical address translation table ("L2P table").

[0029] The controller 120 includes a host interface 152 connected to and communicating with the host 102. In one embodiment, the host interface 152 provides a PCIe interface. Other interfaces, such as SCSI, SATA, etc., may also be used. The host interface 152 is also connected to a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of the system on chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of the integrated subsystem continues to increase, compared with previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges), NOC provides enhanced performance (such as throughput) and scalability. In other embodiments, NOC154 can be replaced by a bus. The processor 156, ECC engine 158, memory interface 160 and DRAM controller 164 are connected to and communicate with the NOC 154. The DRAM controller 164 is used to operate and communicate with the local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 140 can be SRAM or another type of volatile memory.

[0030] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a customized dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0031] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a customized dedicated hardware circuit without any software. Processor 156 also implements a conversion module, as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using a physical address associated with one or more memory tube cores. However, the host system can use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the storage system is idle to store data between the locations of one or more memory tube cores as desired. In order to implement such a system, a controller (e.g., a conversion module) performs address conversion between the logical address used by the host and the physical address used by the memory tube core. An exemplary specific implementation is to maintain a table (i.e., the above-mentioned L2P table) that identifies the current conversion between the logical address and the physical address. The entries in the L2P table may include identification of the logical address and the corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table", they need not be tables in the literal sense. Rather, logical address to physical address tables (or L2P tables) may be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In this case, the entire set of L2P tables is stored in the memory die 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed volatile memory 140.

[0032] The memory interface 160 communicates with the one or more memory dies 130. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some exemplary implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory dies.

[0033] Figure 2AAn embodiment is depicted in which the elements of the memory system are grouped into two separate dies including a memory structure die 303 (e.g., a die having only a memory array structure) and a memory array support circuit die 301 (e.g., a die including control circuits that facilitate memory operations of the memory structure 326). In some cases, the memory structure die 303 and the memory array support circuit die 301 may be bonded together or arranged as vertically stacked dies within an integrated memory component. The memory structure die 303 may include non-volatile memory cells and word lines and bit lines for accessing the non-volatile memory cells. The arrangement of control circuits for performing memory operations (e.g., read and write operations) using the memory structure 326 on the memory array support circuit die 301 allows the control circuits (e.g., row decoders, column decoders, and read / write circuits) to be manufactured using a process technology different from the process technology used to manufacture the memory structure die 303. Therefore, the memory structure die 303 can be optimized for the memory array structure without having to worry about the CMOS elements or control circuits.

[0034] In some cases, memory structure 326 may be formed on one die (such as memory structure die 303), and some or all of the peripheral circuit elements (including one or more control circuits) may be formed on a separate die (such as memory array support circuit die 301). In one example, memory structure die 303 may be formed of only one memory array of memory elements, such as a memory cell array of flash NAND memory, PCM memory, or ReRAM memory. In some cases, Figure 1 Each of the one or more memory dies 130 may correspond to Figure 2A The memory structure die 303 is provided.

[0035] refer to Figure 2A , the word lines within the memory structure 326 can be biased by the row decoder 324 within the memory array support circuit die 301, and the bit lines within the memory structure 326 can be biased by the column decoder 332 within the memory array support circuit die 301. The read / write circuit 328 includes a plurality of sense blocks 350 (the plurality of sense blocks include SB1, SB2, ..., SBp (sense circuits)) and allows one (or more) data pages of a plurality of memory cells to be read in parallel or programmed (written) in parallel. In one embodiment, each sense block includes a sense amplifier and a set of latches. The latches store data to be written and / or data that has been read. Commands and data can be received by a controller (such as a Figure 1 The controller 120 in the memory array supports transmission between the circuit die 301.

[0036] The control circuit 310 cooperates with the read / write circuit 328 to perform memory operations (e.g., write, read, erase, etc.) on the memory structure 326. In one embodiment, the control circuit 310 includes a state machine 312, an on-chip address decoder 314, a power control circuit 316, a temperature sensor circuit 318, and an ECC engine 330. The ECC engine 330 can generate an ECC code for protecting data to be stored in the memory structure 326. The state machine 312 provides die-level control of memory operations. In one embodiment, the state machine 312 is programmable by software. In other embodiments, the state machine 312 does not use software and is completely implemented in hardware (e.g., electronic circuits). In some embodiments, the state machine 312 can be replaced by a programmable microcontroller or microprocessor. In one embodiment, the control circuit 310 includes a buffer, such as a register, a ROM fuse, and other storage devices for storing default values ​​(such as base voltage and other parameters). The temperature sensor circuit 318 detects the die temperature of the memory array support circuit die 301.

[0037] In some embodiments, one or more components (alone or in combination) within the memory array support circuit die 301 may be referred to as management or control circuits. For example, the one or more management or control circuits may include any one or combination of control circuit 310, state machine 312, decoder 314, power control 316, sense block 350, or read / write circuit 328. The one or more management circuits or one or more control circuits may perform or facilitate one or more memory array operations, including erase, program, or read operations.

[0038] On-chip address decoder 314 provides an address interface between addresses used by controller 120 to hardware addresses used by decoder 324 and decoder 332. Power control module 316 controls the power and voltage provided to word lines and bit lines during memory operations. Power control module 316 may include a charge pump for generating voltages.

[0039] In one embodiment, the memory structure 326 includes a monolithic three-dimensional memory array of non-volatile memory cells, wherein multiple memory levels are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical layers of a memory cell array having an active area disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells of the memory structure 326 may be arranged in vertical NAND strings. In another embodiment, the memory structure 326 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates.

[0040] The exact type of memory array architecture or memory cells included in the memory structure 326 is not limited to the above examples. Many different types of memory array architectures or memory cell technologies can be used to form the memory structure 326. Other examples of suitable technologies for the memory cells of the memory structure 326 include ferroelectric memory (FeRAM or FeFET), ReRAM memory, magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), phase change memory (e.g., PCM), etc. Examples of suitable technologies for the architecture of the memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0041] An example of ReRAM, or PCMRAM, cross-point memory includes a reversible resistance switching element arranged in a cross-point array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0042] Magnetoresistive memory (MRAM) stores data via magnetic storage elements. The element is formed by two ferromagnetic plates, each of which can remain magnetized, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write wires that are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated.

[0043] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses a Ge2Sb2Te5 alloy to achieve phase change by electrically heating the phase change material. The programming dose is an electrical pulse of different amplitude and / or length, resulting in different resistance values ​​of the phase change material.

[0044] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but encompasses many related memory structures within the spirit and scope of the technology described herein and as understood by those of ordinary skill in the art.

[0045] Figure 2B One embodiment of a plurality of stacked dies including a memory array die 331 and a CMOS die 335 is shown. The memory array die 331 may correspond to Figure 2A The memory structure die 303 in FIG. CMOS die 335 may correspond to Figure 2A The memory array supports the circuit die 301 in FIG. Figure 2B As shown, the memory array die 331 has been positioned above the CMOS die 335 and bonded to the CMOS die 335. The memory array die 331 includes a memory array 329 having a plurality of memory cells. In one example, the memory array 329 may include a plurality of vertical NAND strings. The CMOS die 335 also includes a die mapping circuit 317 for mapping or electrically connecting one or more CMOS dies within the plurality of stacked dies to one or more memory array dies within the plurality of stacked dies. The die mapping circuit 317 may electrically connect the gate-controlled sensing circuit 313 to the bit line connection line 325 or electrically disconnect the bit line connection line 325. The die mapping circuit 317 may electrically connect the gate-controlled word line WL driver 315 to the word line connection line 323, or electrically disconnect or cut off the word line connection line 323.

[0046] CMOS die 335 also includes gated sense circuitry 313 and gated word line WL drivers 315. Gated sense circuitry 313 may include a set of sense amplifiers (or a set of read / write circuits, such as a gated word line WL driver) in series with analog multiplexers or other gated transistors. Figure 2A 325), the analog multiplexer or other gate-controlled transistor can cut off the gate-controlled sense circuit 313 from the bit line connection line 325. Since the bit line connection line 325 is already connected to the bit line BL309 of the memory array die 301 via the bonding pad 331, if the group of sense amplifiers within the gate-controlled sense circuit 313 is electrically connected to the bit line connection line 325, then the group of sense amplifiers can bias the bit line BL309 connected to the memory array 329 and sense the current from the memory cells within the memory array 329. However, if a sense amplifier from another CMOS die not shown is electrically connected to the bit line connection line 325 instead, the gate-controlled sense circuit 313 will prevent the group of sense amplifiers from being electrically connected to the bit line connection line 325.

[0047] The gated word line WL driver 315 may include a set of word line drivers (or a final row decoder) in series with an analog multiplexer or other gate-controlled transistor that may cut off or electrically disconnect the gated word line WL driver 315 from the word line connection line 323. Since the word line connection 323 is already connected to the word line WL311 of the memory array 329, if a set of word line drivers within the gated word line WL driver 315 is electrically connected to the word line connection line 323, the set of word line drivers may drive or bias the word line WL311 connected to the memory array 329. However, if a word line driver from another CMOS die not shown is instead electrically connected to the word line WL311 connected to the memory array 329, the gated word line WL driver 315 will prevent the set of word line drivers within the gated word line WL driver 315 from being electrically connected to the word line connection line 323. The word line connection line 323 and the word line WL311 connected to the memory array 329 are both electrically connected to a portion of a vertical TSV bus that includes a first TSV 325 extending through the substrate 305 of the memory array die 331 and a second TSV 327 extending through the substrate 307 of the CMOS die 335. This portion of the vertical TSV bus may allow other dies (not shown) disposed above or below the memory array die 331 to be electrically connected to the word line WL311.

[0048] Figure 3A An embodiment of an integrated memory component 104 is depicted. As shown, a memory die 302 is bonded to a control die 304. Note that although gaps are depicted between adjacent die pairs, such gaps may be filled with epoxy or other resins or polymers. The memory die 302 includes a memory structure 326. The memory structure 326 may be fabricated on a substrate 1072 of the memory die 302. In some embodiments, the substrate 1072 is formed by a portion of a silicon wafer. The memory structure 326 may include a three-dimensional memory array or a vertical NAND string array. As shown, the memory structure 326 may include a plurality of word line (WL) layers and a bit line (BL) layer. The word line layers may be separated by dielectric layers. The dielectric layers are represented by gaps between the word line layers. There are multiple columns of stacks extending through the word line layers. A column 1002 is referred to in each stack by reference numeral 1002. The column contains memory cells. For example, each column may contain a NAND string. There are many bit lines (BL) adjacent to the stack.

[0049] The word line driver 560 simultaneously provides voltage to the word line 1042 in the memory tube core 302. The conductive path from the word line driver 560 to the word line 1042 includes a conductive path 1032, a bonding pad 574a1, a bonding pad 570a1, and a conductive path 1034. In some embodiments, the conductive paths 1032, 1034 are referred to as a path pair. The conductive paths 1032, 1034 can each include one or more through holes (which can extend vertically relative to the main surface of the tube core) and one or more metal interconnects (which can extend horizontally relative to the main surface of the tube core). Conductive paths 1032, 1034 can include transistors or other circuit elements. In one embodiment, the transistor can actually be used to open or close the path. Other word line drivers ( Figure 3A ) provides voltage to other word lines. Therefore, in addition to the bonding pads 574a1, 570a1, there are additional bonding pads 574a, 570a. The bonding pads can be formed of, for example, copper, aluminum, and alloys thereof.

[0050] Sense amplifier 350 communicates with the bit line in memory die 302. The path from sense amplifier 350 to the bit line includes conductive path 1052, bonding pad 574b, bonding pad 570b and conductive path 1054. In some embodiments, conductive paths 1052, 1054 are referred to as path pairs. Conductive paths 1052, 1054 may include one or more through holes (which may extend vertically relative to the main surface of the tube core) and one or more metal interconnects (which may extend horizontally relative to the main surface of the tube core). The metal interconnects may be formed of a variety of conductive metals including aluminum, tungsten and copper, and the through holes may be lined with and / or filled with a variety of conductive metals including tungsten, copper and copper alloys. Conductive paths 1052, 1054 may include transistors or other circuit elements. In one embodiment, transistors may actually be used to open or close the path.

[0051] The control die 304 has a substrate 1076, which may be formed from a silicon wafer. The sense amplifier 350, the word line driver 560, and other circuits 1020 may be formed on and / or in the substrate 1076. The circuits 1020 may include Figure 2A In some embodiments, sense amplifier 350, word line driver 560, and / or other circuits 1020 include CMOS circuits.

[0052] There may be a connection that allows control of circuits on die 304 and entities external to integrated memory component 104 (eg, Figure 11072). The external path includes a through hole 1058 in the control die 304, a bonding pad 574c, a bonding pad 570c, a through silicon via (TSV) 1060, and an external pad 1078. The TSV 1060 extends through the substrate 1072. The TSV 1060 can be formed before, during, or after the formation of the integrated circuits in the semiconductor die 302, 304. The TSV can be formed by etching a hole through the wafer. For example, a hole can be etched through the substrate 1072.

[0053] Figure 3B Another embodiment of the integrated memory component 104 is depicted. Figure 3B The configuration in Figure 3A The configuration depicted in adds an additional memory die. Figure 3B The memory die 302a in the Figure 3A 302 in FIG. 1 . In one embodiment, the first memory die 302a is bonded to the control die 304, and the control die 304 is bonded to the second memory die 302b. Note that although gaps are depicted between adjacent die pairs, such gaps may be filled with epoxy or other resins or polymers.

[0054] Each memory die 302a, 302b includes a memory structure 326. Memory structure 326a is adjacent to substrate 1072 of memory die 302a. Memory structure 326b is adjacent to substrate 1074 of memory die 302b. In some embodiments, substrates 1072, 1074 are formed from a portion of a silicon wafer. In this example, memory structures 326 each include a three-dimensional memory array.

[0055] The word line driver 560 provides voltage to the first word line 1042 in the memory die 302a and the second word line 1044 in the memory die 302b at the same time. The path from the word line driver 560 to the second word line 1044 includes the conductive path 1032, the through silicon via (TSV) 1068, the bonding pad 576a1, the bonding pad 572a1 and the conductive path 1036. Figure 3B (not shown) provides voltage to other word lines.

[0056] Sense amplifier 350a communicates with a bit line in memory die 302a. The path from sense amplifier 350a to the bit line includes conductive path 1052, bonding pad 574b, bonding pad 570b, and conductive path 1054. Sense amplifier 350b communicates with a bit line in memory die 302b. The path from sense amplifier 350b to the bit line includes conductive path 1054, TSV 1056, bonding pad 576b, bonding pad 572b, and conductive path 1048. Figure 3B Various modifications of the illustrated embodiment are possible. One modification is to place sense amplifier 350a on the first memory die 302a and sense amplifier 350b on the second memory die 302b.

[0057] Figure 4 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array that may include a memory structure 326 including a plurality of nonvolatile memory cells arranged as vertical NAND strings. For example, Figure 4 A portion of a memory block is shown. The depicted structure includes a set of bit lines BL, which are located above a stack of alternating dielectric layers and conductive layers. For exemplary purposes, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes 108-300 alternating dielectric layers and conductive layers. An example embodiment includes 96 data word line layers, 8 selection layers, 6 dummy word line layers, and 110 dielectric layers. More or less than 108 to 300 layers may also be used. As will be explained below, the alternating dielectric layers and conductive layers are divided into four "fingers" by local interconnects LI. Figure 4 Two fingers and two local interconnects LI are shown. A source line layer SL is located below the alternating dielectric and word line layers. A memory hole is formed in the stack of alternating dielectric and conductive layers. For example, a memory hole is labeled MH. Note that Figure 4 In the , dielectric layers are depicted as perspective views so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form vertical columns of memory cells. Each memory cell can store one or more data bits.

[0058] The memory systems discussed herein can be erased, programmed, and read. At the end of a successful programming process (with verification), the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Figure 5is a graph of threshold voltage versus number of memory cells and illustrates an exemplary threshold voltage distribution for a memory array when each memory cell stores three bits of data. However, other embodiments may use other data capacities per memory cell (e.g., such as one bit of data, two bits of data, four bits of data, or five bits of data per memory cell). Figure 5 Eight threshold voltage distributions are shown, corresponding to eight data states. For data state N, the data state N has a higher threshold voltage than data state N-1 and a lower threshold voltage than data state N+1. The first threshold voltage distribution (data state) S0 represents an erased memory cell. The other seven threshold voltage distributions (data states) S1 to S7 represent programmed memory cells and are therefore also referred to as programming states or programming data states. In some embodiments, data states S1-S7 may overlap, where the controller 122 relies on error correction to identify the correct data being stored.

[0059] Figure 5 Seven read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 are shown for reading data from memory cells. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine the data state (i.e., S0, S1, S2, S3, ...) that the memory cell is in.

[0060] Figure 5 Also shown are seven verification reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 (also referred to as verification target voltages). When programming memory cells to data state S1, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv1. When programming memory cells to data state S2, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv2. When programming memory cells to data state S3, the system will determine whether the memory cells have a threshold voltage greater than or equal to Vv3. When programming memory cells to data state S4, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv4. When programming memory cells to data state S5, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv5. When programming memory cells to data state S6, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv6. When programming memory cells to data state S7, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv7.

[0061] In one embodiment, referred to as full sequence programming, memory cells may be programmed directly from erased data state S0 to any of programmed data states S1-S7. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state S0. Then, a programming process is used to program the memory cells directly into data states S1, S2, S3, S4, S5, S6, and / or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and / or from data state S0 to data state S3, and so on. Figure 5 The arrows represent full sequence programming. In addition to full sequence programming, the techniques described herein can also be used with other types of programming (including but not limited to multi-level programming / multi-phase programming).

[0062] Figure 5 Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits stored in the memory cell. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme adopted by the memory cell. In one embodiment, the data values ​​are assigned to the threshold voltage range using a Gray code assignment so that if the threshold voltage of the memory is erroneously shifted to its adjacent physical state, only one bit will be affected.

[0063] Fig. 6A is a table that describes an example of assigning data values ​​to data states. Fig. 6A In the table of , S0=111 (erased state), S1=110, S2=100, S3=000, S4=010, S5=011, S6=001, and S7=101. Other encodings of data may also be used. The technology disclosed herein does not require a specific data encoding. In one embodiment, when a block is subjected to an erase operation, all memory cells are moved to data state S0, i.e., the erased state.

[0064] Generally speaking, during a verify operation and a read operation, a selected word line is connected to a voltage (an example of a reference signal) whose level is determined for each read operation (eg, see Figure 5 of read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7) or a verification operation (eg, see Figure 5Verification reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7) are specified in order to determine whether the threshold voltage of the associated memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducting current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, unselected memory cells are provided with one or more read pass voltages (also called bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are programmed or erased).

[0065] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured at the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string including the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has been discharged. It should be noted that the techniques described herein can be used with different methods known in the art for verification / reading. Other reading and verification techniques known in the art can also be used.

[0066] As described above, memory cells may become overprogrammed. For example, consider an example of a memory cell intended to be programmed to data state S4. The programming process is designed to increase the threshold voltage of the memory cell from the threshold voltage distribution of data state S0 to the threshold voltage distribution of data S4, specifically by applying a programming signal as a set of programming pulses that increase the step size in amplitude, and testing whether the threshold voltage of the memory cell reaches Vv4 between programming pulses. However, due to structural changes or increased programming speed caused by program / erase cycles, when the threshold voltage of the memory cell reaches Vv4, it also exceeds Vr5, which may cause errors when reading the memory cell later. This is an example of overprogramming. If a small number of memory cells become overprogrammed, the ECC process during reading may be able to correct the error. However, if too many memory cells are overprogrammed or errors occur, the ECC may not be able to correct all errors and the reading process may fail, resulting in data loss.

[0067] In order to prevent data loss, a non-volatile storage system is proposed to include a mechanism for compensating for over-programming during a programming process. That is, after starting a programming process for a set of data and target memory cells and before completing the programming process for the set of data and target memory cells, the system determines whether there are over-programmed memory cells exceeding a threshold number, and if so, the system adjusts the programming process midway (e.g., in progress) during the programming process to compensate for the over-programming that has occurred so far in the programming process currently being executed.

[0068] Figure 6B One embodiment of a series of programming and verify pulses applied to a selected word line during a programming operation is depicted. The programming operation may include multiple program-verify iterations, wherein each iteration applies one or more programming pulses to the selected word line and then applies one or more verify pulses (e.g., to verify or determine the programming state or programming level of the memory cell). In one embodiment, the programming pulses are increased in steps in successive iterations. In addition, each programming pulse may include a first portion having a pass voltage (Vpass) level (e.g., 6V to 8V) followed by a second highest amplitude portion at a programming voltage (Vpgm) level (e.g., 12V to 25V). For example, as Figure 6B As shown, the first programming pulse 800, the second programming pulse 802, the third programming pulse 804, and the fourth programming pulse 806 have programming voltage levels of Vpgm1, Vpgm2, Vpgm3, and Vpgm4, respectively. One or more verification voltages 808, such as verification voltages Vva, Vvb, and Vvc, may be provided after each programming pulse. In some cases, one or more initial programming pulses are not followed by a verification pulse because it is not expected that any storage element may have reached the lowest programming state (e.g., the A state). Subsequently, in some cases, a programming iteration may verify the A state, followed by a programming iteration using a verification pulse for the A state and the B state, followed by a programming iteration using a verification pulse for the B state and the C state.

[0069] Figure 7 One embodiment of a plurality of stacked dies is depicted. As shown, the plurality of stacked dies include memory array dies 701-703 and CMOS dies 706-708 interleaved in a vertical stack. The CMOS dies 706-708 may include CMOS circuitry for controlling various memory operations performed using the memory array dies 701-703. The CMOS die 706 includes a controller 713, which may include a die mapping controller for assigning one or more CMOS dies within the plurality of stacked dies to one or more memory array dies within the plurality of stacked dies. In one example, the controller 713 may correspond to Figure 2BThe die mapping circuit 317 in the plurality of stacked dies. Each die in the plurality of stacked dies can communicate with other dies in the plurality of stacked dies via a vertical TSV bus 712. The vertical TSV bus 712 may include configurable electrical connections spanning the length of the stacked dies and may include through silicon vias passing through each of the memory array dies 701-703. The configurable electrical connections may utilize a crossbar structure or a transistor-based multiplexer.

[0070] CMOS die 706 may be flipped so that its substrate is positioned over the interconnect layer of CMOS die 706 and then positioned over and connected to memory array die 702. Some of the memory array die and CMOS die may utilize a flip chip paired with support circuits 711 located over the interconnects of CMOS die 706 and active elements of a memory array 710 (e.g., including vertical NAND strings) located over substrate 709 of memory array die 702. Electrical connectors including a portion of a vertical TSV bus 712 may extend from CMOS die 706 through substrate 709 of memory array die 702 using TSVs. Portions of vertical TSV bus 712 may be connected to support circuits of CMOS die 707 and then extend from CMOS die 707 through the substrate of memory array die 703 using another TSV. Although vertical TSV bus 712 is depicted as extending along one side of multiple stacked dies, other vertical TSV buses or electrical connectors may extend through the middle of the stacked dies.

[0071] The support circuit 711 may include a sense amplifier and a data latch for storing data read from the memory array 710. The support circuit 711 may also include a voltage regulator for generating voltages to be applied to the data latches over time. For example, the support circuit 711 may generate a body voltage (e.g., 0V or -1V) to be applied to the PWELL body of the low VT NMOS transistor within the data latch and a source voltage (e.g., 0.7V or 0V) to be applied to the source of the low VT NMOS transistor within the data latch. An analog multiplexer may be used to select between various regulated voltage levels such that 0V is applied to the source of the low VT NMOS transistor within the data latch when new data is latched, and 0.7V is applied to the source of the low VT NMOS transistor after the new data is latched.

[0072] Fig. 8A One embodiment of a portion of a sense amplifier is shown. A sense amplifier (or sense amplifier circuit) may include Figure 7802. As shown, this portion of the sense amplifier includes a bit line BL802 connected at the source side of the NMOS transistor 801, having a gate controlled by BLC. During the sensing operation, the NMOS transistor 801 can be arranged in a source follower configuration, wherein the bit line is biased to the bit line voltage by applying an appropriate voltage to BLC (e.g., setting BLC approximately to the NMOS transistor threshold voltage higher than the bit line voltage). The NMOS transistor threshold voltage may be increased due to the body effect. The precharge path for precharging the bit line BL802 can be via the precharge path 822.

[0073] Before sensing the current drawn from the bit line BL802 during the sensing operation, the bit line BL802 can be precharged to a first voltage VDD_SA (e.g., 2V or 1.5V), and the sensing node SEN804 electrically coupled to the bit line BL802 can be precharged to a second voltage VHIGH (e.g., 4V) greater than the first voltage via a precharge path 824 for precharging the sensing node. During the sensing operation, when charge is drawn from the sensing node, the voltage at the sensing node can decrease or drop from the second voltage. As the voltage of the sensing node SEN804 drops, as the PMOS transistor 810 is turned on or set to an on state, the voltage of the feedback node LBUS806 can increase via the sensing path 826.

[0074] In one embodiment, if the sense node SEN804 drops beyond the PMOS transistor threshold voltage below the second voltage VHIGH, the feedback node LBUS806 can be charged via the sense path 826. As the voltage of the feedback node LBUS806 increases, the NMOS transistor 812 can be turned on or set to a conductive state, thereby causing the PMOS transistor 814 to be turned on or set to a conductive state. When the drain of the PMOS transistor 814 is connected to the feedback node LBUS806, the voltage of the feedback node LBUS806 can be quickly raised to the second voltage VHIGH via the active pull-up of the PMOS transistor 814. Once the feedback node LBUS806 has been pulled up to the second voltage, the precharge path 824 for precharging the sense node SEN804 can be disabled when the PMOS transistor 828 has been turned off or set to a non-conductive state. If the feedback node LBUS 806 has not been charged to a voltage sufficient to turn off the PMOS transistor 828 , the sense node SEN 804 will be precharged via the precharge path 824 during a subsequent precharge phase for a subsequent sensing operation.

[0075] The local data latch 830 may include one or more data latches for storing data from the feedback node LBUS806. The local data latch 830 may be located within the sense amplifier circuit and may store a plurality of data bits corresponding to the data state of the multi-level memory cell. The external data latch 831 may include a data latch located outside the sense amplifier circuit. Various logic operations (e.g., AND operations and OR operations) may be performed using the data stored in the local data latch 830 and the external data latch 831. The stored data may also be transferred from the local data latch 830 to the external data latch 831.

[0076] The voltages VDD_SA (e.g., a supply voltage for a sense amplifier), VSS_DL (e.g., a source connection for an NMOS transistor within a data latch), and VWELL_DL (e.g., a PWELL connection for an NMOS transistor within a data latch) used to power the data latches may be generated using a voltage regulator and an analog multiplexer to select the appropriate voltages. In one example, during sensing of a memory cell current from a bit line BL802, VDD_SA may be set to 1.5V, VSS_DL may be set to 0V, and VWELL_DL may be set to 0V. After latching new data by the local data latch 830, the voltage applied to VSS_DL may be increased from 0V to 0.7V and / or the voltage applied to VWELL_DL may be decreased from 0V to -0.7V to reduce parasitic current flowing from VDD_SA. In some embodiments, each of the data latches of the local data latch 830 receives the same VSS_DL and VPWELL_DL voltage levels.

[0077] Figure 8B Depicted with Fig. 8A 802. An embodiment of a voltage waveform corresponding to the operation of the portion of the sense amplifier depicted in FIG. As shown, at time T1, LBUS and LSLH are converted from a high voltage (e.g., VHIGH) to a low voltage (e.g., 0V), so that the sense node SEN is precharged to VHIGH via the precharge path 824. The ACOM node driving the gate of the PMOS transistor 814 is also set to VHIGH. Before time T2, the voltage VSS_DL applied to the source of the low VTNMOS transistor in the data latch of the sense amplifier is converted from 0.7V to 0V. At time T2, LSLH is converted from a low voltage to a high voltage, cutting off the precharge path 824, and the NMOS transistor 803 is set to a conductive state, so that the sense node SEN804 is electrically coupled or connected to the bit line BL802.

[0078] As shown, between time T2 and T3, a first sensing operation is performed, wherein the word line voltage applied to the memory cell connected to the bit line BL802 is insufficient to set the memory cell to a high conduction state (HC), and instead the memory cell remains in a non-conducting state (NC). Due to charge leakage from the sense node (e.g., due to parasitic leakage current), the voltage of the sense node may drop slightly; however, since the feedback node LBUS806 has not been sufficiently pulled up to cut off the PMOS transistor 828, the precharge path 824 will be enabled once LSLH drops. At time T3, LSLH drops, causing the precharge path 824 to charge the sense node SEN804 to VHIGH, and STB rises, causing the feedback node LBUS to drop to VSS or 0V.

[0079] At time T4, LSLH transitions from a low voltage to a high voltage, cutting off the precharge path 824, and the NMOS transistor 803 is set to a conductive state, so that the sensing node SEN804 is electrically coupled or connected to the bit line BL802. In this case, between time T4 and T5, a second sensing operation is performed, in which the word line voltage applied to the memory cell is sufficient to set the memory cell to a conductive state or a high conductive state (HC), thereby causing the voltage of the sensing node SEN804 to drop and pull up the voltage of the feedback node LBUS806 via the sensing path 826. In the case where XFAST is low, the feedback circuit including the PMOS transistor 814 and the NMOS transistor 812 is enabled, and once LBUS is charged to the threshold voltage of the NMOS transistor 812, the gate of the PMOS transistor 814 will be pulled to ground, causing the PMOS transistor 814 to pull up the feedback node LBUS806 to VHIGH. This active pull-up on feedback node LBUS806 caused by the configuration of PMOS transistor 814 and NMOS transistor 812 allows precharge path 824 to be quickly disabled and also reduces the memory cell state data dependency on the precharge time of the sense node via precharge path 824 during subsequent sensing operations. At time T5, LSLH falls, but sense node SEN804 is not charged to VHIGH because feedback node LBUS806 has been pulled up to VHIGH, which sets PMOS transistor 828 into a non-conductive state and cuts off precharge path 824. After time T5, the voltage VSS_DL applied to the source of the low VT NMOS transistor within the data latch transitions back from 0V to 0.7V. The increase in the voltage VSS_DL applied to the source of the low VT NMOS transistor within the data latch increases the threshold voltage of the low VT NMOS transistor due to the increase in the body effect of the low VT NMOS transistor.

[0080] Figure 8C shows a data latch (such as Fig. 8A 830 in a local data latch). The data latch includes a pair of cross-coupled inverters and a latch transistor 846 controlled by a latch enable signal LAT_EN. The first inverter includes a PMOS transistor 845 and a low VT NMOS transistor 841, wherein their gates are controlled by a node XLAT. The second inverter includes a PMOS transistor 844 and a low VT NMOS transistor 840, wherein their gates are controlled by a node LAT. The latch transistor 846 includes an NMOS transistor, whose gate is controlled by a latch enable signal LAT_EN. When the latch transistor 846 is set to a conducting state, the voltage of the feedback node LBUS is transmitted to the node LAT. The enabling transistor for the data latch includes PMOS transistors 842-843. When the data latch is set to a disabled state, the PMOS transistors 842-843 are set to a non-conducting state so as to minimize the parasitic current drawn from the supply voltage VDD_SA.

[0081] As shown, when the data latch is set to an enabled state, where XEN is set to 0V, a parasitic current path may exist through one of the low VT NMOS transistors 840-841, which is set to a non-conductive state. In one example, the threshold voltage of the low VT NMOS transistor 840 may include 300mV. The use of the low VT NMOS transistors 840-841 may allow the data latch to operate at a reduced supply voltage VDD_SA at the expense of an increase in subthreshold current.

[0082] Fig.8D Shows Figure 8C One embodiment of a cross-sectional view of low VT NMOS transistors 840 and 844 is shown. Low VT NMOS transistor 840 includes gate 852, N+ source diffusion 864 within PWELL 856, and PWELL contact 862. PMOS transistor 844 includes gate 854 and P+ source / drain diffusions within NWELL 858.

[0083] Fig. 8E Depicted Fig.8D One embodiment of a cross-sectional view of a low VT NMOS transistor is depicted, wherein the gates 852 and 854 of low VTNMOS transistors 840 and 844 are set to 1.5V, the N+ source diffusion 864 is set to 0V, and PWELL 856 is set to 0V via PWELL contact 862. In this case, the source-to-bulk voltage of low VT NMOS transistor 840 is 0V, and latch node LAT can store a voltage of 1.5V corresponding to a logical "1".

[0084] Fig.8F Depicted Fig.8D One embodiment of a cross-sectional view of a low VT NMOS transistor is depicted, wherein gates 852 and 854 of low VTNMOS transistors 840 and 844 are set to 0V, N+ source diffusion 864 is set to 0V, and PWELL 856 is set to 0V via PWELL contact 862. In this case, the source-to-bulk voltage of low VT NMOS transistor 840 is 0V, and latch node LAT can store a voltage of 0V corresponding to a logical "0".

[0085] Figure 8G Depicted Fig.8D One embodiment of a cross-sectional view of a low VT NMOS transistor is depicted, wherein the gates 852 and 854 of low VTNMOS transistors 840 and 844 are set to 0.7V, the N+ source diffusion 864 is set to 0.7V, and PWELL 856 is set to 0V via PWELL contact 862. In this case, the source-to-body voltage of low VT NMOS transistor 840 is 0.7V, which increases the threshold voltage of low VT NMOS transistor 840 and reduces the subthreshold current. The gates 852 and 854 of low VT NMOS transistors 840 and 844 can be set to 0.7V instead of a lower voltage value because Figure 8C The pull-down path from the latch node LAT in will reach VSS_DL, which is set to 0.7V.

[0086] Figure 8H Depicted Fig.8D One embodiment of a cross-sectional view of a low VT NMOS transistor is depicted, wherein gates 852 and 854 of low VTNMOS transistors 840 and 844 are set to 0V, N+ source diffusion 864 is set to 0V, and PWELL 856 is set to -1V via PWELL contact 862. In this case, the source-to-bulk voltage of low VT NMOS transistor 840 is 1V, which increases the threshold voltage of low VT NMOS transistor 840 and reduces the subthreshold current.

[0087] Figure 8I Depicted Fig.8DOne embodiment of a cross-sectional view of a low VT NMOS transistor is depicted, wherein gates 852 and 854 of low VTNMOS transistors 840 and 844 are set to 0.7V, N+ source diffusion 864 is set to 0.7V, and PWELL 856 is set to -1V via PWELL contact 862. In this case, the source-to-body voltage of low VT NMOS transistor 840 is 1.7V, which increases the threshold voltage of low VT NMOS transistor 840 and reduces the subthreshold current.

[0088] In one embodiment, the data transfer time of data between data latches, the performance of logic operations between data in a plurality of data latches, and Figure 8C The performance of the data latch shown in FIG. 8 can be improved by setting N+ source diffusion 864 to 0V and PWELL 856 to 0V to minimize or eliminate the body effect of low VT NMOS transistor 840. After the new data has been latched, parasitic currents can be minimized by setting N+ source diffusion 864 to 0.7V and / or setting PWELL 856 to -1V.

[0089] Figure 8J shows a data latch (such as Fig. 8A 830 in the local data latch 830). The data latch includes a pair of cross-coupled inverters and a latch transistor controlled by a latch enable signal LAT_EN. The PMOS transistor of the cross-coupled inverter may include a high VT PMOS transistor. As shown, NMOS transistor 884 includes a high VT NMOS transistor (e.g., having a threshold voltage of 0.7V), and NMOS transistor 882 includes a low VT NMOS transistor (e.g., having a threshold voltage of 0.3V). The source of high VT NMOS transistor 884 is set to VSS or 0V, and the source of low VT NMOS transistor 882 is set to VSS_DL, which may be set to 0V or 0.7V. The gate of low VT NMOS transistor 882 is connected to a latch node LAT, which latches data transmitted from the LBUS node on the falling edge of the latch enable signal LAT_EN. One benefit of minimizing the number of low VT NMOS transistors within the data latch is that parasitic currents can be reduced.

[0090] FIG. 9A to FIG. 9B A flow chart describing one embodiment of a process for dynamically adjusting the body effect of a data latch transistor within a sense amplifier circuit during a sensing operation is depicted. The sensing operation may include a memory cell sensing operation, such as a read operation or a program verify operation. In one embodiment, FIG. 9A to FIG. 9B The process can be controlled by a control circuit (such as Figure 2A 310) and / or sensing circuits (such as Figure 2A The read / write circuit 328 in is executed. FIG. 9A to FIG. 9B The process may also use memory array support circuits such as Figure 7 Executed by the support circuit 711 in.

[0091] In step 902, a read operation is detected to be performed to read a set of data from a set of memory cells. The set of memory cells may include memory cell transistors. The set of memory cells may include NAND string memory cells, floating gate transistors, or charge trap transistors. In one example, it may be detected that a read operation is to be performed in response to obtaining a set of data from a memory array such as Figure 7 In step 904, a power supply voltage of a set of data latches for storing the set of data is determined. In one example, the power supply voltage may correspond to Fig. 8A . In some cases, if at least a threshold number of memory cells are to be accessed during a read operation or a low power mode of operation is enabled, the supply voltage may be set to 1.5V; otherwise, the supply voltage may be set to 1.8V.

[0092] In step 906, the number of data latches comprising the set of data latches is determined. The number of data latches may depend on the number of memory arrays enabled during the read operation. In step 908, the source voltage of one or more transistors in the set of data latches is determined based on the supply voltage and the number of data latches. In one example, for each sense amplifier used during the read operation, the set of data latches may correspond to Fig. 8A The source voltage of one or more transistors may correspond to the voltage applied to the local data latch 830 in FIG. Fig.8D The voltage of the N+ diffusion 864 in.

[0093] In one embodiment, if the number of data latches is greater than a threshold number of data latches (e.g., greater than 32,000 data latches), the source voltage of one or more transistors in the group of data latches may be set to 0.7 V to increase the body effect of the one or more transistors; however, if the number of data latches is not greater than the threshold number of data latches, the source voltage of one or more transistors in the group of data latches may be set to 0 V. In another embodiment, if the power supply voltage is less than a specific voltage (e.g., less than 1.6 V), the source voltage of one or more transistors in the group of data latches may be set to 0.7 V to increase the body effect of the one or more transistors; however, if the power supply voltage is not less than the specific voltage, the source voltage of the one or more transistors may be set to 0 V.

[0094] In step 910, a well voltage of one or more transistors of the set of data latches is determined based on the power supply voltage and the number of data latches. The well voltage of the one or more transistors may correspond to the voltage applied to the PWELL contact 862 via the PWELL contact 862. Fig.8D In one embodiment, if the number of data latches is greater than a threshold number of data latches (e.g., greater than 64,000 data latches), the well voltage of one or more transistors of the group of data latches may be set to negative 1V; however, if the number of data latches is not greater than the threshold number of data latches, the well voltage of one or more transistors of the data latch may be set to 0V. In another embodiment, if the power supply voltage of the group of data latches is less than a specific voltage (e.g., less than 1.6V), the well voltage of one or more transistors of the group of data latches may be set to negative 1V; however, if the power supply voltage of the group of data latches is not less than a specific voltage, the well voltage of one or more transistors of the group of data latches may be set to 0V.

[0095] In step 912, one or more sources of one or more transistors are set to a source voltage. In one example, the one or more sources may correspond to Fig.8D N+ diffusion 864 in, and one or more transistors may correspond to Fig.8D The low VT NMOS transistor 840 in the transistor 840 is set to 0.7V. If the number of data latches is greater than the threshold number of data latches or the power supply voltage is less than a certain voltage (e.g., less than 1.6V), one or more sources may be set to 0.7V. In step 914, one or more wells of one or more transistors are set to a well voltage. In one example, the one or more wells may correspond to Fig.8D The PWELL856 in the , and one or more transistors may correspond to Fig.8D The low VT NMOS transistor 840 in FIG.

[0096] In step 916, the set of data is read from the set of memory cells. A sense amplifier such as Fig. 8A The sense amplifier shown in FIG. 1 reads the set of data from the set of memory cells. In step 918, the set of data latches are used to store the set of data. The set of data latches may correspond to Fig. 8A In step 920, a logic operation may be performed using the set of data stored in the set of data latches. In one example, a combination of a logical AND operation and an OR operation may be performed. In step 922, at least one subset of the set of data may be obtained from the set of data latches (such as Fig. 8A 830) to a set of external data latches (such as Fig. 8A In step 924, a second source voltage greater than the source voltage is determined. In step 926, a second well voltage less than the well voltage is determined. In step 928, after storing the set of data using the set of data latches, one or more sources of the one or more transistors are set to the second source voltage. In step 930, after storing the set of data using the set of data latches, one or more wells of the one or more transistors are set to the second well voltage.

[0097] FIG. 9C to FIG. 9D A flow chart describing an alternative embodiment of a process for dynamically adjusting the body effect of a data latch transistor within a sense amplifier circuit during a sensing operation is depicted. In one embodiment, FIG. 9C to FIG. 9D The process can be controlled by a control circuit (such as Figure 2A 310) and / or sensing circuits (such as Figure 2A The read / write circuit 328 in is executed. FIG. 9C to FIG. 9D The process may also use support circuits such as Figure 7 Executed by the support circuit 711 in.

[0098] In step 932, a memory operation including determining a set of data states of a set of memory cells is initiated. The memory operation may include a read operation or a program verification operation. In step 934, a temperature associated with the set of memory cells is determined. In one example, an on-die temperature sensor may be used to determine the temperature associated with the set of memory cells. In step 936, the number of data latches used to store the set of data states is identified. The number of data latches used for the memory operation may correspond to the number of memory arrays enabled for the memory operation. In step 938, a first source voltage of one or more transistors in the set of data latches is determined based on the temperature and the number of data latches. In one embodiment, if the number of data latches is greater than a threshold number of data latches (e.g., greater than 16,000 data latches), the first source voltage may be set to 0.7V. However, if the number of data latches is not greater than the threshold number of data latches, the first source voltage may be set to 0V. In another embodiment, if the temperature is greater than a threshold temperature (e.g., if the temperature is greater than 55 degrees Celsius), the first source voltage may be set to 0.7V. However, if the temperature is not greater than the threshold temperature, the first source voltage may be set to 0V.

[0099] In step 940, a first well voltage of one or more transistors of the group of data latches is determined based on the temperature and the number of data latches. In one embodiment, if the number of data latches is less than a threshold number of data latches (e.g., if the number of data latches is less than 16,000 data latches), the first well voltage of the one or more transistors may be set to 0V. However, if the number of data latches is greater than the threshold number of data latches, the first well voltage of the one or more transistors may be set to negative 1V. In another embodiment, if the temperature is greater than a threshold temperature (e.g., greater than 55 degrees Celsius), the first well voltage for the one or more transistors may be set to negative 1V. However, if the temperature associated with the group of memory cells is not greater than the threshold temperature, the first well voltage of the one or more transistors may be set to 0V.

[0100] In step 942, one or more sources of one or more transistors are set to a first source voltage. The one or more sources may correspond to one or more source diffusions, such as Fig.8D In step 944, one or more wells of the one or more transistors are set to a first well voltage. The one or more transistors may correspond to Figure 8C. In step 946, data associated with the set of data states is stored using the set of data latches when one or more sources are set to a first source voltage and one or more wells are set to a first well voltage. In step 948, a second source voltage greater than the source voltage is determined. In step 950, a second well voltage less than the well voltage is determined. In step 952, after storing the data associated with the set of data states using the set of data latches, one or more sources of the one or more transistors are set to a second source voltage. In step 954, after storing the data associated with the set of data states using the set of data latches, one or more wells of the one or more transistors are set to a second well voltage. In step 956, the data associated with the set of data states is transmitted. In one example, the data associated with the set of data states is transmitted from the set of data latches to a control circuit, such as Figure 2A The control circuit 310 in.

[0101] An embodiment of the disclosed technology includes a read circuit and a data latch circuit in communication with the read circuit. The read circuit is configured to read data from a memory cell. The data latch circuit includes a transistor in a non-conducting state. The data latch circuit is configured to latch data from the read circuit and increase a threshold voltage of the transistor after the data is latched.

[0102] An embodiment of the disclosed technology includes: detecting that a read operation is to be performed to read a set of data from a set of memory cells; identifying a set of data latches for storing the set of data; determining a source voltage of one or more transistors in the set of data latches; determining a well voltage of one or more transistors of the set of data latches; setting one or more sources of the one or more transistors to a source voltage; setting one or more wells of the one or more transistors to a well voltage; reading a set of data from a set of memory cells; storing a set of data using a set of data latches when one or more sources are set to a source voltage and one or more wells are set to a well voltage; determining a second source voltage greater than the source voltage; and after storing a set of data using the set of data latches, setting one or more sources of the one or more transistors to the second source voltage.

[0103] One embodiment of the disclosed technology includes a sensing circuit and a data latch circuit. The sensing circuit is configured to determine a data state of a memory cell. The data latch circuit includes a transistor. The data latch circuit is configured to latch data corresponding to the data state of the memory cell when a source-to-body voltage of the transistor is set to a first voltage. The data latch circuit is configured to retain data corresponding to the data state of the memory cell when the source-to-body voltage of the transistor is set to a second voltage greater than the first voltage.

[0104] For purposes herein, if zero, one, or more intermediate layers are between a first layer and a second layer, then the first layer may be on or over the second layer.

[0105] For the purposes of this document, it should be noted that the dimensions of the various features depicted in the drawings are not necessarily drawn to scale.

[0106] For purposes herein, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments and do not necessarily refer to the same embodiment.

[0107] For purposes herein, a connection may be a direct connection or an indirect connection (e.g., via another part). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element.

[0108] Two devices may be "in communication" if they are directly connected or indirectly connected such that they are capable of communicating electronic signals between them.

[0109] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0110] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0111] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0112] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A device comprising: a read circuit configured to read data from the memory cell; a data latch circuit in communication with the read circuit, the data latch circuit comprising a transistor in a non-conductive state, the data latch circuit being configured to latch the data from the read circuit and to increase a threshold voltage of the transistor after latching the data; as well as A control circuit is configured to determine a chip temperature and apply a first voltage to a source of the transistor based on the chip temperature to increase the threshold voltage of the transistor after latching the data.

2. The device according to claim 1, wherein: The memory cell is arranged on a first die; and The data latch circuit is disposed on the second die.

3. The device according to claim 1, wherein: The data latch circuit is configured to increase a source-to-bulk voltage of the transistor after latching the data.

4. The device according to claim 1, wherein: The transistor comprises an NMOS transistor.

5. The device according to claim 1, wherein: The transistor includes an NMOS transistor, and a body voltage of the transistor is reduced after latching the data.

6. The device according to claim 1, wherein: The control circuit is configured to determine a number of enabled data latches and determine the first voltage to be applied to the source of the transistor based on the number of enabled data latches.

7. The device according to claim 1, wherein: The memory cell is disposed on a first die and the data latch circuit is disposed on the first die.

8. The device according to claim 1, wherein: The control circuit is configured to identify a number of enabled data latches and determine the first voltage to be applied to the source of the transistor based on the number of enabled data latches.

9. The device according to claim 1, wherein: The memory cell includes a floating gate transistor.

10. A method comprising: detecting that a read operation is to be performed to read a set of data from a set of memory cells; identifying a set of data latches for storing the set of data; determining a source voltage of one or more transistors for the set of data latches; determining a well voltage of the one or more transistors for the set of data latches; prior to storing the set of data using the set of data latches, setting one or more sources of the one or more transistors to the source voltage; prior to storing the set of data using the set of data latches, setting one or more wells of the one or more transistors to the well voltage; reading the set of data from the set of memory cells; storing the set of data using the set of data latches when the one or more sources are set to the source voltage and the one or more wells are set to the well voltage; Determine chip temperature; determining a second source voltage greater than the source voltage based on the chip temperature; and After the set of data has been latched using the one or more transistors, the second source voltage greater than the source voltage is applied to the one or more sources of the one or more transistors to increase one or more threshold voltages of the one or more transistors.

11. The method according to claim 10, further comprising: determining a second well voltage less than the well voltage; as well as After the set of data has been latched using the one or more transistors, the one or more wells of the one or more transistors are set to the second well voltage.

12. An apparatus comprising: a sensing circuit configured to determine a data state of a memory cell; a data latch circuit, the data latch circuit comprising a transistor, the data latch circuit being configured to latch data corresponding to the data state of the memory cell when a source of the transistor is set to a first voltage, the data latch circuit being configured to retain the data corresponding to the data state of the memory cell when the source of the transistor is set to a second voltage greater than the first voltage; as well as A control circuit is configured to determine a chip temperature and apply the second voltage to the source of the transistor to increase a threshold voltage of the transistor after the data has been latched based on the chip temperature.

13. The device according to claim 12, wherein: The data latch circuit is configured to latch the data corresponding to the data state of the memory cell when the source-to-body voltage of the transistor is 0V, and to maintain the data corresponding to the data state of the memory cell when the source-to-body voltage of the transistor is greater than 600mV.

14. The device according to claim 12, wherein: The memory cell is arranged on a first die; and The data latch circuit is disposed on the second die.

15. The device according to claim 12, wherein: The control circuit is configured to set the body of the transistor to a third voltage that is less than the first voltage.

16. The apparatus of claim 12, wherein: The control circuit is configured to detect that the chip temperature has exceeded a temperature threshold.

17. The apparatus of claim 12, wherein: The control circuit is configured to determine a number of data latches enabled during a particular time period, and determine the first voltage based on the number of the data latches enabled during the particular time period.

18. The apparatus of claim 12, wherein: The transistor includes an NMOS transistor.

Images