Semiconductor package

Abstract

A semiconductor package includes a package substrate including a first substrate via pad and a second substrate via pad; a chip stack including a plurality of semiconductor chips stacked on the package substrate to be offset in a first direction, wherein first semiconductor chips among the plurality of semiconductor chips located at odd layers and second semiconductor chips among the plurality of semiconductor chips located at even layers are offset in a second direction perpendicular to the first direction, each of the first semiconductor chips includes a first chip via pad, and each of the second semiconductor chips includes a second chip via pad; first inter-chip connection wires configured to electrically connect the first chip via pads of the first semiconductor chips to each other; and second inter-chip connection wires configured to electrically connect the second chip via pads of the second semiconductor chips to each other.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0078046, filed on June 25, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor package, and more specifically, to a semiconductor package having a structure in which a plurality of semiconductor chips are vertically stacked on top of each other. Background Technology

[0004] Semiconductor products require high-capacity data processing while their size is constantly decreasing. Semiconductor packages with structures in which multiple semiconductor chips are stacked can process large amounts of data quickly while having a small footprint. However, as the number of stacked semiconductor chips and the number of electrode pads formed on the semiconductor chips increase, the electrical connections between the semiconductor chips become difficult and complex. Summary of the Invention

[0005] The present invention provides a semiconductor package that can improve the reliability of electrical connections between multiple semiconductor chips and the reliability of electrical connections between multiple semiconductor chips and a substrate.

[0006] According to one aspect of the present invention, a semiconductor package is provided, the semiconductor package comprising: a package substrate including a first substrate channel pad and a second substrate channel pad; a chip stack comprising a plurality of semiconductor chips stacked on the package substrate and offset in a first direction, wherein first semiconductor chips located at odd-numbered layers and second semiconductor chips located at even-numbered layers of the plurality of semiconductor chips are offset in a second direction perpendicular to the first direction, each of the first semiconductor chips including a first chip channel pad, and each of the second semiconductor chips including a second chip channel pad; a first inter-chip interconnect configured to electrically connect the first chip channel pads of the first semiconductor chips to each other; a second inter-chip interconnect configured to electrically connect the second chip channel pads of the second semiconductor chips to each other; a first substrate-chip interconnect configured to connect the first chip channel pad of the bottommost first semiconductor chip to the first substrate channel pad; and a second substrate-chip interconnect configured to connect the second chip channel pad of the bottommost second semiconductor chip to the second substrate channel pad.

[0007] According to another aspect of the present invention, a semiconductor package is provided, the semiconductor package comprising: a package substrate including a common substrate pad, a first substrate channel pad, and a second substrate channel pad; a plurality of semiconductor chips stacked on the package substrate and offset in a first direction, each of the plurality of semiconductor chips including a common pad and a channel pad; a first inter-chip interconnect configured to electrically connect the channel pads of the semiconductor chips located on an odd-numbered layer among the plurality of semiconductor chips to each other; a second inter-chip interconnect configured to electrically connect the channel pads of the semiconductor chips located on an even-numbered layer among the plurality of semiconductor chips to each other; and a third inter-chip interconnect configured to... The plurality of semiconductor chips have common pads electrically connected to each other; a first substrate-chip connection wire configured to electrically connect the channel pad of the lowest semiconductor chip in the odd-numbered layers to a first substrate channel pad; a second substrate-chip connection wire configured to electrically connect the channel pad of the lowest semiconductor chip in the even-numbered layers to a second substrate channel pad; a third substrate-chip connection wire configured to electrically connect the common pad of the lowest semiconductor chip in the odd-numbered layers to a common substrate pad; and a controller mounted on a package substrate, including a first channel and a second channel separated from each other. The first channel of the controller is electrically connected to the semiconductor chips in the odd-numbered layers via the first substrate-chip connection wire and a first inter-chip connection wire, and the second channel of the controller is electrically connected to the semiconductor chips in the even-numbered layers via the second substrate-chip connection wire and the second inter-chip connection wire.

[0008] According to another aspect of the present invention, a semiconductor package is provided, the semiconductor package comprising: a package substrate including a common substrate pad, a first substrate channel pad, and a second substrate channel pad; a plurality of semiconductor chips stacked vertically on the package substrate, each of the plurality of semiconductor chips including a common pad and a channel pad; a first inter-chip interconnect configured to electrically connect the channel pads of semiconductor chips located in odd-numbered layers to each other; a second inter-chip interconnect configured to electrically connect the channel pads of semiconductor chips located in even-numbered layers to each other; a third inter-chip interconnect configured to electrically connect the common pads of the plurality of semiconductor chips to each other; a first substrate-chip connection wire configured to connect the channel pad of the lowest layer of the semiconductor chips located in odd-numbered layers to the first substrate channel pad; and a second substrate-chip connection wire configured to connect the channel pad of the lowest layer of the semiconductor chips located in odd-numbered layers to the first substrate channel pad; and a second substrate-chip connection wire, wherein... The package includes a third substrate-chip interconnect configured to connect a channel pad of the lowest semiconductor chip in an even-numbered semiconductor chip layer to a second substrate channel pad; a third substrate-chip interconnect configured to electrically connect a common pad of the lowest semiconductor chip in an odd-numbered semiconductor chip layer to a common substrate pad; and a controller mounted on a package substrate, electrically connected to the odd-numbered semiconductor chips via a first substrate-chip interconnect and a first inter-chip interconnect, and electrically connected to the even-numbered semiconductor chips via a second substrate-chip interconnect and a second inter-chip interconnect, wherein the number of first inter-chip interconnects is equal to the number obtained by subtracting 1 from the total number of semiconductor chips in odd-numbered layers, the number of second inter-chip interconnects is equal to the number obtained by subtracting 1 from the total number of semiconductor chips in even-numbered layers, and the number of third inter-chip interconnects is equal to the number obtained by subtracting 1 from the total number of semiconductor chips. Attached Figure Description

[0009] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a perspective view of a semiconductor package according to an exemplary embodiment of the present invention;

[0011] Figure 2 yes Figure 1 A plan view of a semiconductor package;

[0012] Figure 3 and Figure 4 It is shown Figure 1 Cross-sectional views of different sections of a semiconductor package;

[0013] Figure 5This is a plan view of a semiconductor package according to an exemplary embodiment of the present invention;

[0014] Figure 6 This is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention;

[0015] Figure 7 It is shown Figure 6 A block diagram of the main components of a semiconductor package;

[0016] Figure 8 This is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention;

[0017] Figure 9 This is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention;

[0018] Figure 10 It is shown Figure 9 A block diagram of the main components of a semiconductor package; and

[0019] Figure 11 This is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. Detailed Implementation

[0020] In the following description, embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. In the drawings, the same reference numerals may denote the same elements, and repeated descriptions of the same elements will be omitted.

[0021] Figure 1 This is a perspective view of a semiconductor package 100 according to an exemplary embodiment of the present invention. Figure 2 yes Figure 1 A plan view of the semiconductor package 100. Figure 3 and Figure 4 This is a cross-sectional view showing different sections of the semiconductor package 100.

[0022] Reference Figures 1 to 4 The semiconductor package 100 may include a package substrate 130 and a chip stack 101.

[0023] Package substrate 130 may include, for example, a printed circuit board (PCB), a flexible substrate, or a strip substrate. Package substrate 130 may include upper substrate pads disposed on the upper surface of package substrate 130. For example, one or more substrate common pads 135, one or more first substrate channel pads 131, and one or more second substrate channel pads 133 may be disposed on the upper surface of package substrate 130. Package substrate 130 may include lower substrate pads 139 disposed on the lower surface of package substrate 130. External connection terminals 190 configured to electrically connect external devices to semiconductor package 100 may be disposed on lower substrate pads 139. External connection terminals 190 may be, for example, solder balls.

[0024] The chip stack 101 may include a plurality of semiconductor chips stacked on the package substrate 130 in a vertical direction (Z direction). Although the chip stack 101 is... Figures 1 to 4 The chip stack 101 includes eight semiconductor chips stacked vertically, but the embodiments are not limited to this. For example, the chip stack 101 may include three to seven semiconductor chips, or nine or more semiconductor chips.

[0025] According to an exemplary embodiment of the present invention, the chip stack 101 may include a first semiconductor chip 110 located in an odd-numbered layer among the plurality of semiconductor chips and a second semiconductor chip 120 located in an even-numbered layer among the plurality of semiconductor chips. The odd-numbered layers and odd-numbered layers are defined based on the upper surface of the package substrate 130 on which the chip stack 101 is mounted. The lowest-ranking first semiconductor chip 110 among the first semiconductor chips 110 refers to the semiconductor chip of the first semiconductor chip 110 that is closest to the upper surface of the package substrate 130 in a direction perpendicular to the upper surface of the package substrate 130, and the lowest-ranking second semiconductor chip 120 among the second semiconductor chips 120 refers to the semiconductor chip of the second semiconductor chip 120 that is closest to the upper surface of the package substrate 130 in a direction perpendicular to the upper surface of the package substrate 130 (e.g., the Z-direction).

[0026] like Figures 1 to 4 As shown, the first semiconductor chip 110 and the second semiconductor chip 120 may alternate with each other in the vertical direction on the upper surface of the package substrate 130. For example, when the chip stack 101 includes eight semiconductor chips, the chip stack 101 may include four first semiconductor chips 110 and four second semiconductor chips 120.

[0027] According to exemplary embodiments, the plurality of semiconductor chips included in the chip stack 101 may be semiconductor chips of the same type. For example, the plurality of semiconductor chips may be memory semiconductor chips. Each of the memory semiconductor chips may be, for example, a volatile memory semiconductor chip (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or a non-volatile memory semiconductor chip (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)). According to some exemplary embodiments, the plurality of semiconductor chips may be flash memory, such as NAND flash memory.

[0028] According to other exemplary embodiments, the plurality of semiconductor chips included in the chip stack 101 may include different types of semiconductor chips. For example, some of the plurality of semiconductor chips may be logic chips, and others may be memory chips. For example, each of the logic chips may be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0029] Each semiconductor chip may include chip pads adjacent to and arranged along a first edge of the semiconductor chip. For example, the chip pads of each semiconductor chip may be arranged in a second direction (Y direction), adjacent to an edge parallel to the second direction (Y direction). The chip pads included in each semiconductor chip may be electrically connected to an integrated circuit disposed within the semiconductor chip. For example, the integrated circuit may include memory circuitry or logic circuitry.

[0030] According to an exemplary embodiment, multiple semiconductor chips may have the same dimensions. For example, multiple semiconductor chips may have the same horizontal width, the same vertical width, and the same thickness.

[0031] Multiple semiconductor chips can have pad arrangements with the same shape. For example, the number of chip pads included in each semiconductor chip, the arrangement order of the chip pads, the size of each chip pad, and the spacing between the chip pads can all be the same in multiple semiconductor chips.

[0032] Adhesive members 180 may be disposed on the lower surfaces of each first semiconductor chip 110 and each second semiconductor chip 120. The first semiconductor chip 110 may be stacked on the second semiconductor chip 120 disposed below the first semiconductor chip 110 via the adhesive members 180, and the second semiconductor chip 120 may be stacked on the first semiconductor chip 110 disposed below the second semiconductor chip 120 via another adhesive member 180. The lowest layer of the first semiconductor chip 110 may be attached to the upper surface of the package substrate 130 via another adhesive member 180. For example, the adhesive member 180 may be a bare die attachment film (DAF).

[0033] Multiple semiconductor chips included in the chip stack 101 can be stacked such that they are sequentially offset from each other in a first direction (X direction), such that each semiconductor chip extends beyond the side surface of the underlying semiconductor chip. For example, a second semiconductor chip 120 can be stacked on top of a first semiconductor chip 110 disposed below it, such that a portion of the second semiconductor chip 120 protrudes from the first semiconductor chip 110 in the first direction (X direction). Similarly, a first semiconductor chip 110 can be stacked on top of a second semiconductor chip 120 disposed below it, such that a portion of the first semiconductor chip 110 protrudes from the second semiconductor chip 120 in the first direction (X direction). For example, multiple semiconductor chips can be stacked on top of each other in a stepped manner.

[0034] Multiple semiconductor chips can be stacked to be offset by a first offset distance 171 in a first direction (X direction), thereby exposing chip pads included in each semiconductor chip. For example, a second semiconductor chip 120 can be stacked to be offset by the first offset distance 171 in the first direction (X direction), such that it does not cover the chip pads of a first semiconductor chip 110 disposed below the second semiconductor chip 120. The first semiconductor chip 110 can be stacked to be offset by the first offset distance 171 in the first direction (X direction), such that it does not cover the chip pads of the second semiconductor chip 120 disposed below the first semiconductor chip 110.

[0035] According to an exemplary embodiment, the first offset distance 171 can be between approximately 230 micrometers (μm) and approximately 400 μm. When the first offset distance 171 is less than 230 μm, the chip pads of each semiconductor chip can be covered by other semiconductor chips. When the first offset distance 171 is greater than 400 μm, the stacked structure of multiple semiconductor chips collapses.

[0036] According to an exemplary embodiment, the second semiconductor chip 120 can be offset relative to the first semiconductor chip 110 in a second direction (Y direction) perpendicular to the first direction (X direction). For example, the second semiconductor chip 120 can be stacked on top of the first semiconductor chip 110 disposed below it, such that a portion of the second semiconductor chip 120 protrudes from the first semiconductor chip 110 in the second direction (Y direction). The first semiconductor chip 110 can be stacked on top of the second semiconductor chip 120 disposed below it, such that a portion of the first semiconductor chip 110 protrudes from the second semiconductor chip 120 in the second direction (Y direction). Because the plurality of semiconductor chips included in the chip stack 101 are sequentially offset in the first direction (X direction), and the second semiconductor chip 120 is offset from the first semiconductor chip 110 in the second direction (Y direction), the plurality of semiconductor chips can... Figure 2 The planar diagram shown is arranged in a zigzag pattern. For example, the side surfaces of the first semiconductor chip 110 can be aligned along the first direction (X direction), and the side surfaces of the second semiconductor chip 120 can be aligned along the first direction (X direction).

[0037] According to an exemplary embodiment, when the distance by which the second semiconductor chip 120 is offset relative to the first semiconductor chip 110 in the second direction (Y direction) is defined as the second offset distance 172, the second offset distance 172 can be approximately 60 μm to approximately 80 μm. For example, the side surface of the first semiconductor chip 110 can be offset by the second offset distance 172 relative to the adjacent side surface of the second semiconductor chip 120 in the second direction (Y direction).

[0038] Each of the first semiconductor chips 110 may include chip pads arranged along a first edge of each of the first semiconductor chips 110. The chip pads of each of the first semiconductor chips 110 may include one or more first chip channel pads 111 and one or more first chip common pads 115.

[0039] Each of the first semiconductor chips 110 may have the same pad arrangement. For example, the arrangement order of the chip pads, including the first chip channel pads 111 and the first chip common pads 115, the number of first chip channel pads 111, the number of first chip common pads 115, and the spacing between the chip pads may be the same in each of the first semiconductor chips 110. When viewed in a plan view, the first chip channel pads 111 of the first semiconductor chips 110 located on different layers may be arranged side by side in a first direction (X direction). For example, the first chip channel pads 111 of the first semiconductor chips 110 located on different layers may be aligned in the first direction (X direction). When viewed in a plan view, the first chip common pads 115 of the first semiconductor chips 110 located on different layers may be arranged side by side in the first direction (X direction). For example, the first chip common pads 115 of the first semiconductor chips 110 located on different layers may be aligned in the first direction (X direction). According to an exemplary embodiment, the width 175 of each of the first chip channel pads 111 in the second direction (Y direction) can be approximately 50 μm to approximately 80 μm. According to an exemplary embodiment, the spacing 176 between two adjacent first chip channel pads 111 in the second direction (Y direction) can be approximately 80 μm to approximately 180 μm.

[0040] First chip channel pads 111 of first semiconductor chips 110 located on different layers can be electrically connected to each other via first inter-chip interconnects 141. Each of the first inter-chip interconnects 141 can connect the first chip channel pads 111 of two first semiconductor chips 110 that are spaced apart from each other in the vertical direction, with a single second semiconductor chip 120 between the two first semiconductor chips 110. For example, the first chip channel pads 111 of first semiconductor chips 110 located on the first and third layers can be electrically connected to each other via different first inter-chip interconnects 141, the first chip channel pads 111 of first semiconductor chips 110 located on the third and fifth layers can be electrically connected to each other, and the first chip channel pads 111 of first semiconductor chips 110 located on the fifth and seventh layers can be electrically connected to each other. In this case, the number of first inter-chip interconnects 141 can be equal to the number obtained by subtracting 1 from the total number of first semiconductor chips 110 included in the chip stack 101. For example, three first chip-to-chip interconnect wires 141 can be used to electrically connect four first semiconductor chips 110 to first chip channel pads 111 aligned in a first direction (X direction). For example, each group of first chip channel pads 111 aligned in the first direction (X direction) can be electrically connected to each other by the first chip-to-chip interconnect wires 141, wherein the number of first chip-to-chip interconnect wires 141 is one less than the total number of first chip channel pads 111 aligned in the first direction (X direction).

[0041] According to an exemplary embodiment, the first semiconductor chip 110 may be a NAND flash memory and may be connected to the same channel. A channel may refer to a set of signals used in NAND flash memory. For example, because the first chip channel pads 111 of the first semiconductor chips 110 located on different layers are electrically connected to each other via first inter-chip interconnect wires 141, the first semiconductor chips 110 may be connected to the same channel.

[0042] The first chip channel pad 111 of the lowest layer of the first semiconductor chip 110 can be electrically connected to the first substrate channel pad 131 of the package substrate 130 via the first substrate-chip connection wire 151. The first substrate-chip connection wire 151 can be configured to transmit various signals to the first chip channel pad 111 of the first semiconductor chip 110 connected to the same channel.

[0043] According to an exemplary embodiment, each of the first chip channel pads 111 may correspond to one of the following: an I / O pad through which data input / output (I / O) signals are transmitted, a DQS pad through which data strobe signals (DQS) are transmitted, a CE pad through which chip enable (CE) signals are transmitted, an RE pad through which read enable (RE) signals are transmitted, a WE pad through which write enable (WE) signals are transmitted, a CLE pad through which command latch enable (CLE) signals are transmitted, an ALE pad through which address latch enable (ALE) signals are transmitted, and an R / B pad through which ready / busy (R / B) signals are transmitted.

[0044] According to an exemplary embodiment, each of the first chip common pads 115 may correspond to a Vcc pad for supplying a power supply voltage (e.g., a voltage from 2.0V to 5.0V) to the first semiconductor chip 110 or a Vss pad for supplying a ground voltage to the first semiconductor chip 110.

[0045] Each of the second semiconductor chips 120 may include chip pads arranged along a first edge of each of the second semiconductor chips 120. The chip pads of each of the second semiconductor chips 120 may include one or more second chip channel pads 121 and one or more second chip common pads 125.

[0046] Each of the second semiconductor chips 120 may have the same pad arrangement. For example, the arrangement order of the chip pads, including the second chip channel pads 121 and the second chip common pads 125, the number of second chip channel pads 121, the number of second chip common pads 125, and the spacing between the chip pads may be the same in each of the second semiconductor chips 120. When viewed in a plan view, the second chip channel pads 121 of the second semiconductor chips 120 located on different layers may be arranged side by side in a first direction (X direction). For example, the second chip channel pads 121 of the second semiconductor chips 120 located on different layers may be aligned along the first direction (X direction). When viewed in a plan view, the second chip common pads 125 of the second semiconductor chips 120 located on different layers may be arranged side by side in the first direction (X direction). For example, the second chip common pads 125 of the second semiconductor chips 120 located on different layers may be aligned along the first direction (X direction). According to an exemplary embodiment, the width 173 of each of the second chip channel pads 121 in the second direction (Y direction) may be approximately 50 μm to approximately 80 μm. According to an exemplary embodiment, the spacing 174 between two adjacent second chip channel pads 121 in the second direction (Y direction) can be approximately 80 μm to approximately 180 μm. According to an exemplary embodiment, the pad arrangement of the chip pads of the second semiconductor chip 120 can be the same as the pad arrangement of the chip pads of the first semiconductor chip 110.

[0047] Second chip channel pads 121 of second semiconductor chips 120 located on different layers can be electrically connected to each other via second inter-chip interconnects 143. Each of the second inter-chip interconnects 143 can connect the second chip channel pads 121 of two second semiconductor chips 120 that are spaced apart from each other in the vertical direction, with a single first semiconductor chip 110 between the two second semiconductor chips 120. For example, the second chip channel pads 121 of second semiconductor chips 120 located on the second and fourth layers can be electrically connected to each other via different second inter-chip interconnects 143, the second chip channel pads 121 of second semiconductor chips 120 located on the fourth and sixth layers can be electrically connected to each other, and the second chip channel pads 121 of second semiconductor chips 120 located on the sixth and eighth layers can be electrically connected to each other. In this case, the number of second inter-chip interconnects 143 can be equal to the number obtained by subtracting 1 from the total number of second semiconductor chips 120 included in the chip stack 101. For example, three second inter-chip interconnect wires 143 can be used to electrically connect four second semiconductor chips 120 to second chip channel pads 121 aligned in a first direction (X direction). For example, each group of second chip channel pads 121 aligned in the first direction (X direction) can be electrically connected to each other by the second inter-chip interconnect wires 143, wherein the number of second inter-chip interconnect wires 143 is one less than the total number of second chip channel pads 121 aligned in the first direction (X direction).

[0048] According to an exemplary embodiment, the second semiconductor chip 120 may be a NAND flash memory and may be connected to the same channel. For example, because the second chip channel pads 121 of the second semiconductor chips 120 located on different layers are electrically connected to each other via second inter-chip interconnect wires 143, the second semiconductor chips 120 may be connected to the same channel. In this case, the second semiconductor chip 120 may be connected to a different channel than the channel connected to the first semiconductor chip 110.

[0049] The second chip channel pad 121 of the lowest layer of the second semiconductor chip 120 can be electrically connected to the second substrate channel pad 133 of the package substrate 130 via the second substrate-chip connection wire 153. The second substrate-chip connection wire 153 can be configured to transmit various signals to the second chip channel pad 121 of the second semiconductor chip 120 connected to the same channel.

[0050] According to an exemplary embodiment, each of the second chip channel pads 121 may correspond to one of the I / O pads, DQS pads, CE pads, RE pads, WE pads, CLE pads, ALE pads, and R / B pads.

[0051] According to an exemplary embodiment, each of the second chip common pads 125 may correspond to a Vcc pad for supplying power supply voltage to the second semiconductor chip 120 or a Vss pad for supplying ground voltage to the second semiconductor chip 120.

[0052] A first chip common pad 115 of a first semiconductor chip 110 located on a different layer can be electrically connected to a second chip common pad 125 of a second semiconductor chip 120 located on a different layer via a third inter-chip connection wire 145. Each of the third inter-chip connection wires 145 can extend between the first semiconductor chip 110 and the second semiconductor chip 120 to connect to each other in a vertical direction. For example, each first semiconductor chip 110 can be connected to one or more second semiconductor chips 120 located at adjacent horizontal levels via the third inter-chip connection wire 145. In this case, the number of third inter-chip connection wires 145 can be equal to the number obtained by subtracting 1 from the sum of the number of first semiconductor chips 110 and the number of second semiconductor chips 120. For example, when the chip stack 101 includes eight semiconductor chips, seven third inter-chip connection wires 145 can be used to electrically connect the first chip common pad 115 of the first semiconductor chip 110 to the second chip common pad 125 of the second semiconductor chip 120.

[0053] The first chip common pad 115 of the first semiconductor chip 110 located at the bottom layer can be electrically connected to the substrate common pad 135 of the package substrate 130 through the third substrate-chip connection wire 155.

[0054] Signals commonly supplied to the first semiconductor chip 110 and the second semiconductor chip 120 can be transmitted via the third inter-chip interconnect 145 and the third substrate-chip interconnect 155. For example, the power supply voltage and ground voltage necessary to drive each of the semiconductor chips can be supplied to each of the semiconductor chips via the third inter-chip interconnect 145 and the third substrate-chip interconnect 155.

[0055] The first inter-chip interconnect 141, the second inter-chip interconnect 143, the third inter-chip interconnect 145, the first substrate-chip interconnect 151, the second substrate-chip interconnect 153, and the third substrate-chip interconnect 155 can be formed via a wire bonding process and can be conductive wires including conductive materials (such as gold (Au) or copper (Cu)).

[0056] The first chip channel pad 111 of the first semiconductor chip 110, connected by the first inter-chip interconnect 141, can be spaced apart in the second direction (Y direction) from the second chip channel pad 121 of the second semiconductor chip 120, connected by the second inter-chip interconnect 143. In this case, the first inter-chip interconnect 141 connecting the first chip channel pads 111 of the first semiconductor chip 110 to each other can be spaced apart in the second direction (Y direction) from the second inter-chip interconnect 143 connecting the second chip channel pads 121 of the second semiconductor chip 120 to each other.

[0057] According to an exemplary embodiment, each of the spacing 176 between adjacent first chip channel pads 111 and the spacing 174 between adjacent second chip channel pads 121 may be different from a second offset distance 172, which is the distance by which the second semiconductor chip 120 is offset relative to the first semiconductor chip 110 in the second direction (Y direction). When the spacing 176 between adjacent first chip channel pads 111 and the spacing 174 between adjacent second chip channel pads 121 are different from the second offset distance 172, the first chip channel pads 111 of the first semiconductor chip 110 and the second chip channel pads 121 of the second semiconductor chip 120 may be staggered in the second direction (Y direction), and therefore, the first inter-chip connection wire 141 and the second inter-chip connection wire 143 may be spaced apart from each other in the second direction (Y direction).

[0058] For example, each of the spacing 176 between adjacent first chip channel pads 111 and the spacing 174 between adjacent second chip channel pads 121 is greater than the second offset distance 172. According to an exemplary embodiment, the second offset distance 172 may be approximately 70% to approximately 90% of the spacing 176 between adjacent first chip channel pads 111, or approximately 70% to approximately 90% of the spacing 174 between adjacent second chip channel pads 121.

[0059] although Figures 1 to 4 Although not shown, the semiconductor package 100 may include a molding layer covering a chip stack 101 disposed on the package substrate 130. For example, the molding layer may be formed to cover the upper surface of the package substrate 130 and the respective lateral surfaces of the semiconductor chips included in the chip stack 101. For example, the molding layer may include an insulating resin or an epoxy molding compound (EMC).

[0060] Semiconductor packages, typically comprising multiple semiconductor chips stacked vertically, use long conductors extending beyond two or more chips to facilitate electrical connections between the chips or between the chips and the package substrate. Compared to relatively short conductors, long conductors have a large loop height and are prone to displacement or sag during manufacturing processes such as molding. This displacement or sag can cause the long conductors to come into contact with other conductors, leading to frequent short circuits.

[0061] However, according to embodiments of the present invention, the semiconductor package 100 can implement electrical connections between semiconductor chips or between semiconductor chips and the package substrate 130 using conductive wires of relatively short length. Therefore, electrical short circuits caused by displacement or sag of the conductive wires can be resolved. Furthermore, since the first semiconductor chip 110 and the second semiconductor chip 120 connected to different channels can be stacked alternately, electrical connections between the first semiconductor chip 110 and the package substrate 130 or between the second semiconductor chip 120 and the package substrate 130 can be implemented without using long wires. Therefore, electrical short circuits between conductive wires constituting different channels can be prevented. Thus, in the semiconductor package 100, electrical connections between multiple semiconductor chips and electrical connections between multiple semiconductor chips and the substrate can have improved reliability.

[0062] Figure 5 This is a plan view of a semiconductor package 100a according to an exemplary embodiment of the present invention. Besides the pad arrangement for each semiconductor chip, Figure 5 The semiconductor package 100a can be compared with the above reference. Figures 1 to 4 The semiconductor package 100 described is substantially the same. For ease of explanation, descriptions identical to those given above will be omitted or briefly given.

[0063] Reference Figure 5Each first semiconductor chip 110 may include two or more first chip common pads 115 and two or more first chip channel pads 111. In each first semiconductor chip 110, a first chip channel pad 111 may be disposed between two adjacent first chip common pads 115 in a second direction (Y direction), and the two adjacent first chip channel pads 111 may be spaced apart from each other in the second direction (Y direction) with a first chip common pad 115 located between them. In this case, the first chip channel pads 111, configured such as data input or output, are spaced apart from each other, while the first chip common pads 115 are located between them. The first chip common pads 115 are provided with a power supply voltage or a ground voltage, thus preventing signal interference between the first chip channel pads 111 due to noise.

[0064] Each second semiconductor chip 120 may include two or more second chip common pads 125 and two or more second chip channel pads 121. In each second semiconductor chip 120, a second chip channel pad 121 may be disposed between two adjacent second chip common pads 125 in the second direction (Y direction), and the two adjacent second chip channel pads 121 may be spaced apart from each other in the second direction (Y direction) with a second chip common pad 125 located between them. In this case, the second chip channel pads 121, configured such as input or output data, are spaced apart from each other while the second chip common pads 125 are located between them. The second chip common pads 125 are provided with a power supply voltage or a ground voltage, thus preventing signal interference between the second chip channel pads 121 due to noise.

[0065] Figure 6 This is a cross-sectional view of a semiconductor package 100b according to an exemplary embodiment of the present invention. Figure 7 It is shown Figure 6 A block diagram of the main components of the semiconductor package 100b. For ease of explanation, descriptions identical to those given above will be omitted or briefly presented.

[0066] Reference Figure 6 and Figure 7 The semiconductor package 100b may include a controller 160 configured to control the operation of the semiconductor chip included in the chip stack 101.

[0067] The controller 160 can be mounted on the package substrate 130. For example, the controller 160 can be mounted on the package substrate 130 in a flip-chip manner. Connection bumps can be located between the pads of the controller 160 and the pads of the package substrate 130 to facilitate electrical connection of the pads of the controller 160 to the pads of the package substrate 130. The controller 160 can be electrically connected to the semiconductor chip of the chip stack 101 via interconnect paths disposed within the package substrate 130. According to some exemplary embodiments, with Figure 6 Conversely, the controller 160 may be located outside the semiconductor package 100b.

[0068] According to an exemplary embodiment, the controller 160 may include two separate channels and can be connected to the semiconductor chips of the chip stack 101 through the two channels. For example, the first channel CH1 of the controller 160 may be connected to the first semiconductor chip 110 located on an odd-numbered layer in the chip stack 101, and the second channel CH2 of the controller 160 may be connected to the second semiconductor chip 120 located on an even-numbered layer in the chip stack 101. The controller 160 may provide a first channel signal and a second channel signal to the first semiconductor chip 110 and the second semiconductor chip 120 respectively through the two separate channels (e.g., the first channel CH1 and the second channel CH2). For example, each of the first channel signal and the second channel signal may include an I / O signal, a DQS signal, a CE signal, a RE signal, a WE signal, a CLE signal, an ALE signal, an R / B signal, etc.

[0069] According to an exemplary embodiment, the controller 160 can be electrically connected to the first semiconductor chip 110 and the second semiconductor chip 120 via separate electrical paths. For example, the first pad 161 of the controller 160 can be electrically connected to the first substrate channel pad 131 of the package substrate 130 via the first interconnect path 137 of the package substrate 130, and the second pad 163 of the controller 160 can be electrically connected to the second substrate channel pad 133 of the package substrate 130 via the second interconnect path 138 of the package substrate 130. In this case, the first channel signal provided to the first pad 161 of the controller 160 can be provided to the first semiconductor chip 110 via the first interconnect path 137 of the package substrate 130, the first substrate-to-chip connection wire 151, and the first inter-chip connection wire 141. The second channel signal provided to the second pad 163 of the controller 160 can be provided to the second semiconductor chip 120 via the second interconnect path 138 of the package substrate 130, the second substrate-to-chip connection wire 153, and the second inter-chip connection wire 143.

[0070] exist Figure 6 and Figure 7In this configuration, controller 160 has two channels. However, controller 160 may have three or more channels. In this case, each of the channels of controller 160 may be configured to connect to two or more connected semiconductor chips.

[0071] Figure 8 This is a cross-sectional view of a semiconductor package 100c according to an exemplary embodiment of the present invention. Besides the pad arrangement for each semiconductor chip, Figure 8 The semiconductor package 100c can be compared with the above reference. Figure 6 and Figure 7 The semiconductor package 100b described is substantially the same. For ease of explanation, descriptions identical to those given above will be omitted or briefly given.

[0072] Reference Figure 8 The controller 160 can be mounted on the package substrate 130 to be at least partially stacked with the chip stack 101 in a vertical direction perpendicular to the upper surface of the package substrate 130. For example, viewed from above, a portion of the controller 160 may be stacked with and covered by some semiconductor chips. As another example, viewed from above, the controller 160 may be completely stacked with and covered by some semiconductor chips. When the controller 160 is stacked with the chip stack 101, the semiconductor package 100c may have a reduced planar dimension.

[0073] Figure 9 This is a cross-sectional view of a semiconductor package 100d according to an exemplary embodiment of the present invention. Figure 10 It is shown Figure 9 A block diagram of the main components of the semiconductor package 100d. For ease of explanation, descriptions identical to those given above will be omitted or briefly presented.

[0074] Reference Figure 9 and Figure 10 The semiconductor package 100d may include a package substrate 130, a first chip stack 101a, a second chip stack 101b, and a controller 160.

[0075] The first chip stack 101a may include a plurality of semiconductor chips stacked vertically on the upper surface of the package substrate 130 using an adhesive member 180. The first chip stack 101a may include a first semiconductor chip 110 located on an odd-numbered layer and a second semiconductor chip 120 located on an even-numbered layer. First chip channel pads 111 of the first semiconductor chips 110 may be electrically connected to each other via first inter-chip interconnects 141, and the first chip channel pad 111 of the bottommost first semiconductor chip 110 may be electrically connected to the first substrate channel pad 131 of the package substrate 130 via a first substrate-chip interconnect 151. Second chip channel pads 121 of the second semiconductor chips 120 may be electrically connected to each other via second inter-chip interconnects 143, and the second chip channel pad 121 of the bottommost second semiconductor chip 120 may be electrically connected to the second substrate channel pad 133 of the package substrate 130 via a second substrate-chip interconnect 153. The first chip common pad 115 of the first semiconductor chip 110 (see...) Figure 1 ) and the second chip common pad 125 of the second semiconductor chip 120 (see Figure 1 It can be connected via a third inter-chip wire 145 (see...) Figure 1 The first chip common pad 115 of the lowest layer of the first semiconductor chip 110 is electrically connected to each other, and can be connected via the third substrate-chip interconnect wire 155 (see...). Figure 1 Electrically connected to the substrate common pad 135 of the package substrate 130 (see...) Figure 1 The first semiconductor chip 110 and the second semiconductor chip 120, the first inter-chip interconnect 141, the second inter-chip interconnect 143, the third inter-chip interconnect 145, the first substrate-chip interconnect 151, the second substrate-chip interconnect 153, and the third substrate-chip interconnect 155 included in the first chip stack 101a can be referenced above. Figures 1 to 4 The descriptions are basically the same.

[0076] The second chip stack 101b may include a plurality of semiconductor chips stacked in a vertical direction on the lower surface of the package substrate 130 using an adhesive member 280.

[0077] The second chip stack 101b may include a third semiconductor chip 210 located on an odd-numbered layer and a fourth semiconductor chip 220 located on an even-numbered layer among a plurality of semiconductor chips. The second chip stack 101b may be related to the above-mentioned reference. Figures 1 to 4 The described chip stack 101 is substantially the same as or similar to the chip stack 101.

[0078] The third semiconductor chip 210 may include a third chip channel pad 211 and a third chip common pad. The third chip channel pads 211 of the third semiconductor chip 210 can be electrically connected to each other via a fourth inter-chip interconnect 241. The third chip channel pad 211 of the lowest layer of the third semiconductor chip 210 can be electrically connected to the third substrate channel pad 231 of the package substrate 130 via a fourth substrate-chip interconnect 251. The third semiconductor chips 210 can be connected to the same channel. The third semiconductor chip 210, the fourth inter-chip interconnect 241, and the fourth substrate-chip interconnect 251 can respectively connect to the aforementioned references. Figures 1 to 4 The first semiconductor chip 110, the first inter-chip interconnect 141, and the first substrate-chip interconnect 151 described are substantially the same or similar.

[0079] The fourth semiconductor chip 220 may include a fourth chip channel pad 221 and a fourth chip common pad. The fourth chip channel pads 221 of the fourth semiconductor chip 220 can be electrically connected to each other via a fifth inter-chip interconnect 243. The fourth chip channel pad 221 of the lowest layer of the fourth semiconductor chip 220 can be electrically connected to the fourth substrate channel pad 233 of the package substrate 130 via a fifth substrate-chip interconnect 253. The fourth semiconductor chip 220 can be connected to the same channel. The fourth semiconductor chip 220, the fifth inter-chip interconnect 243, and the fifth substrate-chip interconnect 253 can respectively connect to the aforementioned references. Figures 1 to 4 The second semiconductor chip 120, the second inter-chip connection wire 143, and the second substrate-chip connection wire 153 described are substantially the same or similar.

[0080] The third chip common pad of the third semiconductor chip 210 and the fourth chip common pad of the fourth semiconductor chip 220 can be electrically connected to each other via a sixth inter-chip interconnect. The third chip common pad of the lowest layer of the third semiconductor chip 210 can be electrically connected to a substrate common pad disposed on the lower surface of the package substrate 130 via a sixth substrate-chip interconnect. The sixth inter-chip interconnect and the sixth substrate-chip interconnect can respectively connect to the aforementioned reference... Figures 1 to 4 The third inter-chip connection wire 145 and the third substrate-chip connection wire 155 are substantially the same or similar. The third semiconductor chip 210 and the fourth semiconductor chip 220 can be configured to receive power supply voltage or ground voltage through the sixth substrate-chip connection wire and the sixth inter-chip connection wire.

[0081] The controller 160 may have four channels that are separate from each other. For example, two channels of the controller 160 may be connected to the first chip stack 101a, and the remaining two channels of the controller 160 may be connected to the second chip stack 101b.

[0082] For example, the first channel CH1 of controller 160 can be connected to the first semiconductor chip 110 included in the first chip stack 101a, the second channel CH2 of controller 160 can be connected to the second semiconductor chip 120 included in the first chip stack 101a, the third channel CH3 of controller 160 can be connected to the third semiconductor chip 210 included in the second chip stack 101b, and the fourth channel CH4 of controller 160 can be connected to the fourth semiconductor chip 220 included in the second chip stack 101b. Controller 160 can provide the first channel signal, the second channel signal, the third channel signal, and the fourth channel signal to the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 210, and the fourth semiconductor chip 220 respectively through four separate channels. For example, each of the first channel signal to the fourth channel signal may include an I / O signal, a DQS signal, a CE signal, a RE signal, a WE signal, a CLE signal, an ALE signal, an R / B signal, etc.

[0083] According to an exemplary embodiment, the controller 160 can be electrically connected to the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 210, and the fourth semiconductor chip 220 via separate circuits. For example, the first pad 161 of the controller 160 can be electrically connected to the first substrate channel pad 131 of the package substrate 130 via a first interconnect path inside the package substrate 130; the second pad 163 of the controller 160 can be electrically connected to the second substrate channel pad 133 of the package substrate 130 via a second interconnect path inside the package substrate 130; the third pad 165 of the controller 160 can be electrically connected to the third substrate channel pad 231 of the package substrate 130 via a third interconnect path inside the package substrate 130; and the fourth pad 167 of the controller 160 can be electrically connected to the fourth substrate channel pad 233 of the package substrate 130 via a fourth interconnect path inside the package substrate 130.

[0084] For example, a first channel signal provided to the controller 160 via the first pad 161 can be provided to the first semiconductor chip 110 via a first interconnect path within the package substrate 130, a first substrate-to-chip interconnect 151, and a first inter-chip interconnect 141. A second channel signal provided to the controller 160 via the second pad 163 can be provided to the second semiconductor chip 120 via a second interconnect path within the package substrate 130, a second substrate-to-chip interconnect 153, and a second inter-chip interconnect 143. A third channel signal provided to the controller 160 via the third pad 165 can be provided to the third semiconductor chip 210 via a third interconnect path within the package substrate 130, a fourth substrate-to-chip interconnect 251, and a fourth inter-chip interconnect 241. A fourth channel signal provided to the controller 160 via the fourth pad 167 can be provided to the fourth semiconductor chip 220 via a fourth interconnect path within the package substrate 130, a fifth substrate-to-chip interconnect 253, and a fifth inter-chip interconnect 243.

[0085] Figure 11 This is a cross-sectional view of a semiconductor package 100e according to an exemplary embodiment of the present invention. For ease of explanation, descriptions identical to those given above will be omitted or briefly provided.

[0086] Reference Figure 11 Semiconductor package 100e can be a stacked semiconductor package in which upper semiconductor package 100U is stacked on lower semiconductor package 100L.

[0087] The lower semiconductor package 100L may include a package substrate 130, a first chip stack 101a including a first semiconductor chip 110 and a second semiconductor chip 120, a controller 160, a first inter-chip interconnect 141, a second inter-chip interconnect 143, a third inter-chip interconnect, a first substrate-chip interconnect 151, a second substrate-chip interconnect 153, and a third substrate-chip interconnect 155 (not shown in the image). Figure 11 (As shown in the image). The lower semiconductor package 100L can be compared with the above reference. Figure 8 The semiconductor package 100c described has a basically similar structure.

[0088] However, the lower semiconductor package 100L may also include a redistribution pattern 191 on the highest layer of semiconductor chips. The redistribution pattern 191 may be electrically connected via electrical connection members to the controller 160, at least one of the semiconductor chips included in the first chip stack 101a, or the package substrate 130.

[0089] The upper semiconductor package 100U may include an upper package substrate 230, a second chip stack 101b including a third semiconductor chip 210 and a fourth semiconductor chip 220, a fourth inter-chip interconnect 241, a fifth inter-chip interconnect 243, a sixth inter-chip interconnect, a fourth substrate-chip interconnect 251, a fifth substrate-chip interconnect 253, and a sixth substrate-chip interconnect. The upper package substrate 230 may be electrically connected to the redistribution pattern 191 of the lower semiconductor package 100L via package interconnect bumps 290.

[0090] The second chip stack 101b and the third semiconductor chip 210 and the fourth semiconductor chip 220 included in the second chip stack 101b can be referenced above. Figure 9 and Figure 10 The semiconductor packages 100d described are substantially the same as or similar to those of the semiconductor package 100d.

[0091] The third chip channel pads 211 of the third semiconductor chip 210 can be electrically connected to each other via the fourth inter-chip interconnect 241. The third chip channel pad 211 of the lowest layer of the third semiconductor chip 210 can be electrically connected to the third substrate channel pad 231 of the upper package substrate 230 via the fourth substrate-chip interconnect 251. The third semiconductor chips 210 can be connected to the same channel.

[0092] According to an exemplary embodiment, the signal provided by the controller 160 can be transmitted to the third semiconductor chip 210 via the redistribution pattern 191, the inter-package connection bump 290, the upper package substrate 230, the fourth substrate-chip connection wire 251 and the fourth chip connection wire 241.

[0093] The fourth chip channel pads 221 of the fourth semiconductor chip 220 can be electrically connected to each other via the fifth inter-chip interconnect 243. The fourth chip channel pad 221 of the lowest layer of the fourth semiconductor chip 220 can be electrically connected to the fourth substrate channel pad 233 of the package substrate 130 via the fifth substrate-chip interconnect 253. The fourth semiconductor chips 220 can be connected to the same channel.

[0094] According to an exemplary embodiment, the signal provided by the controller 160 can be transmitted to the fourth semiconductor chip 220 via the redistribution pattern 191, the inter-package connection bump 290, the upper package substrate 230, the fifth substrate-chip connection wire 253 and the fifth chip connection wire 243.

[0095] The third common pad of the third semiconductor chip 210 and the fourth common pad of the fourth semiconductor chip 220 can be electrically connected to each other via a sixth inter-chip interconnect. The third common pad of the lowest layer of the third semiconductor chip 210 can be electrically connected to the substrate common pad of the upper package substrate 230 via a sixth substrate-chip interconnect. Externally received power supply voltage or ground voltage can be transmitted to the third semiconductor chip 210 and the fourth semiconductor chip 220 through the redistribution pattern 191, the inter-package interconnect bumps 290, the upper package substrate 230, the sixth substrate-chip interconnect, and the sixth inter-chip interconnect.

[0096] References above Figure 9 and Figure 10 Similar to those described, controller 160 may have four channels that are separate from each other and may be configured to transmit different channel signals to first semiconductor chip 110, second semiconductor chip 120, third semiconductor chip 210 and fourth semiconductor chip 220 through the four channels.

[0097] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: The package substrate includes a first substrate channel pad and a second substrate channel pad; A chip stack comprising a plurality of semiconductor chips stacked on a package substrate and offset in a first direction, wherein a plurality of first semiconductor chips located on an odd-numbered layer and a plurality of second semiconductor chips located on an even-numbered layer are offset in a second direction perpendicular to the first direction, each of the plurality of first semiconductor chips including a first chip channel pad and each of the plurality of second semiconductor chips including a second chip channel pad. A first chip-to-chip interconnect wire is configured to electrically connect the first chip channel pads of the plurality of first semiconductor chips to each other. The second inter-chip connection wire is configured to electrically connect the second chip channel pads of the plurality of second semiconductor chips to each other. A first substrate-chip connection wire is configured to connect a first chip channel pad of the lowest layer of the plurality of first semiconductor chips to the first substrate channel pad. A second substrate-chip interconnect wire is configured to connect a second chip channel pad of the lowest-level second semiconductor chip among the plurality of second semiconductor chips to a second substrate channel pad; and The controller comprises a first channel and a second channel that are separate from each other. The controller's first channel is electrically connected to the first chip channel pads of the plurality of first semiconductor chips via the first substrate-chip connection wire and the first inter-chip connection wire. The controller's second channel is electrically connected to the second chip channel pads of the plurality of second semiconductor chips via the second substrate-chip connection wire and the second chip-to-chip connection wire.

2. The semiconductor package according to claim 1, wherein, From the plan view, the first chip channel pads of the plurality of first semiconductor chips are arranged side by side in the first direction, and the second chip channel pads of the plurality of second semiconductor chips are arranged side by side in the first direction.

3. The semiconductor package according to claim 2, wherein, From the plan view, the first chip channel pads of the plurality of first semiconductor chips are spaced apart from the second chip channel pads of the plurality of second semiconductor chips in the second direction.

4. The semiconductor package according to claim 1, in, The first chip channel pads of the plurality of first semiconductor chips include at least one of the following: input / output pads, data strobe signal pads, chip enable pads, read enable pads, write enable pads, command latch enable pads, address latch enable pads, and ready / busy pads. The second chip channel pads of the plurality of second semiconductor chips include at least one of the following: input / output pads, data strobe signal pads, chip enable pads, read enable pads, write enable pads, command latch enable pads, address latch enable pads, and ready / busy pads.

5. The semiconductor package according to claim 1, in, The package substrate includes a common substrate pad. Each of the plurality of first semiconductor chips includes a first common pad. Each of the plurality of second semiconductor chips includes a second common pad, and The semiconductor package further includes: A third inter-chip connection wire is configured to electrically connect a first common pad of the plurality of first semiconductor chips to a second common pad of the plurality of second semiconductor chips; and A third substrate-chip connection wire is configured to electrically connect a first common pad of the lowest layer of the plurality of first semiconductor chips to the common substrate pad.

6. The semiconductor package according to claim 5, in, The first common pad of the plurality of first semiconductor chips includes at least one of Vcc pad and Vss pad, and The second common pad of the plurality of second semiconductor chips includes at least one of the Vcc pad and the Vss pad.

7. The semiconductor package according to claim 6, in, From the plan view, the first common pads of the plurality of first semiconductor chips are arranged side by side in the first direction, and the second common pads of the plurality of second semiconductor chips are arranged side by side in the first direction. In the plan view, the first common pads of the plurality of first semiconductor chips are spaced apart from the second common pads of the plurality of second semiconductor chips in the second direction.

8. The semiconductor package according to claim 5, in, Each of the plurality of first semiconductor chips has a pad arrangement in which two first chip channel pads are spaced apart from each other and a first common pad is located between the two first chip channel pads. Each of the plurality of second semiconductor chips has a pad arrangement in which two second chip channel pads are spaced apart from each other and a second common pad is located between the two second chip channel pads.

9. The semiconductor package according to claim 1, wherein, The distance by which the plurality of semiconductor chips are offset in the first direction is from 230 μm to 400 μm.

10. The semiconductor package according to claim 1, in, Each of the plurality of first semiconductor chips includes a plurality of first chip channel pads arranged along one edge of the first semiconductor chip, wherein each of the plurality of second semiconductor chips includes a plurality of second chip channel pads arranged along one edge of the second semiconductor chip, and wherein the spacing between the plurality of first chip channel pads is equal to the spacing between the plurality of second chip channel pads.

11. The semiconductor package of claim 10, wherein, The spacing between the plurality of first chip channel pads and the spacing between the plurality of second chip channel pads are greater than the distance by which the plurality of first semiconductor chips and the plurality of second semiconductor chips are offset in the second direction.

12. The semiconductor package according to claim 1, wherein, Each of the plurality of semiconductor chips includes NAND flash memory.

13. The semiconductor package according to claim 1, wherein, Each of the first inter-chip connection wires is configured to connect two first semiconductor chips spaced apart from each other, while a second semiconductor chip is located between the two first semiconductor chips.

14. A semiconductor package, comprising: The package substrate includes a common substrate pad, a first substrate channel pad, and a second substrate channel pad; Multiple semiconductor chips are stacked on the package substrate and offset in a first direction, each of the multiple semiconductor chips including a common pad and a channel pad; A first inter-chip connection wire is configured to electrically connect the channel pads of semiconductor chips located in odd-numbered layers among the plurality of semiconductor chips to each other. The second inter-chip connection wire is configured to electrically connect the channel pads of the semiconductor chips located on even-numbered layers among the plurality of semiconductor chips to each other. A third inter-chip connection wire is configured to electrically connect the common pads of the plurality of semiconductor chips to each other; A first substrate-chip connection wire is configured to electrically connect the channel pad of the lowest layer semiconductor chip in the odd-numbered semiconductor chips to the first substrate channel pad. The second substrate-chip connection wire is configured to electrically connect the channel pad of the lowest layer semiconductor chip in the even-numbered semiconductor chip to the second substrate channel pad. A third substrate-chip connection wire is configured to electrically connect the common pad of the lowest semiconductor chip in the odd-numbered semiconductor chips to the common substrate pad. as well as The controller, mounted on the substrate of the package, includes a first channel and a second channel separated from each other. The controller's first channel is electrically connected to the semiconductor chip located in the odd-numbered layer via the first substrate-chip connection wire and the first inter-chip connection wire. The controller's second channel is electrically connected to the semiconductor chip located on the even-numbered layer via the second substrate-chip connection wire and the second chip-to-chip connection wire.

15. The semiconductor package according to claim 14, in, The number of interconnecting wires between the first chips is equal to the number obtained by subtracting 1 from the total number of semiconductor chips located in the odd-numbered layers. The number of inter-chip connecting wires is equal to the number obtained by subtracting 1 from the total number of semiconductor chips located in the even-numbered layers, and The number of interconnecting wires between the third chips is equal to the number obtained by subtracting 1 from the total number of the plurality of semiconductor chips.

16. The semiconductor package of claim 14, wherein, Each of the first inter-chip connection wires extends in the first direction, and each of the second inter-chip connection wires extends in the first direction.

17. The semiconductor package of claim 14, wherein, The channel pads of the semiconductor chip located on the odd-numbered layers are spaced apart from the channel pads of the semiconductor chip located on the even-numbered layers in the first direction and in a second direction perpendicular to the first direction.

18. The semiconductor package according to claim 14, in, The channel pads of the plurality of semiconductor chips correspond to input / output pads, data strobe signal pads, chip enable pads, read enable pads, write enable pads, command latch enable pads, address latch enable pads, or ready / busy pads, and The common pad of the plurality of semiconductor chips corresponds to the Vcc pad or the Vss pad.

19. A semiconductor package, comprising: The package substrate includes a common substrate pad, a first substrate channel pad, and a second substrate channel pad; Multiple semiconductor chips are stacked vertically on the package substrate, each of the multiple semiconductor chips including a common pad and a channel pad; A first inter-chip connection wire is configured to electrically connect the channel pads of semiconductor chips located in odd-numbered layers among the plurality of semiconductor chips to each other. The second inter-chip connection wire is configured to electrically connect the channel pads of the semiconductor chips located on even-numbered layers among the plurality of semiconductor chips to each other. A third inter-chip connection wire is configured to electrically connect the common pads of the plurality of semiconductor chips to each other; A first substrate-chip connection wire is configured to connect the channel pad of the lowest layer semiconductor chip in the odd-numbered semiconductor chip to the first substrate channel pad. The second substrate-chip connection wire is configured to connect the channel pad of the lowest layer semiconductor chip in the even-numbered semiconductor chip to the channel pad of the second substrate. A third substrate-chip connection wire is configured to electrically connect the common pad of the lowest semiconductor chip in the odd-numbered semiconductor chips to the common substrate pad. as well as The controller is mounted on the substrate of the package and is electrically connected to the semiconductor chip located on the odd-numbered layer via the first substrate-chip interconnect and the first inter-chip interconnect via the second substrate-chip interconnect and the second inter-chip interconnect via the second substrate-chip interconnect and the second inter-chip interconnect. The number of interconnecting wires between the first chips is equal to the number obtained by subtracting 1 from the total number of semiconductor chips located in the odd-numbered layers. The number of inter-chip connecting wires is equal to the number obtained by subtracting 1 from the total number of semiconductor chips located in the even-numbered layers, and The number of interconnecting wires between the third chips is equal to the number obtained by subtracting 1 from the total number of the plurality of semiconductor chips.

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