Semiconductor package and its forming method

Abstract

Embodiments of the present invention provide a semiconductor package, comprising: a leadframe; a chip located within the leadframe; a dielectric layer covering the leadframe and the chip; and a redistribution layer located on the active surface of the chip and the dielectric layer, the redistribution layer contacting the active surface of the chip, the redistribution layer having a first stepped structure extending on the dielectric layer and the active surface, and a portion of the redistribution layer on the dielectric layer being lower than the active surface of the chip. The object of the present invention is to provide a semiconductor package and a method for forming the same, to optimize the performance of the semiconductor package.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor package and a forming method thereof. BACKGROUND

[0002] In a lead frame based chip first fan out process, when a direct copper interconnection (DCI) is made on the active surface of a chip, a tape with a chip bonded thereon is laminated with an adhesive tape, the adhesive tape is removed after a dielectric layer is filled, and a redistribution layer (RDL) is directly made on the active surface of the chip. However, a general lamination method cannot tightly laminate the chip and the adhesive tape, and thus resin or epoxy molding compound (EMC) in a subsequent process can easily penetrate into a gap between the adhesive tape and the chip to cover pads of the chip, so that the RDL cannot be directly formed on the pads. If a tape with high adhesion is used to solve the above problem, there are technical problems in removing the tape, such as product deformation and residual tape. SUMMARY

[0003] To solve the problems in the related art, the present application aims to provide a semiconductor package and a forming method thereof to optimize the performance of the semiconductor package.

[0004] To achieve the above object, an embodiment of the present application provides a semiconductor package, comprising: a lead frame; a chip in the lead frame; a dielectric layer covering the lead frame and the chip; and a redistribution layer on the active surface of the chip and the dielectric layer, the redistribution layer contacting the active surface of the chip, the redistribution layer having a first stepped structure extending on the dielectric layer and the active surface, and a portion of the redistribution layer on the dielectric layer being lower than the active surface of the chip.

[0005] In some embodiments, a lower surface of the first stepped structure comprises a first curved surface tapering towards a corner of the chip.

[0006] In some embodiments, an upper surface of the portion of the redistribution layer on the dielectric layer is higher than the active surface of the chip.

[0007] In some embodiments, a thickness of the redistribution layer is greater than a height difference between the active surface and a top surface of the dielectric layer.

[0008] In some embodiments, the thickness of the redistribution layer is greater than 30 μm.

[0009] In some embodiments, the redistribution layer has a second stepped structure extending on the dielectric layer and the lead frame, and the portion of the redistribution layer on the dielectric layer is lower than a top surface of the lead frame.

[0010] In some embodiments, the lower surface of the second step structure comprises a second curved surface tapering towards a corner of the leadframe.

[0011] In some embodiments, the top surface of the leadframe is flush with the active surface.

[0012] In some embodiments, the chip further comprises a pad on the active surface. The redistribution layer covers the pad.

[0013] In some embodiments, no dielectric layer is disposed between the active surface of the chip and the redistribution layer.

[0014] Embodiments of the present application also provide a method of forming a semiconductor package, comprising: disposing a chip in a leadframe; vacuum pressing a top surface of the leadframe and an active surface of the chip with a tape, the active surface being recessed into the tape; forming a dielectric layer covering the leadframe and the chip; removing the tape; and forming a redistribution layer directly on the active surface.

[0015] In some embodiments, no air bubbles exist between the active surface of the chip and the tape when the active surface is recessed into the tape.

[0016] In some embodiments, after the tape is removed, a height difference exists between the active surface and a top surface of the dielectric layer.

[0017] In some embodiments, when the active surface is recessed into the tape, the top surface of the leadframe is also recessed into the tape.

[0018] In some embodiments, when the redistribution layer is formed, a first step structure of the redistribution layer extends over the dielectric layer and the active surface.

[0019] In some embodiments, when the redistribution layer is formed, a second step structure of the redistribution layer extends over the dielectric layer and the leadframe.

[0020] In some embodiments, further comprising: forming a protective layer on the redistribution layer.

[0021] In some embodiments, a backside of the leadframe not covered by the protective layer is etched to form a circuit.

[0022] In some embodiments, further comprising: forming a connection on the circuit.

[0023] In some embodiments, the chip has a pad on the active surface, and when the active surface is recessed into the tape, the pad is also recessed into the tape. BRIEF DESCRIPTION OF DRAWINGS

[0024] Various aspects of the present application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that, as used in the specification and the appended claims, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the entities mentioned. The articles are not intended to signify the existence of

[0025] Figures 1-2 A semiconductor package and a partial enlarged view thereof according to an embodiment of the present application are shown.

[0026] Figures 3-10 A forming process of a semiconductor package according to an embodiment of the present application is shown.

[0027] Figures 11-16 A process of forming a semiconductor package according to another embodiment of the present application is shown.

[0028] Figure 17 is shown according to Figure 16 a partial enlarged view of the embodiment shown.

[0029] Figure 18 An intermediate process diagram of forming a semiconductor package according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] For a better understanding of the spirit of the embodiments of the present application, the following further describes the embodiments of the present application in combination with some preferred embodiments of the present application.

[0031] The embodiments of the present application will be described in detail below. In the entire specification of the present application, the same or similar components and components having the same or similar functions are denoted by the same reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative, diagrammatic and for providing a basic understanding of the present application. The embodiments of the present application should not be interpreted as limiting the present application.

[0032] As used herein, the terms "substantially," "generally," "essentially," and "approximately" are used to describe and account for small variations. When utilized in connection with an event or circumstance, such terms can refer to instances in which the event or circumstance occurs exactly, as well as instances in which the event or circumstance occurs with a minor approximation. For example, when used in connection with a numerical value, the terms can refer to a range of variation that is less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be considered "generally" the same if the difference between the two values is less than or equal to ±10% of the average of the values (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0033] In this specification, unless expressly specified or limited, relative terms such as "central," "longitudinal," "lateral," "forward," "rearward," "rightward," "leftward," "internal," "external," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description only and do not require that the application be practiced with the particular orientation specified.

[0034] In addition, quantities, ratios and other numerical values are sometimes presented in a range format. It is to be understood that such range format is used for convenience and brevity and should be construed as having been followed had each numerical value within the range been individually listed. To the extent that any numerical range is stated herein to include endpoints, the range format is also meant to include the endpoint values themselves.

[0035] Further, for the sake of brevity, the terms "first," "second," "third," etc. can be used herein to refer to different components. The terms "first," "second," "third," etc. are also used herein, not necessarily to describe corresponding components.

[0036] The existing general semiconductor packaging process often causes the adhesion of the chip on the tape to be low in order to control the depth of the chip embedded in the tape, and then the resin or EMC easily penetrates into the gap between the chip and the tape, the subsequent RDL and the chip are not well connected, or the chip is easy to deviate / rotate.

[0037] The semiconductor package and its formation method of this application will now be described in detail with reference to the accompanying drawings.

[0038] See Figure 1 Embodiments of the present invention provide a semiconductor package 100, comprising: a leadframe 10; a chip 12 located within the leadframe 10; a dielectric layer 14 covering the leadframe 10 and the chip 12; and a redistribution layer 16 located on the active surface 121 of the chip 12 and the dielectric layer 14, the redistribution layer 16 contacting the active surface 121 of the chip 12, the redistribution layer 16 having a first stepped structure 161 (the portion in box A) extending on the dielectric layer 14 and the active surface 121, the portion of the redistribution layer 16 on the dielectric layer 14 being lower than the active surface 121 of the chip 12. In some embodiments, the height difference between the top surface of the dielectric layer 14 and the active surface 121 is greater than 5 μm.

[0039] In some embodiments, the upper surface of a portion of the redistribution layer 16 located on the dielectric layer 14 is higher than the active surface 121 of the chip 12.

[0040] In some embodiments, the thickness of the redistribution layer 16 is greater than the height difference between the active surface 121 and the top surface 141 of the dielectric layer 14. In some embodiments, the thickness of the redistribution layer is greater than 30 μm.

[0041] In some embodiments, the redistribution layer 16 has a second stepped structure 162 (the portion in box B) extending on the dielectric layer 14 and the leadframe 10, with a portion of the redistribution layer 16 on the dielectric layer 14 lower than the top surface 101 of the leadframe 10. In some embodiments, the top surface 101 of the leadframe 10 is flush with the active surface 121.

[0042] In some embodiments, chip 12 further includes pads 122 located on the active surface 121. The redistribution layer 16 covers the top and side surfaces of pads 122.

[0043] In some embodiments, a dielectric layer 14 is not provided between the pad 122 of the chip 12 and the redistribution layer 16. In some embodiments, a dielectric layer 14 is not provided between the active surface 121 of the chip 12 and the redistribution layer 16.

[0044] Figure 2 It shows Figure 1 An enlarged view of another embodiment of the middle frame A shows that the lower surface of the first stepped structure 161 includes a first curved surface 163 that tapers toward the corner 122 of the chip 12. Similarly, in some embodiments, the lower surface of the second stepped structure 162 also includes a second curved surface (not shown) that tapers toward the corner of the leadframe 10.

[0045] Figures 3-10 The process of forming a semiconductor package 100 according to an embodiment of this application is shown.

[0046] Referring to Figure 3 , a leadframe 10 is provided.

[0047] Referring to Figure 4 , a chip 12 is disposed in the leadframe 10.

[0048] Referring to Figure 5 , a tape 50 is vacuum-bonded to active side 131 of chip 12 and top side 101 of leadframe 10. In some embodiments, pads 122 of chip 12 are recessed into tape 50. In some embodiments, active side 121 and top side 101 of leadframe 10 (shown as bottom side in Figure 5 ) are also recessed into tape 50.

[0049] Referring to Figure 6 , a dielectric layer 14 is formed that covers leadframe 10 and chip 12. In embodiments where only pads 122 of chip 12 are recessed into tape 50, a bottom side of dielectric layer 14 is flush with active side 121. In embodiments where active side 121 and top side 101 of leadframe 10 are also recessed into tape 50, a bottom side of dielectric layer is higher than active side 121 and top side 101 of leadframe 10 (shown as bottom side in Figure 6 ). In some embodiments, there are no air bubbles between active side 121 and tape 50 when active side 121 of chip 12 is recessed into tape 50.

[0050] Referring to Figure 7 , tape 50 is removed. In some embodiments where active side 121 and top side 101 of leadframe 10 are also recessed into tape 50, there is a height difference between active side 121 and a top side of dielectric layer 14 after the tape is removed.

[0051] Referring to Figure 8 , a redistribution layer 16 is formed directly on active side 121, redistribution layer 16 engaging pads 122 of chip 12.

[0052] Referring to Figure 9 , in some embodiments, further comprising forming a protective layer 90 on redistribution layer 16.

[0053] Referring to Figure 10 , in some embodiments, a back side of leadframe 10 not covered by protective layer 90 is etched to form a trace. In some embodiments, further comprising forming a connector 102 on the trace. In some embodiments, connector 102 is a solder ball.

[0054] Figures 11-16 A process of forming a semiconductor package 100 according to some embodiments of the application is shown.

[0055] Referring to Figure 11Provide a carrier 110 and place the tape 50 on the carrier 110.

[0056] See Figure 12 The chip 12 is placed on the tape 50, and the chip's pad 122 and active surface 121 are both embedded in the tape 50.

[0057] See Figure 13 The chip 12 is packaged using a dielectric layer 14. In some embodiments, the dielectric layer 14 is a resin or molding compound.

[0058] See Figure 14 Remove carrier 110 and tape 50.

[0059] See Figure 15 A second dielectric layer 150 is formed on the chip 12 and the dielectric layer 14, and the second dielectric layer 150 exposes the pads 122 of the chip 12.

[0060] See Figure 16 A first metal layer 160 is formed on a second dielectric layer 150, and the first metal layer 160 and the second dielectric layer 150 constitute a redistribution layer 16. This completes the semiconductor package 100 of this application.

[0061] Figure 17 It shows Figure 16 In the enlarged view of region C, it can be seen that the top surface of dielectric layer 14 is lower than the active surface 121 of chip 12, and the second dielectric layer 150 and the first metal layer 160 have a stepped structure at the junction of dielectric layer 14 and chip 12.

[0062] Figure 18 A schematic diagram of embedding chip 12 into tape 50 according to another embodiment of this application is shown. In some embodiments, chip 12 is embedded into tape 50 using vacuum bonding. In this way, when a dielectric layer is subsequently used for encapsulation, the dielectric layer will not be formed between chip 12 and tape 50.

[0063] In embodiments of the present invention, tape bonding is performed by vacuum pressing, which embeds the chip into the tape, improves the tape adhesion quality, and enhances the bonding between the chip and the tape, thus preventing chip misalignment or rotation during subsequent molding.

[0064] The embodiments of this application increase the thickness of the RDL, making the thickness of the RDL greater than the height difference between the top surface of the dielectric layer and the top surface of the chip, thereby increasing the resistance to structural stress.

[0065] Embodiments of the present application belong to fan-out products of lead frame substrates (chip-first process). A big advantage of the present application is high heat dissipation. Another advantage is to realize low impedance connection (no dielectric layer between the contact pad of the chip and the redistribution layer), which improves the window that can be operated in the process (for example, the selection space of the adhesive tape is more flexible, solves the residual glue problem, improves the yield, etc.), and the semiconductor package of the embodiments of the present application is more in line with the demand of mass production.

[0066] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor package, characterized by, Comprising: a leadframe; a chip located in the leadframe; a dielectric layer covering the leadframe and the chip; a redistribution layer located on an active surface of the chip and on the dielectric layer, the redistribution layer contacting the active surface of the chip, the redistribution layer having a first stepped structure extending over the dielectric layer and the active surface, a portion of the redistribution layer located on the dielectric layer being lower than the active surface of the chip, wherein a thickness of the redistribution layer is greater than a height difference between the active surface and a top surface of the dielectric layer, wherein a lower surface of the first stepped structure comprises a first curved surface tapering towards a corner of the chip, and the first curved surface is spaced apart from a sidewall of the chip proximate to the active surface by the dielectric layer.

2. The semiconductor package of claim 1, wherein, An upper surface of the portion of the redistribution layer located on the dielectric layer is higher than the active surface of the chip.

3. The semiconductor package of claim 1, wherein, The thickness of the redistribution layer is greater than 30 pm.

4. The semiconductor package of claim 1, wherein, The redistribution layer has a second stepped structure extending over the dielectric layer and the leadframe, a portion of the redistribution layer located on the dielectric layer being lower than a top surface of the leadframe.

5. The semiconductor package of claim 4, wherein, A lower surface of the second stepped structure comprises a second curved surface tapering towards a corner of the leadframe.

6. The semiconductor package of claim 1, wherein, The top surface of the leadframe is flush with the active surface.

7. The semiconductor package of claim 1, wherein, The chip further comprises a pad located on the active surface, the redistribution layer covering the pad.

8. The semiconductor package of claim 1, wherein, The dielectric layer is not disposed between the active surface of the chip and the redistribution layer.

9. A method of forming a semiconductor package, comprising: Comprising: disposing a chip in a leadframe; vacuum pressing an active surface of the chip and a top surface of the leadframe with a tape, the active surface being recessed into the tape; forming a dielectric layer covering the leadframe and the chip; removing the tape; forming a redistribution layer directly on the active surface, wherein a thickness of the redistribution layer is greater than a height difference between the active surface and a top surface of the dielectric layer, wherein, in forming the redistribution layer, a first stepped structure of the redistribution layer extending over the dielectric layer and the active surface is formed, a lower surface of the first stepped structure comprising a first curved surface tapering towards a corner of the chip, and the first curved surface is spaced apart from a sidewall of the chip proximate to the active surface by the dielectric layer.

10. The method of forming a semiconductor package of claim 9, wherein, In the active surface of the chip being recessed into the tape, there is no air bubble between the active surface and the tape.

11. The method of claim 9, wherein, after removing the tape, there is a height difference between the active surface and the top surface of the dielectric layer.

12. The method of forming a semiconductor package of claim 9, wherein, In the active surface being recessed into the tape, a top surface of the leadframe is also recessed into the tape.

13. The method of forming a semiconductor package of any of claims 10-12, wherein, In forming the redistribution layer, a second stepped structure of the redistribution layer extending over the dielectric layer and the leadframe is formed.

14. The method of forming a semiconductor package of claim 13, wherein, Further comprising: forming a protective layer located on the redistribution layer; etching a backside of the leadframe not covered by the protective layer to form a circuit.

15. The method of forming a semiconductor package of claim 9, wherein, The chip has a pad located on the active surface, in the active surface being recessed into the tape, the pad is also recessed into the tape.

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