A semiconductor device, a manufacturing method thereof, and an electronic device

Abstract

The application discloses a semiconductor device and a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductor devices, which aims to increase the cross-sectional area of the upper part of a storage contact, reduce the contact resistance between the storage contact and a corresponding landing pad, and improve the performance of the semiconductor device. The semiconductor device comprises a substrate, a bit line structure, a storage contact, and an isolation part. The substrate has an active region. The bit line structure is formed on the active region. The isolation part is used for isolating two adjacent storage contacts. Each active region has an overlapping region overlapping with a corresponding storage contact. The contact area between each storage contact and the overlapping region of the corresponding active region is greater than a preset threshold. The radial cross-sectional area of each part of at least one storage contact is equal. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device. The semiconductor device provided by the application is applied to an electronic device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] A contact structure is a structure that interconnects the active region within a semiconductor device with metal leads located outside the dielectric layer. Electrical signals within the active region or the metal leads can be transmitted through the contact structure, thereby enabling corresponding operations on the semiconductor device. Therefore, the quality of the contact structure directly affects the interconnection quality between the active region and the metal leads within the semiconductor device.

[0003] However, the cross-sectional area of ​​the upper part of the storage contact in existing semiconductor devices is small, resulting in a small contact area between the storage contact and the corresponding landing pad. This leads to a large contact resistance between the storage contact and the corresponding landing pad, which in turn results in poor performance of the semiconductor device. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, and an electronic device, to increase the cross-sectional area of ​​the upper part of the storage contact portion, thereby increasing the contact area between the storage contact portion and the corresponding landing pad, reducing the contact resistance between the storage contact portion and the corresponding landing pad, and thus improving the performance of the semiconductor device.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0006] A substrate with an active region;

[0007] Bit line structure formed on the active region;

[0008] Storage contacts and isolation portions are formed between two adjacent bit line structures. The isolation portion is used to isolate two adjacent storage contacts. Each active region has an overlapping area that overlaps with the corresponding storage contact. The contact area between the overlapping area of ​​each storage contact and the corresponding active region is greater than a preset threshold. The radial cross-sectional area of ​​each part of at least one storage contact is equal.

[0009] Compared to existing technologies, the semiconductor device provided by this invention forms a storage contact and an isolation portion between two adjacent bit line structures. Each active region has an overlapping area that overlaps with the corresponding storage contact, and the contact area between the overlapping area of ​​each storage contact and the corresponding active region is greater than a preset threshold, i.e., the contact area between the bottom of the storage contact and the corresponding active region is larger. Simultaneously, the radial cross-sectional area of ​​each part of at least one storage contact is equal. Compared to existing technologies where the radial cross-sectional area of ​​the storage contact gradually decreases with increasing height, the semiconductor device provided by this invention has at least one storage contact with equal cross-sectional area, increasing the upper radial cross-sectional area of ​​the storage contact, i.e., increasing the contact area between the storage contact and the corresponding landing pad. Since contact resistance is inversely proportional to contact area, increasing the contact area can reduce contact resistance, improve the conductivity of the storage contact, and thus enhance the performance of the semiconductor device.

[0010] The present invention also provides a method for fabricating a semiconductor device, the method comprising:

[0011] Provide a substrate having an active region;

[0012] A bitline structure is formed in the active region;

[0013] A storage contact and an isolation portion are formed between two adjacent bit line structures. The isolation portion is used to isolate two adjacent storage contacts. Each active region has an overlapping area that overlaps with the corresponding storage contact. The contact area between the overlapping area of ​​each storage contact and the corresponding active region is greater than a preset threshold. The radial cross-sectional area of ​​each part of at least one storage contact is equal.

[0014] Compared with the prior art, the semiconductor device manufacturing method provided by the present invention has the same beneficial effects as the semiconductor device provided by the above-mentioned technical solutions, and will not be repeated here.

[0015] The present invention also provides an electronic device comprising the semiconductor device provided by the above-described technical solution.

[0016] Compared with the prior art, the electronic device provided by the present invention has the same beneficial effects as the semiconductor device provided by the above-mentioned technical solutions, and will not be repeated here. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0018] Figure 1This is a schematic diagram of the process of etching the contact material layer to form the storage contact in the prior art;

[0019] Figure 2 This is a schematic diagram of a semiconductor device structure provided in an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of the structure after trenches are formed in the substrate in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the structure after the contact material layer is formed in the trench in an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of the structure after planarization treatment of the contact material layer in an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram of the structure after forming a metal mask on the contact material layer in an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of a process for etching the contact material layer using a metal-assisted chemical etching method in an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of another process for etching the contact material layer using a metal-assisted chemical etching method in an embodiment of the present invention;

[0026] Figure 9 This is a perspective view of the structure after the contact material layer has been etched using a metal-assisted chemical etching method in an embodiment of the present invention.

[0027] Figure 10 This is a perspective view of the structure after removing the metal mask in an embodiment of the present invention;

[0028] Figure 11 This is a perspective view of the structure after the isolation material layer is formed in an embodiment of the present invention;

[0029] Figure 12 This is a perspective view of the structure after the isolation section is formed in an embodiment of the present invention;

[0030] Figure 13 This is a perspective view of the structure after etching a certain height of the storage contact portion in an embodiment of the present invention;

[0031] Figure 14 This is a top view schematic diagram of the electrical connection between the storage contact and the active area in the prior art;

[0032] Figure 15 This is a top view schematic diagram of the formation of the storage contact portion and the corresponding active area in an embodiment of the present invention;

[0033] Figure 16 This is a flowchart illustrating the method for fabricating a semiconductor device according to an embodiment of the present invention.

[0034] Figure label:

[0035] 1 is a trench, 2 is a bit line structure, 3 is a storage contact, 4 is an isolation part, 5 is a contact material layer, 6 is a metal material layer, 7 is a metal mask, 8 is an etching solution, 9 is a groove, 10 is an isolation material layer, 11 is an active region, and 12 is an overlapping region. Detailed Implementation

[0036] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0037] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0038] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0040] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0041] like Figure 1 As shown, after the transistor, the dielectric layer covering the transistor, and the bit line structure located on the active region included in the transistor are fabricated in the semiconductor device, it is usually necessary to form trenches in the dielectric layer between two adjacent bit line structures, and to form memory contacts in the trenches that contact the active region included in the corresponding transistor to facilitate the transmission of electrical signals.

[0042] As semiconductor devices miniaturize, the dimensions of various parts of the device gradually decrease. The aspect ratio of trenches formed within the dielectric layer also gradually increases. This leads to over-etching of the upper part of the sacrificial layer formed within the trench, resulting in a "wider at the top and narrower at the bottom" shape. In this case, the remaining sacrificial layer between adjacent trenches also exhibits a "narrower at the top and wider at the bottom" shape. The area containing this remaining sacrificial layer will subsequently form the memory contact, which will also have a "narrower at the top and wider at the bottom" shape. Furthermore, the reduced radial cross-sectional area at the top of the memory contact results in a smaller contact area between the memory contact and the landing pad, increasing the contact resistance between them and potentially worsening the conductivity of the memory contact, thereby reducing the performance of the semiconductor device.

[0043] To address the problem of poor contact caused by a decrease in the contact area between the storage contact and the landing pad due to an increased trench aspect ratio, embodiments of the present invention provide a semiconductor device, a method for manufacturing the same, and an electronic device. In the semiconductor device provided by the present invention, at least one portion of the storage contact has an equal radial cross-sectional area, increasing the cross-sectional area of ​​the upper part of the storage contact. This increases the contact area between the storage contact and the corresponding landing pad, reducing the contact resistance between the storage contact and the corresponding landing pad, thereby improving the performance of the semiconductor device.

[0044] To address the aforementioned problems, embodiments of the present invention provide a semiconductor device that can be applied to electronic devices such as Dynamic Random Access Memory (DRAM) or Flash Memory (FLASH). Figure 2 and Figure 13As shown, the semiconductor device includes a substrate (not shown), a bit line structure 2, a storage contact portion 3, and an isolation portion 4. The substrate can be a stack of layers in which a partial semiconductor structure has already been formed. For example, in DRAM, the surface of the bit line structure 2 and the surface of the dielectric layer between the bit line structures 2 can be the surface of the substrate 1.

[0045] like Figure 2 and Figure 15 As shown, the substrate has active regions 11. Active electrodes and drain electrodes can be formed within these active regions 11. The number of active regions 11 is not limited here, as long as it can be applied to the semiconductor device provided in this embodiment of the invention. The arrangement of these active regions 11 can be designed according to the actual application scenario, and is not specifically limited here.

[0046] In some cases, the substrate also has a dielectric layer (not shown in the figure). The dielectric layer covers the active region 11. Whether the dielectric layer is single-layered or multi-layered, and the specific types of materials it contains, can be selected according to the actual situation, and will not be elaborated here.

[0047] like Figure 2 and Figure 15 As shown, the bit line structure 2 is formed on the active region 11. It should be understood that the bit line structure 2 may include bit lines and bit line sidewalls surrounding the bit lines. The bit lines are electrically connected to the source (or drain) of the corresponding active region 11. The material contained in the bit lines can be conductive materials such as tungsten (W), aluminum (Al), copper (Co), nickel (Ni), or cobalt (Co). The material contained in the bit line sidewalls is an insulating material, commonly SiCN, SiOCN, or SiN. Of course, in some cases, the bit line contact structure can be considered as part of the bit line structure 2. The material contained in the bit line contact structure can be conductive materials such as doped polycrystalline silicon or boron-doped silicon-germanium.

[0048] like Figure 2 and Figure 15As shown, the aforementioned storage contact portion 3 and isolation portion 4 are formed between two adjacent bit line structures 2. The isolation portion 4 is used to isolate two adjacent storage contact portions 3. Each active region 11 has an overlapping region 12 that overlaps with the corresponding storage contact portion 3, and the contact area between each storage contact portion 3 and the overlapping region 12 of the corresponding active region 11 is greater than a preset threshold. The radial cross-sectional area of ​​each part of at least one storage contact portion 3 is equal. It should be understood that when a storage contact portion 3 is formed between two adjacent bit line structures 2, if one storage contact portion 3 is electrically connected to the drain (or source) of an active region 11, then this storage contact portion 3 corresponds to this active region 11. Furthermore, when there are at least two active regions 11 between two adjacent bit line structures 2, in order to ensure that performing corresponding operations on one active region 11 does not affect the state of other active regions 11 adjacent to that active region 11, an isolation portion 4 needs to be provided between adjacent storage contact portions 3 to isolate the two adjacent storage contact portions 3 located between two adjacent bit line structures 2. In some cases, the bottom surface of the isolation part 4 is on the same plane as the bottom surface of the storage contact part 3, that is, the depth of the isolation part 4 extending into the substrate is equal to the depth of the storage contact part 3 extending into the substrate.

[0049] like Figure 2 and Figure 15 As shown, when the substrate also has a dielectric layer, the storage contact 3 can be formed only within the dielectric layer between adjacent bit line structures 2. In this case, the storage contact 3 extends into the substrate to a shallow depth, and the bottom of the storage contact 3 just contacts the top of the corresponding active region 11. Alternatively, the storage contact 3 can be formed both within the dielectric layer of the substrate and extend into a portion of the active region 11. In this case, the storage contact 3 extends into the substrate to a greater depth, and the bottom of the storage contact 3 contacts multiple surface portions of the active region 11 after processing, increasing the contact area between the storage contact 3 and the corresponding active region 11.

[0050] The material contained in the storage contact portion 3 is a conductive material, commonly used conductive materials can be doped polycrystalline silicon or boron-doped silicon germanium, etc. The material contained in the isolation portion 4 is an insulating material, commonly used insulating materials can be SiBCN, SiCN, SiOCN or SiN.

[0051] It is important to note that, such as Figure 14As shown, in the prior art, the storage contact portion 3 only contacts the end of the corresponding active region 11. In this embodiment of the invention, the contact area between the storage contact portion 3 and the corresponding active region 11 is defined as a preset threshold. It is conceivable that the range of the preset threshold will change with the size of the semiconductor device. The specific range of the preset threshold can be set according to the actual application scenario, as long as it can be applied to the semiconductor device provided in this embodiment of the invention. For example, when the size of the semiconductor device is 80nm, the preset threshold can be 500nm. 2 .

[0052] In practical applications, such as Figure 2 and Figure 15 As shown, when the semiconductor device is applied to DRAM, the dielectric layer may include an insulating layer and a buffer layer sequentially covering the active region 11. The insulating layer and buffer layer may contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Storage contacts 3 are located between adjacent bit line structures 2. Furthermore, the storage contacts 3 are formed within the dielectric layer and extend into a portion of the active region 11. The radial cross-sectional area of ​​each portion of the storage contact 3 is equal, resulting in good conductivity between the storage contact 3 and the corresponding landing pad.

[0053] In the semiconductor device provided by this embodiment of the invention, a storage contact portion 3 and an isolation portion 4 are formed between two adjacent bit line structures 2. Each active region 11 has an overlapping region 12 that overlaps with the corresponding storage contact portion 3, and the contact area between the overlapping region 12 of each storage contact portion 3 and the corresponding active region 11 is greater than a preset threshold, that is, the contact area between the bottom of the storage contact portion 3 and the corresponding active region 12 is larger. Simultaneously, the radial cross-sectional area of ​​each part of at least one storage contact portion 3 is equal. Compared to the prior art where the radial cross-sectional area of ​​the storage contact portion 3 gradually decreases with increasing height, in the semiconductor device provided by this embodiment of the invention, the cross-sectional area of ​​each part of at least one storage contact portion 3 is equal, increasing the upper radial cross-sectional area of ​​the storage contact portion 3, that is, increasing the contact area between the storage contact portion 3 and the corresponding landing pad. Since contact resistance is inversely proportional to contact area, increasing the contact area can reduce contact resistance, improve the conductivity of the storage contact portion 3, and thus improve the performance of the semiconductor device.

[0054] As one possible implementation, such as Figures 3 to 13 As shown, at least one storage contact portion 3 is a storage contact portion 3 formed by metal-assisted chemical etching.

[0055] Specifically, such as Figures 3 to 13As shown, when at least one of the above-mentioned storage contact portions 3 is a storage contact portion 3 formed by metal-assisted chemical etching, the masking and catalytic effects of the metal mask 7 can be used to make the wet etching be performed in a vertically downward manner, thereby generating a storage contact portion 3 that meets the above requirements (the radial cross-sectional area of ​​each part of the storage contact portion 3 is equal).

[0056] Specifically, such as Figures 3 to 13 As shown, a trench 1 is formed in the substrate between two adjacent bit line structures 2. Then, a contact material layer 5 covering the bottom of the trench 1 is formed within the trench 1, and a metal mask 7 is formed on the contact material layer 5. The metal mask 7 serves as a mask for the contact material layer 5 and has catalytic activity; it can chemically react with the oxidizing components contained in the etching solution 8, releasing holes in the form of metal ions at the interface between the metal mask 7 and the contact material layer 5. As the reaction between the metal mask 7 and the etching solution 8 proceeds, more and more holes are released at the interface between the metal mask 7 and the contact material layer 5. When these holes diffuse from the metal mask 7 to the surface of the contact material layer 5, a substance easily dissolved by the reaction (e.g., silicon oxide) forms on the surface of the contact material layer 5 that receives the holes, thus achieving etching of the contact material layer 5. It should be understood that the interface between the metal mask 7 and the contact material layer 5 is the starting point for hole diffusion, where the hole concentration is highest. Furthermore, the etching rate is directly proportional to the number of holes. When etching reaches the bottom of the contact material layer 5, the catalytically active metal mask 7 is located deeper with increasing etching depth. Since the top of the contact material layer 5 does not contact the metal mask 7, the number of holes at the top of the contact material layer 5 is relatively small, preventing over-etching and a decrease in radial cross-sectional area. Therefore, when forming the storage contact portion 3 using metal-assisted chemical etching, it is possible to ensure that the radial cross-sectional area of ​​each part of the storage contact portion 3 is equal.

[0057] As one possible implementation, such as Figure 2 and Figure 15 As shown, the substrate also has an isolation region (not shown in the figure) for isolating two adjacent active regions 11. The isolation region may contain insulating materials such as silicon oxide or silicon nitride.

[0058] When the aforementioned substrate also includes an isolation region, the isolation portion 4 can be formed on both the isolation region and the active region 11. Alternatively, the isolation portion 4 can be formed only on the isolation region.

[0059] Specifically, when the substrate has at least two active regions 11, an isolation region can be provided between adjacent active regions 11 to facilitate the definition of each active region 11. In this case, a dielectric layer covers the surfaces of the at least two active regions 11 and the isolation region. Based on this, a trench 1 is formed in the dielectric layer between adjacent bit line structures 2. The bottom of the trench 1 contacts not only the at least two active regions 11 but also the isolation region between the active regions 11. At this time, at least two memory contacts 3 and an isolation region 4 located between adjacent memory contacts 3 are formed within the same trench 1. If each isolation region 4 is located on the isolation region, it means that each memory contact 3 completely covers the portion of the corresponding active region 11 exposed within the trench 1, increasing the contact area between the memory contact 3 and the corresponding active region 11. Meanwhile, since the radial cross-sectional area of ​​each part of the storage contact portion 3 is equal, the increased contact area between the storage contact portion 3 and the corresponding active region 11 will also increase the cross-sectional area of ​​the upper part of the storage contact portion 3, thereby increasing the contact area between the storage contact portion 3 and the corresponding landing pad, thereby further reducing the contact resistance between the storage contact portion 3 and the corresponding landing pad and improving the conductivity of the storage contact portion 3.

[0060] This invention also provides a method for fabricating a semiconductor device, such as... Figure 16 As shown, the method for fabricating this semiconductor device includes:

[0061] Step S101: Provide a substrate having active regions 11. The structure, number, and arrangement of the active regions 11 can be found in the preceding text and will not be repeated here. In some cases, the substrate also has an isolation region and a dielectric layer. The isolation region is used to isolate two adjacent active regions 11. The dielectric layer covers the isolation region and the active regions 11. The materials contained in the isolation region and the dielectric layer can be found in the preceding text.

[0062] Step S102: As Figure 3 As shown, a bit line structure 2 is formed on the active region 11. Exemplarily, the bit line structure 2 includes a bit line and bit line sidewalls. The bit line is electrically connected to the source (or drain) of the corresponding active region 11. Of course, in some cases, the bit line contact structure can be considered as part of the bit line structure 2. The specific structure of the bit line structure 2 and the materials contained in each part of the bit line structure 2 can be referred to the preceding text and will not be repeated here. Specifically, the bit line structure 2 can be formed in various ways. How the bit line structure 2 is formed is not the main feature of the embodiments of the present invention; therefore, it is only briefly described in this specification so that those skilled in the art can easily implement the embodiments provided by the present invention. Those skilled in the art can certainly imagine other ways to fabricate the bit line structure 2.

[0063] Step S103: As Figures 3 to 12 As shown, a storage contact portion 3 and an isolation portion 4 are formed between two adjacent bit line structures 2. The isolation portion 4 is used to isolate two adjacent storage contact portions 3. Each active region 11 has an overlapping region 12 that overlaps with the corresponding storage contact portion 3. The contact area between each storage contact portion 3 and the overlapping region 12 of the corresponding active region 11 is greater than a preset threshold. The radial cross-sectional area of ​​each part of at least one storage contact portion 3 is equal. As for the materials contained in the storage contact portion 3 and the isolation portion 4, as well as the size of the preset threshold, please refer to the previous text, and will not be repeated here.

[0064] like Figures 3 to 12 As shown, the storage contact portion 3 and the isolation portion 4 formed between two adjacent bit line structures 2 include:

[0065] Step S103.1: A storage contact 3 is formed between two adjacent bit line structures 2 using a controlled etching method. It should be understood that using a controlled etching method here can limit the shape parameters of the storage contact 3 formed between two adjacent bit line structures 2. For example, the controlled etching method limits the height direction of the storage contact 3 to be perpendicular to the substrate surface, or limits the width of the storage contact 3. The controlled etching method includes metal-assisted chemical etching. Specifically, the specific parameters of the metal-assisted chemical etching method can be determined according to the actual situation.

[0066] Specifically, such as Figures 3 to 10 As shown, when a metal-assisted chemical etching method is used to form a storage contact 3 between two adjacent bit line structures 2, the specific process includes:

[0067] Step S103.1.1: As Figure 3 As shown, a groove 1 is formed in the substrate between two adjacent bit line structures 2, and the bottom of the groove 1 contacts the corresponding active region 11.

[0068] For example, when the semiconductor device is applied to DRAM, after forming the bit line structure 2, the bit line sidewalls of the bit line structure 2 can be used as a mask to form a trench 1 by etching from the top of the dielectric layer downwards using a cover etching method. No additional photoresist mask is required to form the trench 1. The bottom of the trench 1 contacts the corresponding active region 11. The width direction of the trench 1 can be the same as the extension direction of the word line. The length direction of the trench 1 is perpendicular to the extension direction of the word line.

[0069] Step S103.1.2: As Figure 4 and Figure 5As shown, a contact material layer 5 covering the bottom of the trench 1 is formed within the trench 1. Exemplarily, the contact material layer 5 can be formed within the trench 1 using direct deposition or epitaxial growth. The top height of the contact material layer 5 should be greater than or equal to the top height of the bit line structure 2. To ensure that subsequent etching from the top of the contact material layer 5 downwards forms grooves 9 of equal depth, the top of the contact material layer 5 needs to be planarized after its formation. The material contained in the contact material layer 5 is a conductive material; common conductive materials include doped polycrystalline silicon or boron-doped silicon-germanium.

[0070] It should be noted that when the contact material layer 5 is formed in the trench 1 using a direct deposition method, and the material contained in the contact material layer 5 is doped polycrystalline silicon, a heat treatment process is required after the formation of the contact material layer 5. The specific temperature, time, and gas environment of the heat treatment process can be designed according to the actual application scenario. For example, the heat treatment process is carried out at a temperature of 650°C for 30 to 60 minutes, and the contact material layer 5 is heat treated in an N2 gas environment.

[0071] Step S103.1.3: As Figures 5 to 10 As shown, the contact material layer 5 is etched using a metal-assisted chemical etching method to obtain the storage contact portion 3.

[0072] Specifically, such as Figure 5 and Figure 6 As shown, a catalytically active metal mask 7 is formed on the surface of the contact material layer 5. The area covered by this metal mask 7 is the region of the contact material layer 5 other than the area where the storage contact portion 3 needs to be formed. For example, one or more catalytically active metal material layers 6, such as gold, silver, platinum, titanium nitride, and copper, can be first formed on the surface of the contact material layer 5. The metal mask 7 is formed using any existing metal removal process.

[0073] like Figures 7 to 10As shown, under the masking and catalytic action of the catalytically active metal mask 7, the contact material layer 5 is etched using a wet etching method to form the storage contact portion 3. Exemplarily, after forming the metal mask 7 on the contact material layer 5, an etching solution 8 composed of a mixed chemical solution of HNO3, H2O2, and HF is introduced into the metal mask 7. It should be understood that the etching rate of the contact material layer 5 to form the storage contact portion 3 is related to the depth of the groove 9 and the concentration of the etching solution 8. Specifically, the higher the concentration of the etching solution 8, the greater the etching rate and the deeper the etching. Therefore, the etching rate of the contact material layer 5 and the depth of the groove 9 formed between the storage contact portions 3 can be controlled by controlling the concentration of the etching solution 8. Furthermore, when etching the contact material layer 5, the angle between the plane containing the substrate surface and the horizontal plane can be adjusted to adjust the etching direction. The angle is 0° to 90°. Specifically, the degree of the angle can be designed according to the actual application scenario and is not specifically limited here.

[0074] It should be noted that after forming the storage contact portion 3 in the trench 1 using metal-assisted chemical etching, the metal mask 7 located in the trench 1 needs to be removed to avoid affecting subsequent operations. Specifically, after forming the storage contact portion 3 in the trench 1 using wet etching, the etching solution 8 in the trench 1 can be removed from the trench 1. Then, the metal mask 7 in the trench 1 can be removed using either wet etching or dry etching. For example, when the metal mask 7 is any one of gold (Au), silver (Ag), platinum (Pt), titanium nitride (TiN), or copper (Cu), aqua regia (also known as aquatic acid, nitrohydrochloric acid), concentrated sulfuric acid, nitric acid, or other strong oxidizing solutions can be used to remove the metal mask 7. It should be understood that the concentration of the strong oxidizing solution can be selected according to the actual situation. After the metal mask 7 is completely removed using aqua regia, the aqua regia containing dissolved metal mask layer material is removed from the trench 1, and the formed structure is cleaned and dried.

[0075] like Figure 11 and Figure 12 As shown, after forming the storage contact portion 3 between two adjacent bit line structures 2, an isolation portion 4 needs to be formed between the two adjacent bit line structures, specifically including:

[0076] Step S103.2: An isolation portion 4 is formed between two adjacent bit line structures, each isolation portion 4 being adjacent to two memory contacts 3. For example, after etching the contact material layer 5 to form at least two memory contacts 3 within the trench 1, a groove 9 is formed between adjacent memory contacts 3. Then, an isolation material layer 10 can be formed on the surface of the dielectric layer and within the groove 9 using processes such as physical vapor deposition. The isolation portion 4 is obtained by planarizing the isolation material layer 10. The material contained in the isolation portion 4 can be referred to the preceding text and will not be repeated here.

[0077] Specifically, when the substrate also includes an isolation region, each isolation portion 4 can be located on the isolation region. It should be understood that in this case, each storage contact portion 3 completely covers the portion of the corresponding active region 11 exposed within the trench 1, increasing the contact area between the storage contact portion 3 and the corresponding active region 11. Simultaneously, since the radial cross-sectional area of ​​each portion of the storage contact portion 3 is equal, the increased contact area between the storage contact portion 3 and the corresponding active region 11 also increases the cross-sectional area of ​​the upper part of the storage contact portion 3, thereby increasing the contact area between the storage contact portion 3 and the corresponding landing pad. This further reduces the contact resistance between the storage contact portion 3 and the corresponding landing pad, improving the conductivity of the storage contact portion 3.

[0078] The present invention also provides an electronic device comprising the semiconductor device provided in the above embodiments.

[0079] Compared with the prior art, the electronic device provided in the embodiments of the present invention has the same beneficial effects as the semiconductor device provided in the embodiments of the present invention, and will not be repeated here.

[0080] As one possible implementation, the aforementioned electronic devices include terminal devices or communication devices.

[0081] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0082] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate having an active region; A bit line structure is formed on the active region; The bit line structure includes a bit line and a bit line sidewall surrounding the sidewall of the bit line; A storage contact portion and an isolation portion are formed between two adjacent bit line structures. The isolation portion is used to isolate two adjacent storage contacts. Each active region has an overlapping area that overlaps with the corresponding storage contact portion. The contact area between each storage contact portion and the overlapping area of ​​the corresponding active region is greater than a preset threshold. The radial cross-sectional area of ​​each part of at least one storage contact portion is equal. The orthographic projection of the storage contact portion on the substrate surface and the orthographic projection of the bit line sidewall on the substrate surface do not overlap. The step of forming a storage contact and an isolation portion between two adjacent bit line structures includes: The memory contact is formed between two adjacent bit line structures using a controlled etching method; An isolation portion is formed between two adjacent bit line structures, and each isolation portion is adjacent to two memory contacts. The method of forming the memory contact between two adjacent bit line structures using a controllable etching method includes: A trench is formed in the substrate between two adjacent bit line structures, and the bottom of the trench contacts the corresponding active region; A contact material layer covering the bottom of the trench is formed within the trench; The contact material layer is etched using a metal-assisted chemical etching method to obtain the storage contact portion.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The contact material layer is formed by epitaxial growth.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The contact material layer formed within the trench covering the bottom of the trench includes: The contact material layer covering the bottom of the trench is formed in the trench using a direct deposition method; The contact material layer is subjected to a heat treatment process.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The mask used for etching the contact material layer using the metal-assisted chemical etching method is a catalytically active metal mask.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The catalytically active metal mask is one or more of gold, silver, platinum, titanium nitride, and copper.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching solution used to etch the contact material layer using the metal-assisted chemical etching method is an oxidizing etching solution, which is a mixed chemical solution of HNO3, H2O2 and HF.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching of the contact material layer using a metal-assisted chemical etching method includes: Adjust the angle between the plane containing the substrate surface and the horizontal plane to adjust the etching direction; wherein the angle is 0°~90°.

8. An electronic device, characterized in that, The invention includes a semiconductor device, which is manufactured using the manufacturing method described in any one of claims 1 to 7.

9. The electronic device according to claim 8, characterized in that, The electronic device includes terminal equipment or communication equipment.

Images