Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are provided. A semiconductor device includes: a stacked structure having conductive layers and insulating layers alternately stacked on each other; an insulating column passing through the stacked structure; a first channel pattern surrounding a sidewall of the insulating column; a second channel pattern surrounding the sidewall of the insulating column; a first insulator formed between the first channel pattern and the second channel pattern; and a memory layer surrounding the first channel pattern, the second channel pattern and the first insulator, the memory layer having a first opening located between the first channel pattern and the second channel pattern.

Description

Technical Field

[0001] Various embodiments of the present invention relate generally to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0002] The nonvolatile memory device retains the stored data regardless of the power on / off condition. The increase in integration density of a two-dimensional nonvolatile memory in which memory cells are formed in a single layer on a substrate has recently been limited. Therefore, a three-dimensional nonvolatile memory device in which memory cells are stacked in a vertical direction on a substrate has been proposed. In addition, various structures and manufacturing methods have been developed to improve the operational reliability of the three-dimensional nonvolatile memory device. Summary of the invention

[0003] According to one embodiment, a semiconductor device may include: a stacked structure having conductive layers and insulating layers alternately stacked on each other; an insulating column passing through the stacked structure; a first channel pattern surrounding a sidewall of the insulating column; a second channel pattern surrounding the sidewall of the insulating column; a first insulator located between the first channel pattern and the second channel pattern; and a memory layer surrounding the first channel pattern, the second channel pattern and the first insulator, the memory layer having a first opening located between the first channel pattern and the second channel pattern.

[0004] According to one embodiment, a semiconductor device may include: a stacked structure having conductive layers and insulating layers alternately stacked on each other; a source contact structure passing through the stacked structure; a channel structure passing through the stacked structure and arranged around the source contact structure; insulating patterns, each of the insulating patterns having a first portion surrounding a side wall of the source contact structure and a second portion protruding from the first portion and extending to the channel structure; and an insulator located between the second portions adjacent to each other in the stacking direction.

[0005] According to one embodiment, a method for manufacturing a semiconductor device may include the following steps: forming a stacked structure having a first material layer and a second material layer alternately stacked with each other; forming channel structures passing through the stacked structure, each channel structure including a channel layer; forming a first opening passing through the stacked structure, the first opening being located between the channel structures; forming a second opening having a contact point with the channel structure by etching the second material layer through the first opening; and patterning the channel structure through the contact point to separate the channel layer into a channel pattern.

[0006] According to one embodiment, a semiconductor device may include: a stacked structure having conductive layers and insulating layers alternately stacked on each other; an insulating column passing through the stacked structure; a first channel pattern surrounding a side wall of the insulating column; a second channel pattern surrounding the side wall of the insulating column; a first insulator located between the first channel pattern and the second channel pattern; and a memory layer surrounding the first channel pattern, the second channel pattern and the first insulator, wherein the memory layer provides an opening exposing the first channel pattern and the second channel pattern or the insulating column at a level corresponding to the insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure;

[0008] FIG. 2A to FIG. 2F is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure;

[0009] FIG. 3A to FIG. 3E is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure;

[0010] Figure 4 is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure;

[0011] Figure 5A and Figure 5B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure;

[0012] Fig. 6A and Figure 6B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure;

[0013] FIG. 7A to FIG. 7D , FIG. 8A to FIG. 8C , Fig.9A and Fig. 9B , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12C , FIG. 13A to FIG. 13D and FIG. 14A to FIG. 14D is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0014] FIG. 15A to FIG. 15C , FIG. 16A to FIG. 16C as well as 17A to 17C is a diagram showing a method of manufacturing a semiconductor device according to an embodiment;

[0015] Fig.18A and Fig.18B , FIG. 19A to FIG. 19C , FIG. 20A to FIG. 20C as well as Fig.21A and Fig. 21B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0016] Fig. 22 is a diagram showing a memory system according to an embodiment of the present disclosure;

[0017] Fig.23 is a diagram showing a memory system according to an embodiment of the present disclosure;

[0018] Fig.24 is a diagram showing a memory system according to an embodiment of the present disclosure;

[0019] Fig.25 is a diagram showing a memory system according to an embodiment of the present disclosure; and

[0020] Fig.26 is a diagram illustrating a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The advantages and features of the present invention and the methods for achieving these advantages and features will be clarified from the embodiments described in detail below with reference to the accompanying drawings. However, they can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the example embodiments to those skilled in the art.

[0022] In the following description of the embodiments, when a parameter is referred to as being "predetermined", it may mean that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the period of execution of the process or algorithm.

[0023] It should be understood that although the terms "first", "second", and "third" etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of the present disclosure.

[0024] In addition, it should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0025] Various embodiments relate to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the same.

[0026] Figure 1A and Figure 1B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1A is a plan view of a conductive level C_LV, and Figure 1B It is a cross-sectional view taken along line A-A'.

[0027] Reference Figure 1A and Figure 1B The semiconductor device may include a stack structure ST, a channel structure CH, and a source contact structure SCT, and may further include a base 10 .

[0028] The stack structure ST may include a conductive layer C_LV including a conductive material and an insulating layer I_LV including an insulating material. According to an embodiment, the stack structure ST may include conductive layers 11 and insulating layers 12 alternately stacked on each other. The conductive layers 11 and insulating layers 12 may be stacked on each other in a third direction III.

[0029] At least one uppermost conductive layer and at least one lowermost conductive layer among the conductive layers 11 may be a selection line, and the remaining conductive layers may be word lines. The conductive layer 11 may include a conductive material such as polysilicon, or a metal such as tungsten (W) or molybdenum (Mo). The insulating layer 12 may include an insulating material such as oxide, nitride, or an air gap.

[0030] The channel structure CH may pass through the stacked structure ST. More specifically, the channel structure CH may pass through the stacked structure ST in the third direction III and may be coupled to the base 10. The base 10 may be a semiconductor substrate, or may include a source region or a source layer. The base 10 may include a lower structure having a peripheral circuit and an interconnection.

[0031] The channel structure CH may include a channel layer 14, and may further include an insulating pillar 15, a memory layer M, or a conductive pad 16. The insulating pillar 15 may pass through the stacked structure ST, and may include an insulating material such as an oxide. The channel layer 14 may surround the sidewalls of the insulating pillar 15. The channel layer 14 may refer to a region in which a channel of a memory cell or a selection transistor is formed, and may include a semiconductor material or a nanostructure. A conductive pad 16 may be provided to electrically connect the channel layer 14 to a conductive line such as a bit line. The conductive pad 16 may include a conductive material such as polysilicon. During the manufacturing process, the conductive pad 16 may be used as a mask pattern.

[0032] The source contact structure SCT may pass through the stacked structure ST and may extend in the third direction III. The source contact structure SCT may include a source contact plug 22 and an insulating spacer 21. The source contact plug 22 may be electrically coupled to the base 10 and the source region or source layer included in the base 10. The source contact plug 22 may have a single-layer structure or a multi-layer structure. The multi-layer structure may include a first conductive layer 22A and a second conductive layer 22B, the second conductive layer 22B having a lower resistance than the first conductive layer 22A. The second conductive layer 22B may include a material having a lower resistance than the first conductive layer 22A. According to an embodiment, the first conductive layer 22A may include polysilicon, and the second conductive layer 22B may include a metal such as tungsten or molybdenum. The insulating spacer 21 may surround the sidewall of the source contact plug 22, and may include an insulating material such as an oxide. The source contact plug 22 and the conductive layer 11 may be electrically isolated from each other by the insulating spacer 21.

[0033] According to the above structure, the source contact structure SCT in the form of a plug may be located between the channel structures CH.

[0034] FIG. 2A to FIG. 2F is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2A is a plan view of the insulation level I_LV. Figure 2B is a plan view of the conductive level C_LV. Figure 2C It is a cross-sectional view taken along line B-B'. Figure 2D 1 is a perspective view showing the structure of the source contact structure SCT and the insulating pattern 17 . Figure 2E 14A, the second channel pattern 14B, and the third channel pattern 14C. Figure 2F 1 is a perspective view showing the structure of the memory layer M.

[0035] Reference FIG. 2A to FIG. 2F The semiconductor device may include a stack structure ST, a channel structure CH, and first, second, and third insulators 18A, 18B, and 18C. In addition, the semiconductor device may further include an insulating pattern 17 , a source contact structure SCT, or a base 10 .

[0036] The stacked structure ST may include conductive layers 11 and insulating layers 12 alternately stacked with each other. At least one uppermost conductive layer and at least one lowermost conductive layer among the conductive layers 11 may be a selection line, and the remaining conductive layers may be word lines. The conductive layer 11 may include a conductive material such as polysilicon, or a metal such as tungsten (W) or molybdenum (Mo). The insulating layer 12 may include an insulating material such as oxide, nitride, or an air gap.

[0037] The channel structure CH may pass through the stack structure ST. The channel structure CH may pass through the stack structure ST in the third direction III and may be coupled to the base 10. The base 10 may be a semiconductor substrate, or may include a source region or a source layer. The base 10 may include a lower structure having a peripheral circuit and an interconnection.

[0038] The channel structure CH may include first to third channel patterns 14A to 14C, and may further include an insulating pillar 15 or a memory layer M. The insulating pillar 15 may pass through the stack structure ST and may include an insulating material such as an oxide. The channel patterns 14A to 14C may refer to regions where channels of memory cells or selection transistors are formed, and may include a semiconductor material or a nanostructure.

[0039] The channel patterns 14A to 14C may surround the sidewalls of the insulating pillars 15 and may extend in the third direction III. The channel patterns 14A to 14C may be separated from each other in the horizontal direction. The horizontal direction may be parallel to the plane defined in the first direction I and the second direction II. The second direction II may intersect the first direction I. The first direction I and the second direction II may intersect the third direction III.

[0040] The channel structure CH may include a first channel pattern 14A and a second channel pattern 14B. A first insulator 18A may be located between the first channel pattern 14A and the second channel pattern 14B to separate the first channel pattern 14A and the second channel pattern 14B from each other. In the third direction III, the distance between the first channel pattern 14A and the second channel pattern 14B may be constant or variable. For example, the distance between the first channel pattern 14 and the second channel pattern 14B in the insulating level I_LV may be greater than, substantially equal to, or less than the distance between the first channel pattern 14A and the second channel pattern 14B in the conductive level C_LV.

[0041] The channel structure CH may further include a third channel pattern 14C. The third channel pattern 14C may share an insulating pillar 15 with the first channel pattern 14A and the second channel pattern 14B, and may be separated from the first channel pattern 14A and the second channel pattern 14B. The second insulator 18B may be located between the second channel pattern 14B and the third channel pattern 14C. The third insulator 18C may be located between the third channel pattern 14C and the first channel pattern 14A.

[0042] The first to third insulators 18A to 18C may be located in the conductive level C_LV. In this plane, the first to third insulators 18A to 18C may be located between the insulating pillars 15 and the memory layer M. The first to third insulators 18A to 18C may include an insulating material or an insulating layer such as an air gap.

[0043] The memory layer M may surround the channel patterns 14A to 14C and the insulators 18A to 18C, and may extend in the third direction III. The memory layer M may also include at least one of a tunnel insulating layer 13C, a data storage layer 13B, and a barrier layer 13A. The data storage layer 13B may include a floating gate, a charge trapping material, polysilicon, a nitride, a nanostructure, a variable resistance material, or a phase change material, etc. The barrier layer 13A may include a high-k dielectric material. The memory layer M may include an opening OP that partially exposes the channel patterns 14A to 14C or the insulating pillars 15. The opening OP may be located between the channel patterns 14A to 14C in the insulating level I_LV.

[0044] Figure 2F 2 shows an opening OP located between memory cells MC. However, the opening OP may extend into adjacent memory cells MC (eg, Figure 2F ). According to one embodiment, the width of the opening OP may extend in the third direction III. According to one embodiment, in a plane defined in the first direction I and the second direction II, the width of the opening OP may be greater than the distance between the channel patterns 14A to 14C.

[0045] Although not shown, the channel structure CH may further include a conductive pad. The conductive pad may be coupled to the channel patterns 14A to 14C and may electrically couple the channel patterns 14A to 14C to conductive lines such as bit lines.

[0046] The source contact structure SCT may pass through the stacked structure ST and may extend in the third direction III. The source contact structure SCT may include a source contact plug 22 and an insulating spacer 21. The source contact plug 22 may be electrically coupled to the base 10 and a source region or source layer included in the base 10. The source contact plug 22 may have a single-layer structure or a multi-layer structure. The multi-layer structure may include a first conductive layer and a second conductive layer, the second conductive layer having a lower resistance than the first conductive layer. According to one embodiment, the first conductive layer may include polysilicon, and the second conductive layer may include a metal such as tungsten or molybdenum. The insulating spacer 21 may surround the sidewalls of the source contact plug 22, and may include an insulating material such as an oxide. The source contact plug 22 and the conductive layer 11 may be electrically isolated from each other by the insulating spacer 21.

[0047] The insulating patterns 17 may surround the sidewalls of the source contact structure SCT and may be stacked on each other in the third direction III. Each of the insulating patterns 17 may include a first portion 17A surrounding the sidewalls of the source contact structure SCT and a second portion 17B protruding from the first portion 17A.

[0048] The first portion 17A may have a loop shape and may be located in the insulating layer level I_LV. In the cross section, the first portion 17A may be interposed between the conductive layers 11. In other words, in a portion of the stacked structure ST, the first portion 17A and the conductive layers 11 may be alternately stacked with each other. The first portion 17A may include a point (hereinafter referred to as a "contact point") contacting the adjacent channel structure CH.

[0049] The second portion 17B may protrude from the contact point and may extend into the channel structure CH. The second portion 17B may penetrate the memory layer M through the opening OP and may extend into the channel patterns 14A to 14C. Therefore, the channel patterns 14A to 14C sharing the insulating pillar 15 may be separated from each other by the second portion 17B in the insulating level I_LV. In addition, the insulators 18A to 18C may be located between the second portions 17B adjacent to each other in the third direction III. Therefore, the channel patterns 14A to 14C sharing the insulating pillar 15 may be separated from each other by the insulators 18A to 18C in the conductive level C_LV.

[0050] In a plan view, a plurality of channel structures CH may be arranged around one source contact structure SCT, and the distances from the source contact structure SCT to the channel structures CH may be substantially the same as each other. According to one embodiment, the channel structures CH may be arranged in the form of a regular polygon or concentric circles, and the source contact structure SCT may be located at the center of the regular polygon or the concentric circle. The channel structures CH located around the source contact structure SCT may be arranged at substantially regular intervals.

[0051] According to the above structure, the memory cell MC or the selection transistor can be located at the intersection between the channel patterns 14A to 14C and the conductive layer 11. The memory cells MC and the selection transistors sharing the channel patterns 14A to 14C can form a single memory string. Therefore, a plurality of memory cells MC can be stacked along the channel structure CH so that the integration of the semiconductor device can be improved.

[0052] FIG. 3A to FIG. 3E is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 3A is a plan view of the insulation level I_LV. Figure 3B is a plan view of the conductive level C_LV. Figure 3C It is a cross-sectional view of B-B'. In addition, Figure 3D and Figure 3E 1 is a perspective view showing the structure of the channel patterns 14A to 14C and the first, second, and third memory patterns MPA, MPB, and MPC. Hereinafter, descriptions of certain elements discussed above are omitted for the sake of brevity.

[0053] Reference FIG. 3A to FIG. 3E The semiconductor device may include a stack structure ST, a channel structure CH, and first to third insulators 18A′ to 18C′. In addition, the semiconductor device may further include an insulating pattern 17 , a source contact structure SCT, or a base 10 .

[0054] The stack structure ST may include conductive layers 11 and insulating layers 12 alternately stacked on each other. The channel structure CH may include channel patterns 14A to 14C, and may further include insulating pillars 15 or memory patterns MPA to MPC.

[0055] The channel patterns 14A to 14C may surround the sidewalls of the insulating pillars 15. The memory patterns MPA to MPC may surround the channel patterns 14A to 14C, respectively. More specifically, the first memory pattern MPA may surround the first channel pattern 14A, the second memory pattern MPB may surround the second channel pattern 14B, and the third memory pattern MPC may surround the third channel pattern 14C. The memory patterns MPA to MPC may be separated from each other in the horizontal direction.

[0056] The width between the memory patterns MPA to MPC may be substantially the same as or different from the width between the channel patterns 14A to 14C. Figure 3D , the width between the memory patterns MPA to MPC may be substantially the same as the width between the channel patterns 14A to 14C. Figure 3E , the width between the memory patterns MPA to MPC may be greater than the width between the channel patterns 14A to 14C. Figure 3E In the embodiment, the channel patterns 14A to 14C may be exposed between the memory patterns MPA to MPC.

[0057] The first to third insulators 18A' to 18C' may be located in the conductive level C_LV. The first to third insulators 18A' to 18C' may be located between the insulating pillars 15 and the conductive layer 11. The first to third insulators 18A' to 18C' may include an insulating material or may include an air gap.

[0058] In the conductive level C_LV, the first insulator 18A' may be located between the first channel pattern 14A and the second channel pattern 14B and between the first memory pattern MPA and the second memory pattern MPB. The second insulator 18B' may be located between the second channel pattern 14B and the third channel pattern 14C and between the second memory pattern MPB and the third memory pattern MPC. In addition, the third insulator 18C' may be located between the third channel pattern 14C and the first channel pattern 14A and between the third memory pattern MPC and the first memory pattern MPA.

[0059] Each of the insulating patterns 17 may include a first portion 17A surrounding a sidewall of the source contact structure SCT and a second portion 17B protruding from the first portion 17A.

[0060] The second portion 17B may extend between the memory patterns MPA to MPC and the channel patterns 14A to 14C. Therefore, the channel patterns 14A to 14C sharing the insulating pillar 15 may be separated from each other by the second portion 17B in the insulating level I_LV. The memory patterns MPA to MPC sharing the insulating pillar 15 may be separated from each other by the second portion 17B in the insulating level I_LV.

[0061] In addition, the insulators 18A' to 18C' may be located between the second portions 17B adjacent to each other in the third direction III. Therefore, the channel patterns 14A to 14C sharing the insulating pillar 15 may be separated from each other by the insulators 18A' to 18C' in the conductive level C_LV. Therefore, the memory patterns MPA to MPC sharing the insulating pillar 15 may be separated from each other by the insulators 18A' to 18C' in the conductive level C_LV.

[0062] According to the above structure, the memory patterns MPA to MPC of the memory cells MC adjacent in the horizontal direction can be separated from each other. Therefore, the data retention characteristic can be improved.

[0063] Figure 4 is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 4 It may be a plan view of the insulation level I_LV. In the following, descriptions of certain elements discussed above are omitted for the sake of brevity.

[0064] Reference Figure 4 , each insulating pattern 17' may include a first portion 17A and a second portion 17B'. The second portion 17B' may pass through the memory layer M and may extend between the channel patterns 14A to 14C. The width between the channel patterns 14A to 14C adjacent to each other in the horizontal direction may be greater than the width of the opening of the memory layer M. Therefore, in a plan view, the second portion 17B' may have a T-shape.

[0065] Figure 5A and Figure 5B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 5B yes Figure 5A Hereinafter, for the sake of brevity, descriptions of certain elements discussed above are omitted.

[0066] Reference Figure 5A and Figure 5BThe semiconductor device may include a stack structure ST, a channel structure CH, an insulator 18 , an isolation pattern 31 , and an interconnection structure ( 33 to 36 ). In addition, the semiconductor device may further include a source contact structure SCT or a base 10 .

[0067] The channel structure CH may include channel patterns 14A to 14C, and may further include an insulating pillar 15 or a memory layer M. The source contact structure SCT may include a source contact plug 22 and an insulating spacer 21 .

[0068] The isolation pattern 31 may pass through a portion of the stacked structure ST. The isolation pattern 31 may be deep enough to pass through at least one uppermost conductive layer. At least one uppermost conductive layer may be a selection line. As a result, the selection line and the word line may be patterned into different shapes. The isolation pattern 31 may overlap with the source contact structure SCT. The isolation pattern 31 may extend in the second direction II and may pass through the source contact structures SCT adjacent to each other in the second direction II.

[0069] The interconnect structures (33 to 36) may be electrically coupled to the channel structures CH or the source contact structures SCT. The interconnect structures (33 to 36) may include contact plugs and conductive lines, etc. The contact plugs and conductive lines may be located in an insulating layer (not shown) and may be provided at multiple levels.

[0070] The first contact plugs 33 may be coupled to the channel patterns 14A to 14C, respectively. The first conductive wires 34 may be coupled to the channel patterns 14A to 14C through the first contact plugs 33. The first conductive wires 34 may extend in the first direction I and may be commonly coupled to the channel patterns 14A to 14C adjacent to each other in the first direction I. According to one embodiment, one channel structure CH may be coupled to three first conductive wires 34. The first conductive wires 34 may be bit lines.

[0071] The second contact plug 35 may be coupled to the source contact structure SCT. The second conductive wire 36 may be coupled to the source contact structure SCT through the second contact plug 35. Some of the first contact plugs 33 may be electrically coupled to the second contact plugs 35, and the second conductive wire 36 may be coupled to the source contact structure SCT through the first contact plug 33 and the second contact plug 35. The second conductive wire 36 may extend in the second direction II and may be commonly coupled to the source contact structures SCT adjacent to each other in the second direction II. The second conductive wire 36 may apply a source voltage and may be disposed above the first conductive wire 34.

[0072] A portion of the stacked structure ST located between the second conductive lines 36 adjacent in the first direction I may form a single memory block MB. The single memory block MB may include at least one isolation pattern 31. Figure 5A and Figure 5B Although not shown in the drawings, a slit insulating structure passing through the stack structure ST may be located at a boundary between the memory blocks MB.

[0073] According to the embodiment as described above, the channel structure CH may include a memory layer M. However, the present invention is not limited thereto. The channel structure CH may include the memory layer M as described above with reference to FIG. FIG. 3A to FIG. 3E The memory pattern M' is described, rather than the memory layer M. In addition, in order to better understand the present disclosure, Figure 5A Only a portion of the first contact plug 33 , the second contact plug 35 , and the first conductive line 34 are shown.

[0074] Fig. 6A and 6B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 6B yes Fig. 6A In the following, for the sake of brevity, descriptions of some of the elements discussed above are omitted.

[0075] Reference Fig. 6A and Figure 6B , the semiconductor device may include a stacked structure ST, a channel structure CH, an insulator 18, an isolation pattern 31, and an interconnection structure (33 to 36). In addition, the semiconductor device may further include a source contact structure (SCT or SCT') or a base 10. The channel structure CH may include channel patterns 14A to 14C, and may further include an insulating pillar 15 or a memory layer M.

[0076] The source contact structure SCT may include a source contact plug 22 and an insulating spacer 21. The source contact structure SCT′ may include a source contact plug 22′ and an insulating spacer 21′. At least one of the source contact plug 22 or the source contact plug 22′ may contact a source layer or a source region and may be electrically coupled to the source layer or the source region included in the base 10.

[0077] The source contact structure SCT' may pass through the stacked structure ST and may extend in the second direction II. The source contact structure SCT' may separate the stacked structures ST adjacent in the first direction I. The source contact structure SCT' may have a width defined in the first direction I and a length defined in the second direction II. The width of the source contact structure SCT' may vary based on its area. According to one embodiment, the source contact structure SCT' may include a first portion P1 having a relatively large width and a second portion P2 having a relatively small width. The source contact structure SCT' may include a first portion P1 and a second portion P2 arranged alternately with each other. The source contact plug 22' may be formed only in the first portion P1, or in both the first portion P1 and the second portion P2.

[0078] The stack structure ST between the source contact structures SCT′ adjacent to each other in the first direction I may be a single memory block MB. The single memory block MB may include at least one isolation pattern 31 .

[0079] According to one embodiment, the channel structure CH may include a memory layer M. However, the present invention is not limited thereto. Figures 3A to 3D As described above, the channel structure CH may include memory patterns MPA to MPC instead of the memory layer M. In addition, in order to better understand the present disclosure, Fig. 6A Only a portion of the first contact plug 33 and the first conductive line 34 are shown.

[0080] FIG. 7A to FIG. 7D and FIG. 8A to FIG. 8C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 7A and Fig. 8A It is a floor plan. Figure 7B , Figure 7C and Fig.7D is along Fig. 7A A cross-sectional view taken along line D-D'. Figure 8B and Figure 8C It is along Fig. 8A Hereinafter, for the sake of brevity, descriptions of some elements discussed above are omitted.

[0081] Reference FIG. 7A to FIG. 7D The stack structure ST may be formed on a base (not shown). First openings OP1 may be formed through the stack structure ST, and channel structures CH may be formed in the first openings OP1, respectively. This manufacturing method is described in more detail below.

[0082] Reference Fig. 7A and Figure 7B , the stacked structure ST may include a first material layer 51 and a second material layer 52. The first material layer 51 may include a material having a high etching selectivity relative to the second material layer 52. For example, the first material layer 51 may include a sacrificial material such as nitride, and the second material layer 52 may include an insulating material such as oxide. For example, the first material layer 51 may include a conductive material such as polysilicon, tungsten, or molybdenum, and the second material layer 52 may include an insulating material such as oxide.

[0083] A mask pattern 53 may be formed on the stack structure ST. The mask pattern 53 may include a material having a high etching selectivity with respect to the first material layer 51 and the second material layer 52. The mask pattern 53 may include a carbon layer or a nitride layer, etc. According to one embodiment, the mask pattern 53 may include silicon carbon nitride (SiCN).

[0084] Subsequently, first openings OP1 may be formed through the stack structure ST. The first openings OP1 may be formed by etching the stack structure ST using the mask pattern 53 as an etching barrier. The respective first openings OP1 may be arranged in the form of a regular polygon or a circle and may be disposed at substantially regular intervals.

[0085] Subsequently, a memory layer 54 may be formed in the first opening OP1. The memory layer 54 may include at least one of a barrier layer 54A, a data storage layer 54B, and a tunnel insulating layer 54C. The memory layer 54 may be formed in the first opening OP1 and may be disposed on the stacked structure ST. Subsequently, a channel layer 55 may be formed in the memory layer 54. The channel layer 55 may be conformally formed along a surface of the memory layer 54.

[0086] Subsequently, insulating pillars 56 may be formed in each of the first openings OP1. The insulating pillars 56 may include an insulating material such as an oxide. First, after forming a gap filling material to fill the first openings OP1, the gap filling material may be partially removed to form the insulating pillars 56. According to one embodiment, the insulating pillars 56 may be formed by etching the gap filling material through a planarization process or an etching process. The planarization process may be a chemical mechanical polishing (CMP) process. The etching process may be a wet etching process or a dry etching process.

[0087] Reference Fig. 7A and Figure 7C , the channel layer 55 and the memory layer 54 exposed by the insulating pillar 56 may be etched. The channel layer 55, the tunnel insulating layer 54C, the data storage layer 54B, and the barrier layer 54A may be sequentially etched. As a result, the top of the first opening OP1 may be reopened.

[0088] The upper surfaces of the channel layer 55 and the memory layer 54 may be exposed through the first opening OP1. The upper surfaces of the insulating pillars 56, the channel layer 55, the tunnel insulating layer 54C, the data storage layer 54B, and the barrier layer 54A may be located at substantially the same level or at different levels. The channel layer 55 may protrude further than the insulating pillars 56 and the memory layer 54. The upper surface of the memory layer 54 may have a stepped shape. The upper surface of the tunnel insulating layer 54C may protrude further than the upper surface of the data storage layer 54B, and the upper surface of the data storage layer 54B may protrude further than the barrier layer 54A. The upper surface of the barrier layer 54A may be higher than the upper surface of the stacked structure ST to avoid exposing the stacked structure ST. According to one embodiment, the upper surface of the barrier layer 54A may be higher than the upper surface of the second material layer 52.

[0089] Reference Fig. 7A and Fig.7D , a conductive pad 57 may be formed in the first opening OP1. After forming a conductive material to fill the first opening OP1, the conductive material may be planarized to form a conductive pad 57. The conductive pad 57 may include a conductive material such as polysilicon. As a result, a channel structure CH having a channel layer 55 may be formed. Each channel structure CH may include an insulating pillar 56, a channel layer 55 surrounding a sidewall of the insulating pillar 56, a memory layer 54 surrounding the channel layer 55, and a conductive pad 57.

[0090] Reference FIG. 8A to FIG. 8C , the second opening OP2 may be formed through the stack structure ST and may be located between the channel structures CH, which will be described in more detail below.

[0091] Reference Fig. 8A and Figure 8B , the mask pattern 53 may be removed. As a result, the upper portion of the channel structure CH may be exposed, and the channel structure CH may protrude further than the upper surface of the stacked structure ST. Subsequently, a spacer material 58 may be formed. The spacer material 58 may be conformally formed on the upper surface of the stacked structure ST and the protruding upper portion of the channel structure CH. The spacer material 58 may include a first portion 58A formed along the sidewall of the channel structure CH and a second portion 58B formed on the upper surface of the stacked structure ST or the upper surface of the channel structure CH. The spacer material 58 may include a material having a high etching selectivity relative to the first material layer 51 and the second material layer 52. The spacer material 58 may include polysilicon.

[0092] Reference Fig. 8A and Figure 8C , the spacer material 58 may be etched. As a result, the second portion 58B may be removed from the spacer material 58, and the first portion 58A may remain on the sidewall of the channel structure CH in the form of a spacer. Hereinafter, the remaining first portion is referred to as a spacer 58A. The spacer material 58 may expose a portion of the upper surface of the stacked structure ST corresponding to the center of each channel structure CH.

[0093] The second opening OP2 can be formed by etching the stacked structure ST using the conductive pad 57 and the spacer 58A as an etching barrier. In a plan view, the second opening OP2 can be located in the center of each channel structure CH. However, the planar shape of the second opening OP2 can vary based on the number and arrangement of adjacent channel structures CH. In a plan view, the second opening OP2 can have a shape such as a circle, a rectangle, a hexagon, or a polygon.

[0094] According to the above-mentioned manufacturing method, the position of the second opening OP2 can be defined by the spacer 58A. Therefore, the second opening OP2 can be formed by self-alignment without using an additional mask pattern. According to one embodiment, the second opening OP2 can be used as a path for patterning the channel structure CH or for replacing the first material layer 51 with a conductive layer. In addition, although not shown, a source contact structure can be formed in the second opening OP2.

[0095] Fig.9A and Fig. 9B , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12C , FIG. 13A to FIG. 13D as well as FIG. 14A to FIG. 14D is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the accompanying drawings, the cross-sectional view shows a cross section of EE'. Hereinafter, for the sake of brevity, descriptions of certain elements discussed above are omitted.

[0096] Reference Fig.9A and Fig. 9B The stacked structure ST may include first material layers 51 and second material layers 52 alternately stacked with each other. The channel structure CH may be formed through the stacked structure ST. The second opening OP2 may be formed between the channel structures CH. According to an embodiment, the second opening OP2 may be as described above with reference to 7A to 8C However, the second opening OP2 may also be formed by an etching process using a mask pattern.

[0097] The third opening OP3 can be formed by etching the second material layer 52 through the second opening OP2. Since the second material layer 52 is selectively etched, the width of the second opening OP2 can extend only at the level corresponding to the second material layer 52, and the third opening OP3 can be formed at the widened portion of the second opening OP2. When etching the second material layer 52, the third opening OP3 can extend in the horizontal direction. Therefore, the third opening OP3 can have a contact point that contacts the channel structure CH adjacent to the second opening OP2. In addition, the channel structure CH can be exposed through the contact point.

[0098] Reference FIG. 10A to FIG. 10C , the channel structure CH may be etched through the third opening OP3. After etching the memory layer 54 through the contact point, the channel layer 55 may be etched. As a result, the fourth opening OP4 may be formed through the memory layer 54 and the channel layer 55. The fourth opening OP4 may be located only at a level corresponding to the second material layer 52. When etching the memory layer 54 and the channel layer 55, the first material layer 51 may be partially etched, and the width of the third opening OP3 in the third direction III may extend.

[0099] Reference FIG. 11A to FIG. 11C , the channel layer 55 may be selectively etched through the fourth opening OP4. As a result, the fourth opening OP4 may extend in the third direction III, and the fifth opening OP5 may be formed in the region from which the channel layer 55 is etched. The fifth opening OP5 may be located only at a level corresponding to the first material layer 51. The fourth openings OP4 adjacent to each other in the third direction III may be coupled to each other through the fifth opening OP5. In addition, the channel layer 55 may be separated into a channel pattern 55A by the fourth opening OP4 and the fifth opening OP5.

[0100] The channel layer 55 may be selectively etched. More specifically, the channel layer 55 exposed through the fourth opening OP4 may be etched in the horizontal direction, and the fourth opening OP4 may extend in the horizontal direction. Therefore, the fourth opening OP4 may have a T-shaped plane at a level corresponding to the second material layer 52 .

[0101] Reference FIG. 12A to FIG. 12C , an insulating pattern 59 may be formed. After depositing the insulating material, the insulating material in the second opening OP2 may be etched to form the insulating pattern 59. The insulating material may be deposited by a method such as atomic layer deposition (ALD). The insulating material may be etched by dry etching or wet etching. When the insulating material is etched by dry etching, the insulating pattern 59 may have a flat sidewall. When the insulating material is etched by wet etching, the insulating pattern 59 may have a concave sidewall.

[0102] The insulating pattern 59 may be formed in the third opening OP3 and the fourth opening OP4. Alternatively, the insulating pattern 59 may be formed in the third opening OP3, and the air gap in the fourth opening OP4 may be sealed by the insulating pattern 59. The insulating pattern 59 may include an insulating material such as oxide or nitride.

[0103] The insulator 60 may be formed in the fifth opening OP5. According to one embodiment, an air gap in the fifth opening OP5 may be sealed by the insulating pattern 59, and the insulator 60 may be an air gap. According to one embodiment, the insulating pattern 59 may extend into the fifth opening OP5, and the insulator 60 may be an insulating layer having oxide or nitride.

[0104] Reference FIG. 13A to FIG. 13D , the first material layer 51 may be replaced by a conductive layer 61 , which will be described in more detail below.

[0105] Reference Fig.13A , Fig. 13B and Fig. 13C, the sixth opening OP6 may be formed by removing the first material layer 51 through the second opening OP2. Fig.13A , Fig. 13B and Fig.13D , a conductive layer 61 may be formed in the sixth opening OP6. After depositing a conductive material to fill the sixth opening OP6, the conductive material in the second opening OP2 may be etched to form the conductive layer 61. More specifically, the conductive material deposited on a portion of the sixth opening OP6 adjacent to the second opening OP2 may be etched. As a result, a portion of the sixth opening OP6 adjacent to the second opening OP2 may be reopened. The conductive layer 61 may include a metal such as tungsten or molybdenum.

[0106] Reference FIG. 14A to FIG. 14D , a source contact structure SCT may be formed in the second opening OP2 , which will be described in more detail below.

[0107] Reference Fig.14A , Fig. 14B and Fig. 14C , an insulating spacer 62 may be formed in the second opening OP2. According to one embodiment, the insulating spacer 62 may be formed by oxidizing the conductive layer 61. The insulating spacer 62 may not be formed on a level corresponding to the second material layer 52. In other words, the insulating spacer 62 may be formed only on a level corresponding to the conductive layer 61. In addition, the spacer 58A may be oxidized, and the insulating spacer 62 may be further formed on the sidewall of the spacer 58A. According to one embodiment, the insulating spacer 62 may be formed by depositing an insulating material in the second opening OP2. The insulating spacer 62 may be conformally formed along the inner surface of the second opening OP2. The insulating spacer 62 may fill the reopened sixth opening OP6 and may include a protrusion on its sidewall. The protrusion may be located on a level corresponding to the conductive layer 61.

[0108] Although not shown, the insulating spacer 62 may be further formed on the bottom surface of the second opening OP2 (eg, the upper surface of the base). For example, the upper surface of the base may be exposed by etching a portion of the insulating spacer 62 formed on the bottom surface of the second opening OP2.

[0109] Reference Fig.14A , Fig. 14B and Fig.14D , a source contact plug 63 may be formed in the second opening OP2. Then a process of exposing the channel pattern 55A may be performed. The channel pattern 55A may be exposed by removing the conductive pad 57. According to one embodiment, the spacer 58A, the conductive pad 57, and the source contact structure SCT may be planarized by a chemical mechanical polishing (CMP) process until the channel pattern 55A is exposed. FIG. 14A to FIG. 14CAs shown, the second material layers 52 may have a uniform thickness. However, to take into account some loss during the planarization process, the uppermost second material layer 52 may be thicker than the other second material layers 52 .

[0110] Although not shown, an isolation pattern partially penetrating the stack structure ST, a slit insulation structure located at a boundary between the memory blocks MB, an interconnection structure coupled to the channel structure CH, and an interconnection structure coupled to the source contact structure SCT may be further formed. In addition, when the base includes a sacrificial layer for forming a source layer, a process of replacing the sacrificial layer with the source layer may be further performed.

[0111] According to the above-described manufacturing method, the third opening OP3 having a contact point with the channel structure CH adjacent thereto can be formed by selectively extending the second opening OP2 at a level corresponding to the second material layer 52. In addition, by selectively etching the channel layer 55 through the third opening OP3, the channel layer 55 can be separated into the channel pattern 55A. Therefore, the channel structure CH having the channel patterns 55A separated from each other can be formed.

[0112] FIG. 15A to FIG. 15C , FIG. 16A to FIG. 16C as well as 17A to 17C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment. In the accompanying drawings, the cross-sectional view shows a cross section of FF'. Hereinafter, for the sake of brevity, descriptions of certain elements discussed above are omitted.

[0113] FIG. 15A to FIG. 15C Can correspond to the above reference FIG. 10A to FIG. 10C The manufacturing method described. FIG. 15A to FIG. 15C , the memory layer 54 and the channel layer 55 may be etched through the third opening OP3. After etching the memory layer 54 through the contact point, the channel layer 55 may be etched. As a result, the fourth opening OP4 may be formed through the memory layer 54 and the channel layer 55.

[0114] Reference FIG. 16A to FIG. 16C , the channel layer 55 and the memory layer 54 may be selectively etched through the fourth opening OP4. The channel layer 55 may be selectively etched after the memory layer 54 is selectively etched. The channel layer 55 may be etched by dry etching or wet etching. According to one embodiment, the channel layer 55 may be selectively etched by using tetramethylammonium hydroxide (TMAH). According to one embodiment, at least one of the tunnel insulating layer 54C, the data storage layer 54B, and the barrier layer 54A may be etched. As a result, the fourth opening OP4' may extend in the third direction III, and the fifth opening OP5' may be formed in the region from which the channel layer 55 and the memory layer 54 are etched.

[0115] The fourth openings OP4' adjacent to each other in the third direction III may be coupled to each other through the fifth opening OP5'. In addition, the channel layer 55 may be separated into the channel pattern 55A through the fourth opening OP4' and the fifth opening OP5'. In addition, the memory layer 54 may be separated into the memory pattern 54' through the fourth opening OP4' and the fifth opening OP5'.

[0116] The channel layer 55 may be selectively etched. More specifically, the channel layer 55 exposed through the fourth opening OP4' may be etched in the horizontal direction. In the same manner, the memory layer 54 may be selectively etched. More specifically, the memory layer 54 exposed through the fourth opening OP4' may be etched in the horizontal direction. Therefore, the fourth opening OP4' may extend in the horizontal direction in a level corresponding to the second material layer 52.

[0117] Reference 17A to 17C , the insulating pattern 59 may be formed in the third opening OP3 and the fourth opening OP4'. The insulator 60' may be formed in the fifth opening OP5'. The insulator 60' may be located between the channel patterns 55A adjacent in the horizontal direction and between the memory patterns 54' adjacent in the horizontal direction. As described above, the insulating pattern 59 may have a flat sidewall or a concave sidewall. In addition, the insulating pattern 59 may extend to the fifth opening OP5'.

[0118] Subsequently, the first material layer 51 may be replaced by the conductive layer 61. Then a source contact structure SCT may be formed in the second opening OP2.

[0119] Although not shown, a planarization process may be additionally performed to expose the channel pattern 55A. In addition, an isolation pattern penetrating a portion of the stack structure ST, an interconnection structure coupled to the channel structure CH, and an interconnection structure coupled to the source contact structure SCT may be further formed. In addition, when the base includes a sacrificial layer for forming a source layer, a process of replacing the sacrificial layer with a source layer may be further performed.

[0120] According to the above-described manufacturing method, the channel layer 55 may be separated into the channel pattern 55A, and the memory layer 54 may be separated into the memory pattern 54'. Therefore, the channel structure CH having the channel pattern 55A and the memory pattern 54' separated from each other may be formed.

[0121] Fig.18A and Fig.18B , FIG. 19A to FIG. 19C , FIG. 20A to FIG. 20C as well as Fig.21A and Fig. 21Bis a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the accompanying drawings, the cross-sectional view shows a cross section of G-G'. Hereinafter, for the sake of brevity, descriptions of certain elements discussed above are omitted.

[0122] Reference Fig.18A and Fig.18B , the stacked structure ST may include first material layers 71 and second material layers 72 alternately stacked with each other. A channel structure CH may be formed through the stacked structure ST. Each channel structure CH may include an insulating pillar 76, a channel layer 75 surrounding the sidewall of the insulating pillar 76, a memory layer 74 surrounding the channel layer 75, and a conductive pad 77. A spacer 78 may be formed around the upper sidewall of the channel structure CH.

[0123] The second opening OP2 and the slit SL may be formed through the stack structure ST and may be located between the channel structures CH. The stack structure ST may be etched using the spacer 78 and the conductive pad 77 as an etching barrier to form the second opening OP2 and the slit SL. According to an embodiment, the slit SL may be located at a boundary between memory blocks, and the second opening OP2 may be formed in a memory block.

[0124] Each slit SL may extend in the second direction II. The slit SL may include a first portion SL_A and a second portion SL_B. The first portion SL_A may have a relatively large width, and the second portion SL_B may have a relatively small width. The slit SL may have a structure in which the first portion SL_A and the second portion SL_B are alternately arranged with each other.

[0125] Reference FIG. 19A to FIG. 19C , the second material layer 72 may be selectively etched through the second opening OP2 and the slit SL. As a result, the second opening OP2 may extend at a level corresponding to the second material layer 72 to form a third opening OP3 having a contact point with the channel structure CH adjacent thereto. In addition, the slit SL may extend at a level corresponding to the second material layer 72 to form a third opening OP3' having a contact point with the channel structure CH adjacent thereto.

[0126] The channel structure CH may be etched through the contact point of the third opening OP3. As a result, the fourth opening OP4 may be formed through the memory layer 74 and the channel layer 75. In addition, the channel structure CH' may be etched through the contact point of the third opening OP3'. As a result, the fourth opening OP4' may be formed through the memory layer 74 and the channel layer 75. The contact point of the third opening OP3' may have substantially the same width as that of the contact point of the third opening OP3 or a greater width than that of the contact point of the third opening OP3. Therefore, the fourth opening OP4' may have substantially the same width as that of the fourth opening OP4 or a greater width than that of the fourth opening OP4.

[0127] Subsequently, by selectively etching the channel layer 75 through the fourth opening OP4, the channel layer 75 may be separated into channel patterns 75A. As a result, a fifth opening OP5 may be formed in the channel structure CH. In addition, by selectively etching the channel layer 75 through the fourth opening OP4', the channel layer 75 may be separated into channel patterns 75A'. As a result, a fifth opening OP5' may be formed in the channel structure CH'. The fifth opening OP5' may have a width substantially the same as that of the fifth opening OP5 or a width greater than that of the fifth opening OP5. The number of channel patterns included in the channel structure CH' may be less than or equal to the number of channel patterns included in the channel structure CH.

[0128] Reference FIG. 20A to FIG. 20C , an insulating pattern 79 may be formed in the third openings OP3 and OP3' and the fourth openings OP4 and OP4', and an insulator 80 may be formed in the fifth openings OP5 and OP5'. The insulating pattern 79 may extend to the fifth openings OP5 and OP5' or seal the air gaps in the fifth openings OP5 and OP5'. Subsequently, the first material layer 71 may be replaced with a conductive layer 81 through the second opening OP2 and the slit SL.

[0129] Subsequently, source contact structures SCT and SCT' may be formed in the second opening OP2 and the slit SL. The source contact structure SCT may include an insulating spacer 82 and a source contact plug 83. The source contact plug 83 may include a first conductive layer and a second conductive layer. The source contact structure SCT' may include an insulating spacer 82' and a source contact plug 83'. The source contact plug 83' may include a first conductive layer and a second conductive layer. According to one embodiment, both the source contact structure SCT and the source contact structure SCT' may be electrically connected to the source layer of the base. According to one embodiment, only portions of the source contact structure SCT and the source contact structure SCT' may be electrically connected to the source layer of the base. A planarization process may then be performed to expose the channel patterns 75A and 75A'.

[0130] Reference Fig.21A and Fig. 21B , an isolation pattern 84 may be formed. After forming a trench to a predetermined depth through the stack structure ST, an isolation pattern 84 may be formed in the trench. According to one embodiment, the second material layer 72, the conductive layer 81, and the source contact structure SCT may be etched to form a trench.

[0131] A conductive line 85 electrically connected to the channel structures CH and CH' may be formed. The conductive line 85 may be formed above the stacked structure ST and may extend in the first direction. Fig.21A Wire 85 is shown in a portion of FIG.

[0132] According to the above manufacturing method, slits may be formed when forming the second opening OP2. Therefore, a channel structure CH having channel patterns 75A separated from each other and a channel structure CH' having channel patterns 75A' separated from each other may be formed. In addition, the stack structure ST may be divided in units of memory blocks.

[0133] Fig. 22 is a diagram showing a memory system 1000 according to an embodiment of the present disclosure.

[0134] Reference Fig. 22 , the memory system 1000 may include a memory device 1200 configured to store data and a controller 1100 performing communication between the memory device 1200 and a host 2000 .

[0135] The host 2000 may be a device or system configured to store data in the memory system 1000 or obtain data from the memory system 1000. The host 2000 may generate requests for various operations and output the generated requests to the memory system 1000. These requests may include a programming request for a programming operation, a read request for a read operation, and an erase request for an erase operation. The host 2000 may communicate with the memory system 1000 by using at least one interface protocol among Peripheral Component Interconnect Express (PCIe), Advanced Technology Connection (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0136] The host 2000 may include at least one of a computer, a portable digital device, a tablet computer, a digital camera, a digital audio player, a television, a wireless communication device, or a cellular phone. However, embodiments of the disclosed technology are not limited thereto.

[0137] The controller 1100 may control the overall operation of the memory system 1000. The controller 1100 may control the memory device 1200 in response to a request of the host 2000. The controller 1100 may control the memory device 1200 to perform a program operation, a read operation, and an erase operation at the request of the host 2000. Alternatively, the controller 1100 may perform a background operation without a request from the host 2000 for improving the performance of the memory system 1000.

[0138] In order to control the operation of the memory device 1200, the controller 1100 may transmit a control signal and a data signal to the memory device 1200. The control signal and the data signal may be transmitted to the memory device 1200 through different input / output lines. The data signal may include a command, an address, or data. The control signal may be used to distinguish a period of an input data signal.

[0139] The memory device 1200 may perform a program operation, a read operation, and an erase operation in response to the control of the controller 1100. The memory device 1200 may be a volatile memory that loses data when power is blocked, or a nonvolatile memory that retains data in the absence of power. According to one embodiment, the memory device 1200 may be the semiconductor device described above, which may be a flash memory device.

[0140] Under a request from the host 2000 for a program operation, a read operation, or an erase operation, the controller 1100 may command the Figures 1A to 6B The structure described or by reference FIG. 7A to FIG. 21B The memory device 1200 manufactured by the method described above performs a programming operation, a reading operation, or an erasing operation. In this way, cell performance characteristics and retention characteristics can be improved.

[0141] Fig.23 is a diagram showing a memory system 30000 according to an embodiment of the present disclosure.

[0142] Reference Fig.23 The memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet computer, a personal computer (PC), a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 that controls the operation of the memory device 2200.

[0143] The controller 2100 may control a data access operation of the memory device 2200 , for example, a program operation, an erase operation, or a read operation of the memory device 2200 , in response to the control of the processor 3100 .

[0144] In response to the control of the controller 2100 , the data programmed into the memory device 2200 may be output through the display 3200 .

[0145] The radio transceiver 3300 can exchange radio signals through the antenna ANT. For example, the radio transceiver 3300 can change the radio signal received through the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300 and transmit the processed signal to the controller 2100 or the display 3200. The controller 2100 can transmit the signal processed by the processor 3100 to the memory device 2200. In addition, the radio transceiver 3300 can change the signal output from the processor 3100 into a radio signal and output the radio signal to an external device through the antenna ANT. A control signal for controlling the operation of the host or the data to be processed by the processor 3100 can be input through the input device 3400, and the input device 3400 may include a pointing device such as a touch pad and a computer mouse, a keypad or a keyboard. The processor 3100 may control the operation of the display 3200 so that data output from the controller 2100 , data output from the radio transceiver 3300 , or data output from the input device 3400 may be output through the display 3200 .

[0146] According to one embodiment, the controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as a part of the processor 3100 , or as a chip separate from the processor 3100 .

[0147] Fig.24 is a diagram showing a memory system 40000 according to an embodiment of the present disclosure.

[0148] Reference Fig.24 , the memory system 40000 can be implemented as a personal computer (PC), a tablet computer, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0149] The memory system 40000 may include a memory device 2200 and a controller 2100 that controls a data processing operation of the memory device 2200 .

[0150] The processor 4100 may output data stored in the memory device 2200 through the display 4300 according to data input through the input device 4200. Examples of the input device 4200 may include a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0151] The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the controller 2100. According to one embodiment, the controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as a part of the processor 4100 or as a chip separate from the processor 4100.

[0152] Fig.25 is a diagram showing a memory system 50000 according to an embodiment of the present disclosure.

[0153] Reference Fig.25 , the memory system 50000 may be implemented into an image processor (eg, a digital camera, a cellular phone with a digital camera attached, a smart phone with a digital camera attached, or a desktop PC with a digital camera attached).

[0154] The memory system 50000 may include a memory device 2200 and a controller 2100 that controls a data processing operation (eg, a program operation, an erase operation, or a read operation) of the memory device 2200 .

[0155] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal. The converted digital signal may be transmitted to the processor 5100 or the controller 2100. In response to the control of the processor 5100, the converted digital signal may be output through the display 5300, or may be stored in the memory device 2200 through the controller 2100. In addition, in response to the control of the processor 5100 or the controller 2100, the data stored in the memory device 2200 may be output through the display 5300.

[0156] According to one embodiment, the controller 2100 capable of controlling the operation of the memory device 2200 may be formed as a part of the processor 5100 , or a chip separate from the processor 5100 .

[0157] Fig.26 is a diagram showing a memory system 70000 according to an embodiment of the present disclosure.

[0158] Reference Fig.26 , the memory system 70000 may include a memory card or a smart card. The memory system 70000 may include a memory device 2200 , a controller 2100 , and a card interface 7100 .

[0159] The controller 2100 may control data exchange between the memory device 2200 and the card interface 7100. According to one embodiment, the card interface 7100 may be, but is not limited to, a secure digital (SD) card interface or a multimedia card (MMC) interface.

[0160] The card interface 7100 may interface the data exchange between the host 60000 and the controller 2100 according to the protocol of the host 60000. According to one embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. The card interface 7100 may refer to hardware capable of supporting the protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0161] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, console video game hardware, or a digital set-top box, the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 in response to the control of the microprocessor 6100.

[0162] According to the embodiments of the present invention, a semiconductor device having a stable structure and improved reliability can be provided.

[0163] CROSS-REFERENCE TO RELATED APPLICATIONS

[0164] This application claims the priority of Korean Patent Application No. 10-2020-0078380 filed on June 26, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device, comprising: A stacked structure having conductive layers and insulating layers alternately stacked on each other; an insulating column, the insulating column passing through the stacked structure; a first channel pattern surrounding a sidewall of the insulating pillar; a second channel pattern surrounding the sidewall of the insulating pillar; a first insulator, the first insulator being located between the first channel pattern and the second channel pattern; as well as A memory layer surrounds the first channel pattern, the second channel pattern, and the first insulator, the memory layer having a first opening located between the first channel pattern and the second channel pattern and located at a level corresponding to each of the insulating layers.

2. The semiconductor device according to claim 1, wherein The first insulator is an air gap.

3. The semiconductor device according to claim 1, further comprising: a third channel pattern, the third channel pattern surrounding the sidewall of the insulating pillar; a second insulator, the second insulator being located between the second channel pattern and the third channel pattern; as well as A third insulator is located between the third channel pattern and the first channel pattern.

4. The semiconductor device according to claim 3, wherein: The memory layer further includes a second opening located between the second channel pattern and the third channel pattern, and a third opening located between the first channel pattern and the third channel pattern. 5 . The semiconductor device according to claim 1 , further comprising a source contact structure passing through the stacked structure.

6. The semiconductor device according to claim 1, further comprising: a first bit line coupled to the first channel pattern; as well as A second bit line is coupled to the second channel pattern.

7. A semiconductor device, comprising: A stacked structure having conductive layers and insulating layers alternately stacked on each other; a source contact structure, wherein the source contact structure passes through the stacked structure; a channel structure passing through the stacked structure and arranged around the source contact structure; insulating patterns, each of the insulating patterns having a first portion surrounding a sidewall of the source contact structure and a second portion protruding from the first portion and extending into the channel structure; as well as An insulator is located between the second portions adjacent to each other in a stacking direction.

8. The semiconductor device according to claim 7, wherein: The first portion includes a contact point with the channel structure, and the second portion protrudes from the contact point.

9. The semiconductor device according to claim 7, wherein: Each of the channel structures includes an insulating pillar, a channel pattern surrounding a sidewall of the insulating pillar, and a memory layer surrounding the channel pattern, and The second portion passes through the memory layer to extend between the channel patterns.

10. The semiconductor device according to claim 9, wherein: The insulator is located between the insulating pillar and the memory layer, and the channel patterns are separated from each other by the insulator.

11. The semiconductor device according to claim 8, wherein Each of the channel structures includes an insulating pillar, a channel pattern surrounding a sidewall of the insulating pillar, and a memory pattern surrounding the channel pattern, and The second portion extends between the memory patterns and between the channel patterns.

12. The semiconductor device according to claim 11, wherein The insulator is located between the insulating column and the conductive layer, and The insulator separates the memory patterns from each other and separates the channel patterns from each other.

13. The semiconductor device according to claim 7, wherein: The source contact structure includes a source contact plug and an insulating spacer, wherein the insulating spacer surrounds a sidewall of the source contact plug.

14. The semiconductor device according to claim 7, wherein: The distances from the source contact structure to the respective channel structures are the same as each other.

15. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stacked structure having first material layers and second material layers alternately stacked on each other; forming channel structures passing through the stacked structure, each of the channel structures comprising a channel layer; forming a first opening through the stacked structure, the first opening being located between the channel structures; forming a second opening having a contact point with the channel structure by etching the second material layer through the first opening; as well as The channel structure is patterned through the contact points to separate the channel layer into channel patterns.

16. The method according to claim 15, wherein: The step of forming the channel structure comprises the following steps: forming a mask pattern on the stacked structure; forming an opening by etching the stack structure using the mask pattern as an etching barrier; and The channel structure is formed in the opening.

17. The method according to claim 16, wherein: The step of forming the first opening comprises the following steps: removing the mask pattern; forming spacers on sidewalls of the channel structure; and The first opening is formed by etching the stack structure using the spacer as an etching barrier.

18. The method according to claim 15, wherein: Each of the channel structures comprises: Insulation column; a channel layer surrounding a sidewall of the insulating column; and A memory layer surrounds the channel layer.

19. The method according to claim 18, wherein: The step of patterning the channel structure comprises the following steps: forming a third opening by etching the memory layer and the channel layer of each of the channel structures; and A fourth opening connecting the third opening is formed by selectively etching the channel layer through the third opening.

20. The method according to claim 19, wherein: The channel patterns are separated from each other by the third opening and the fourth opening.

21. The method according to claim 19, wherein: When the channel layer is selectively etched, the third opening extends in a horizontal direction, and the fourth opening extends in a stacking direction.

22. The method according to claim 19, further comprising the steps of: Insulation patterns are formed in the second opening and the third opening.

23. The method according to claim 22, wherein: An air gap in the fourth opening is sealed by the insulating pattern.

24. The method according to claim 22, wherein: The insulation pattern extends into the fourth opening.

25. The method according to claim 15, further comprising the steps of: An insulating pattern is formed in the second opening.

26. The method according to claim 15, further comprising the steps of: A source contact structure is formed in the first opening.

27. The method according to claim 15, further comprising the steps of: forming an insulating spacer in the first opening; as well as A source contact plug is formed in the first opening.

28. A semiconductor device, comprising: A stacked structure having conductive layers and insulating layers alternately stacked on each other; an insulating column, the insulating column passing through the stacked structure; a first channel pattern surrounding a sidewall of the insulating pillar; a second channel pattern surrounding the sidewall of the insulating pillar; a first insulator, the first insulator being located between the first channel pattern and the second channel pattern; as well as a memory layer surrounding the first channel pattern, the second channel pattern, and the first insulator, The memory layer provides an opening exposing the first and second channel patterns or the insulating pillars at a level corresponding to each of the insulating layers.

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