Manufacturing method of driving backboard, driving backboard and display device

Abstract

The application provides a manufacturing method of a driving backboard, the driving backboard and a display device. The method comprises the following steps: providing a substrate and forming a circuit structure layer on the substrate; forming a seed layer with uniform thickness on the circuit structure layer through a sputtering process; the seed layer comprises a buffer layer and a metal layer which are sequentially arranged; forming a first pattern structure corresponding to a metal trace to be formed on the seed layer through a patterning process; forming the metal trace through an electroplating process and removing the first pattern structure; forming a second pattern structure corresponding to a pad to be formed on the seed layer through a patterning process; removing the part of the seed layer which is not covered by the second pattern structure and the metal trace through an etching process, and removing the second pattern structure, so that the remaining seed layer forms the pad. The scheme of the application can avoid the phenomenon of virtual welding and poor contact when the electrode of the Micro LED chip is bound with the pad, improve the yield of the product, and ensure normal display.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a method for manufacturing a driving backplane, the driving backplane, and a display device. Background Technology

[0002] A micro light-emitting diode (Micro LED) is a light-emitting diode with a size on the micrometer scale. Due to its small size, Micro LEDs can be used as pixels on display panels. Micro-LED display panels have self-emissive display characteristics and offer advantages such as being all-solid-state, having a long lifespan, high brightness, low power consumption, small size, ultra-high resolution, and the ability to operate in extreme environments such as high temperatures or radiation, making them promising for future applications.

[0003] In the fabrication of Micro-LED display panels, Micro LED chips, epitaxially grown on a wafer substrate, are transferred to a driver backplane via a transfer substrate to form an LED array. During this transfer, the electrodes of the Micro LED chips need to be bonded to the pads on the driver backplane. However, when bonding the Micro LED chips to the pads using the driver backplane fabricated with related technologies, poor soldering and contact issues frequently occur, severely reducing product yield and affecting normal display performance. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a method for manufacturing a driving backplane, a driving backplane, and a display device.

[0005] To achieve the above objectives, this application provides a method for manufacturing a drive backplane, comprising:

[0006] A substrate is provided, and a circuit structure layer is formed on the substrate;

[0007] A seed layer of uniform thickness is formed on the circuit structure layer by a sputtering process; the seed layer includes a buffer layer and a metal layer stacked sequentially.

[0008] A first pattern structure corresponding to the metal trace to be formed is formed on the seed layer by a patterning process.

[0009] Metal traces are formed by electroplating and the first pattern structure is removed;

[0010] A second pattern structure corresponding to the pads to be formed is formed on the seed layer by a patterning process;

[0011] The portion of the seed layer not covered by the second pattern structure and the metal trace is removed by an etching process, and the second pattern structure is removed so that the remaining seed layer forms a pad.

[0012] In some embodiments, the formation of a seed layer of uniform thickness on the circuit structure layer by sputtering specifically includes:

[0013] A buffer layer, a metal layer, and a protective layer are sequentially formed on the circuit structure layer by a sputtering process, so that the stacked buffer layer, the metal layer, and the protective layer constitute the seed layer.

[0014] In some embodiments, the buffer layer is made of titanium-molybdenum alloy or titanium-neodymium alloy; the metal layer is made of copper; and the protective layer is made of copper-nickel alloy, copper-aluminum alloy or copper-titanium alloy.

[0015] In some embodiments, the thickness of the buffer layer is 1 / 80 to 1 / 2 of the thickness of the metal layer; the thickness of the protective layer is 1 / 80 to 1 / 2 of the thickness of the metal layer.

[0016] In some embodiments, the thickness of the metal trace is 6 to 100 times the thickness of the metal layer.

[0017] In some embodiments, the first pattern structure includes a retaining wall, on which a plurality of strip-shaped hollow structures are formed by a patterning process; one hollow structure corresponds to a metal trace to be formed.

[0018] In some embodiments, the spacing between any two adjacent perforated structures is the same.

[0019] In some implementations, after forming the pads, the process further includes:

[0020] A flat protective layer is formed to improve the coverage of the metal traces;

[0021] A planarization layer is formed on the planarization protective layer, and holes are made in the planarization layer at positions corresponding to the pads to expose the pads.

[0022] Based on the same inventive concept, this application also provides a driving backplane, including: a substrate, and a circuit structure layer disposed on the substrate; the circuit structure layer is further formed with metal traces and pads disposed on the same layer, the pads group including two pads of uniform thickness; the thickness of the metal traces is greater than the thickness of the pads.

[0023] Based on the same inventive concept, embodiments of this application also provide a display device, which includes a driving backplate as described above.

[0024] As can be seen from the above, the method for manufacturing the driving backplane, the driving backplane, and the display device provided in this application first fabricate a seed layer of uniform thickness for forming pads using a sputtering process. After forming metal traces using a patterned electroplating process, pads are then formed based on the seed layer using an etching process. In the patterned electroplating process of this application, only the pattern structure corresponding to the metal traces is formed, not the pattern structure corresponding to the pads. This simplifies the formed pattern structure and ensures a uniform distribution of the pattern structure, resulting in better uniformity of the thickness of the subsequently formed metal traces. Correspondingly, the pads formed by sputtering based on the pre-formed seed layer of uniform thickness also have uniform thickness, ensuring that the spacing between each electrode of the Micro LED chip and its corresponding pad is basically the same during the subsequent bonding process. This avoids the phenomenon of poor soldering and contact caused by excessive spacing, improves product yield, and ensures normal display. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the manufacturing process of the drive backplane according to an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of the substrate and circuit structure layer obtained in the manufacturing method of this application embodiment;

[0028] Figure 3 This is a schematic diagram of the structure of the seed layer obtained in the manufacturing method of this application embodiment;

[0029] Figure 4 This is a schematic diagram of the first pattern structure obtained in the manufacturing method of this application embodiment;

[0030] Figure 5 This is a schematic diagram of the structure of the metal trace obtained in the manufacturing method of this application embodiment;

[0031] Figure 6 This is a schematic diagram of the second pattern structure obtained in the manufacturing method of this application embodiment;

[0032] Figure 7 This is a schematic diagram of the structure of the pads obtained in the manufacturing method of this application embodiment;

[0033] Figure 8This is a schematic diagram of the structure of the planar protective layer and the planarization layer obtained in the manufacturing method of this application embodiment;

[0034] Figure 9 This is a schematic diagram of the structure of the drive backplane after bonding according to an embodiment of this application;

[0035] Figure 10 This is a top view schematic diagram of the metal traces formed by the manufacturing method of this application embodiment. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0037] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] As described in the background section, during the bonding process of the driving backplane fabricated using related technologies, the electrodes and pads of the Micro LED chip often experience poor soldering and contact issues. In developing this application, the applicant discovered that the reason for these problems in the related technologies is that, in the manufacturing process of the driving backplane, to avoid resistive voltage drop (IR Drop, a phenomenon where voltage drops or rises on the power and ground networks of an integrated circuit) on the metal traces on the driving backplane, the thickness of the metal traces (generally VDD / VSS) is made relatively thick (this thickness refers to the dimension perpendicular to the substrate, and the thickness described in the subsequent embodiments of this application also has the same definition). Thicker metal traces are typically formed using electroplating, and considering the thickness requirements, a semi-additive method is used to pattern the metal material. For patterned electroplating processes, the uniformity of the pattern structure distribution formed by the mask has a significant impact on the thickness of the electroplated structure; that is, to ensure a uniform thickness of the electroplated structure, the uniform distribution of the pattern structure must be guaranteed. However, forming the aforementioned metal traces requires a patterned electroplating process. This patterning process involves creating the pattern structure corresponding to the pads, resulting in a dense distribution of the pattern structure, making uniform distribution difficult. Uneven pattern distribution leads to varying consumption of electroplating material at different structural locations during the electroplating process, resulting in different deposition rates and consequently, variations in the thickness of the formed structure. Therefore, pads formed using the aforementioned techniques often exhibit inconsistent thickness. Due to these varying pad thicknesses, during subsequent bonding of Micro LED chips, thinner pads will have a larger gap between themselves and the Micro LED chip electrodes, making them highly susceptible to cold solder joints, thus exacerbating the problems inherent in the aforementioned technologies.

[0039] To address the problems existing in the aforementioned related technologies, this application provides a method for manufacturing a driving backplane, a driving backplane, and a display device. The method involves first fabricating a seed layer of uniform thickness for forming pads using a sputtering process. After forming metal traces using a patterned electroplating process, pads are then formed based on the seed layer using an etching process. In this application's solution, during the patterned electroplating process, only the pattern structure corresponding to the metal traces is formed, not the pattern structure corresponding to the pads. This simplifies the formed pattern structure, ensures a uniform distribution of the pattern structure, and results in better uniformity of the thickness of the subsequently formed metal traces. Correspondingly, the pads formed by sputtering based on the pre-formed uniformly thick seed layer also have uniform thickness, ensuring that the spacing between each electrode of the Micro LED chip and its corresponding pad is essentially the same during the subsequent bonding process. This avoids the phenomenon of poor soldering and contact caused by excessive spacing, improves product yield, and ensures normal display.

[0040] The following detailed description of the present application's solution is provided through specific embodiments.

[0041] First, this application provides a method for manufacturing a driving backplane. This driving backplane is applied to a Micro-LED display panel. Specifically, during the transfer of Micro-LED chips, the driving backplane serves as a target substrate to receive the Micro-LED chips transferred from the transfer substrate. After the Micro-LED chips are bonded together, a Micro-LED chip array is formed, which can then be used as a display backplane to achieve display functionality.

[0042] refer to Figure 1 The method for manufacturing the drive backplane according to embodiments of this application includes the following steps:

[0043] Step S01: Provide a substrate and form a circuit structure layer on the substrate.

[0044] In this step, a substrate is first provided. The substrate can be a flexible material, such as polyimide; it can also be a rigid material, such as glass, silicon, or a PCB (Printed Circuit Board), etc., and this application embodiment does not limit the choice. In this embodiment and other embodiments of this application, the material of the substrate is illustrated using glass as an example.

[0045] A circuit structure layer is formed on a substrate, the circuit structure layer including a driving circuit for driving a Micro-LED chip.

[0046] As an example, see reference Figure 2 The specific formation process of the substrate and circuit structure layer may include the following steps:

[0047] A glass substrate 10 is provided. A light-shielding layer is formed on the substrate 10, which reflects light incident on its surface to cooperate with other structures driving the backplane to achieve display functions. The light-shielding layer can be made of metals or alloys such as aluminum (Al) and molybdenum (Mo). In addition, a bottom gate 101 is formed on the substrate 10.

[0048] A buffer layer 201 is formed on the substrate 100 by a deposition process. The material of the buffer layer 201 can be one or any combination of silicon nitride (SiNx), silicon oxide (SiO2), and silicon oxynitride (SiON); for example, it can be a stacked structure of SiO2 and SiNx.

[0049] An active layer 2011 is fabricated on the buffer layer 201, and the material can be low-temperature polycrystalline silicon (P-Si).

[0050] A first gate insulating layer 202 is formed on the active layer 2011 by a deposition process, and a first gate 2021 is fabricated and electrically connected to the bottom gate 101. The material of the first gate insulating layer 202 can be one or any combination of SiNx, SiO2, and SiON. The material of the first gate 2021 can be a metal or alloy such as Al or Mo.

[0051] A second gate insulating layer 203 is formed on the first gate 2021 by a deposition process, and a second gate 2031 is fabricated. The material of the second gate insulating layer 203 can be one or any combination of SiNx, SiO2, and SiON. The material of the second gate 2031 can be a metal or alloy such as Al or Mo.

[0052] An interlayer insulating layer 204 is formed on the second gate 2031 by a deposition process. The material of the interlayer insulating layer 204 can be one or any combination of SiNx, SiO2, and SiON; for example, it can be a stacked structure of SiO2 and SiNx. Further, a via penetrating to the first gate insulating layer 202 is formed on the interlayer insulating layer 204 by a patterning process.

[0053] Source / drain electrodes 2041 are formed in the interlayer insulating layer 204 by a deposition process. The source / drain electrodes 2041 can be made of materials such as Al, Mo, and Ti. The source / drain electrodes 2041 are electrically connected to the active layer 2011 through vias in the interlayer insulating layer 204.

[0054] A planarization layer 205 is formed on the source and drain electrodes 2041. The planarization layer 205 can be made of resin material. Subsequently, vias corresponding to the metal traces and pads to be formed later are formed on the planarization layer 205 through a patterning process.

[0055] A planar protective layer 206 is formed on the planarization layer 205 by a deposition process, and vias and vent holes with shapes corresponding to the planarization layer 205 are formed thereon. The material of the planar protective layer 206 can be one or any combination of SiNx, SiO2, and SiON.

[0056] At this point, the substrate 10 and the circuit structure layer 20 thereon are complete. A schematic diagram of the overall structure can be found here. Figure 2 As shown. It should be noted that the thickness of each layer of the above-mentioned substrate and circuit structure layer can be set according to specific implementation needs, and is not specifically limited in the embodiments of this application.

[0057] Step S02: A seed layer of uniform thickness is formed on the circuit structure layer by sputtering process.

[0058] In this step, refer to Figure 3A seed layer 30 is formed on the circuit structure layer 20 by a sputtering process. The seed layer 30 formed by the sputtering process can achieve good thickness uniformity.

[0059] In a specific implementation, the seed layer 30 has a stacked structure; specifically, the seed layer 30 includes a buffer layer, a metal layer, and a protective layer stacked together. The buffer layer provides the flat surface required to form the metal layer; the metal layer is the main structure used to form the pads; and the protective layer covers the surface of the metal layer to protect it from oxidation and corrosion.

[0060] Regarding dimensional specifications, using the thickness of the metal layer as a reference, the thickness of the buffer layer can be set to 1 / 80 to 1 / 2 of the thickness of the metal layer. The thickness of the protective layer can also be set to 1 / 80 to 1 / 2 of the thickness of the metal layer. For example, the thickness of the metal layer can be set to 200 nanometers to 800 nanometers; the thickness of the buffer layer can be set to 10 nanometers to 100 nanometers; and the thickness of the protective layer can be set to 10 nanometers to 100 nanometers.

[0061] In terms of material selection, the buffer layer can be made of titanium-molybdenum alloy (MoNd) or titanium-neodymium alloy (MoTi); the metal layer can be made of copper; and the protective layer can be made of copper-nickel alloy (CuNi), copper-aluminum alloy (CuAl), or copper-titanium alloy (CuTi).

[0062] Step S03: A first pattern structure corresponding to the metal trace to be formed is formed on the seed layer by a patterning process.

[0063] In this step, refer to Figure 4 On the seed layer 30, a first pattern structure 40 corresponding to the metal trace to be formed is formed by a patterning process.

[0064] In practice, the first pattern structure 40 formed by the patterning process in this step is only used to form metal traces. Specifically, the first pattern structure 40 includes a barrier wall, on which several strip-shaped hollow structures 401 are formed by the patterning process. Each hollow structure 401 corresponds to a metal trace to be formed.

[0065] Furthermore, to ensure consistent thickness of the metal traces formed by subsequent electroplating, the spacing between any two adjacent hollow structures 401 corresponding to the metal traces is made uniform during this step, resulting in a uniform distribution of the hollow structures. Because the hollow structures 401 are uniformly distributed, the consumption of electroplating material at various locations of the first pattern structure 40 is essentially the same during the subsequent electroplating process, leading to a similar electroplating deposition rate and thus forming metal traces with essentially consistent height.

[0066] Step S04: Form metal traces through electroplating and remove the first pattern structure.

[0067] In this step, refer to Figure 4 and Figure 5 Based on the first pattern structure 40, metal traces 50 are formed through an electroplating process. As described in the preceding steps, since the hollow structure 401 corresponding to the metal traces 50 is evenly distributed, the electroplating deposition rate at the corresponding positions is basically the same during the electroplating process, and the height of each metal trace 50 formed in the end is basically the same.

[0068] Regarding dimensions, the thickness of the metal trace can be set to 6 to 100 times the thickness of the metal layer, using the metal layer thickness as a reference. For example, the thickness of the metal trace can be set to 5 micrometers to 20 micrometers. As for the material, copper can be chosen as the material for the metal trace.

[0069] In practice, after the metal traces 50 are formed, the first pattern structure 40 is removed, thus completing the fabrication of the metal traces 50 on the drive backplate.

[0070] Step S05: A second pattern structure corresponding to the pads to be formed is formed on the seed layer by a patterning process.

[0071] In this step, refer to Figure 6 A patterning process is performed to form a second pattern structure 60 on the seed layer 30, corresponding to the pads to be formed. This second pattern structure 60 is used to prevent the portion corresponding to the second pattern structure 60 on the seed layer 30 from being etched away during the subsequent etching process to form the pads. Specifically, a resist can be coated onto the entire surface of the seed layer 30, and then, after masking, exposure, and development, a second pattern structure 60 corresponding to the shape of the pads to be formed is formed. For example, see reference... Figure 6 As shown, after the patterning process, the remaining resist structure forms a second pattern structure 60 corresponding to the shape of the pad to be formed.

[0072] Step S06: Remove the portion of the seed layer not covered by the second pattern structure and the metal trace by an etching process, and remove the second pattern structure so that the remaining seed layer forms a pad.

[0073] In this step, refer to Figure 6 and Figure 7The seed layer 30, on which the second pattern structure 60 is formed, is etched. After etching, the portion of the seed layer 30 not covered by the second pattern structure 60 and the metal trace 50 is removed, while the portion covered by the second pattern structure 60 is retained. Then, the second pattern structure 60 is removed, exposing the seed layer covered by the second pattern structure 60, thus forming the pad 70. Furthermore, as described in the preceding steps, the pad 70 in this embodiment has a stacked structure, and the outermost protective layer effectively protects the metal layer it covers, resulting in good oxidation resistance of the pad.

[0074] It should be noted that during the etching process, a certain portion of the metal trace 50 will also be etched away. However, since the thickness difference between the metal trace 50 and the seed layer 30 is significant, the removal of a certain portion of the metal trace 50 will not affect its subsequent normal use.

[0075] Further reference Figure 8 After forming the pads 70, a planar protective layer 80 can be formed to improve the coverage of the metal traces. The material of the planar protective layer 80 can be one or any combination of SiNx, SiO2, and SiON. Then, a planarization layer 90 is formed on the planar protective layer 80 to give the drive backplane a flat surface. Finally, openings are made in the planarization layer 90 corresponding to the positions of the pads 70 to expose the pads 70, thus completing the fabrication of the drive backplane in this embodiment. A schematic diagram of the structure of the completed drive backplane is shown below. Figure 8 As shown.

[0076] Based on the manufacturing method of this embodiment, the driver backplane is subsequently processed by transferring Micro LED chips and bonding the Micro LED chips to the pads of the driver backplane. The resulting display panel structure can be illustrated as follows. Figure 9 As shown. Since the thickness of the pad 70 is uniform, the distance between it and the electrode of the Micro LED chip 010 is basically the same, so there will be no phenomenon of cold solder joint or poor contact.

[0077] As can be seen from the above embodiments, the fabrication method of this application, based on the sputtering of a seed layer with uniform thickness, also ensures that the thickness of the pads is uniform. This guarantees that during the subsequent bonding process, the spacing between each electrode of the Micro LED chip and its corresponding pad is basically the same, thereby avoiding the phenomenon of poor soldering and contact caused by excessive spacing. On the other hand, during the patterned electroplating process, only the pattern structure corresponding to the metal traces is formed, not the pattern structure corresponding to the pads. This simplifies the formed pattern structure and makes the pattern structure distribution uniform. (Reference) Figure 10As shown, this is a top view of the structure perpendicular to the substrate. The spacing between any two adjacent metal traces 50 is basically the same, which ensures good uniformity of metal trace thickness in the electroplating process and further improves the product yield.

[0078] Based on the same inventive concept, this application also provides a drive backplane, which is manufactured by the drive backplane manufacturing method described in any of the above embodiments.

[0079] For details, please refer to Figure 8 The driving backplane of this embodiment includes a substrate 10 and a circuit structure layer 20 disposed on the substrate 10. Specifically, the circuit structure layer 20 includes a buffer layer 201, a first gate insulating layer 202, a second gate insulating layer 203, an interlayer insulating layer 204, a planarization layer 205, and a planarization protection layer 206, which are stacked sequentially. A bottom gate 101 is formed on the substrate 10, an active layer 2011 is formed on the buffer layer 201, a first gate 2021 is formed on the first gate insulating layer 202, a second gate 2031 is formed on the second gate insulating layer 203, and an active drain 2041 is formed on the interlayer insulating layer 204.

[0080] refer to Figure 8 and Figure 9 Based on the substrate 10 and the circuit structure layer 20, metal traces 50 and pads 70 are further fabricated using the methods of any of the aforementioned embodiments. Two pads 70 constitute a pad group, and the two pads 70 in this pad group are used to bond to the two electrodes of the Micro LED chip 010, respectively. It is understood that, for simplicity, the number of some components in the accompanying drawings is only illustrative, and the actual number will be greater in specific implementations. For example, only one pad group is shown in the drawings, while in specific implementations, the pad group will be set accordingly to correspond to the number of Micro LED chips included in the display array.

[0081] In this embodiment, reference Figures 3 to 8 The pad 70 is formed by etching the seed layer 30. Accordingly, the pad 70 includes a buffer layer, a metal layer, and a protective layer stacked sequentially. Furthermore, after the seed layer 30 is etched, the portion of the seed layer 30 covered by the metal trace 50 is retained. For details, please refer to [reference needed]. Figures 7 to 9 As shown. Due to the reserved seed layer 30 and the relatively thick fabrication requirement of the metal trace 50 itself to avoid IR drop, the thickness of the metal trace 50 in this embodiment is greater than the thickness of the pad 70.

[0082] In this embodiment, reference Figure 8A flat protective layer 80 and a flat layer 90 are stacked sequentially on the metal trace 50 and the pad 70. The protective layer 80 and the flat layer 90 are provided with through holes at the positions corresponding to the pad 70 to expose the pad 70.

[0083] The specific settings and functions of each of the above-mentioned hierarchical structures can be found in the description of the aforementioned method embodiments, and will not be repeated in this embodiment.

[0084] refer to Figure 10 This is a top view of the driving backplane in this embodiment, perpendicular to the substrate. The metal trace 50 specifically includes a first driving power line VDD and a common power line VSS. Correspondingly, a second driving power line VDDr and a light-emitting control line Gate / EM are also provided within the circuit structure layer. The first driving power line VDD and the common power line VSS extend along a first direction, which in the display technology field can be understood as the column direction; the second driving power line VDDr and the light-emitting control line Gate / EM extend along a second direction, which can be understood as the row direction perpendicular to the column. Since it is manufactured using the method of the aforementioned embodiment, the first driving power line VDD and the common power line VSS are evenly spaced and uniformly arranged in the row direction. This is because the second cluster structure formed in the patterning process is uniformly distributed, which makes the thickness of the first driving power line VDD and the common power line VSS formed by the electroplating process basically the same, and also improves the product yield to a certain extent.

[0085] In this embodiment, the driving backplane, based on the first driving power line VDD, the common power line VSS, the second driving power line VDDr, and the light emission control line Gate / EM, can be divided into several pixel regions arranged in an array. Each pixel region can be referenced... Figure 10 As shown by reference numeral A in the attached figure, a pixel region includes three pad groups, each corresponding to one of the three sub-pixels within the pixel, such as the RGB sub-pixels in a full-color display. For each sub-pixel, two electrodes of the Micro LED chip are bonded to two pads 70 within a pad group.

[0086] Since the driving backplate of this embodiment is manufactured by the driving backplate manufacturing method described in any of the foregoing embodiments, the pads on the resulting driving backplate have uniform thickness. This ensures that the spacing between each electrode of the Micro LED chip and its corresponding pad is basically the same during the subsequent bonding process. This avoids the phenomenon of poor soldering and poor contact caused by excessive spacing between the two, improves the product yield, and ensures normal display.

[0087] Based on the same inventive concept, this application also provides a display device, which includes a driving backplate as described in the above embodiments.

[0088] In practice, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, or navigator.

[0089] The display device in this embodiment uses the driving backplate of the aforementioned embodiment, and thus has the beneficial effects of the driving backplate, which will not be described again in this embodiment.

[0090] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0091] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0092] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A method of fabricating a drive backplane, comprising: The application relates to a method for forming a metal trace and a pad on a substrate. ​ The method comprises the following steps: providing a substrate and forming a circuit structure layer on the substrate; forming a seed layer with uniform thickness and integrity on the circuit structure layer by a sputtering process; forming a first pattern structure corresponding to a metal trace to be formed on the seed layer by a patterning process; forming the metal trace by an electroplating process and removing the first pattern structure; forming a second pattern structure corresponding to a pad to be formed on the seed layer by a patterning process; 2. The method of claim 1, wherein, removing the seed layer not covered by the second pattern structure and the metal trace by an etching process, and removing the second pattern structure, so that the remaining seed layer forms a pad with uniform thickness. The method for forming the seed layer with uniform thickness and integrity on the circuit structure layer comprises the following steps:

3. The method of claim 2, wherein, forming a buffer layer, a metal layer and a protective layer in sequence on the circuit structure layer by a sputtering process, so that the buffer layer, the metal layer and the protective layer in sequence form the seed layer.

4. The method of claim 2, wherein, The material of the buffer layer is titanium-molybdenum alloy or titanium-neodymium alloy; the material of the metal layer is copper; and the material of the protective layer is copper-nickel alloy, copper-aluminum alloy or copper-titanium alloy.

5. The method of claim 2, wherein, The thickness of the buffer layer is 1 / 80 to 1 / 2 of the thickness of the metal layer; and the thickness of the protective layer is 1 / 80 to 1 / 2 of the thickness of the metal layer.

6. The method of claim 1, wherein, The thickness of the metal trace is 6 to 100 times of the thickness of the metal layer.

7. The method of claim 6, wherein, The first pattern structure comprises a barrier wall, and a plurality of strip-shaped hollow structures are formed on the barrier wall by a patterning process; one hollow structure corresponds to one metal trace to be formed.

8. The method of claim 1, wherein, The distance between any two adjacent hollow structures is the same. After the pad is formed, the method further comprises the following steps: forming a flat protective layer for improving the coverage of the metal trace; 9. A drive backplane, characterized by forming a flat layer on the flat protective layer, and opening a hole in the flat layer at a position corresponding to the pad, so that the pad is exposed. The application relates to a substrate and a circuit structure layer arranged on the substrate; the circuit structure layer further comprises metal traces and a pad group arranged in the same layer; the pad group comprises two pads with uniform thickness; and the thickness of the metal traces is greater than that of the pads.

10. The drive backplane of claim 9, wherein, The pad comprises a buffer layer, a metal layer and a protective layer arranged in sequence.

11. The drive backplane of claim 9, wherein, The application further comprises the following steps: a flat protective layer and a flat layer arranged in sequence on the pad group and the metal traces; the flat protective layer and the flat layer are provided with through holes corresponding to the pads for exposing the pads.

12. The drive backplane of claim 9, wherein, The metal traces comprise a first driving power line and a common power line; one pad in the pad group is connected to the first driving power line through the circuit structure layer, and another pad in the pad group is connected to the common power line through the circuit structure layer.

13. The drive backplane of claim 12, wherein, The circuit structure layer is further provided with a second driving power supply line and a light emitting control line; the first driving power supply line and the common power supply line extend along a first direction, and the second driving power supply line and the light emitting control line extend along a second direction perpendicular to the first direction, so as to divide the driving backboard into a plurality of pixel regions arranged in an array; each of the pixel regions comprises three pad groups.

14. A display device comprising: The display panel comprises the driving backboard as claimed in any one of claims 9 to 13.

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