A phase jitter compensation method, module and digital phase-locked loop

Abstract

The application discloses a phase jitter compensation method, a module and a digital phase-locked loop. The phase jitter compensation method comprises the following steps: acquiring a phase error signal of the digital phase-locked loop in a current period and a phase error signal of an adjacent previous period, and determining duty cycle mismatch information according to the phase error signal in the current period and the phase error signal of the adjacent previous period, wherein the phase error signal comprises a digital signal formed by a difference between an input reference signal phase and a feedback signal phase; generating current phase compensation information according to the duty cycle mismatch information; correcting the phase error signal in the current period by using the current phase compensation information, and sending the corrected phase error signal to the digital phase-locked loop, so as to re-perform phase tracking according to the corrected phase error signal. The technical scheme of the embodiment of the application can improve calibration accuracy and reduce the area of a circuit required for calibration.

Description

Technical Field

[0001] This application relates to the field of phase-locked loops, and more particularly to a phase jitter compensation method, module, and digital phase-locked loop. Background Technology

[0002] Currently, the 6th generation wireless technology standard 802.11ax supports 1024 quadrature amplitude modulation (QAM) modulation and demodulation. Its -35dB error vector magnitude (EVM) specification places strict requirements on clock quality and poses a huge challenge to the implementation of clock circuits.

[0003] Generally, increasing the reference frequency of a phase-locked loop (PLL) improves the in-band noise performance of the output clock, greatly alleviating the design pressure of high-performance PLLs. Since the clock frequency of the external reference crystal is fixed, increasing the PLL reference clock frequency is often achieved through an internal frequency multiplier circuit. If a duty cycle mismatch occurs in the input clock source, jitter will appear on the reference clock edges while the reference frequency is increased by the frequency multiplier, thus worsening the in-band noise and spurious performance.

[0004] In existing technologies, duty cycle calibration circuits are commonly implemented using analog methods. Analog clock duty cycle calibration circuits include filters, voltage comparators, and duty cycle adjustment circuits, resulting in large circuit sizes and requiring collaboration between analog and digital circuits, which increases the difficulty of development and design and the simulation verification cycle. Furthermore, the mismatch in analog circuits limits the adjustment accuracy to the matching degree of the analog circuits, making it difficult to achieve ideal calibration results. Moreover, the consistency and reliability of calibration are also affected by factors such as the processing procedure, voltage, and temperature (PVT). Summary of the Invention

[0005] This application provides a phase jitter compensation method, module, and digital phase-locked loop to achieve duty cycle calibration without adding analog circuitry, thereby improving calibration accuracy, reducing the area of ​​the circuitry required for calibration, and lowering development difficulty.

[0006] In a first aspect, embodiments of this application provide a phase jitter compensation method applied in a digital phase-locked loop, comprising:

[0007] The phase error signal of the digital phase-locked loop in the current cycle and the phase error signal of the adjacent previous cycle are obtained. Based on the phase error signal in the current cycle and the phase error signal of the adjacent previous cycle, the duty cycle mismatch information is determined. The phase error signal includes a digital signal formed by the difference between the phase of the input reference signal and the phase of the feedback signal. The input reference signal is the input reference signal of the digital phase-locked loop, and the feedback signal is the feedback signal transmitted in the feedback loop of the digital phase-locked loop when the phase is locked.

[0008] Based on the duty cycle mismatch information, generate the current phase compensation information;

[0009] The phase error signal in the current period is corrected using the current phase compensation information, and the corrected phase error signal is sent to the digital phase-locked loop to instruct the digital phase-locked loop to re-track the phase based on the corrected phase error signal.

[0010] Secondly, embodiments of this application also provide a phase jitter compensation module, configured in a digital phase-locked loop, comprising:

[0011] The duty cycle mismatch detection module is used to acquire the phase error signal of the digital phase-locked loop in the current cycle and the phase error signal of the adjacent previous cycle, and determine the duty cycle mismatch information based on the phase error signal in the current cycle and the phase error signal of the adjacent previous cycle. The phase error signal includes a digital signal formed by the difference between the phase of the input reference signal and the phase of the feedback signal. The input reference signal is the input reference signal of the digital phase-locked loop, and the feedback signal is the feedback signal transmitted in the feedback loop of the digital phase-locked loop when the phase is locked.

[0012] The error accumulation module is used to generate current phase compensation information based on the duty cycle mismatch information.

[0013] The calibration compensation module is used to correct the phase error signal in the current period using the current phase compensation information, and send the corrected phase error signal to the digital phase-locked loop to instruct the digital phase-locked loop to re-track the phase based on the corrected phase error signal.

[0014] Thirdly, embodiments of this application also provide a digital phase-locked loop, including:

[0015] A phase comparison module, a phase jitter compensation module as described in any one of the embodiments of this application, and a phase tracking module;

[0016] The phase comparison module is connected to the phase tracking module. The phase comparison module is used to acquire the input reference signal and the feedback signal sent by the phase tracking module, compare the phase of the input reference signal and the feedback signal, generate a phase error signal, and send the phase error signal to the phase jitter compensation module.

[0017] The phase jitter compensation module is used to correct the phase error signal so that the corrected phase error signal can be sent to the phase tracking module.

[0018] The phase tracking module generates a feedback signal based on the corrected phase error signal and sends it to the phase comparison module. The feedback signal instructs the phase comparison module to continuously adjust the phase error signal until the data in the phase error signal becomes constant.

[0019] This application embodiment applies a phase jitter compensation method in a digital phase-locked loop (PLL). It acquires a digital phase error signal from the PLL, compares the phase errors of adjacent cycles to obtain duty cycle mismatch information, generates current phase compensation information based on the mismatch, and applies this information to the current cycle's phase error signal. The corrected phase error signal is then sent to the PLL to instruct it to continue phase tracking. This method compensates for phase jitter caused by duty cycle mismatch in the PLL, solving the problems of low calibration accuracy and large circuit area associated with analog circuits for duty cycle calibration in existing technologies. It overcomes the limitations of analog circuits in calibrating duty cycles, improving calibration accuracy, reliability, and consistency while reducing the calibration circuit area. Attached Figure Description

[0020] Figure 1 A schematic diagram illustrating phase jitter caused by duty cycle mismatch, provided as an embodiment of this application;

[0021] Figure 2 A schematic flowchart illustrating a phase jitter compensation method provided in an embodiment of this application;

[0022] Figure 3 A schematic flowchart illustrating a phase jitter compensation method provided in an embodiment of this application;

[0023] Figure 4 A schematic diagram of a phase jitter compensation module provided in an embodiment of this application;

[0024] Figure 5 A schematic diagram of a phase jitter compensation module provided in an embodiment of this application;

[0025] Figure 6 A schematic diagram of a phase jitter compensation module provided in an embodiment of this application;

[0026] Figure 7 A schematic diagram of an odd / even period detection module provided in an embodiment of this application;

[0027] Figure 8 A schematic diagram of a duty cycle mismatch detection module provided in an embodiment of this application;

[0028] Figure 9 A schematic diagram of a first direction correction module provided in an embodiment of this application;

[0029] Figure 10 A schematic diagram of an attenuator and an accumulator provided in an embodiment of this application;

[0030] Figure 11 A schematic diagram of a second direction correction module provided in an embodiment of this application;

[0031] Figure 12 A schematic diagram of a phase jitter compensation module provided in an embodiment of this application;

[0032] Figure 13 A schematic diagram of a phase jitter compensation module provided in an embodiment of this application;

[0033] Figure 14 A schematic diagram of a calibration compensation module provided in an embodiment of this application;

[0034] Figure 15 A schematic diagram of a digital phase-locked loop provided in an embodiment of this application;

[0035] Figure 16 A schematic diagram of a digital phase-locked loop provided in an embodiment of this application;

[0036] Figure 17 A schematic diagram of the phase error signal when a phase jitter compensation module stops working, provided as an embodiment of this application;

[0037] Figure 18 A schematic diagram of the phase error signal when an SDM quantization noise calibration correlation module is in operation, as provided in an embodiment of this application;

[0038] Figure 19 A schematic diagram of the phase error signal when a phase jitter compensation module is working, provided in an embodiment of this application;

[0039] Figure 20 A schematic diagram of the phase error signal when a phase jitter compensation module stops working, provided as an embodiment of this application;

[0040] Figure 21 A schematic diagram of the phase error signal when a phase jitter compensation module is working, provided in an embodiment of this application;

[0041] Figure 22 A schematic diagram of the phase error signal when a phase jitter compensation module stops working, provided as an embodiment of this application;

[0042] Figure 23 This is a schematic diagram of the phase error signal when the phase jitter compensation module and the SDM quantization noise calibration associated module are working, as provided in an embodiment of this application. Detailed Implementation

[0043] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0044] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustration in this application and has no inherent meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0046] Current modulation and demodulation methods place more stringent demands on clock quality. Traditional analog phase-locked loops (APLLs) encounter performance bottlenecks in generating such high-quality clocks. Compared to APLLs, digital phase-locked loops (DPLLs) offer greater freedom in loop filter design and bandwidth configuration. By selecting appropriate loop parameters, the integral noise of the DPLL output clock can be optimized. Furthermore, its fully digital implementation allows for the use of various digital calibration techniques, which effectively improve PLL performance. Finally, DPLLs offer significant area and performance advantages over APLLs under advanced manufacturing processes. Therefore, high-performance clock generators are typically implemented using DPLLs.

[0047] Increasing the frequency of the input reference signal in a phase-locked loop (PLL) improves the in-band noise performance of the output clock, significantly alleviating the design pressure of high-performance PLLs. Since the clock frequency of the external input reference signal's crystal is fixed, increasing the PLL input reference signal frequency is often achieved through an internal frequency multiplier circuit. However, if a duty cycle mismatch occurs in the input reference signal source, jitter will appear on the input reference signal edges while increasing the reference frequency through the frequency multiplier. For example, ... Figure 1 As shown, the input reference signal is a square wave signal with a 50% duty cycle. The duty cycle can be the proportion of time the high level occupies in one cycle. However, due to duty cycle mismatch, the t1 and t0 of the input reference signal are different, resulting in a duty cycle that is not 50%. Consequently, after frequency doubling (the frequency is increased to twice the original value), the phase of the actual second-harmonic input reference signal is different in adjacent cycles, which manifests as different durations of adjacent cycles. In fact, if there is no duty cycle mismatch in the input reference signal, i.e., t1 and t0 are the same, then the phase of the ideal second-harmonic input reference signal after frequency doubling is the same in adjacent cycles, and the duration of each cycle is t2. Compared to the ideal second-harmonic input reference signal, the rising edge of a certain cycle in the actual second-harmonic input reference signal is delayed by Δt, or the rising edge of a certain cycle is advanced by Δt. This can be understood as the duty cycle mismatch causing jitter of Δt in the second-harmonic input reference signal. Specifically, if sampling is performed on the falling edge of the feedback signal, a jitter of Δt will occur on the rising edge of the input reference signal in odd-numbered periods. This jitter degrades in-band noise and spurious performance. Therefore, in a phase-locked loop (PLL), a duty cycle calibration circuit is often required where the frequency multiplier circuit appears. Correspondingly, a digital PLL performs phase tracking based on an ideal second-harmonic input reference signal. After phase locking, the generated feedback signal has the same phase in adjacent periods, and the phase error between the feedback signal phase and the ideal second-harmonic input reference signal phase remains constant.

[0048] Current improvements involve using analog duty cycle detection circuits to calibrate the duty cycle. Typically, analog clock duty cycle calibration circuits include filters, voltage comparators, and duty cycle adjustment circuits. These circuits are large in scale and require coordination between analog and digital circuits, increasing development complexity and simulation verification time. Furthermore, the accuracy of analog circuit adjustment is limited by the matching degree of the analog circuit, and analog circuits can also introduce mismatches, making it difficult to achieve ideal calibration results. The consistency and reliability of calibration are also affected by PVT (phase-locked loop) voltage. In addition, the filters in the duty cycle detection circuit increase the overall system chip footprint, making it unsuitable for fully digital phase-locked loop circuits.

[0049] To address the duty cycle mismatch problem in existing phase-locked loops (PLLs), this application creatively proposes analyzing the phase error transmitted by the phase comparison module. The phase error is the digital signal output by the digital PLL. The duty cycle difference is calculated and periodically accumulated to generate a current phase compensation value, compensating for the phase error. Therefore, the entire calibration process requires no additional analog circuitry and eliminates the need to consider the loss of calibration accuracy due to duty cycle detection and calibration circuit mismatch. Thus, the duty cycle compensation technology of this invention will maximize the suppression of non-ideals caused by reference clock duty cycle mismatch in the PLL, namely, in-band noise degradation and reference spurious issues.

[0050] In one exemplary implementation Figure 2 This is a flowchart illustrating a phase jitter compensation method provided in an embodiment of this application. This phase jitter compensation method is applicable to situations where the duty cycle needs to be calibrated without adding additional analog circuitry. The phase jitter compensation method is applied in a digital phase-locked loop (PLL), and can be executed by a phase jitter compensation module configured within the PLL. This embodiment of the application does not limit the type of digital PLL.

[0051] like Figure 2 As shown, the phase jitter compensation method includes:

[0052] S110, acquire the phase error signal of the digital phase-locked loop in the current cycle and the phase error signal of the adjacent previous cycle, and determine the duty cycle mismatch information based on the phase error signal in the current cycle and the phase error signal of the adjacent previous cycle. The phase error signal includes a digital signal formed by the difference between the phase of the input reference signal and the phase of the feedback signal. The input reference signal is the input reference signal of the digital phase-locked loop, and the feedback signal is the feedback signal transmitted in the feedback loop of the digital phase-locked loop when the phase is locked.

[0053] In this embodiment, the digital phase-locked loop includes a phase comparison module and a phase tracking module. The phase comparison module acquires the phase of the input reference signal and the phase of the feedback signal, compares them, generates a phase error, and sends the phase error to the phase tracking module. The phase tracking module generates an output signal based on the phase error and determines a feedback signal based on the output signal, sending it to the phase comparison module to instruct the phase comparison module to continue comparing the phase error between the input reference signal and the feedback signal until the phase error between the input reference signal and the output signal remains constant. This achieves the purpose of generating an output signal synchronized with the input reference signal, thereby realizing phase locking. The feedback signal can be the same as the output signal, or it can be a signal formed by frequency division of the output signal (adding frequency points).

[0054] In fact, the phase jitter compensation method in this application starts working after the digital phase-locked loop locks the phase error between the feedback signal and the input reference signal. At this time, the phase error between the feedback signal and the input reference signal is fixed and can be 0 or a constant.

[0055] In a digital phase-locked loop (PLL), the phase error signal is the digital signal formed by the difference between the phase of the input reference signal and the phase of the feedback signal. The phase error signal can also refer to a digital signal showing how the phase error changes over time. Duty cycle mismatch information is used to represent the phase jitter error caused by duty cycle mismatch.

[0056] In reality, under ideal conditions without phase jitter, the input reference signal and feedback signal of a digital phase-locked loop (PLL) are the same across different cycles. However, since phase jitter is absent, the input reference signal and feedback signal differ across cycles, resulting in different phase differences between the input reference signal and feedback signal. Therefore, by analyzing whether the phase errors between the input reference signal and feedback signal are the same in adjacent cycles, duty cycle mismatch can be detected. Thus, the impact of phase jitter can be characterized by the phase difference between the input reference signal and feedback signal in different cycles. Consequently, the difference between the phase error signal of the PLL in the current cycle and the phase error signal of the adjacent previous cycle can be used to represent the phase jitter error caused by duty cycle mismatch.

[0057] In a specific example, such as Figure 1 As shown, the phase error signal of the current cycle can refer to the information regarding the phase error correlation between the phase of the true second harmonic input reference signal and the phase of the feedback signal within the current cycle. The phase error signal of the adjacent previous cycle can refer to the information regarding the phase error correlation between the phase of the true second harmonic input reference signal and the phase of the feedback signal within the cycle adjacent to the current cycle. Duty cycle mismatch information is used to determine whether the duty cycles in adjacent cycles are the same, thereby determining whether there is a duty cycle mismatch in the input reference signal. Duty cycle mismatch information can refer to the difference between the duty cycles of adjacent cycles, which can be represented by the difference between the phase errors of two adjacent cycles; that is, the difference between the phase errors of two adjacent cycles is used to detect whether there is a duty cycle mismatch.

[0058] In one exemplary embodiment, the digital phase-locked loop is a frequency-doubled digital phase-locked loop, and the phase error signal includes a digital signal formed by the difference between the phase of the frequency-doubled input reference signal and the phase of the feedback signal in the frequency-doubled digital phase-locked loop when the phase is locked. The frequency-doubled input reference signal is a signal formed by frequency-doubled processing of the input reference signal of the frequency-doubled digital phase-locked loop.

[0059] Typically, the phase jitter compensation method in this application is mainly applied to digital phase-locked loops (PLLs) and frequency-doubled PLLs. Furthermore, multiple frequency-doubled PLLs can be stacked to form a 2^n (n is an integer greater than or equal to 2) frequency-doubled PLL. Accordingly, the phase jitter compensation method can be applied to each frequency-doubled PLL separately, so that each frequency-doubled PLL resolves the phase jitter problem caused by duty cycle mismatch, thereby solving the phase jitter problem for the entire system.

[0060] By applying a phase jitter compensation method in a frequency-doubled digital phase-locked loop (PLL), and determining the phase compensation information based on the phase error signal between the frequency-doubled input reference signal and the feedback signal after frequency doubling, and compensating for the phase error signal, the phase jitter error caused by duty cycle mismatch in the frequency-doubled input reference signal in the frequency-doubled PLL can be effectively reduced.

[0061] In the digital phase-locked loop, the phase error sent by the phase comparison module is a value quantized by a time-to-digital converter (TDC). Thus, both the input reference signal and the feedback signal are digital signals. Consequently, the phase error signal formed by the change of the phase error between the input reference signal and the feedback signal over time is actually a digital signal.

[0062] It should be noted that the periods involved in the phase jitter compensation method disclosed in the embodiments of this application are all the clock periods of the feedback signal.

[0063] S120, Generate current phase compensation information based on the duty cycle mismatch information.

[0064] In practice, the phase jitter compensation method is a negative feedback loop-based compensation method. Specifically, it adjusts the phase compensation in each cycle until the phase error caused by duty cycle mismatch in the loop decreases and converges to a stable value. It can track the phase error signal in real time, determine the matching compensation value, and respond promptly to the phase error signal to adjust the compensation value accordingly, thus improving the stability of the compensation system. Duty cycle mismatch information is used to determine the phase compensation value for the current cycle, and this value is continuously adjusted based on the phase compensation situation in historical cycles to generate the phase compensation value for the current cycle. Current phase compensation information is used to compensate for the phase error signal in the current cycle. Current phase compensation information can refer to the phase compensation value for the current cycle.

[0065] This can be understood as the existence of a desired phase compensation value that can compensate for the phase error under duty cycle mismatch conditions, so that the compensated phase error is (or very close to) the phase error between the ideal input reference signal phase and the feedback signal phase. The phase error under duty cycle mismatch conditions actually changes periodically with time, and the corresponding desired phase compensation value also changes periodically with time. Therefore, the phase error signal formed by the phase error changing over time, and the ideal phase compensation signal formed by the desired phase compensation value changing over time, have their amplitudes representing the desired phase compensation value. Thus, phase compensation is not achieved in one step, but rather through compensation in each cycle, gradually bringing the phase error between the actual input reference signal phase and the feedback signal phase closer to the phase error between the ideal input reference signal phase and the feedback signal phase. This, in turn, gradually brings the ideal input reference signal closer to the actual input reference signal, ultimately achieving the compensation effect for the input reference signal. Duty cycle mismatch information is used to adjust the phase compensation information to continuously approach the desired phase compensation value.

[0066] In one exemplary embodiment, generating current phase compensation information based on the duty cycle mismatch information includes: performing attenuation processing on the data in the duty cycle mismatch information; calculating the sum of the attenuated data and the data in the cumulative phase compensation information to determine the current phase compensation information; and using the current phase compensation information as new cumulative phase compensation information.

[0067] Attenuation processing is used to reduce the size of data, for example, by reducing the order of magnitude or the number of bits. This can be achieved through right shifting of a register (shifting right by 's' bits reduces the original data value by a factor of 2^s) or multiplication (multiplying by λ, where 0 < λ < 1). Attenuation processing effectively reduces the adjustment value of the phase compensation value, accumulating the attenuated data into the accumulated phase compensation information. This allows for fine-tuning of the phase compensation value, avoiding large-scale adjustments that could deviate from the desired value, thus precisely adjusting the phase compensation value and improving the stability of phase jitter compensation.

[0068] Accumulated phase compensation information is used to accumulate the phase compensation values ​​from each compensation cycle, continuously approaching the desired phase compensation value. The accumulated phase compensation information can be the phase compensation value obtained from the previous accumulation. Accumulating the values ​​from the duty cycle mismatch information into the accumulated phase compensation information can adjust the previous phase compensation value. The accumulated result can be the phase compensation value obtained through continuous adjustments since the phase jitter compensation method began operating. The current phase compensation information can refer to the phase compensation value accumulated in the current cycle.

[0069] For example, the initial value of the accumulated phase compensation information is 0, meaning that the accumulated phase compensation information includes zero values ​​at the start of operation. The current phase compensation information is used to determine the phase values ​​for duty cycle mismatch compensation of the current cycle phase error. The current phase compensation information may include the phase values ​​to be compensated for in the current cycle phase error. Simultaneously, the current phase compensation information serves as the new accumulated phase compensation information.

[0070] This application embodiment improves the stability of the phase jitter compensation system by attenuating the duty cycle mismatch information and continuously and precisely accumulating and adjusting the phase compensation value to make the phase compensation value approach the desired phase compensation value, thereby ultimately compensating for the phase jitter caused by the duty cycle mismatch and improving the stability and accuracy of phase jitter compensation.

[0071] S130, the phase error signal in the current period is corrected using the current phase compensation information, and the corrected phase error signal is sent to the digital phase-locked loop to instruct the digital phase-locked loop to re-track the phase based on the corrected phase error signal.

[0072] The compensation value included in the current phase compensation information is added to the phase error signal of the current period. For example, the compensation value is added or subtracted from the phase error signal. The corrected phase error signal is used as a phase error to eliminate duty cycle mismatch error and is sent to the digital phase-locked loop (PLL) to instruct the PLL to continue the phase tracking process based on the corrected phase error signal. This eliminates duty cycle mismatch error during the phase tracking process of the PLL, ensuring that the output feedback signal corresponds to the ideal input reference signal.

[0073] This application embodiment applies a phase jitter compensation method in a digital phase-locked loop (PLL). It acquires a digital phase error signal from the PLL, compares the phase errors of adjacent cycles to obtain duty cycle mismatch information, generates current phase compensation information based on the mismatch, and applies this information to the current cycle's phase error signal. The corrected phase error signal is then sent to the PLL to instruct it to continue phase tracking. This method compensates for phase jitter caused by duty cycle mismatch in the PLL, solving the problems of low calibration accuracy and large circuit area associated with analog circuits for duty cycle calibration in existing technologies. It overcomes the limitations of analog circuits in calibrating duty cycles, improving calibration accuracy, reliability, and consistency while reducing the calibration circuit area.

[0074] In one exemplary embodiment, before attenuating the data in the duty cycle mismatch information, the method further includes:

[0075] The input reference signal is sampled using the falling edge of the feedback signal, and the parity information of the current period is determined based on the level of the sampled input reference signal point. The input reference signal point in an odd period has a low level, and the input reference signal point in an even period has a high level. The sign of the data in the duty cycle mismatch information is corrected based on the parity information of the current period and a preset correspondence between parity information and sign. The attenuation processing of the data in the duty cycle mismatch information includes attenuating the data in the corrected duty cycle mismatch information. The calculation of the sum of the attenuated data and the data in the accumulated phase compensation information, and determining this sum as the current phase compensation information, includes calculating the sum of the attenuated data and the data in the accumulated phase compensation information. The sign of the sum is corrected based on the parity information of the current period and a preset correspondence between parity information and sign, and the corrected sum is determined as the current phase compensation information.

[0076] At this point, the digital phase-locked loop (PLL) is a frequency-doubled PLL. The parity information of the current cycle is used to determine the direction of adjustment for the phase compensation value and the direction of compensation for the phase difference information of the current cycle. The parity information of the current cycle is used to correct the sign of the data in the duty cycle mismatch information. In fact, the values ​​in the duty cycle mismatch information are absolute values, and the parity information of the current cycle is used to add a sign to the data in the duty cycle mismatch information. Furthermore, the parity information of the current cycle is used to add a sign to the accumulated data. Since the desired phase compensation value can be positive or negative, by adding a sign to the data in the current phase compensation information, a current phase compensation value that matches the desired phase compensation value is converged.

[0077] In a frequency-doubled digital phase-locked loop (PLL), the period of the input reference signal before frequency doubling is twice the period of the input reference signal after frequency doubling. Specifically, as follows... Figure 1 As shown, t1 and t0 constitute one period of the input reference signal. Simultaneously, t1 forms the first period of the actual second harmonic input reference signal, and t0 forms the second period. When there is no duty cycle mismatch, each period of the actual second harmonic input reference signal is the same. However, due to the duty cycle mismatch in the actual second harmonic input reference signal, the first and second periods are different, while the third and fourth periods repeat the situation of the first and second periods. Therefore, odd and even periods can be used to distinguish the first and second periods. Furthermore, by... Figure 1 It can be seen that the input reference signal is high at time t1 and low at time t0. Therefore, the parity of the period of the second harmonic input reference signal can be determined by the level state of the input reference signal. For example, the input reference signal can be sampled according to the period of the feedback signal, such as by sampling the input reference signal at the rising or falling edge of the electrical feedback signal. Among the sampled signal points, the input reference signal points in odd-numbered periods have a low level, and the input reference signal points in even-numbered periods have a high level.

[0078] During phase compensation, the phase compensation value may be greater than or less than the desired phase compensation value. Therefore, when adjusting the phase compensation value to approach the desired value, it is necessary to increase or decrease the adjustment amount to continuously approach the desired phase compensation value. It can be configured to increase the phase compensation value during odd-numbered periods and decrease it during even-numbered periods, or vice versa. The increase and decrease can be reflected in the sign of the value; adding a positive number to the accumulated phase compensation information is equivalent to increasing the value of the accumulated phase compensation information; adding a negative number to the accumulated phase compensation information is equivalent to decreasing the value of the accumulated phase compensation information.

[0079] In reality, the phase jitter compensation method cannot accurately obtain the desired phase compensation value. It can only obtain the phase compensation value through the known phase error signal and continuously accumulate it until the desired phase compensation value is converged. By adjusting the phase compensation value by increasing or decreasing it according to the odd or even number of the period, the phase compensation value for phase jitter caused by duty cycle mismatch can be accurately converged.

[0080] This application embodiment detects the parity of the period of the actual second harmonic input reference signal by detecting the parity of the period. Based on the parity information, signs are added to the data in the duty cycle mismatch information and the data in the accumulation result to increase or decrease the adjustment phase compensation value, continuously approaching the desired phase compensation value until the desired phase compensation value is converged. Finally, the phase jitter caused by the duty cycle mismatch is compensated, and the stability and accuracy of phase jitter compensation are improved.

[0081] In one exemplary implementation Figure 3 A flowchart illustrating a phase jitter compensation method provided in an embodiment of this application. The method includes:

[0082] S210, acquire the phase error signal of the digital phase-locked loop in the current cycle and the phase error signal of the adjacent previous cycle, and determine the duty cycle mismatch information based on the phase error signal in the current cycle and the phase error signal of the adjacent previous cycle. The phase error signal includes a digital signal formed by the difference between the phase of the input reference signal and the phase of the feedback signal. The input reference signal is the input reference signal of the digital phase-locked loop, and the feedback signal is the feedback signal transmitted in the feedback loop of the digital phase-locked loop when the phase is locked.

[0083] S220, Generate current phase compensation information based on the duty cycle mismatch information.

[0084] S230, using the current phase compensation information, the preset frequency division control information is compensated to generate corrected frequency division control information.

[0085] Among them, the frequency division control information can be a frequency control word (FCW).

[0086] S240, the corrected frequency division control information is quantized to obtain quantized frequency division control information, which is used to instruct the digital phase-locked loop to generate a feedback signal based on the quantized frequency division control information.

[0087] The corrected frequency division control information can refer to the frequency division control information after compensation with the current phase compensation information, that is, the phase jitter error introduced by duty cycle mismatch is reduced in the corrected frequency division control information. The quantized frequency division control information can refer to the frequency division control information formed by quantizing the corrected frequency division control information.

[0088] Specifically, in frequency-multiplying digital phase-locked loops (PLLs), such as a frequency-doubled PLL, a Sigma-Delta Modulator (SDM) quantizes the frequency division control information to generate a digital control signal. This signal instructs the frequency divider to divide the PLL's output signal, forming a feedback signal. However, SDM quantization loses some continuous data, resulting in quantization error. Therefore, the quantization error of the SDM can be calculated and compensated for to reduce the quantization error in the PLL.

[0089] A triangular integral modulator is used to quantize frequency division control information. For example, if the triangular integral modulator is an nth-order SDM, the output quantized frequency division control information includes [-2...]. n-1 +1, 2 n-1 Integers within the range of ] . The trigonometric integral modulator is used to send the quantized frequency division control information to the frequency divider in the digital phase-locked loop (PLL). The quantized frequency division control information instructs the frequency divider to divide the output signal of the PLL to form a feedback signal. Since the quantized frequency division control information includes current phase compensation information, the frequency divider divides the output signal according to the control signal that compensates for the phase jitter error introduced by the duty cycle mismatch. This allows for frequency division adapted to the currently compensated output signal, thereby improving the accuracy of the frequency division.

[0090] S250, determine quantization compensation information based on the corrected frequency division control information and the quantized frequency division control information.

[0091] Because of quantization error, the quantized frequency division control information contains quantization error. Therefore, it is possible to determine whether quantization error has been introduced by analyzing the difference between the frequency division control information before and after quantization. Thus, the compensation value for the quantization error can be determined by analyzing the corrected frequency division control information and the difference between the quantized and corrected frequency division control information.

[0092] Quantization compensation information is used to compensate for duty cycle mismatch and quantization error in phase error signals. This information includes two types: one for phase jitter error introduced by duty cycle mismatch in the input reference signal, and the other for phase error introduced by the quantization operation of the trigonometric integral modulator.

[0093] S260, The phase error signal of the current period is corrected using the quantization compensation information.

[0094] By using quantization compensation information for correction, duty cycle mismatch error and quantization error can be compensated in the phase error signal.

[0095] S270, the corrected phase error signal is sent to the digital phase-locked loop to instruct the digital phase-locked loop to re-perform phase tracking based on the corrected phase error signal.

[0096] This application embodiment adds current phase compensation information to the input frequency division control information of the trigonometric integral modulator and obtains the frequency division control information of the trigonometric integral modulator before and after quantization to determine the quantization compensation information of the trigonometric integral modulator. Since the frequency division control information before and after quantization includes the current phase compensation information, the current phase compensation information is introduced into the quantization compensation information. Therefore, the phase error signal is compensated according to the quantization compensation information, and the error introduced by duty cycle mismatch and the quantization error introduced by the trigonometric integral modulator are also compensated, thereby improving the phase-locked loop accuracy and reducing the system error of the digital phase-locked loop.

[0097] In one exemplary embodiment, the frequency division control information is a frequency control word; determining the quantization compensation information based on the corrected frequency division control information and the quantized frequency division control information includes: obtaining the corrected frequency control word and the quantized frequency control word, calculating quantization error information; accumulating the accumulated quantization compensation information based on the quantization error information to generate current quantization compensation information; using the current quantization compensation information as new accumulated quantization compensation information; obtaining compensation gain information based on the current quantization compensation information and the phase correction feedback signal; and calculating the product of the data in the compensation gain information and the data in the current quantization compensation information as the quantization compensation information.

[0098] Quantization error information can refer to the difference between the data before and after quantization processing by the trigonometric integral modulator, and can be represented by the difference between the corrected frequency control word and the quantized frequency control word.

[0099] In practice, there exists a desired phase compensation value that can compensate for the quantization error of the SDM, so that the compensated quantized data is (or very close to) the unquantized data. Similar to the compensation process for duty cycle mismatch, the calibration compensation module cannot accurately obtain the desired quantization compensation value; it can only obtain the quantization compensation value through known quantization error information and continuously accumulate it until it converges to the desired quantization compensation value. Accumulated quantization compensation information is used to accumulate the quantization compensation values ​​of each compensation iteration, continuously approaching the desired quantization compensation value. The accumulated quantization compensation information can be the quantization compensation value obtained from the previous accumulation. For example, the initial value of the accumulated quantization compensation information is 0, that is, when the phase jitter compensation method starts working, the accumulated quantization compensation information includes 0 values.

[0100] The compensation gain information is used to increase the numerical value of the current quantization compensation information data. Since there is an order of magnitude difference between the current quantization compensation information and the phase error signal—for example, the quantization compensation information is extremely small compared to the phase error signal—the compensation effect of the quantization compensation information on the phase error signal is poor. Therefore, the current quantization compensation information can be increased to make its order of magnitude the same as that of the phase error signal, thereby accurately compensating for the phase error signal.

[0101] Furthermore, the quantization compensation process is a negative feedback loop. The phase correction feedback signal is the phase error signal after the previous correction. Based on the phase correction feedback signal and the current quantization compensation information, the compensation value of the current quantization error can be continuously adjusted according to the compensation status of the previous quantization error, thereby continuously calibrating the compensation value. Using the continuously calibrated values ​​as compensation gain information can improve the accuracy of the compensation value.

[0102] The current quantization compensation information after gain is used as the quantization compensation information, and the phase error signal of the current period is compensated, so as to realize the simultaneous duty cycle mismatch compensation and SDM quantization compensation for phase error.

[0103] The embodiments of this application can accurately calculate the quantization error by calculating the quantization residual, calculating the calibration source, calculating the compensation gain, and correcting the quantization error. Based on the quantization error, the quantization compensation value is determined, and the quantization compensation value is continuously and precisely accumulated and adjusted so that the quantization compensation value approaches the desired quantization compensation value. Ultimately, this achieves compensation for the quantization error caused by SDM quantization, improving the stability and accuracy of quantization compensation.

[0104] In one exemplary embodiment, obtaining compensation gain information based on the current quantization compensation information and the phase correction feedback signal includes: using the least mean square algorithm to determine the compensation gain information based on the current quantization compensation information and the phase error signal of the current period.

[0105] The Least Mean Square (LMS) algorithm is an algorithm that uses the mean square error as the cost function and minimizes it through iterative calculations.

[0106] The embodiments of this application can accurately determine the difference in magnitude between the current quantization compensation information and the phase error signal of the current period through the least mean square algorithm, and determine the gain information based on the difference to increase the value of the current quantization compensation information, so as to achieve accurate compensation of the phase error signal.

[0107] Figure 4This is a schematic diagram of a phase jitter compensation module provided in an embodiment of this application. This phase jitter compensation module is suitable for calibrating the duty cycle without adding additional analog circuitry. The phase jitter compensation module is configured in a digital phase-locked loop (PLL), and this embodiment does not limit the type of PLL.

[0108] like Figure 4 As shown, the phase jitter compensation module 100 provided in this application embodiment includes: a duty cycle mismatch detection module 110, an error accumulation module 120, and a calibration compensation module 130. The duty cycle mismatch detection module 110 is connected to the phase comparison module and the error accumulation module 120 in the digital phase-locked loop, respectively. The error accumulation module 120 is connected to the calibration compensation module 130, and the calibration compensation module 130 is connected to the phase tracking module and the phase comparison module in the digital phase-locked loop, respectively.

[0109] The duty cycle mismatch detection module 110 is used to acquire the phase error signal of the digital phase-locked loop in the current cycle and the phase error signal of the adjacent previous cycle, and determine the duty cycle mismatch information based on the phase error signal in the current cycle and the phase error signal of the adjacent previous cycle. The phase error signal includes a digital signal formed by the difference between the phase of the input reference signal and the phase of the feedback signal. The input reference signal is the input reference signal of the digital phase-locked loop, and the feedback signal is the feedback signal transmitted in the feedback loop of the digital phase-locked loop when phase locking occurs. The error accumulation module 120 is used to generate current phase compensation information based on the duty cycle mismatch information. The calibration compensation module 130 is used to correct the phase error signal in the current cycle using the current phase compensation information, and send the corrected phase error signal to the digital phase-locked loop to instruct the digital phase-locked loop to re-track the phase based on the corrected phase error signal.

[0110] The phase jitter compensation module 100 starts operating after the digital phase-locked loop locks the phase error between the feedback signal and the input reference signal. At this point, the phase error between the feedback signal and the input reference signal remains constant; the phase error can be zero or a constant. The compensation process of the phase jitter compensation module 100 is a negative feedback loop. The compensation process continuously accumulates the compensation value, gradually bringing it closer to the desired phase compensation value. By configuring the compensation process of the phase jitter compensation module 100 as a negative feedback loop, the phase error signal can be tracked in real time, the matching compensation value can be determined, and the compensation value can be adjusted accordingly in a timely manner in response to the phase error signal, thus improving the stability of the compensation system.

[0111] The phase error signal acquired by the duty cycle mismatch detection module 110 is sent by the phase comparison module. The phase error sent by the phase comparison module in the digital phase-locked loop is a value quantized by a time-to-digital converter (TDC). Therefore, the phase error signal formed by the phase error changing over time is actually a digital signal. Consequently, the phase error signal processed by the phase jitter compensation module 100 is also a digital signal. Accordingly, the duty cycle mismatch detection module 110 obtains the duty cycle mismatch information based on the phase error signal output by the time-to-digital converter in the phase comparison module of the digital phase-locked loop.

[0112] It should be noted that the periods involved in the phase jitter compensation module 100 disclosed in this application embodiment are all the clock periods of the feedback signal, and the clock drive signals of each module in the phase jitter compensation module 100 are feedback signals.

[0113] The error accumulation module 120 is actually used to gradually accumulate the phase compensation value and determine the phase compensation value of the current period, so that the phase compensation value of the current period continuously approaches the desired phase compensation value.

[0114] The calibration compensation module 130 is used to compensate the phase error signal with the current phase compensation information. For example, it adds or subtracts the compensation value included in the current phase compensation information from the phase error. The corrected phase error signal is used as a phase error to eliminate duty cycle mismatch error and is sent to the phase-locked loop module to instruct the phase-locked loop module to continue the phase tracking process based on the corrected phase error signal. This eliminates duty cycle mismatch error during the phase tracking process of the digital phase-locked loop, ensuring that the output feedback signal corresponds to the ideal input reference signal.

[0115] This application embodiment configures a phase jitter compensation module in a digital phase-locked loop (PLL), acquires the phase error signal in the PLL through a duty cycle mismatch detection module (the phase error signal is a digital signal), compares the phase errors of adjacent cycles to obtain duty cycle mismatch information, determines a compensation value based on the duty cycle mismatch information through an error accumulation module, and continues to accumulate the accumulated phase compensation information over multiple cycles to generate the current phase compensation information, and uses a calibration compensation module to compensate the current phase compensation information into the phase error signal of the current cycle, and sends the corrected phase error signal to the phase tracking module in the PLL to generate a feedback signal that matches the corrected phase error signal. This achieves phase jitter compensation caused by duty cycle mismatch in the feedback signal, solving the problems of low calibration accuracy and large circuit area caused by analog circuits in the prior art for duty cycle calibration. It can overcome the calibration accuracy limitations of analog circuits for duty cycle calibration, improve calibration accuracy, effectively improve calibration reliability, ensure calibration consistency, and reduce calibration circuit area.

[0116] In one exemplary embodiment, the digital phase-locked loop is a frequency-doubled digital phase-locked loop, and the phase error signal includes the difference between the phase of the frequency-doubled input reference signal and the phase of the feedback signal in the frequency-doubled digital phase-locked loop when the phase is locked. The frequency-doubled input reference signal is a signal formed by frequency-doubled processing of the input reference signal of the frequency-doubled digital phase-locked loop.

[0117] Typically, the phase jitter compensation module in this application embodiment is mainly applied in digital phase-locked loops (PLLs) and frequency-doubled PLLs. Furthermore, multiple frequency-doubled PLLs can be stacked to form a 2^n (n is an integer greater than or equal to 2) frequency-doubled PLL. Correspondingly, the phase jitter compensation module can be configured in each frequency-doubled PLL to ensure that each frequency-doubled PLL resolves the phase jitter problem caused by duty cycle mismatch, thereby solving the phase jitter problem for the entire system.

[0118] In one exemplary embodiment, the phase jitter compensation module further includes a control module; the control module is used to control whether the duty cycle mismatch detection module, the error accumulation module and the calibration compensation module are working respectively.

[0119] The control module is used to control whether each module in the phase jitter compensation module is working.

[0120] In practice, the phase jitter compensation module operates independently of other modules in the digital phase-locked loop (PLL). Its operation can be manually or automatically controlled to start and / or stop. For example, if the phase jitter error is minimal or nonexistent, the phase jitter module can be stopped to reduce the PLL's power consumption.

[0121] When the digital phase-locked loop (PLL) is not locked in phase, the feedback signal is unstable, resulting in inaccurate phase errors. Consequently, the phase compensation value determined based on these inaccurate phase errors deviates significantly from the desired value, increasing the difficulty of phase compensation. Therefore, regardless of whether the control is automatic or manual, the phase jitter compensation module must begin operating after the PLL has locked in phase. That is, the phase jitter compensation module only starts working after the output signal of the PLL is stably synchronized with the input reference signal.

[0122] By controlling whether the phase jitter compensation module is working, the phase jitter compensation module can be controlled independently. Phase jitter compensation can be selected to be activated or not as needed, which improves the flexibility of phase jitter compensation and reduces the power consumption of the digital phase-locked loop.

[0123] In one exemplary implementation Figure 5This is a schematic diagram of a phase jitter compensation module provided in an embodiment of this application. This embodiment is a specific modification of the above embodiment. In this embodiment, the error accumulation module includes: an attenuation module and an accumulation module. Correspondingly, as... Figure 5 As shown, the error accumulation module 120 of this embodiment includes: an attenuation module 121 and an accumulation module 122. The attenuation module 121 is connected to the accumulation module 122 and the duty cycle mismatch detection module 110, respectively, and the accumulation module 122 is connected to the calibration compensation module 130. The attenuation module 121 is used to attenuate the data in the duty cycle mismatch information. The accumulation module 122 is used to calculate the accumulation result of the attenuated data and the data in the accumulated phase compensation information, and determine it as the current phase compensation information. The current phase compensation information is used as the new accumulated phase compensation information.

[0124] This application embodiment configures an attenuation module and an accumulation module to continuously and precisely accumulate and adjust the phase compensation value so that the phase compensation value approaches the desired phase compensation value, ultimately compensating for phase jitter caused by duty cycle mismatch and improving the stability and accuracy of phase jitter compensation.

[0125] In one exemplary implementation Figure 6 This is a schematic diagram of a phase jitter compensation module provided in an embodiment of this application. This embodiment is a specific modification based on the above embodiment. In this embodiment, the error accumulation module includes: an odd / even period detection module; an attenuation module including a first direction correction module and an attenuator; and an accumulation module including an accumulator and a second direction correction module. In this embodiment, the digital phase-locked loop is a double-digital phase-locked loop, and the input reference signal is a signal formed by doubling the frequency of an external input reference signal.

[0126] Correspondingly, such as Figure 6 As shown, the error accumulation module 120 of this embodiment includes: an odd-even period detection module 123, an attenuation module 121 including a first direction correction module 124 and an attenuator 125, and an accumulation module 122 including an accumulator 126 and a second direction correction module 127. The odd-even period detection module 123 is connected to the first direction correction module 124 and the second direction correction module 127 respectively, and the first direction correction module 124, the attenuator 125, the accumulator 126 and the second direction correction module 127 are connected in series.

[0127] The parity period detection module 123 is used to sample the input reference signal using the falling edge of the feedback signal, and determine the parity information of the current period based on the level of the sampled input reference signal point, wherein the level of the input reference signal point in the odd period is low and the level of the input reference signal point in the even period is high; the first direction correction module 124 is used to correct the sign of the data in the duty cycle mismatch information according to the parity information of the current period and the preset correspondence between parity information and sign; the attenuator 125 is used to attenuate the data in the corrected duty cycle mismatch information; the accumulator 126 is used to calculate the accumulation result of the attenuated data and the data in the accumulated phase compensation information; the second direction correction module 127 is used to correct the sign of the accumulation result according to the parity information of the current period and the preset correspondence between parity information and sign, and determine the corrected accumulation result as the current phase compensation information.

[0128] The odd / even cycle detection module 123 is used to detect the odd / even information of the current cycle. The odd / even information of the current cycle is used to determine the direction of adjustment for the phase compensation value and the direction of compensation for the phase difference information of the current cycle.

[0129] The first direction correction module 124 is used to correct the sign of the data in the duty cycle mismatch information. In fact, the value of the data in the duty cycle mismatch information is an absolute value. The first direction correction module 124 is used to add a sign to the data in the duty cycle mismatch information.

[0130] Attenuator 125 is used to reduce the value of the data in the corrected duty cycle mismatch information.

[0131] Accumulator 126 is used to calculate the sum of the attenuated data and the data in the accumulated phase compensation information.

[0132] The second direction correction module 127 is used to correct the sign of the accumulation result according to the parity information of the current period and the preset correspondence between parity information and sign, and to determine the corrected accumulation result as the current phase compensation information.

[0133] In reality, the phase jitter compensation module cannot accurately obtain the desired phase compensation value. It can only obtain the phase compensation value through the known phase error signal and continuously accumulate it until the desired phase compensation value is converged. The first direction correction module 124 and the second direction correction module 127 can accurately and continuously adjust the phase compensation value by increasing or decreasing it, so as to accurately converge the phase compensation value for phase jitter caused by duty cycle mismatch.

[0134] In a specific example, the digital phase-locked loop is a frequency-doubled digital phase-locked loop, such as... Figure 6 As shown, the phase jitter compensation module 100 includes: a duty cycle mismatch detection module 110, an error accumulation module 120, a calibration compensation module 130, and a control module 140. The error accumulation module 120 includes: an attenuation module 121, an accumulation module 122, and an odd / even period detection module 123. The attenuation module 121 includes a first direction correction module 124 and an attenuator 125. The accumulation module 122 includes an accumulator 126 and a second direction correction module 127.

[0135] like Figure 7 As shown, the parity period detection module 123 includes a sampler based on a Class D flip-flop (DFF) or other forms, where the sampling clock is the feedback signal of a digital phase-locked loop, and the input data is the input reference signal before frequency multiplication. The sampler uses the falling edge of the feedback signal to sample the input reference signal before frequency multiplication, and the output C1 of the parity period detection module 123 determines the parity information of the current period. When the sampler output value C1 is 1, it indicates that the current true second harmonic input reference signal is in an even period; when the module output value C1 is 0, it indicates that the current true second harmonic input reference signal is in an odd period.

[0136] like Figure 8 As shown, the duty cycle mismatch detection module 110 includes a delay unit and a subtractor. The delay unit delays the phase error signal by one cycle of the feedback signal, forming a signal D1. D1 and the phase error signal are input to the subtractor for processing to obtain the difference D2 between the phase error signal and the phase error signal of the adjacent previous cycle, which is determined as the duty cycle mismatch information.

[0137] like Figure 9 As shown, the first direction correction module 124 includes an inversion unit and a multiplexer. The inversion unit is used to invert the data D2, and the multiplexer is used to select whether to output the original data or the inverted data. The first direction correction module 124 controls whether to invert D2 based on C1 output by the odd / even period detection module 123. When the actual second harmonic input reference signal is in an odd period, i.e., C1 is 0, then D2 is not inverted, and D4 equals D2; when the actual second harmonic input reference signal is in an even period, i.e., C1 is 1, then D2 is inverted, and D4 equals D3, i.e., -D2.

[0138] like Figure 10As shown, attenuator 125 can be a proportional attenuator to attenuate D4 to obtain D5. Specifically, this attenuation operation can be accomplished through multiplication, that is, D4 is multiplied by a configured value greater than and less than 1, such as D5 = D4 * λ. However, in digital circuits, right shifting of the register is the most effective method for attenuating data. Assuming the configured right shift is s, then D5 = D4 / 2^s. Accumulator 126 continuously accumulates D5 under the clock drive of the feedback signal. After calibration, D6 will converge to a stable value.

[0139] like Figure 11 As shown, the second direction correction module 127 includes an inverting unit and a multiplexer. The inverting unit is used to invert the data D6, and the multiplexer is used to select whether to output the original data or the inverted data. The second direction correction module 127 controls whether to invert D6 based on C1 output by the odd / even period detection module 123. When the actual second harmonic input reference signal is in an odd period, i.e., C1 is 0, D6 is not inverted, and D8 equals D6; when the actual second harmonic input reference signal is in an even period, i.e., C1 is 1, D8 is inverted, and D8 equals D7, i.e., -D6.

[0140] This application embodiment configures an even / odd period detection module to detect the odd / odd information of the actual second harmonic input reference signal period. Based on the odd / odd information, signs are added to the data in the duty cycle mismatch information and the accumulated results to increase or decrease the adjustment phase compensation value, continuously approaching the desired phase compensation value until it converges to the desired phase compensation value. Ultimately, this achieves compensation for phase jitter caused by duty cycle mismatch, improving the stability and accuracy of phase jitter compensation.

[0141] In one exemplary implementation Figure 12 This is a schematic diagram of a phase jitter compensation module provided in an embodiment of this application. This embodiment is a specific modification of the above embodiment. In this embodiment, the calibration compensation module includes: a frequency division control information compensation module, a trigonometric integral modulator, and a quantization error compensation module. The digital phase-locked loop is a double-digit digital phase-locked loop, and the input reference signal is an external input reference signal that has undergone frequency doubling processing.

[0142] Correspondingly, such as Figure 12 As shown, the calibration compensation module 130 of this embodiment includes: a frequency division control information compensation module 131, a trigonometric integral modulator 132, and a quantization error compensation module 133. The frequency division control information compensation module 131 is connected to the error accumulation module 120, the trigonometric integral modulator 132 is connected to the quantization error compensation module 133 and the phase tracking module, and the quantization error compensation module 133 is connected to the phase comparison module and the phase tracking module.

[0143] The frequency division control information compensation module 131 is used to compensate the preset frequency division control information using the current phase compensation information to generate corrected frequency division control information; the triangular integral modulator 132 is used to quantize the corrected frequency division control information to obtain quantized frequency division control information, which is used to instruct the digital phase-locked loop to generate a feedback signal based on the quantized frequency division control information; the quantization compensation module 133 is used to determine quantization compensation information based on the corrected frequency division control information and the quantized frequency division control information; the quantization compensation information is used to correct the phase error signal of the current period, and the corrected phase error signal is sent to the phase tracking module.

[0144] The frequency division control information compensation module 131 is used to add current phase compensation information to the frequency division control information, and introduce phase jitter compensation into the frequency division control information. This can reduce the phase jitter error caused by duty cycle mismatch in the quantized frequency division control information output by the triangular integral modulator 132.

[0145] Frequency division control information can be a frequency control word (FCW). The corrected frequency division control information can refer to the frequency division control information after being compensated by the current phase compensation information, that is, the corrected frequency division control information reduces the phase jitter error introduced by duty cycle mismatch.

[0146] The triangular integral modulator 132 is used to quantize the frequency division control information. For example, the triangular integral modulator 132 is an n-order SDM.

[0147] The quantization compensation module 133 is used to calculate the quantization error of the trigonometric integral modulator 132, superimpose the current phase compensation information to generate quantization compensation information, and use the quantization compensation information to compensate the phase error signal of the current period.

[0148] Current phase compensation information is added to the input of the trigonometric integral modulator 132, so that the quantized frequency division control information output by the trigonometric integral modulator 132 also contains current phase compensation information. Simultaneously, since both the frequency division control information before and after quantization contain current phase compensation information, the quantization error determined based on the frequency division control information before and after quantization contains current phase compensation information. Therefore, the quantization compensation information determined for the quantization error also includes current phase compensation information.

[0149] This application embodiment adds current phase compensation information to the input frequency division control information of the trigonometric integral modulator and obtains the frequency division control information of the trigonometric integral modulator before and after quantization to determine the quantization compensation information of the trigonometric integral modulator. Since the frequency division control information before and after quantization includes the current phase compensation information, the current phase compensation information is introduced into the quantization compensation information. Therefore, the phase error signal is compensated according to the quantization compensation information, and the error introduced by duty cycle mismatch and the quantization error introduced by the trigonometric integral modulator are also compensated, thereby improving the phase-locked loop accuracy and reducing the system error of the digital phase-locked loop.

[0150] In one exemplary implementation, such as Figure 13 As shown, the quantization compensation module 133 includes: a quantization residual calculation module 134, a calibration source calculation module 135, a compensation gain calculation module 136, and a quantization correction module 137. The quantization residual calculation module 134 is connected to the frequency division control information compensation module 131 and the trigonometric integral modulator 132, respectively. The quantization correction module 137 is connected to the phase tracking module. The quantization residual calculation module 134, the calibration source calculation module 135, the compensation gain calculation module 136, and the quantization correction module 137 are connected in series. The calibration source calculation module 135 is connected to the quantization correction module 137. The frequency division control information is a frequency control word.

[0151] The quantization residual calculation module 134 is used to obtain the corrected frequency control word and the quantized frequency control word, and calculate the quantization error information of the trigonometric integral modulator 132; the calibration source calculation module 135 is used to accumulate the cumulative quantization compensation information according to the quantization error information, generate the current quantization compensation information, and use the current quantization compensation information as the new cumulative quantization compensation information; the compensation gain calculation module 136 is used to obtain the compensation gain information according to the current quantization compensation information and the phase correction feedback signal; the quantization correction module 137 is used to calculate the product of the data in the compensation gain information and the data in the current quantization compensation information as the quantization compensation information, use the quantization compensation information to correct the phase error, generate the corrected phase error signal, and send it to the phase tracking module.

[0152] The quantization compensation module 133 includes a negative feedback loop. The corrected phase error signal output by the quantization compensation module 133 is used as a new phase correction feedback signal and fed back to the compensation gain calculation module 136 to calculate the compensation gain information.

[0153] This application embodiment, by configuring a quantization residual calculation module, a calibration source calculation module, a compensation gain calculation module, and a quantization correction module, can accurately calculate the quantization error and determine the quantization compensation value based on the quantization error. At the same time, it continuously and precisely accumulates and adjusts the quantization compensation value to make the quantization compensation value approach the desired quantization compensation value, ultimately compensating for the quantization error caused by SDM quantization and improving the stability and accuracy of quantization compensation.

[0154] In one exemplary implementation, such as Figure 14 As shown, the compensation gain calculation module 136 includes: a minimum root mean square (RMS) calculation module 138; the minimum root mean square (RMS) calculation module 138 is used to determine the compensation gain information based on the current quantization compensation information and the phase error signal of the current period using the minimum root mean square (RMS) algorithm.

[0155] The Least Mean Square (LMS) algorithm is an algorithm that uses the mean square error as the cost function and minimizes it through iterative calculations.

[0156] The embodiments of this application can accurately determine the difference in magnitude between the current quantization compensation information and the phase error signal of the current period through the least mean square algorithm, and determine the gain information based on the difference to increase the value of the current quantization compensation information, so as to achieve accurate compensation of the phase error signal.

[0157] In a specific example, such as Figure 14 As shown, the digital phase-locked loop is a frequency-doubled digital phase-locked loop. The calibration and compensation module 130 includes: a frequency division control information compensation module 131, a trigonometric integral modulator 132, and a quantization error compensation module 133; the quantization compensation module 133 includes: a quantization residual calculation module 134, a calibration source calculation module 135, a compensation gain calculation module 136, and a quantization correction module 137; the compensation gain calculation module 136 includes: a minimum root mean square calculation module 138.

[0158] The frequency division control information compensation module 131 includes an adder for adding the frequency control word to the current phase compensation information D8 to obtain D9, and then using D9 as the frequency control word of the digital phase-locked loop.

[0159] The trigonometric modulator 132 quantizes D9 to obtain D10 by being driven by the clock of the feedback signal.

[0160] The quantization residual calculation module 134 includes a subtractor for calculating the difference between D9 and D10 to obtain D11, which is actually the quantization residual of the trigonometric integral modulator 132.

[0161] The calibration source calculation module 135 includes an accumulator that accumulates the quantization residuals D11 over multiple periods to obtain the calibration source D12.

[0162] The quantization correction module 137 includes a multiplier and a subtractor. The multiplier calculates the product of the calibration source D12 and the calibration gain D16, which is used as the calibration value D13. The subtractor obtains the calibration value D13 output by the multiplier and subtracts it from the phase error of the current cycle to determine the corrected phase error. Since the phase error of the current cycle and the calibration value D13 have the same jitter amplitude and jitter direction, the obtained corrected phase error will be a relatively stable data sequence.

[0163] The compensation gain calculation module 136 includes a least mean square (LMS) calculation module 138, which comprises a multiplier, an accumulator, and an attenuator. The multiplier, accumulator, and attenuator are calculated based on the LMS method. Specifically, the multiplier multiplies the calibration source D12 and the phase error to obtain the gain error D14. The accumulator accumulates the gain errors D14 over multiple cycles to obtain D15. The attenuator reduces the value of D15, which can be achieved through multiplication or right shift operations. The attenuator appropriately attenuates D15 to obtain a relatively stable calibration gain value D16.

[0164] It should be noted that the control module in the aforementioned phase jitter compensation module can also control whether the various modules in the calibration compensation module are working. If at least one of the quantization residual calculation module 134, calibration source calculation module 135, compensation gain calculation module 136, and quantization correction module 137 is not working, the current phase error signal directly corrects the phase error signal of the current period, achieving compensation only for the phase jitter error introduced by duty cycle mismatch. This allows duty cycle mismatch compensation and SDM quantization error compensation to be independent of each other.

[0165] This application provides a digital phase-locked loop. Figure 15 This is a schematic diagram of a digital phase-locked loop provided in this application. The digital phase-locked loop 200 provided in this application includes: a phase comparison module 210, a phase jitter compensation module 100 as described in any one of the embodiments of this application, and a phase tracking module 220.

[0166] The phase comparison module 210 and the phase tracking module 220 are configured to: acquire the input reference signal and the feedback signal sent by the phase tracking module 220; compare the phase of the input reference signal and the feedback signal to generate a phase error signal; and send the phase error signal to the phase jitter compensation module 100. The phase jitter compensation module 100 is configured to correct the phase error signal and send the corrected phase error signal to the phase tracking module 220. The phase tracking module 220 is configured to generate a feedback signal based on the corrected phase error signal and send it to the phase comparison module 210. The feedback signal is used to instruct the phase comparison module 210 to continuously adjust the phase error signal until the data in the phase error signal is constant.

[0167] The feedback signal can be the same as or different from the output signal.

[0168] When the phase jitter compensation module 100 is not working, its compensation value is 0, and the phase error signal output by the phase comparison module 210 is the same as the corrected phase error signal output by the phase jitter compensation module 100. At this time, the phase comparison module 210 and the phase tracking module 220 work together to synchronize the output signal with the input reference signal, i.e., phase locking. Furthermore, frequency synchronization can also be achieved. The input reference signal is the input signal sent from an external device to the digital phase-locked loop.

[0169] After the digital phase-locked loop (PLL) phase is locked, the phase jitter compensation module 100 starts working to compensate for the phase jitter error introduced by the duty cycle mismatch in the output signal and feedback signal of the PLL.

[0170] Currently, typical duty cycle calibration circuits directly adjust the rising or falling edges of the reference clock outside the loop, adjusting the clock duty cycle to an ideal state before it is sent to the phase-locked loop. Because this directly processes the clock duty cycle, an improper design can degrade the reference clock performance, leading to additive jitter. In contrast, the phase jitter module in this embodiment is configured inside the digital phase-locked loop to compensate for non-idealities caused by duty cycle mismatch.

[0171] In one exemplary implementation, such as Figure 16As shown, the phase comparison module 210 includes: a frequency multiplier 211, a phase detector 212, and a time-to-digital converter 213. The frequency multiplier 211 is connected to the phase detector 212, the phase detector 212 is connected to the time-to-digital converter 213, and the phase detector 212 is connected to the phase tracking module 220. The frequency multiplier 211 is used to perform frequency doubling processing on the input reference signal and send the frequency-doubled reference signal to the phase detector 212. The phase detector 212 is used to acquire the frequency-doubled reference signal and the feedback signal sent by the phase tracking module 220, perform phase comparison, acquire the analog signal of the current period, and send it to the time-to-digital converter 213. The time-to-digital converter 213 is used to perform analog-to-digital conversion on the analog signal and send the generated phase error signal to the phase jitter compensation module.

[0172] In one exemplary implementation, such as Figure 16 As shown, the phase tracking module 220 includes: a filter 221, an oscillator 222, and a frequency divider 223. The filter 221 is connected to both the oscillator 222 and the phase jitter compensation module 100. The filter 221 is used to filter the corrected phase error signal and send it to the oscillator 222. The oscillator 222 is connected to the frequency divider 223. The oscillator 222 is used to generate an output signal based on the filtered phase error signal and send the output signal to the frequency divider 223. The frequency divider 223 is connected to the phase comparison module. The frequency divider 223 is used to perform frequency division processing on the output signal based on the quantized frequency division control information, generate a feedback signal, and send it to the phase comparison module 210. The quantized frequency division control information includes data obtained by quantizing the corrected frequency division control information using a trigonometric integral modulator. The corrected frequency division control information is obtained by correcting the preset frequency division control information using the current phase compensation information.

[0173] The trigonometric integrator is configured in the phase jitter compensation module 100. The time-to-digital converter 213 is used to convert analog signals into digital signals.

[0174] In a specific example, the digital phase-locked loop is enabled by frequency doubling. The simulation sets the duty cycle mismatch of the input reference signal to 1%, the clock frequency of the reference source input reference signal to 61.44MHz, the integer division ratio to 19, and the fractional division ratio to 0.1.

[0175] Figure 17 The diagram shows the output jitter of the phase error signal (PHE, Phase Error) from the phase jitter compensation module and the phase error signal (PHE_pre) from the phase comparison module when the phase jitter compensation module stops working. Since the calibration value D13 is 0, the PHE_pre waveform is consistent with the PHE waveform. Large fluctuations on PHE will be converted into in-band noise and spurious signals at the reference frequency by the numerically controlled oscillator.

[0176] Figure 18 The image shows the output jitter of PHE_pre and PHE after the SDM quantization noise calibration correlation module in the phase jitter compensation module is working. At this point, the jitter introduced by SDM quantization is effectively suppressed. However, PHE still exhibits jitter caused by reference duty cycle mismatch.

[0177] Figure 19 The image shows the output jitter of PHE_pre and PHE after the phase jitter compensation module starts working. Because the calibration value D13 tracks PHE_pre in real time, the jitter of PHE_pre is effectively suppressed, and the PHE waveform is very stable. The jitter of PHE_pre includes not only the jitter introduced by duty cycle mismatch but also the jitter caused by SDM quantization residuals.

[0178] For example, the digital phase-locked loop is enabled by frequency doubling. The simulation sets the duty cycle mismatch of the input reference signal to 1%, the clock frequency of the reference source input reference signal to 61.44MHz, the integer division ratio to 19, and the fractional division ratio to 0.

[0179] Figure 20 The image shows the output jitter of PHE_pre and PHE when the phase jitter compensation module stops working. Since the calibration value D13 is 0, the waveforms of PHE and PHE_pre are consistent. Large fluctuations on PHE will be converted into in-band noise and spurious signals at the reference frequency by the digitally controlled oscillator.

[0180] Figure 21 The image shows the output jitter of PHE_pre and PHE after the phase jitter compensation module starts working. Because the calibration value D13 tracks PHE_pre in real time, the jitter of PHE_pre is fully suppressed, and the PHE waveform is very stable.

[0181] For example, the digital phase-locked loop is enabled by frequency doubling. The simulation sets the duty cycle mismatch of the input reference signal to 0%, the clock frequency of the reference source input reference signal to 61.44MHz, the integer division ratio to 19, and the fractional division ratio to 0.1.

[0182] Figure 22 The image shows the output jitter of PHE_pre and PHE when the phase jitter compensation module stops working. Since the reference duty cycle mismatch is 0, the jitter of PHE at this time is mainly introduced by the SDM quantization residual.

[0183] Figure 23The diagram shows the operation of the SDM quantization noise calibration associated module in the phase jitter compensation module, and the output jitter of PHE_pre and PHE after the phase jitter compensation module starts working. Because the calibration value D13 tracks PHE_pre in real time, the jitter of PHE_pre will be fully suppressed, and the PHE waveform is very stable.

[0184] This invention, through the configuration of a phase jitter compensation module in a digital phase-locked loop (PLL), utilizes a fully digital approach to calibrate duty cycle mismatch. This improves calibration accuracy and reduces the chip area occupied by the PLL. Furthermore, the phase jitter compensation module tracks the phase error signal for duty cycle mismatch calibration, eliminating the need to handle the rising or falling edges of the input reference signal and thus avoiding additive jitter. Additionally, the duty cycle mismatch calibration within the phase jitter module can work in conjunction with the quantization noise calibration of the triangular integral modulator in the frequency divider, suppressing phase jitter at the PLL phase detector output, improving the phase locking accuracy of the PLL, and enhancing the overall system stability of the PLL.

[0185] It is worth noting that in the above embodiments applied to the phase jitter compensation module and digital phase-locked loop, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of this application.

[0186] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0187] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0188] Embodiments of this application can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0189] Any block diagram of logical flow in the accompanying drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored in memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Multifunction Discs, DVDs, or CDs), etc. Computer-readable media may include non-transitory storage media. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (FGPAs), and processors based on multi-core processor architectures.

[0190] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of this application. Therefore, the proper scope of this application will be determined by the claims.

Claims

1. A phase jitter compensation method, characterized by, The application is applied to a digital phase-locked loop, and comprises the following steps: obtaining a phase error signal of the digital phase-locked loop in a current period and a phase error signal of an adjacent previous period, and determining a duty cycle mismatch information according to the phase error signal in the current period and the phase error signal of the adjacent previous period, wherein the phase error signal comprises a digital signal formed by a difference between an input reference signal phase and a feedback signal phase, the input reference signal is an input reference signal of the digital phase-locked loop, the feedback signal is a feedback signal transmitted in a feedback loop of the digital phase-locked loop when the phase is locked, and the duty cycle mismatch information is represented by a difference between the phase error signal in the current period and the phase error signal of the adjacent previous period; generating current phase compensation information according to the duty cycle mismatch information; modifying the phase error signal in the current period by using the current phase compensation information, and sending the modified phase error signal to the digital phase-locked loop to instruct the digital phase-locked loop to re-track the phase according to the modified phase error signal.

2. The phase jitter compensation method of claim 1, wherein, The modification of the phase error signal in the current period by using the current phase compensation information comprises the following steps: compensating preset frequency division control information by using the current phase compensation information to generate modified frequency division control information; quantizing the modified frequency division control information to obtain quantized frequency division control information, wherein the quantized frequency division control information is used to instruct the digital phase-locked loop to generate a feedback signal according to the quantized frequency division control information; determining quantization compensation information according to the modified frequency division control information and the quantized frequency division control information; modifying the phase error signal in the current period by using the quantization compensation information.

3. The phase jitter compensation method of claim 1, wherein, The generation of the current phase compensation information according to the duty cycle mismatch information comprises the following steps: attenuating data in the duty cycle mismatch information; calculating an accumulated result of the attenuated data and data in accumulated phase compensation information to determine the current phase compensation information; taking the current phase compensation information as new accumulated phase compensation information.

4. The phase jitter compensation method of claim 3, wherein, Before the attenuation of the data in the duty cycle mismatch information, the following steps are further included: sampling the input reference signal by using a falling edge of the feedback signal, and determining current period parity information according to a level of a sampling input reference signal point, wherein the level of the input reference signal point in an odd period is a low level, and the level of the input reference signal point in an even period is a high level; modifying a sign of the data in the duty cycle mismatch information according to the current period parity information and a preset correspondence between parity information and sign positive and negative; The attenuation of the data in the duty cycle mismatch information comprises the following steps: attenuating the data in the modified duty cycle mismatch information; The calculation of the accumulated result of the attenuated data and the data in the accumulated phase compensation information to determine the current phase compensation information comprises the following steps: calculating the accumulated result of the attenuated data and the data in the accumulated phase compensation information. According to the current cycle parity information and the preset parity information and symbol positive and negative corresponding relationship, the sign of the accumulated result is corrected, and the corrected accumulated result is determined as the current phase compensation information.

5. The phase jitter compensation method of claim 2, wherein, The frequency division control information is a frequency control word; The method comprises the following steps: The modified frequency control word and the quantized frequency control word are obtained, and the quantization error information is calculated; According to the quantization error information, the accumulated quantization compensation information is accumulated to generate current quantization compensation information; The current quantization compensation information is used as new accumulated quantization compensation information; According to the current quantization compensation information and the phase correction feedback signal, compensation gain information is obtained; The product of the data in the compensation gain information and the data in the current quantization compensation information is calculated as quantization compensation information.

6. The phase jitter compensation method of claim 5, wherein, The method comprises the following steps: The least mean square algorithm is used to determine the compensation gain information according to the current quantization compensation information and the phase error signal of the current cycle.

7. The phase jitter compensation method of claim 1, wherein, The digital phase-locked loop is a frequency doubling digital phase-locked loop, and the phase error signal comprises a digital signal formed by the difference between the phase of a frequency doubling input reference signal and the phase of a feedback signal in the frequency doubling digital phase-locked loop when the phase is locked.

8. A phase jitter compensation module, characterized by, The digital phase-locked loop is configured in a digital phase-locked loop, comprising: The duty cycle mismatch detection module is configured to obtain the phase error signal of the digital phase-locked loop in the current cycle and the phase error signal of the adjacent previous cycle, and determine the duty cycle mismatch information according to the phase error signal in the current cycle and the phase error signal of the adjacent previous cycle, wherein the phase error signal comprises a digital signal formed by the difference between the phase of an input reference signal and the phase of a feedback signal, the input reference signal is the input reference signal of the digital phase-locked loop, the feedback signal is the feedback signal transmitted in the feedback loop of the digital phase-locked loop when the phase is locked, and the duty cycle mismatch information is represented by the difference between the phase error signal in the current cycle and the phase error signal of the adjacent previous cycle. The error accumulation module is configured to generate current phase compensation information according to the duty cycle mismatch information. The calibration compensation module is configured to correct the phase error signal in the current cycle using the current phase compensation information, and send the corrected phase error signal to the digital phase-locked loop to instruct the digital phase-locked loop to re-perform phase tracking according to the corrected phase error signal.

9. The phase jitter compensation module of claim 8, wherein, The calibration compensation module comprises a frequency division control information compensation module, a triangular integral modulator and a quantization error compensation module, wherein the frequency division control information compensation module is connected with the error accumulation module, the triangular integral modulator and the quantization error compensation module, and the quantization error compensation module is connected with the phase tracking module. The frequency division control information compensation module is configured to compensate preset frequency division control information by using the current phase compensation information, and generate modified frequency division control information. The triangular integration modulator is configured to quantize the modified frequency division control information, and obtain quantized frequency division control information, where the quantized frequency division control information is used to instruct the digital phase-locked loop to generate a feedback signal according to the quantized frequency division control information. The quantization error compensation module is configured to determine quantization compensation information according to the modified frequency division control information and the quantized frequency division control information, and modify the phase error signal of the current period by using the quantization compensation information.

10. The phase jitter compensation module of claim 8, wherein, Further comprising: a control module; The control module is configured to control whether the duty cycle mismatch detection module, the error accumulation module and the calibration compensation module work respectively.

11. A digital phase locked loop, characterized by Comprising: a phase comparison module, a phase jitter compensation module as claimed in any one of claims 8-10, and a phase tracking module; The phase comparison module is connected to the phase tracking module, and is configured to obtain an input reference signal and a feedback signal sent by the phase tracking module, and perform phase comparison on the input reference signal and the feedback signal to generate a phase error signal, and send the phase error signal to the phase jitter compensation module; The phase jitter compensation module is configured to modify the phase error signal, and send the modified phase error signal to the phase tracking module; The phase tracking module is configured to generate a feedback signal according to the modified phase error signal, and send the feedback signal to the phase comparison module, where the feedback signal is used to instruct the phase comparison module to continuously adjust the phase error signal until the data in the phase error signal is constant.

12. The digital phase locked loop of claim 11, wherein, The phase comparison module comprises a frequency multiplier, a phase detector and a time-to-digital converter, the frequency multiplier is connected to the phase detector, the phase detector is connected to the digital converter, and the phase detector is connected to the phase tracking module; The frequency multiplier is configured to perform frequency doubling on the input reference signal, and send a frequency-doubled reference signal to the phase detector; The phase detector is configured to obtain the frequency-doubled reference signal and a feedback signal sent by the phase tracking module, and perform phase comparison to obtain an analog signal of a current period, and send the analog signal to the time-to-digital converter; The time-to-digital converter is configured to perform analog-to-digital conversion on the analog signal, and send a generated phase error signal to the phase jitter compensation module.

13. The digital phase locked loop of claim 12, wherein, The phase tracking module comprises a filter, an oscillator and a frequency divider; The filter is connected to the oscillator and the phase jitter compensation module respectively, and is configured to filter the modified phase error signal, and send the filtered phase error signal to the oscillator; The oscillator is connected to the frequency divider, and is configured to generate an output signal according to the filtered phase error signal, and send the output signal to the frequency divider; The frequency divider is connected with the phase comparison module, and is configured to perform frequency division processing on the output signal according to quantized frequency division control information to generate a feedback signal and send the feedback signal to the phase comparison module, wherein the quantized frequency division control information comprises data obtained by performing quantization processing on the modified frequency division control information by the triangular integral modulator, and the modified frequency division control information is obtained by modifying preset frequency division control information by using current phase compensation information.

Images