Cadence High Linearity Laser Array Chip Test System

Abstract

The invention belongs to the field of high-linear laser array chip testing. The detection equipment of the high-linear laser array chip is large in size, requires a lot of investment, is time-consuming, cannot be continuously measured, has a low degree of automation, and hardware detection also requires a large number of representative samples for chemical analysis modeling, which is impractical for testing small batches of chips. The invention uses Cadence software, introduces power supply voltage, differential input voltage, reference current, temperature compensation modulation resistor, bias current, laser modulation current, loop failure alarm signal, automatic power control grounding module, and builds a set of convenient, fast, intuitively displayed, and relatively complete intelligent testing system to complete various performance tests of the high-linear laser array chip. The invention does not require any hardware equipment and can verify whether various performances of the high-linear laser array chip meet the standards.

Description

Technical Field

[0001] The invention relates to the field of high linearity laser array chip testing, in particular to a semiconductor laser performance testing system. Background Art

[0002] The application of high-linear laser array chips has become the core technology of today's electronic science. For the measurement of some specific parameters, some domestic research institutions and production units currently generally use some equipment such as optical power meters, drive current sources, spectrum analyzers, network testers, etc. These devices are large in size, require a lot of investment, are time-consuming, cannot measure continuously, and have a low degree of automation. In addition, hardware testing also requires a large number of representative samples for chemical analysis modeling, which is impractical for small batch chip testing. When using hardware equipment, the model needs to be constantly updated. When the instrument changes or the chip changes, the model also needs to change. In the process of hardware testing, it is also susceptible to external factors such as optical system parameters, and curve nonlinearity problems often occur, which has a great impact on the accuracy of the test results. Summary of the invention

[0003] In view of the deficiencies in the prior art, the present invention provides a testing system based on Cadence high linear laser array chips. The present invention is mainly used to measure the performance indicators of high linear laser array chips.

[0004] The technical solution adopted by the present invention is:

[0005] A test system based on a Cadence high linear laser array chip. The test system is built by Cadence and includes a differential input voltage port, an enable voltage signal port, a reference input current port, a bias current input port, an LD modulation current output port, a loop failure alarm signal port, an overcurrent alarm signal port and a ground port.

[0006] Furthermore, the input voltage port voltage of the test system is adjusted to 3.3V, the enable terminal is connected to a high level, and the non-enable terminal is connected to a low level.

[0007] Furthermore, the test system selects different temperatures for transient simulation, and observes the modulated current output at the output end after stabilization for a period of time to verify the operating temperature range; the differential input voltage amplitude is changed according to the relationship between the threshold current and temperature, and the transient simulation output results are observed. The relationship between the threshold current and temperature is as follows:

[0008]

[0009] In the formula, T r） is room temperature, J th ( T)and J th ( T r) are a certain temperature T and room temperature respectively T r The threshold current density measured under ; T0 is a parameter fitted by experiment;

[0010] Change the power supply voltage range, observe the transient simulation output results, and verify whether the threshold current of the laser chip meets the standard.

[0011] Furthermore, the test system verifies whether the central wavelength, output power, side mode suppression ratio, and -20dB spectral width of the high linear laser array chip have met the standards by the following method: a temperature DC scanning method is used to observe the changes in the temperature compensation starting point and the temperature compensation coefficient under different temperature compensation resistance values ​​and temperature compensation coefficient resistance values, thereby verifying the temperature compensation range and the temperature compensation coefficient range to determine whether the central wavelength, output power, side mode suppression ratio, and -20dB spectral width of the laser array chip have met the standards.

[0012] Furthermore, the test system was subjected to AC simulation at three temperature points (-40, 27, 90) to observe whether the filtering results were correct; three voltage points (-0.3, 1.0, 1.8v) with a supply voltage (Vcc) in the range of -0.3-1.8V were selected to perform DC simulation to observe whether normal filtering could be achieved.

[0013] Furthermore, the method for the test system to verify whether the CSO and CTB of the high linear laser array chip have met the standards is as follows: a DC simulation test is performed at the external pin port of the input reference current end, and the input current is verified by observing whether the current at the test point is 4.5mA. This can complete the verification of whether the composite second-order distortion (CSO) and composite third-order beat (CTB) performance of the high linear laser array chip meet the standards.

[0014] In summary, the invention has the following beneficial effects:

[0015] In view of the disadvantages of hardware testing, the present invention adopts Cadence software to build a performance testing system, which can verify whether the performance of the high linear laser array chip meets the standards without any hardware equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Test system built on Cadence;

[0017] Figure 2 Principle block diagram of high linear laser array chip performance test system;

[0018] Figure 3 Flowchart of high linear laser array chip performance test system. DETAILED DESCRIPTION

[0019] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0020] like Figures 1 to 3 As shown, the present invention discloses a test system for high linear laser array chips based on Cadence software. The chips and ports are placed one by one in the Cadence component library, specifically including the following steps:

[0021] S1. Use the component library provided by Cadence software to build a high linear laser array chip test system. The composition and connection methods of the components included in the system, such as Figure 1 shown.

[0022] A test system was built in the Cadence software, with the input terminal connected to the power supply voltage, differential input voltage, reference current, temperature compensation modulation resistor, bias current adjustment input, the output terminal connected to the laser modulation current output, loop failure alarm signal output terminal, and automatic power control grounding.

[0023] S2. After connecting the components, adjust the input power supply voltage to 3.3V, where both enable terminal 1 and enable terminal 2 are connected to a high level, the non-enable terminal is connected to a low level, the input terminal is connected to a differential square wave signal, and the voltage amplitude is selected within the range of 200-1860mV, and enters the chip circuit through capacitor coupling.

[0024] S3. Test steps to verify whether the threshold current of the high linear laser array chip meets the standard: After the voltage amplitude enters the chip circuit, select different temperatures for transient simulation, observe the modulated current output at the output end after stabilization for a period of time, and verify the operating temperature range. Change the differential input voltage amplitude and observe the transient simulation output results. Change the power supply voltage range and observe the transient simulation output results to verify whether the threshold current of the high linear laser array chip meets the standard.

[0025] S4. The test steps for verifying whether the central wavelength, output power, side mode suppression ratio, and -20dB spectrum width of the high linear laser array chip meet the standards are as follows: after the voltage amplitude enters the chip circuit, the test system is disconnected from the external diode, and DC simulation is performed to observe the current supplied to the circuit from the power supply to verify the current consumption. The temperature compensation coefficient resistance value and the temperature compensation resistance value are fixed, and the temperature compensation resistance value and the temperature compensation coefficient resistance value are set as variables, and a temperature DC scan is performed to observe the temperature compensation starting point and the change in the slope of the output curve (temperature compensation coefficient) when the output current of different resistance values ​​changes significantly; the maximum value of the modulation current range is determined by the mode setting resistor. Under different resistance values, transient simulation is performed to observe the current value range of the output waveform and verify the modulation current range. Add a diode equivalent circuit, add a loop gain control function, DC simulation, observe the output range of the bias point current, and verify the range of the bias current to verify whether the central wavelength, output power, side mode suppression ratio, and -20dB spectrum width performance of the high linear laser array chip laser array chip meet the standards.

[0026] S5. Verify whether the CSO and CTB of the high linear laser array chip have reached the standard. The steps are as follows: After connecting the input and output terminals, perform AC simulation at three temperature points (-40, 27, 90) to observe whether the filtering results are correct. Then select the three voltage points (-0.3, 1.0, 1.8v) in the supply voltage (Vcc) range of -0.3-1.8V, perform DC simulation, and observe whether the filtering can be normal. Finally, perform the input current test on the external pin port, and observe whether the test point is 4.5mA by DC simulation. Verify the input current to verify whether the composite second-order distortion (CSO) and composite third-order beat (CTB) performance of the high linear laser array chip meet the standards.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A test system based on Cadence high linear laser array chip, characterized by: The test system is built by Cadence, and includes a differential input voltage port, an enable voltage signal port, a reference input current port, a bias current input port, an LD modulation current output port, a loop failure alarm signal port, an overcurrent alarm signal port and a ground port, wherein: Differential input voltage port: directly connected to the test system, and the transient simulation output results can be observed by changing the differential input voltage amplitude; Bias current input port: directly connected to the test system; Reference input current port: directly connected to the test system; LD modulation current output port: directly connected to the test system; The loop failure alarm signal port, the overcurrent alarm signal port and the ground port are all directly connected to the test system; the test process of the test system is as follows: S1. Use the component library provided by Cadence software to build a high linear laser array chip test system, and the composition and connection methods of the components included in the system; S2. After connecting the components, adjust the input power supply voltage to 3.3V, where both enable terminal 1 and enable terminal 2 are connected to a high level, the non-enable terminal is connected to a low level, the input terminal is connected to a differential square wave signal, and the voltage amplitude is selected within the range of 200-1860mV, and enters the chip circuit through capacitive coupling; S3. Test steps for verifying whether the threshold current of the high linear laser array chip meets the standard: after the voltage amplitude enters the chip circuit, select different temperatures for transient simulation, observe the modulated current output at the output end after stabilization for a period of time, and verify the operating temperature range; change the differential input voltage amplitude, and observe the transient simulation output results; change the power supply voltage range, and observe the transient simulation output results, so as to verify whether the threshold current of the high linear laser array chip meets the standard; S4. The test steps for verifying whether the central wavelength, output power, side mode suppression ratio, and -20dB spectrum width of the high linear laser array chip meet the standards are as follows: after the voltage amplitude enters the chip circuit, the test system is made without an external diode, and DC simulation is performed to observe the current supplied to the circuit from the power supply to verify the current consumption; the temperature compensation coefficient resistance value and the temperature compensation resistance value are fixed, and the temperature compensation resistance value and the temperature compensation coefficient resistance value are set as variables, and a temperature DC scan is performed to observe the temperature compensation starting point and the change in the slope of the output curve when the output current of different resistance values ​​changes significantly; the maximum value of the modulation current range is determined by the mode setting resistor, and at different resistance values, transient simulation is performed to observe the current value range of the output waveform and verify the modulation current range; a diode equivalent circuit is added, a loop gain control function is added, DC simulation is performed, the output range of the bias point current is observed, and the range of the bias current is verified, so as to verify whether the central wavelength, output power, side mode suppression ratio, and -20dB spectrum width performance of the high linear laser array chip laser array chip meet the standards; S5. To verify whether the CSO and CTB of the high linear laser array chip have reached the standard, the steps are as follows: after connecting the input and output terminals, perform AC simulation at three temperature points (-40, 27, 90) to observe whether the filtering result is correct; then select three voltage points (-0.3, 1.0, 1.8v) where the supply voltage Vcc is in the range of -0.3-1.8V, perform DC simulation to observe whether it can filter normally; finally, perform an input current test on the external pin port, and observe whether the test point voltage is 4.5mA by DC simulation to verify the input current, so as to verify whether the performance of the composite second-order distortion CSO and composite third-order beat CTB of the high linear laser array chip meets the standard.

2. The test system based on Cadence high linear laser array chip according to claim 1, characterized in that: The input voltage port voltage of the test system is adjusted to 3.3V, the enable terminal is connected to a high level, and the disable terminal is connected to a low level.

3. The test system based on Cadence high linear laser array chip according to claim 1 or 2, characterized in that: The test system selects different temperatures for transient simulation, observes the modulated current output at the output end after a period of stabilization, and verifies the operating temperature range; changes the differential input voltage amplitude according to the relationship between the threshold current and the temperature, and observes the transient simulation output results. The relationship between the threshold current and the temperature is as follows: Where, T r is room temperature, J th (T) and J th (T r ) are a certain temperature T and room temperature T r The threshold current density measured under T0 is a parameter fitted by experiments; Change the power supply voltage range, observe the transient simulation output results, and verify whether the threshold current of the laser chip meets the standard.

4. The test system based on Cadence high linear laser array chip according to claim 1 or 2, characterized in that: The test system verifies whether the central wavelength, output power, side mode suppression ratio, and -20dB spectral width of the high linear laser array chip have reached the standard by the following method: a temperature DC scanning method is used to observe the changes in the temperature compensation starting point and the temperature compensation coefficient under different temperature compensation resistance values ​​and temperature compensation coefficient resistance values, thereby verifying the temperature compensation range and the temperature compensation coefficient range to determine whether the central wavelength, output power, side mode suppression ratio, and -20dB spectral width of the laser array chip have reached the standard.

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