A peripheral component high-speed interconnection device fault detection method, device and server

Abstract

The application provides a PCIE device fault detection method, device and server, the server comprises a CPU and a BMC, the BMC receives the device information of the PCIE device in place acquired by the CPU;And obtain the device information of the PCIE device supporting MCTP on the PCIE bus;According to the obtained device information of the PCIE device in place and the device information of the PCIE device supporting MCTP, determine the PCIE device to be detected;The fault detection of the PCIE device to be detected is carried out, and the fault PCIE device in the fault state is determined.In the application, the BMC no longer depends on the BIOS interrupt service program to detect the PCIE device fault, the BMC can actively determine the PCIE device to be detected, and the fault detection of the PCIE device to be detected is carried out, so that the fault detection means of the PCIE device is expanded, and the system fault diagnosis rate can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the fault diagnosis technology, and particularly relates to a PCIE device fault detection method and device and a server. BACKGROUND

[0002] The BMC (Baseboard Management Controller) mainly realizes the timely monitoring and reporting of the faults of various components of a server, so as to guarantee the reliable operation of the server. At present, the fault detection of the PCIE (Peripheral Component Interconnect Express) device such as a network card and a GPU (graphics processing unit) card by the BMC mainly depends on the interrupt fault detection of the PCIE device by the processor on the server through the BIOS (Basic Input Output System) interrupt service program to report the PCIE device fault interrupt, and the transmission of the BIOS to the BMC. The detection of the PCIE device by the BMC itself is limited to the acquisition of the sensor information such as the temperature sensing of the PCIE device through the I2C bus.

[0003] However, in actual application, since the fault types of the PCIE device are various, some faults may not be detected through the fault detection interrupt of the PCIE device by the processor on the server, for example, one PCIE device fault, the operating system processes the PCIE device offline, causing the loss of the PCIE device, but this kind of fault is not detected by the BIOS interrupt service program, and will not be sent to the BMC. That is to say, the processor on the server and the BMC do not detect this kind of fault, so that the PCIE device of this kind of fault is missed, and the system fault diagnosis rate is low. SUMMARY

[0004] The present application provides a PCIE device fault detection method, device and server, so as to improve the fault diagnosis rate of the system.

[0005] The technical scheme provided by the present application comprises:

[0006] In a first aspect, the present application provides a PCIE fault detection method, which is applied to the BMC on a server, and the server further comprises at least a CPU (Central Processing Unit), and the CPU is connected with the PCIE device through a PCIE bus. The method comprises the following steps:

[0007] receiving the device information of the PCIE device in place acquired by the CPU when the CPU is started.

[0008] obtaining device information of PCIE devices supporting MCTP (Management Component Transport Protocol) on the PCIE bus;

[0009] determining PCIE devices to be detected according to the obtained device information of PCIE devices in place and the device information of PCIE devices supporting MCTP;

[0010] performing fault detection on the PCIE devices to be detected to determine fault PCIE devices in a fault state.

[0011] Optionally, after the CPU obtains the device information of PCIE devices in place at the time of receiving the CPU startup, the method further comprises:

[0012] outputting the received device information to a management device to enable the management device to display the device information of PCIE devices in place in the server;

[0013] after the determination of the fault PCIE devices in a fault state, the method further comprises:

[0014] outputting the device information of the fault PCIE devices to the management device to enable the management device to update the displayed state of the PCIE devices in place to a fault state.

[0015] Optionally, before the obtaining of the device information of PCIE devices supporting MCTP on the PCIE bus, the method further comprises:

[0016] for each PCIE device connected to the CPU through the PCIE bus, sending a detection request for determining whether the PCIE device supports MCTP to the PCIE device to enable the PCIE device to send a response to the BMC when it is determined that the PCIE device supports MCTP according to the received detection request;

[0017] if the response of the PCIE device to the detection request is received, it is determined that the PCIE device supports MCTP.

[0018] Optionally, the performing of the fault detection on the PCIE devices to be detected comprises:

[0019] for each PCIE device to be detected, sending a discovery request to the PCIE device to be detected, and if no response is received after continuously sending the discovery request for a preset number of times, it is determined that the PCIE device to be detected is in a fault state.

[0020] Optionally, after the fault PCIE device in the fault state is determined, the method further comprises:

[0021] For each fault PCIE device, the fault information of the fault PCIE device is output to the management device, so that the management device updates the fault information log corresponding to the fault PCIE device.

[0022] In a second aspect, the embodiments of the present application provide a PCIE device fault detection apparatus, which is applied to a BMC on a server, the server further comprising at least a CPU, the CPU being connected to PCIE devices through a PCIE bus, the apparatus comprising:

[0023] a first device information obtaining unit, configured to receive device information of the PCIE devices in place obtained by the CPU when the CPU is started;

[0024] a second device information obtaining unit, configured to obtain device information of the PCIE devices supporting MCTP on the PCIE bus;

[0025] a to-be-detected device determining unit, configured to determine the PCIE devices to be detected according to the obtained device information of the PCIE devices in place and the device information of the PCIE devices supporting MCTP;

[0026] a fault detection unit, configured to perform fault detection on the PCIE devices to be detected, and determine fault PCIE devices in a fault state.

[0027] Optionally, the apparatus further comprises:

[0028] an information output unit, configured to output the received device information to a management device, so that the management device displays the device information of the PCIE devices in place in the server;

[0029] the information output unit is further configured to output the device information of the fault PCIE devices to the management device, so that the management device updates the displayed state of the PCIE devices in place to the fault state.

[0030] Optionally, the apparatus further comprises:

[0031] a device identifying unit, configured to, for each PCIE device connected to the CPU through the PCIE bus, send a detection request for determining whether the PCIE device supports MCTP to the PCIE device, so that the PCIE device sends a response to the BMC when it is determined that the PCIE device supports MCTP according to the received detection request; and if the response of the PCIE device to the detection request is received, it is determined that the PCIE device supports MCTP.

[0032] Optionally, the fault detection unit is specifically configured to:

[0033] For each PCIE device to be detected, a discovery request is sent to the PCIE device to be detected, and if no response is received after continuously sending the discovery request for a preset number of times, it is determined that the PCIE device to be detected has a fault.

[0034] Optionally, the information output unit is further configured to:

[0035] For each fault PCIE device, the fault information of the fault PCIE device is output to the management device, so that the management device updates the fault information log corresponding to the fault PCIE device.

[0036] In a third aspect, an embodiment of the present application provides a server, comprising a BMC and a machine readable storage medium, the machine readable storage medium stores machine executable instructions capable of being executed by the BMC; the BMC is configured to execute the machine executable instructions to implement any of the method steps described above.

[0037] As can be seen from the above technical solutions, in the present application, the BMC no longer relies on the BIOS interrupt service program to detect PCIE device faults, and the BMC can actively determine PCIE devices to be detected according to the obtained device information of the in-place PCIE device and the device information of the PCIE device supporting MCTP on the PCIE bus, and perform fault detection on the PCIE devices to be detected, thereby expanding the means for detecting PCIE device faults and effectively improving the system fault diagnosis rate. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure together with the specification.

[0039] Figure 1 A flowchart of a PCIE device fault detection method provided by the present application;

[0040] Figure 2 A structural schematic diagram of a server provided by the present application;

[0041] Figure 3 An implementation flow of identifying a PCIE device supporting MCTP provided by the present application;

[0042] Figure 4 A structural schematic diagram of a PCIE device fault detection apparatus provided by the present application. DETAILED DESCRIPTION

[0043] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be described in detail below with reference to the drawings and specific embodiments.

[0044] Referring to Figure 1 A flow chart of a PCIE fault detection method is shown in the embodiments of the present application, which is applied to a BMC included in a server, and the server further includes a CPU, and the CPU is connected to PCIE devices through a PCIE bus.

[0045] Referring to Figure 2 A server structure schematic diagram is shown in the embodiments of the present application. The server includes a BMC, a CPU and a PCH (Platform Controller Hub) chip. The BMC is connected to the PCH chip through a PCIE bus, the PCH chip is connected to the CPU through a DMI (Direct Media Interface) bus, and the CPU is connected to PCIE devices (PCIE device 1-PCIE device 4) plugged in the server through a PCIE bus. It should be noted that the PCH chip can access any PCIE device under the CPU through the DMI bus.

[0046] As Figure 1 shown, the flow can include the following steps:

[0047] Step 101, the BMC receives the device information of the PCIE devices in place acquired by the CPU at the time of starting up the CPU.

[0048] As described above, the CPU is connected to each PCIE device through a PCIE bus, so it can perceive all the PCIE devices in place and transmit the device information of each PCIE device in place to the BMC. The device information mainly includes the position information of the PCIE device, such as the slot number and device number of the device.

[0049] The BMC receives and records the device information of each PCIE device in place acquired by the CPU.

[0050] As an embodiment, the BMC can also output the received device information of each PCIE device in place to a management device, and the management device displays the device information of each PCIE device in place in the server, so that the administrator can intuitively understand the situation of each PCIE device in the server.

[0051] Step 102, the BMC obtains the device information of the PCIE devices supporting MCTP on the PCIE bus.

[0052] Here, it should be noted that the PCIE devices connected with the CPU through the PCIE bus can include PCIE devices supporting MCTP and PCIE devices not supporting MCTP, and therefore, it is necessary to identify the PCIE devices supporting MCTP from the PCIE devices.

[0053] The process in which the BMC identifies the PCIE devices supporting MCTP is described below, and will not be described here in detail.

[0054] In step 103, the PCIE devices to be detected are determined according to the device information of the PCIE devices in place and the device information of the PCIE devices supporting MCTP.

[0055] Here, it should be noted that the device information of the PCIE devices in place obtained in step 101 can include device information of PCIE devices not supporting MCTP, and the device information of the PCIE devices supporting MCTP obtained in step 102 can include device information of PCIE devices not in place when the CPU is started, such as device information of PCIE devices supporting MCTP newly inserted after the CPU is started, which is not included in the device information of the PCIE devices in place obtained when the CPU is started.

[0056] As an embodiment, the intersection of the device information obtained in step 101 and step 102 can be obtained, that is, the set of device information existing in both the device information obtained in step 101 and the device information obtained in step 102, and the PCIE devices corresponding to each device information in the set are determined as the PCIE devices to be detected. In short, the PCIE devices to be detected are PCIE devices in place when the CPU is started and supporting MCTP.

[0057] In step 104, the BMC performs fault detection on the PCIE devices to be detected to determine the fault PCIE devices in a fault state.

[0058] As an embodiment, the BMC can periodically (for example, 5 minutes) send a discovery request to the PCIE devices to be detected. If the PCIE device receiving the discovery request is normal, it will reply a discovery response to the BMC, that is, reply to the request sent by the BMC; if the PCIE device is faulty, it cannot reply.

[0059] In order to improve the accuracy of fault judgment, in the embodiment of the present application, for each PCIE device to be detected, the BMC counts the number of times of continuously not receiving the reply of the PCIE device to be detected, and if the counted number of times reaches a preset number of times (for example, 3 times), that is, there is a situation that the discovery request is continuously sent for a preset number of times and no reply is received, it is determined that the PCIE device to be detected has a fault.

[0060] As an embodiment, after detecting the PCIE device failure, the BMC can send the device information of the failed PCIE device to the management device, and the management device can update the displayed status of the in-place failed PCIE device to the failure status, so that the administrator can discover the PCIE device failure in time and perform maintenance management.

[0061] Further, the BMC can also send the failure information (used for identifying the failure cause) of the failed PCIE device to the management device, and the management device can update the failure information log corresponding to the failed PCIE device based on the failure information, so that the administrator can quickly locate the failure cause by browsing the failure information log.

[0062] At this point, the process shown in Figure 1 is completed.

[0063] As can be seen from the above technical solutions, in the present application, the BMC no longer relies on the BIOS interrupt service program to detect the PCIE device failure, and the BMC can actively determine the PCIE device to be detected and perform failure detection on the PCIE device to be detected, thereby expanding the failure detection means for the PCIE device and effectively improving the system failure diagnosis rate.

[0064] The process of the BMC identifying the PCIE device supporting MCTP will be described below. Referring to Figure 3 , an implementation process of identifying the PCIE device supporting MCTP is shown.

[0065] As shown in Figure 3 , the process can include the following steps:

[0066] Step 301, for each PCIE device connected to the CPU through the PCIE bus, a detection request for determining whether the PCIE device supports MCTP is sent to the PCIE device.

[0067] As an embodiment, the BMC can directly send a detection request based on the MCTP protocol to each PCIE device connected to the CPU. If the PCIE device receiving the detection request supports the MCTP protocol, the detection request based on the MCTP protocol can be identified and a response to the detection request can be made.

[0068] Step 302, if the BMC receives a response to the detection request from the PCIE device, it is determined that the PCIE device supports MCTP.

[0069] At this point, the process shown in Figure 3 is completed.

[0070] Through the above process, the BMC can identify the PCIE device supporting MCTP. Figure 3The flow shown realizes the identification of the BMC to the PCIE device supporting MCTP.

[0071] The following still takes the server as an example to describe the PCIE device fault detection process: Figure 2 The server shown is taken as an example to describe the PCIE device fault detection process:

[0072] When the CPU starts, the PCIE device in place can be detected, and the device information of the PCIE device in place is transmitted to the BMC.

[0073] The BMC can save the PCIE device information obtained through the CPU in list 1, and the PCIE device information in place includes PCIE device 1, PCIE device 2, PCIE device 3 and PCIE device 4.

[0074] Here, it needs to be explained that PCIE device 1, PCIE device 2, PCIE device 3 and PCIE device 4 can also appear due to the damage of the link or the PCIE device itself, so that some PCIE devices are not perceived, which makes it impossible to deliver all the PCIE device information to the BMC, but in such a case, the fault will be detected by the BIOS interrupt service program and reported to the BMC.

[0075] The BMC can send a detection request to each PCIE device connected with the CPU through the ME (Intel Management Engine) module (which can provide MCTP related functions) in the PCH, and when receiving the response of the PCIE device to the detection request, the PCIE device is identified as a PCIE device supporting MCTP. For example, if the BMC receives the response of PCIE device 1, PCIE device 2 and PCIE device 3 to the detection request, it is determined that PCIE device 1, PCIE device 2 and PCIE device 3 are PCIE devices supporting MCTP. The BMC stores the device information of PCIE device 1, PCIE device 2 and PCIE device 3 obtained in list 2.

[0076] The BMC determines the same PCIE device in list 1 and list 2 as the PCIE device to be detected, and saves it in the PCIE device list. Specifically, according to the PCIE device information stored in list 1 and list 2 respectively, it can be determined that the PCIE device in the PCIE device list is PCIE device 1, PCIE device 2 and PCIE device 3 respectively.

[0077] The BMC periodically sends a discovery request for each PCIE device to be detected in the PCIE device list. Assuming that PCIE device 1 is normal, PCIE device 2 is normal, and PCIE device 3 is faulty, PCIE device 1 and PCIE device 2 respond to the discovery request, the BMC receives the response of PCIE device 1 and confirms that PCIE device 1 is normal, the BMC receives the response of PCIE device 2 and confirms that PCIE device 2 is normal, and PCIE device 3 cannot respond because it is faulty, so the BMC cannot receive the response of PCIE device 3. In this application, the BMC determines that PCIE device 3 is faulty when it determines that the connection is not received for a preset number of times (for example, 3 times).

[0078] The BMC can push the device information of the faulty PCIE device to the management device to display the state of the faulty PCIE device as a fault state and remind the administrator to repair in time.

[0079] Thus, the description of this embodiment is completed.

[0080] Reference is made to Figure 4 A structural diagram of a PCIE device fault detection device provided in this embodiment. The device is applied to a BMC on a server, the server further includes at least a CPU, the CPU is connected to a PCIE device through a PCIE bus, and the device includes:

[0081] A first device information obtaining unit 401 is configured to receive device information of an in-place PCIE device obtained by the CPU when the CPU is started;

[0082] A second device information obtaining unit 402 is configured to obtain device information of a PCIE device supporting MCTP on the PCIE bus;

[0083] A to-be-detected device determining unit 403 is configured to determine a PCIE device to be detected according to the obtained device information of the in-place PCIE device and the device information of the PCIE device supporting MCTP;

[0084] A fault detection unit 404 is configured to perform fault detection on the PCIE device to be detected and determine a faulty PCIE device in a fault state.

[0085] As an embodiment, the device further includes:

[0086] An information output unit is configured to output the received device information to a management device to display device information of an in-place PCIE device in the server by the management device;

[0087] The information output unit is further configured to output device information of the faulty PCIE device to the management device, so that the management device updates the displayed status of the in-place faulty PCIE device to a faulty status.

[0088] As an embodiment, the apparatus further comprises:

[0089] The device identification unit is configured to, for each PCIE device connected on the CPU through the PCIE bus, send a detection request for determining whether the PCIE device supports MCTP to the PCIE device, so that the PCIE device sends a response to the BMC when it determines that it supports MCTP according to the received detection request; and if the response of the PCIE device to the detection request is received, it is determined that the PCIE device supports MCTP.

[0090] As an embodiment, the fault detection unit 404 is specifically configured to:

[0091] For each PCIE device to be detected, a discovery request is sent to the PCIE device to be detected, and if no response is received after continuously sending the discovery request for a preset number of times, it is determined that the PCIE device to be detected has a fault.

[0092] As an embodiment, the information output unit is further configured to:

[0093] For each faulty PCIE device, the fault information of the faulty PCIE device is output to the management device, so that the management device updates the fault information log corresponding to the faulty PCIE device.

[0094] Thus, the structure of the apparatus is completed. Figure 4 The structure diagram of the apparatus is shown.

[0095] As can be seen from the above technical solutions, in the present application, the BMC no longer relies on the BIOS interrupt service program to detect PCIE device faults, and the BMC can actively determine the PCIE device to be detected according to the obtained device information of the in-place PCIE device and the device information of the PCIE device supporting MCTP on the PCIE bus, and perform fault detection on the PCIE device to be detected, thereby expanding the means for detecting PCIE device faults and effectively improving the system fault diagnosis rate.

[0096] The implementation process of the functions and roles of each unit in the above apparatus is specifically described in the implementation process of the corresponding steps in the above method, which will not be repeated here.

[0097] The embodiment of the present application further provides a server, comprising a BMC and a machine readable storage medium, wherein the machine readable storage medium stores machine executable instructions capable of being executed by the BMC; and the BMC is used to execute the machine executable instructions to implement the PCIE fault detection method steps disclosed in the above examples.

[0098] Here, the machine readable storage medium can be any electronic, magnetic, optical or other physical storage device, and can contain or store information such as executable instructions, data, etc. For example, the machine readable storage medium can be a RAM (Random Access Memory), a volatile memory, a non-volatile memory, a flash memory, a storage drive (such as a hard disk drive), a solid state disk, any type of storage disk (such as an optical disk, a DVD, etc.), or similar storage medium, or a combination thereof.

[0099] The above only describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for detecting a PCIE device fault in peripheral component interconnect express (PCIE) high-speed interconnection, the method being applied to a baseboard management controller (BMC) on a server, the server further comprising at least a central processing unit (CPU), the CPU being connected to a PCIE device through a PCIE bus, and the method comprising the steps of: The method comprises: ​ receiving the device information of the PCIE device in place acquired by the CPU when the CPU starts; obtaining the device information of the PCIE device supporting the management device transmission protocol (MCTP) on the PCIE bus; determining the PCIE device to be detected according to the obtained device information of the PCIE device in place and the device information of the PCIE device supporting the MCTP; the PCIE device to be detected is determined by determining the intersection of the obtained device information of the PCIE device in place and the device information of the PCIE device supporting the MCTP, and determining the PCIE device corresponding to each device information in the intersection as the PCIE device to be detected; performing fault detection on the PCIE device to be detected to determine the fault PCIE device in the fault state; the fault detection on the PCIE device to be detected comprises: for each PCIE device to be detected, sending a discovery request to the PCIE device to be detected, and if no response is received after continuously sending the discovery request for a preset number of times, it is determined that the PCIE device to be detected has a fault.

2. The method of claim 1, wherein, After the receiving the device information of the PCIE device in place acquired by the CPU when the CPU starts, the method further comprises: outputting the received device information to the management device, so that the management device displays the device information of the PCIE device in place in the server; after the determining the fault PCIE device in the fault state, the method further comprises: outputting the device information of the fault PCIE device to the management device, so that the management device updates the displayed state of the PCIE device in place to the fault state.

3. The method according to claim 1 or 2, characterized in that, Before the obtaining the device information of the PCIE device supporting the MCTP on the PCIE bus, the method further comprises: for each PCIE device connected to the CPU through the PCIE bus, sending a detection request for determining whether the PCIE device supports the MCTP to the PCIE device, so that the PCIE device sends a response to the BMC when it is determined that the PCIE device supports the MCTP according to the received detection request; if the response of the PCIE device to the detection request is received, it is determined that the PCIE device supports the MCTP.

4. The method of claim 2, wherein, After the determining the fault PCIE device in the fault state, the method further comprises: for each fault PCIE device, outputting the fault information of the fault PCIE device to the management device, so that the management device updates the fault information log corresponding to the fault PCIE device.

5. A peripheral component interconnect express (PCIE) device fault detection apparatus, applied to a baseboard management controller (BMC) of a server, wherein the server further comprises at least a central processing unit (CPU), and the CPU is connected with a PCIE device through a PCIE bus, and the apparatus is characterized in that, The device comprises: a first device information obtaining unit, configured to receive the device information of the PCIE device in place acquired by the CPU when the CPU starts; a second device information obtaining unit, configured to obtain the device information of the PCIE device supporting the management device transmission protocol (MCTP) on the PCIE bus; The device to be detected determination unit is configured to determine the PCIE device to be detected according to the obtained device information of the in-place PCIE device and the device information of the PCIE device supporting MCTP; the PCIE device to be detected is determined by the following manner: determining the intersection of the obtained device information of the in-place PCIE device and the device information of the PCIE device supporting MCTP, and determining the PCIE device corresponding to each device information in the intersection as the PCIE device to be detected; The fault detection unit is configured to perform fault detection on the PCIE device to be detected, and determine the fault PCIE device in the fault state; the fault detection on the PCIE device to be detected comprises: for each PCIE device to be detected, sending a discovery request to the PCIE device to be detected, and if there is no response after continuously sending the discovery request for a preset number of times, it is determined that the PCIE device to be detected has a fault.

6. The apparatus of claim 5, wherein, The apparatus further comprises: The information output unit is configured to output the received device information to the management device, so that the management device displays the device information of the in-place PCIE device in the server; The information output unit is further configured to output the device information of the fault PCIE device to the management device, so that the management device updates the displayed state of the in-place fault PCIE device to the fault state.

7. The apparatus of claim 5 or 6, wherein, The apparatus further comprises: The device identification unit is configured to, for each PCIE device connected to the CPU through the PCIE bus, send a detection request for determining whether the PCIE device supports MCTP to the PCIE device, so that the PCIE device sends a response to the BMC when it is determined that the PCIE device supports MCTP according to the received detection request; if the response of the PCIE device to the detection request is received, it is determined that the PCIE device supports MCTP.

8. A server, characterized by The BMC and a machine readable storage medium are included, and the machine readable storage medium stores machine executable instructions which can be executed by the BMC; the BMC is configured to execute the machine executable instructions to implement the method steps of any one of claims 1 to 4.

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