Semiconductor Memory Device and Control Method Thereof

Abstract

An embodiment provides a semiconductor memory device and a control method thereof that can improve the reliability of the erasing operation of memory cell transistors. According to one embodiment, the semiconductor memory device includes a first wiring electrically connected to a plurality of memory cell transistors. The device further includes an erasing unit that applies a first voltage to the first wiring to erase data stored in the memory cell transistors. Moreover, the erasing unit applies the first voltage such that the first voltage rises to a first value, drops from the first value to a second value, and is maintained at the second value.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-103218 (filing date: June 15, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device and a control method thereof. Background Art

[0004] In a semiconductor memory device, it is desired to improve the reliability of the erasing operation of memory cell transistors. Summary of the Invention

[0005] Embodiments provide a semiconductor memory device and a control method thereof capable of improving the reliability of the erasing operation of memory cell transistors.

[0006] According to one embodiment, a semiconductor memory device includes a first wiring electrically connected to a plurality of memory cell transistors. The device further includes an erasing unit that applies a first voltage to the first wiring to erase data stored in the memory cell transistors. Moreover, the erasing unit applies the first voltage such that the first voltage rises to a first value, drops from the first value to a second value, and is maintained at the second value. Brief Description of the Drawings

[0007] Figure 1 is a block diagram showing the configuration of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 is a circuit diagram showing the configuration of a NAND string according to the first embodiment.

[0009] Figure 3 is a graph for explaining the erasing operation according to the first embodiment.

[0010] Figure 4 is a cross-sectional view showing the structure of the semiconductor memory device according to the first embodiment.

[0011] Figure 5 is a cross-sectional view showing the structure of the semiconductor memory device according to a modification of the first embodiment.

[0012] Figure 6 is a graph for explaining the erasing operation according to the first embodiment.

[0013] Figure 7 is another graph for explaining the erasing operation according to the first embodiment.

[0014] Figure 8 It is another curve graph for explaining the erasing operation of the first embodiment.

[0015] Description of Reference Numerals

[0016] 1: Memory cell array, 2: Sense amplifier, 3: Row decoder, 4: Driver circuit, 5: BL / SL driver, 6: Voltage generation circuit, 7: Detection circuit, 8: Control circuit, 11: Substrate, 12: Interlayer insulating film, 13: Interlayer insulating film, 14: Insulating layer, 15: Interlayer insulating film, 21: Barrier insulating film, 22: Charge storage layer, 23: Tunnel insulating film, 24: Channel semiconductor layer, 25: Core insulating film, 26: Buried semiconductor layer, 27: Contact plug, BLK: Block, GP: Memory bank, S: NAND string, MT: Memory cell transistor, ST: Selection transistor, SL: Source line, GL: Gate line, SGS: Source side selection line, WL: Word line, BL: Bit line, SGD: Drain side selection line Detailed Embodiment

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 8 the same components are denoted by the same reference numerals and redundant descriptions are omitted.

[0018] (First Embodiment)

[0019] Figure 1 It is a block diagram showing the configuration of a semiconductor memory device according to the first embodiment. The semiconductor memory device of this embodiment is, for example, a three-dimensional NAND memory.

[0020] The semiconductor memory device of this embodiment includes a memory cell array 1, a sense amplifier 2, a plurality of row decoders 3, a driver circuit 4, a BL / SL driver 5, a voltage generation circuit 6, a detection circuit 7, and a control circuit 8. The driver circuit 4, the BL / SL driver 5, the voltage generation circuit 6, the detection circuit 7, etc. are examples of an erasing unit.

[0021] The memory cell array 1 includes a plurality of (here, four) blocks BLK0 to BLK3, and these blocks BLK0 to BLK3 each include a plurality of (here, four) memory banks GP0 to GP3. Further, these memory banks GP0 to GP3 each include a plurality of NAND strings S. Each NAND string S includes a plurality of memory cell transistors (memory cells) connected in series with each other, and two selection transistors (selection gates) arranged so as to sandwich these memory cell transistors. Hereinafter, the blocks BLK0 to BLK3 will be respectively labeled as "block BLK", and the memory banks GP0 to GP3 will be respectively labeled as "memory bank GP".

[0022] The memory cell array 1 can store data in the memory cells of each NAND string S. The data stored in the memory cells is erased together for each block BLK. The number of blocks BLK in the memory cell array 1 is four in the present embodiment, but may be other than four. Similarly, the number of memory cell groups GP in each block BLK is four in the present embodiment, but may be other than four.

[0023] When reading data from the memory cell array 1, the sense amplifier 2 detects and amplifies the read data. In addition, when writing data to the memory cell array 1, the sense amplifier 2 transfers the write data to the memory cell array 1.

[0024] Each row decoder 3 corresponds to one block BLK. The semiconductor memory device of the present embodiment includes four row decoders 3 corresponding to four blocks BLK. Each row decoder 3 selects a row in the corresponding block BLK during data reading and writing.

[0025] The driving circuit 4 supplies the voltages required for data reading, writing, and erasing to each row decoder 3. This voltage is applied to the memory cells through each row decoder 3.

[0026] The BL / SL driver 5 applies the voltages required for data reading, writing, and erasing to the bit lines and / or source lines described later. For example, when erasing the data stored in the memory cell array 1, the BL / SL driver 5 applies an erase voltage V ERA .

[0027] The voltage generation circuit 6 generates the voltages required for data reading, writing, and erasing, and supplies this voltage to the driving circuit 4 and the BL / SL driver 5. For example, when erasing data, the voltage generation circuit 6 generates an erase voltage V ERA .

[0028] The detection circuit 7 monitors the erase voltage V generated from the voltage generation circuit 6 during data erasing ERA . The detection circuit 7 also generates a flag signal based on the value of the erase voltage V ERA and controls the driving circuit 4.

[0029] The control circuit 8 controls the operation of the semiconductor memory device of the present embodiment. For example, during data reading, writing, and erasing, the control circuit 8 controls the operation of the voltage generation circuit 6 to generate the voltages required for data reading, writing, and erasing.

[0030] Figure 2 is a circuit diagram showing the configuration of the NAND string S of the first embodiment.

[0031] Figure 2Shows a NAND string S within the memory cell array 1. Figure 2 The shown NAND string S includes a plurality (here, 48) of memory cell transistors MT0 to MT47 connected in series with each other, and two select transistors ST1, ST2 arranged to sandwich these memory cell transistors MT0 to MT47. One main terminal of the select transistor ST1 is electrically connected to the memory cell transistor MT47, and the other main terminal of the select transistor ST1 is electrically connected to the bit line BL. One main terminal of the select transistor ST2 is electrically connected to the memory cell transistor MT0, and the other main terminal of the select transistor ST2 is electrically connected to the source line SL. Hereinafter, the memory cell transistors MT0 to MT47 will be respectively labeled as "memory cell transistor MT", and the select transistors ST1, ST2 will be respectively labeled as "select transistor ST".

[0032] As Figure 2 Shown, the memory cell array 1 further includes a plurality (here, 48) of word lines WL0 to WL47 electrically connected to the control terminals (gate terminals) of the memory cell transistors MT0 to MT47, a drain side select line SGD electrically connected to the control terminal of the select transistor ST1, and a source side select line SGS electrically connected to the control terminal of the select transistor ST2. The memory cell array 1 further includes the above-mentioned bit line BL and source line SL. The bit line BL and the source line SL are examples of the first wiring. The source side select line SGS and the drain side select line SGD are examples of the second wiring. Hereinafter, the word lines WL0 to WL47 will be respectively labeled as "word line WL".

[0033] The word line WL is electrically connected to the corresponding memory cell transistor MT and is provided to control the operation of the corresponding memory cell transistor MT. The drain side select line SGD is provided to control the operation of the select transistor ST1. The source side select line SGS is provided to control the operation of the select transistor ST2.

[0034] The bit line BL is electrically connected to the memory cell transistors MT0 to MT47 via the select transistor ST1. The source line SL is electrically connected to the memory cell transistors MT0 to MT47 via the select transistor ST2. The bit line BL and the source line SL are used, for example, for reading, writing, and erasing data targeted at the memory cell transistors MT0 to MT47.

[0035] Figure 2 Shows the memory cell transistors MT0, MT1, ··· MTm, ··· MT23, MT24, ··· MTn, ··· MT46, MT47. m is any integer satisfying 1 < m < 23, and n is any integer satisfying 24 < n < 46. Figure 2Word lines WL0, WL1, ··· WLm, ··· WL23, WL24, ··· WLn, ··· WL46, WL47 are also shown. m and n are used in the description of Figure 3 described later.

[0036] Figure 3 is a graph for explaining the erasing operation of the first embodiment.

[0037] Figure 3 Various voltages used in the erasing operation of the semiconductor memory device of the present embodiment are shown. Specifically, Figure 3 the voltage (erasing voltage) V applied to the source line SL is shown ERA , the voltage V applied to the source-side select line SGS ERA_GIDL , and the voltages VSWL0 to VSWL47 applied to the word lines WL0 to WL47. The erasing voltage V ERA is an example of the first voltage. The voltage V ERA_GIDL is an example of the second voltage. Hereinafter, the voltages VSWL0 to VSWL47 will also be referred to as "voltage VSWL" respectively.

[0038] The erasing voltage V ERA is generated by the voltage generation circuit 6 (see Figure 1 . The same applies hereinafter) and is applied to the source line SL through the BL / SL driver 5. The voltage V ERA_GIDL is generated by the voltage generation circuit 6 and is applied to the source-side select line SGS through the driver circuit 4 and the row decoder 3. The voltages VSWL0 to VSWL47 are generated by the voltage generation circuit 6 and are applied to the word lines WL0 to WL47 through the driver circuit 4 and the row decoder 3. As Figure 3 shown, the values of these voltages are set such that V ERA > V ERA_GIDL > VSWL0 = VSWL24 > VSWL1 = VSWL25 > ··· > VSWLm = VSWLn ··· > VSWL22 = VSWL46 > VSWL23 = VSWL47 holds.

[0039] In the present embodiment, the data stored in the memory cell transistor MT is erased together for each block BLK. Specifically, in the semiconductor memory device of the present embodiment, when erasing data from all the memory cell transistors MT of a certain NAND string S at once, the erasing voltage V ERA is applied to the source line SL connected to the NAND string S.

[0040] At this time, the semiconductor memory device of the present embodiment applies the voltage V ERA_GIDLAs a result, a GIDL (Gate Induced Drain Leakage) current is generated in the channel region of the select transistor ST2. This GIDL current flows from the source line SL side to the memory cell transistor MT side. Data stored in each memory cell transistor MT is erased by this GIDL current. Further, at the time of this erasing operation, voltages VSWL0 to VSWL47 are applied to the word lines WL0 to WL47.

[0041] In the semiconductor memory device of the present embodiment, at the time of this erasing operation, one or more erasing verification operations and one or more erasing voltage application operations are alternately repeated. In the erasing voltage application operation, an erasing voltage V is applied to the source line SL ERA , a voltage V is applied to the source side select line SGS ERA_GIDL , and a voltage VSWL is applied to each word line WL. Figure 3 The number of cycles shown represents the number of times the erasing voltage application operation is performed. In the present embodiment, the erasing voltage V ERA and the voltage V ERA_GIDL increase linearly according to the number of cycles. On the other hand, the voltage VSWL is constant regardless of the number of cycles.

[0042] Figure 4 is a cross-sectional view showing the structure of the semiconductor memory device of the first embodiment.

[0043] The semiconductor memory device of the present embodiment includes a substrate 11, an interlayer insulating film 12, an interlayer insulating film 13, a plurality of insulating layers 14, and a plurality of memory holes MH. Figure 4 Two of these memory holes MH are shown. The semiconductor memory device of the present embodiment further includes a barrier insulating film 21, a charge storage layer 22, a tunnel insulating film 23, a channel semiconductor layer 24, and a core insulating film 25 that are sequentially formed in each memory hole MH. The channel semiconductor layer 24 is an example of a semiconductor layer.

[0044] As a plurality of wiring layers formed on the substrate 11, the semiconductor memory device of the present embodiment further includes a source line SL, a gate line GL, a source side select line SGS, and a plurality of word lines WL. The source line SL includes a metal layer SLa, a lower semiconductor layer SLb, an intermediate semiconductor layer SLc, and an upper semiconductor layer SLd. The source side select line SGS includes three wiring layers SGSa, SGSb, and SGSc.

[0045] The substrate 11 is a semiconductor substrate such as a silicon substrate, for example. Figure 4The X direction and the Y direction, which are parallel to and perpendicular to each other on the surface of the substrate 11, and the Z direction, which is perpendicular to the surface of the substrate 11, are shown. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0046] The interlayer insulating film 12 is formed on the substrate 11. The interlayer insulating film 12 is, for example, a silicon oxide film. The interlayer insulating film 12 may be formed directly on the substrate 11 or may be formed on the substrate 11 with other layers therebetween.

[0047] The source line SL includes a metal layer SLa, a lower semiconductor layer SLb, an intermediate semiconductor layer SLc, and an upper semiconductor layer SLd that are sequentially formed on the interlayer insulating film 12. The metal layer SLa is, for example, a tungsten layer. The lower semiconductor layer SLb, the intermediate semiconductor layer SLc, and the upper semiconductor layer SLd are, for example, polysilicon layers. The intermediate semiconductor layer SLc of the present embodiment is in contact with the channel semiconductor layer 24 in each memory hole MH. Thereby, the source line SL is electrically connected to the channel semiconductor layer 24 in each memory hole MH.

[0048] The interlayer insulating film 13 is formed on the source line SL. The interlayer insulating film 13 is, for example, a silicon oxide film.

[0049] The gate line GL is formed on the interlayer insulating film 13. The gate line GL is, for example, a polysilicon layer.

[0050] As described above, the source-side selection line SGS includes three wiring layers SGSa, SGSb, and SGSc. These wiring layers SGSa to SGSc are stacked separately above the gate line GL. A plurality of insulating layers 14 are provided between these wiring layers SGSa to SGSc. Similarly, the above-described plurality of word lines WL are stacked separately above the source-side selection line SGS. A plurality of insulating layers 14 are provided between these word lines WL. Each insulating layer 14 includes, for example, a silicon oxide film. Each of the wiring layers SGSa to SGSc includes, for example, a tungsten layer. Each word line WL includes, for example, a tungsten layer.

[0051] Each memory hole MH penetrates through each insulating layer 14, each word line WL, the wiring layers SGSa to SGSc of the source-side selection line SGS, the gate line GL, and the interlayer insulating film 13. A part of each memory hole MH is formed within the source line SL. The blocking insulating film 21, the charge storage layer 22, the tunnel insulating film 23, the channel semiconductor layer 24, and the core insulating film 25 are sequentially formed within each memory hole MH. The blocking insulating film 21 is, for example, a silicon oxide film. The charge storage layer 22 is, for example, a silicon nitride film. The charge storage layer 22 may also be a polysilicon layer. The tunnel insulating film 23 is, for example, a silicon oxide film. The channel semiconductor layer 24 is, for example, a polysilicon layer. The channel semiconductor layer 24 of the present embodiment is electrically connected to the source line SL, and the gate line GL, the source-side selection line SGS, and each word line WL are electrically insulated. The core insulating film 25 is, for example, a silicon oxide film.

[0052] The blocking insulating film 21, the charge storage layer 22, the tunnel insulating film 23, the channel semiconductor layer 24, and the core insulating film 25 within each memory hole MH together with the above-mentioned multiple word lines WL constitute a NAND string S (refer to Figure 2 ). Figure 4 One memory cell transistor MT included in the NAND string S is shown by a dashed line.

[0053] As Figure 4 shown, the channel semiconductor layer 24 of the present embodiment includes an n-type diffusion layer on the sides of the source line SL and the gate line GL. This n-type diffusion layer contains n-type impurities at a high concentration. As Figure 4 shown, the channel semiconductor layer 24 of the present embodiment also includes an n － -type diffusion layer on the side of the wiring layer SGSa within the source-side selection line SGS. This n － -type diffusion layer is located above the above-mentioned n-type diffusion layer and contains n-type impurities in such a manner that the concentration of n-type impurities changes sharply in the Z direction. In the present embodiment, GIDL current can be generated by the action of this n － -type diffusion layer.

[0054] In the semiconductor memory device of the present embodiment, by applying an erase voltage V to the source line SL ERA and applying a voltage V to the source-side selection line SGS ERA_GIDL , GIDL current is generated in the channel region of the selection transistor ST2. Figure 4 The n － -type diffusion layer shown is provided within the channel region of the selection transistor ST2. The data stored in the memory cell transistor MT shown in Figure 4 is erased by this GIDL current. In Figure 4 , the source line SL is an example of the first wiring, and the source-side selection line SGS is an example of the second wiring.

[0055] In this case, if n － the concentration distribution of the n-type impurities in the n-type diffusion layer varies significantly for each memory hole MH, the amount of GIDL current generated varies significantly for each memory hole MH. As a result, there is a risk of a decrease in the reliability of the erasing operation of the present embodiment. Therefore, the semiconductor memory device of the present embodiment employs the erasing operation described with reference to Figures 6 to 8 Explanation of the erasing operation.

[0056] Figure 5 is a cross-sectional view showing the structure of a semiconductor memory device according to a modified example of the first embodiment.

[0057] The semiconductor memory device of this modified example, in addition to Figure 4 the components shown, further includes a drain-side selection line SGD, an interlayer insulating film 15, a buried semiconductor layer 26 and a contact plug 27 provided for each memory hole MH, and a bit line BL. The drain-side selection line SGD includes four wiring layers SGDa, SGDb, SGDc, and SGDd.

[0058] These wiring layers SGDa to SGDd are the same as the word line WL and are stacked separately above the word line WL. A plurality of insulating layers 14 are provided between these wiring layers SGDa to SGDd. Each of the wiring layers SGDa to SGDd includes, for example, a tungsten layer. The drain-side selection line SGD of this modified example is electrically insulated from the channel semiconductor layer 24 in each memory hole MH.

[0059] The interlayer insulating film 15 is formed above the drain-side selection line SGD. The interlayer insulating film 15 is, for example, a silicon oxide film. In this modified example, each memory hole MH penetrates through the insulating layers 14, the word lines WL, and the wiring layers SGDa to SGDd of the drain-side selection line SGD, and a part of each memory hole MH is formed within the interlayer insulating film 15.

[0060] In each memory hole MH, the buried semiconductor layer 26 is formed on the core insulating film 25 and is in contact with the channel semiconductor layer 24. On each memory hole MH, the contact plug 27 is formed on the buried semiconductor layer 26 and is in contact with the buried semiconductor layer 26. As a result, Figure 5 the two contact plugs 27 shown are electrically connected to the channel semiconductor layer 24 in the corresponding memory hole MH respectively.

[0061] The bit line BL is formed on these contact plugs 27 within the interlayer insulating film 15. As a result, the bit line BL of this modified example is electrically connected to the channel semiconductor layer 24 in each memory hole MH.

[0062] As shown in Figure 5 the channel semiconductor layer 24 of this modified example includes an n-type diffusion layer on the side of the interlayer insulating film 15. This n-type diffusion layer contains n-type impurities at a high concentration. As shown inFigure 5 As shown, the channel semiconductor layer 24 of this modification further includes n － type diffusion layer. － The n-type diffusion layer is located below the above-mentioned n-type diffusion layer and contains n-type impurities in such a way that the concentration of the n-type impurities changes sharply toward the -Z direction. － The GIDL current is generated by the action of the type diffusion layer.

[0063] The semiconductor memory device of this modification applies an erase voltage V to the bit line BL. ERA , apply voltage V to the drain side selection line SGD ERA_GIDL , thereby generating a GIDL current in the channel region of the selection transistor ST1. Figure 5 The n shown － The type diffusion layer is provided in the channel region of the selection transistor ST1. Figure 5 The data in the memory cell transistor MT shown is erased by the GIDL current. Figure 5 In FIG. 1 , the bit line BL is an example of a first wiring, and the drain side selection line SGD is an example of a second wiring.

[0064] In this way, the semiconductor memory device of this modification applies the erase voltage V to the bit line BL instead of the source line SL. ERA , a voltage V is applied to the drain side selection line SGD instead of the source side selection line SGS ERA_GIDL . Reference Figure 3 as well as Figure 4 The described erasing operation can also be realized by the method of this variation.

[0065] Reference Figure 4 The problem described above may also occur in this variant. That is, if n － Since the concentration distribution of the n-type impurities in the n-type diffusion layer greatly varies for each memory hole MH, the amount of GIDL current generated greatly varies for each memory hole MH. As a result, there is a risk that the reliability of the erase operation of this variant will be reduced. Therefore, the semiconductor memory device of this variant adopts the reference Figures 6 to 8 Describes the erasing action.

[0066] Below, refer to Figures 6 to 8 , the erase operation of the first embodiment will be described in further detail. In addition, by replacing the source line SL with the bit line BL and the source side selection line SGS with the drain side selection line SGD, the reference Figures 6 to 8 The content of the description applies to Figure 5 A variation of .

[0067] Figure 6It is a graph for explaining the erasing operation of the first embodiment.

[0068] Curve C1 shows the time variation of the source line voltage during the erasing operation of the semiconductor memory device of the comparative example of the present embodiment. Curve C1' shows the time variation of the source line voltage during the erasing operation of the semiconductor memory device of the present embodiment. The semiconductor memory device of the present embodiment has substantially the same configuration as that of the semiconductor memory device of the comparative example, but performs different erasing operations as shown by curves C1 and C1'.

[0069] The source line voltage during the erasing operation refers to the erasing voltage V applied to the source line SL during the erasing operation. ERA In the following description, not only the terms "source line SL" and "erasing voltage V" ERA are used in the description of the semiconductor memory device of the present embodiment, but also other terms are used in the description of the semiconductor memory device of the comparative example. For details of these terms, refer to Figures 1 to 5 the description section.

[0070] As shown by curve C1', the erasing voltage V of the present embodiment ERA rises from zero to value V1, drops from value V1 to value V2, and then remains at value V2 (0 < V2 < V1). Value V1 is the maximum value of the erasing voltage V ERA , and value V2 is the stable value of the erasing voltage V ERA . Reference numeral t1 represents the time when the erasing voltage V of the present embodiment ERA reaches value V1, and reference numeral t2 represents the time when the erasing voltage V of the present embodiment ERA converges to value V2. Thus, the erasing voltage V of the present embodiment ERA temporarily reaches the maximum value V1 higher than the stable value V2, and then drops from the maximum value V1 to the stable value V2. Value V1 is an example of the first value, and value V2 is an example of the second value. In addition, the erasing voltage V Figure 3 shown above is more specifically the stable value V2. ERA

[0071] On the other hand, as shown by curve C1, the erasing voltage V of the comparative example ERA rises from zero to value V2 and then remains at value V2. The difference between the erasing voltage V of the comparative example ERA and the erasing voltage V of the present embodiment ERA is indicated by arrow P1. The waveform of the erasing voltage V of the present embodiment ERA is achieved by applying a jump component that causes a voltage rise, such as arrow P1, to the waveform of the erasing voltage V of the comparative example ERA .

[0072] As referred to​Figure 4 and Figure 5 As described above, if n － the concentration distribution of the n-type impurities in the n-type diffusion layer varies significantly for each memory hole MH, the amount of GIDL current generated varies significantly for each memory hole MH. Thus, there is a risk of a decrease in the reliability of the erasing operation of the present embodiment. Therefore, in the erasing operation of the present embodiment, an erasing voltage V that changes as shown by curve C1’ is used ERA . Thus, even if n － the concentration distribution of the n-type impurities in the n-type diffusion layer varies significantly for each memory hole MH, the difference in the erasing operation between different memory holes MH can be reduced. The details will be described with reference to Figure 7 it.

[0073] Figure 7 FIG. is another graph for explaining the erasing operation of the first embodiment.

[0074] Figure 7 In addition to the above-described curve C1’, curves C2, C3, and C3’ are also shown. Curve C2 shows the time variation of the channel voltage (channel potential) during the erasing operation of the semiconductor memory device of the above-described comparative example. Curve C3 also shows the time variation of the channel voltage during the erasing operation of the semiconductor memory device of the above-described comparative example. However, curve C2 shows the time variation of the channel voltage in the memory hole MH where the amount of GIDL current generated is large, and curve C3 shows the time variation of the channel voltage in the memory hole MH where the amount of GIDL current generated is small.

[0075] In addition, curve C3’ shows the time variation of the channel voltage during the erasing operation of the semiconductor memory device of the present embodiment. Among them, curve C3’ shows the time variation of the channel voltage in the memory hole MH where the amount of GIDL current generated is small, similarly to curve C3. In addition, the channel voltage during the erasing operation means the voltage applied to the channel semiconductor layer 24 during the erasing operation.

[0076] Here, the present embodiment is compared with the comparative example.

[0077] The channel voltage of the comparative example rises to a higher stable value (curve C2) in the memory hole MH where the amount of GIDL current generated is large, but only rises to a lower stable value (curve C3) in the memory hole MH where the amount of GIDL current generated is small. Reference numeral D represents the difference between the stable value of curve C2 and the stable value of curve C3. Thus, during the erasing operation of the comparative example, the stable value of the channel voltage deviates between the memory holes MH. In the comparative example, since n －The concentration distribution of the n-type impurities in the type diffusion layer varies significantly for each memory hole MH, and thus the amount of generated GIDL current varies significantly for each memory hole MH. Therefore, the deviation of the channel voltage as described above occurs (refer to the difference D).

[0078] On the other hand, for the channel voltage GIDL in the present embodiment, in the memory holes MH with a large amount of generated current, it changes as the curve C2 as in the comparative example. However, in the memory holes MH with a small amount of generated GIDL current, it changes differently from the comparative example, as the curve C3'. That is, the channel voltage GIDL in the present embodiment not only rises to a relatively high stable value (curve C2) in the memory holes MH with a large amount of generated current, but also rises to a relatively high stable value (curve C3') in the memory holes MH with a small amount of generated GIDL current. The reference sign D' represents the difference between the stable value of the curve C2 and the stable value of the curve C3'. The difference D' is smaller than the above-mentioned difference D (D' < D). Thus, according to the present embodiment, it is possible to suppress the deviation of the stable value of the channel voltage among the memory holes MH during the erasing operation.

[0079] The difference between the curve C3 of the comparative example and the curve C3' of the present embodiment is indicated by the arrow P2. In the present embodiment, the erasing voltage V ERA temporarily rises to the maximum value V1 higher than the stable value V2. The temporary rise of the erasing voltage V ERA has the effect of helping the rise of the channel voltage in the memory holes MH with a small amount of generated GIDL current. The arrow P2 shows the case where the curve C3 changes to the curve C3' by this effect. Thereby, in the present embodiment, the deviation of the stable value of the channel voltage is suppressed.

[0080] As described with reference to Figure 4 and Figure 5 if the concentration distribution of the n-type impurities in the n － -type diffusion layer varies significantly for each memory hole MH, the amount of generated GIDL current varies significantly for each memory hole MH. Thereby, there is a risk of a decrease in the reliability of the erasing operation in the present embodiment. Therefore, in the erasing operation of the present embodiment, the erasing voltage V that changes as the curve C1' is used ERA . Thereby, it is possible to help the rise of the channel voltage in the memory holes MH with a small amount of generated GIDL current, and it is possible to suppress the deviation of the stable value of the channel voltage. Thereby, according to the present embodiment, even if the concentration distribution of the n-type impurities in the n － -type diffusion layer varies significantly for each memory hole MH, it is possible to reduce the difference in the erasing operation among different memory holes MH. Thereby, it is possible to improve the reliability of the erasing operation in the present embodiment.

[0081] Figure 8It is another curve graph for explaining the erasing operation of the first embodiment.

[0082] Curve C4 shows the relationship between the threshold voltage Vth of the memory cell transistor MT in the above comparative example and the bit count. Curve C4’ shows the relationship between the threshold voltage Vth of the memory cell transistor MT in the present embodiment and the bit count. According to the present embodiment, as Figure 8 shown, the distribution of the threshold voltage Vth can be improved.

[0083] Hereinafter, referring again to Figure 6 , the further details of the erasing operation of the present embodiment will be described.

[0084] As described above, the erasing voltage V of the present embodiment ERA rises from zero to the value V1, drops from the value V1 to the value V2, and then is maintained at the value V2 (curve C1’). If the value V1 is larger than the value V2, it can also be set to any value. However, if the value V1 is too large, the waste of the erasing operation becomes large. Therefore, the value V1 is preferably set to be 2 times or less of the value V2 (V1≤2×V2), for example, preferably set to a value of 1.1 times to 1.3 times of the value V2 (1.1×V2≤V1≤1.3×V2). In addition, the value of the erasing voltage V ERA can be measured, for example, by measuring the potential of a wiring that penetrates the insulating layer 14 and the word line WL in the same manner as the channel semiconductor layer 24 and is electrically connected to the source line SL.

[0085] In addition, the erasing voltage V of the present embodiment ERA rises to the value V2 before the time t1, rises to the value V1 at the time t1, and drops to the value V2 after the time t1 (specifically, the time t2). The time from when the erasing voltage V ERA rises to the value V1 to when it drops to the value V1 can also be adjusted to any value, but if it is too long, the waste of the erasing operation becomes large. Therefore, this time is preferably adjusted to 1 μs to 100 μs, for example, preferably adjusted to several μs to several tens of μs.

[0086] As described above, the erasing voltage V of the present embodiment ERA is generated by, for example, the voltage generation circuit 6. This voltage generation circuit 6 includes, for example, a pump circuit capable of switching the output voltage between the value V1 and the value V2. In this case, the semiconductor memory device of the present embodiment can apply the erasing voltage V ERA as shown in curve C1’ to the source line SL by switching the output voltage from the voltage generation circuit 6 between the value V1 and the value V2.

[0087] As described above, the semiconductor memory device of the present embodiment applies the erasing voltage V to the source line SL ERA, so that the erase voltage V ERA rises to the value V1, drops from the value V1 to the value V2, and is maintained at the value V2. Thus, the reliability of the erase operation of the memory cell transistor MT can be improved.

[0088] As described above, several embodiments have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. The new devices and methods described in this specification can be implemented in various other ways. In addition, various omissions, substitutions, and changes can be made to the forms of the devices and methods described in this specification without departing from the gist of the invention. It is intended that the scope of the invention or the gist thereof include such forms or modifications included in the appended claims and equivalents thereof.

Claims

1. A semiconductor storage device comprising: A plurality of memory cell transistors are connected in series with each other; a source-side selection transistor connected to one end of the plurality of memory cell transistors; a source side selection line electrically connected to a control terminal of the source side selection transistor; a source line, electrically connected to a main terminal of the source side selection transistor, to which a first voltage is applied; as well as The control circuit performs an erasing operation for erasing the data stored in the plurality of memory cell transistors by repeatedly performing an erasing voltage application operation one or more times, The control circuit In a first erasing voltage application operation among the one or more erasing voltage application operations, the first voltage is applied in such a manner that the first voltage rises from an initial value to a first value, then drops from the first value to a second value greater than the initial value at a first timing, and is maintained at the second value, In the first erasing voltage application operation, a second voltage lower than the first voltage is applied to the source side selection line at the first timing.

2. The semiconductor memory device according to claim 1, The plurality of memory cell transistors include: A plurality of word lines are stacked separately from each other on the substrate; A charge storage layer is provided in the word line; as well as a semiconductor layer provided in the word line via the charge storage layer; The source line is electrically connected to the semiconductor layer.

3. The semiconductor memory device according to claim 2, The source line is disposed between the substrate and the word line.

4. The semiconductor memory device according to claim 2, The source line is arranged above the word line.

5. The semiconductor memory device according to claim 1, The first applied voltage increases from zero to the first value, then decreases from the first value to the second value, and is maintained at the second value.

6. The semiconductor memory device according to claim 1, The first value is a maximum value of the first voltage.

7. The semiconductor memory device according to claim 1, The second value is a stable value of the first voltage.

8. The semiconductor memory device according to claim 1, A first time when the first voltage reaches the first value is earlier than a second time when the first voltage converges to the second value.

9. The semiconductor memory device according to claim 1, The first value reaches a maximum value of the first voltage that is higher than a stable value of the first voltage, and decreases from the maximum value to the stable value.

10. A method for controlling a semiconductor storage device, the semiconductor storage device comprising: A plurality of memory cell transistors are connected in series with each other; a source side selection transistor is connected to one end of the plurality of memory cell transistors; a source side selection line is electrically connected to a control terminal of the source side selection transistor; and a source line is electrically connected to a main terminal of the source side selection transistor, The control method of the semiconductor storage device comprises the following steps: generating a first voltage using a control circuit, The control circuit is used to perform an erasing operation to erase the data stored in the memory cell transistor by repeatedly applying an erasing voltage one or more times. In a first erasing voltage application operation among one or more erasing voltage application operations, when performing the erasing operation to erase data stored in the plurality of memory cell transistors, the following steps are included: the control circuit applies the first voltage to the source line in such a manner that the first voltage rises from an initial value to a first value, then drops from the first value to a second value greater than the initial value at a first timing, and is maintained at the second value. In the first erasing voltage application operation, the following steps are further included: applying a second voltage smaller than the first voltage to the source side selection line at the first timing.

11. The control method of a semiconductor memory device according to claim 10, The applied first voltage rises from zero to the first value, then drops from the first value to the second value, and is maintained at the second value.

12. The control method of a semiconductor memory device according to claim 10, The first value is the maximum value of the first voltage.

13. The control method of a semiconductor memory device according to claim 10, The second value is the stable value of the first voltage.

14. The control method of a semiconductor memory device according to claim 10, A first time when the first voltage reaches the first value is earlier than a second time when the first voltage converges to the second value.

15. The control method of a semiconductor memory device according to claim 10, The first value reaches the maximum value of the first voltage that is higher than the stable value of the first voltage, and then drops from the maximum value to the stable value.

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