A silicon-based capacitor integrated structure and its preparation method

Abstract

The present invention provides a silicon-based capacitor integrated structure and a preparation method thereof, wherein the silicon-based capacitor integrated structure comprises: a substrate, an isolation layer, the isolation layer being formed on the substrate; a lower electrode layer, the lower electrode layer being arranged on the isolation layer; a step structure, the step structure being arranged on the lower electrode layer, the step structure surrounding at least one dielectric layer, the dielectric layer covering the lower electrode layer; and an upper electrode layer, the upper electrode layer covering the dielectric layer; wherein the step structure separates the bonding area of ​​the dielectric layer and the upper electrode layer. Based on the above structure, the step structure can separate the bonding area of ​​the dielectric layer and the upper electrode layer, so that the bonding area of ​​the capacitor is located outside the step structure, avoiding the bonding stress from being concentrated in the dielectric layer, thereby preventing the thin film area of ​​the capacitor from being broken down, and realizing a visual embedded capacitor structure.

Description

Technical Field

[0001] The present invention relates to a capacitor structure, and in particular to a silicon-based capacitor structure and a preparation method thereof. Background Art

[0002] Semiconductor lasers are widely used in optical communications, optical pumping, optical storage, laser display and other fields due to their advantages of simple production, small size, light weight, long service life and high efficiency.

[0003] Current semiconductor lasers are typically packaged using TO sockets. Inside traditional TOs, the laser chip heat sink is an aluminum nitride thin-film circuit, connecting components like capacitors and resistors to the chip via wire bonding. Leveraging mature silicon processes, high-frequency TO substrates can be designed and implemented, enabling the integration of components like resistors and capacitors, saving materials and simplifying the TO assembly process.

[0004] However, silicon-based integrated capacitors are thin-film capacitors, typically with a dielectric layer between metals, typically less than 1 micron thick. Thin-film capacitors are not suitable for wire bonding processes, as the stress from the bonding process can damage the thin dielectric layer, causing capacitor failure or long-term reliability issues. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: to provide a silicon-based capacitor integrated structure and its preparation method in view of the technical defect in the prior art that the wire bonding stress damages the dielectric layer during the wire bonding process of silicon-based thin film capacitors, resulting in capacitor failure.

[0006] To solve the above technical problems, the present invention provides a silicon-based capacitor integrated structure, comprising: a substrate, an isolation layer, the isolation layer being formed on the substrate; a lower electrode layer, the lower electrode layer being arranged on the isolation layer; a step structure, the step structure being arranged on the lower electrode layer, the step structure being surrounded by at least one dielectric layer, the dielectric layer being covered on the lower electrode layer; and an upper electrode layer, the upper electrode layer being covered on the dielectric layer; wherein the step structure separates the wiring area of ​​the dielectric layer and the upper electrode layer.

[0007] The silicon-based capacitor integrated structure provided by the present invention may also have the following feature: the area of ​​the lower electrode layer and the area of ​​the upper electrode layer are both larger than the dielectric layer.

[0008] The silicon-based capacitor integrated structure provided by the present invention may also have the following feature: the lower electrode layer is connected to leads connected to external electrical components, and the leads form a bonding area of ​​the lower electrode layer.

[0009] The silicon-based capacitor integrated structure provided by the present invention may also have the following feature: an opening area is provided at a position on the step structure corresponding to the lead.

[0010] The silicon-based capacitor integrated structure provided by the present invention may also have the following feature: the wiring area of ​​the upper electrode layer is separated from the lower electrode layer.

[0011] The silicon-based capacitor integrated structure provided by the present invention may also have the following feature: the materials of the step structure and the dielectric layer are silicon dioxide, silicon nitride, zirconium oxide, or hafnium oxide.

[0012] The silicon-based capacitor integrated structure provided by the present invention may also have the following features: the material of the dielectric layer is silicon nitride; the material of the step structure is silicon dioxide, and the height is 500 angstroms to 2 microns.

[0013] The silicon-based capacitor integrated structure provided by the present invention may also have the following features: the substrate is made of silicon, glass or ceramic, and the isolation layer is a silicon dioxide film with a thickness of 0.2 micrometers to 1 micrometer.

[0014] The silicon-based capacitor integrated structure provided by the present invention may also have the following characteristics: the lower electrode layer is made of aluminum, copper, gold, silver, polysilicon or single crystal silicon, and has a thickness of 0.1 micron to 1 micron.

[0015] The silicon-based capacitor integrated structure provided by the present invention may also have the following feature: the upper electrode layer is one or more of gold, titanium, aluminum, copper and silver.

[0016] The present invention also provides a method for preparing a silicon-based capacitor integrated structure, comprising the following steps: selecting a substrate; forming an isolation layer on the silicon substrate; forming a lower electrode layer on the isolation layer, and forming a lower electrode and a lead on the lower electrode layer; forming a step structure on the lower electrode layer, and depositing a dielectric layer within the encirclement of the step structure; etching a lead area of ​​the lower electrode on the lower electrode layer; and depositing an upper electrode layer on the dielectric layer.

[0017] The method for preparing the silicon-based capacitor integrated structure provided by the present invention may also have the following features: forming a lower electrode and leads on the lower electrode layer by an evaporation stripping process; forming a step structure by photolithography and etching; etching the lead area of ​​the lower electrode by photolithography and etching; and depositing an upper electrode layer on the dielectric layer by photolithography and metal stripping.

[0018] The beneficial effects of the present invention are:

[0019] In the silicon-based capacitor integrated structure of the present invention, an isolation layer is formed on the substrate, and then a lower electrode layer is arranged on the isolation layer. A step structure is arranged on the lower electrode layer, and the step structure is surrounded by a dielectric layer. The upper electrode layer covers the dielectric layer. Based on the above structure, the step structure can separate the wiring area of ​​the dielectric layer and the upper electrode layer, so that the wiring area of ​​the capacitor is located outside the step structure, avoiding the wiring stress from being concentrated in the dielectric layer, thereby avoiding the occurrence of breakdown of the thin film area of ​​the capacitor, and realizing a visual embedded capacitor structure.

[0020] In addition, the area of ​​the lower electrode layer is larger than that of the dielectric layer, and is connected to a lead wire that can be connected to other components. The lead wire portion serves as a bonding area of ​​the lower electrode layer, which is separated from the dielectric layer.

[0021] In addition, the step structure is surrounded by the outside of the dielectric layer, and an opening area is provided at a position corresponding to the lead of the lower electrode layer to achieve the connection between the lead and other components.

[0022] Furthermore, the height of the step structure ranges from 500 angstroms to 2 microns, which allows the bonding area of ​​the top electrode layer to be separated from the dielectric layer.

[0023] In addition, after the upper electrode layer is covered on the dielectric layer, since the area of ​​the upper electrode layer is larger than that of the dielectric layer, the step structure is clearly visible under a microscope.

[0024] In the preparation method of the silicon-based capacitor integrated structure provided by the invention, a substrate is selected; an isolation layer is formed on the silicon substrate; a lower electrode layer is formed on the isolation layer, and a lower electrode and a lead are formed on the lower electrode layer; a step structure is formed on the lower electrode layer, and a dielectric layer is deposited within the encirclement of the step structure; a lead area of ​​the lower electrode is etched on the lower electrode layer; and an upper electrode layer is deposited on the dielectric layer. This preparation method can realize the integration of heat sinks, resistors, embedded capacitors, high-frequency digital displays, gold-tin pads, etc. into a single chip, and has the characteristics of small size, small temperature drift, and easy integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a cross-sectional view of a silicon-based capacitor integrated structure in an embodiment of the present invention;

[0026] Figure 2 FIG. 4 is a top view of a silicon-based capacitor integrated structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] like Figures 1-2 As shown, the silicon-based capacitor integrated structure in this embodiment includes a substrate 10 , an isolation layer 20 , a lower electrode layer 30 , a step structure 40 , a dielectric layer 50 , and an upper electrode layer 60 .

[0029] The substrate 10 is made of silicon, glass or ceramic. In this embodiment, the substrate 10 is made of silicon.

[0030] The isolation layer 20 is formed on the substrate 10. The isolation layer 20 is made of a silicon dioxide film with a thickness of 0.2 to 1 μm. This allows the isolation layer 20 to have a similar thermal expansion coefficient to the substrate 10 and both are good insulating materials.

[0031] The lower electrode layer 30 is formed on the isolation layer 20. The lower electrode layer 30 is made of aluminum, copper, gold, silver, polysilicon, or single crystal silicon. In this embodiment, the lower electrode layer 30 is made of aluminum. The thickness of the lower electrode layer 30 is 0.1 to 1 μm.

[0032] The lower electrode layer 30 is connected to a lead 31, which is connected to other components that need to be connected. The lead 31 is the wiring area of ​​the lower electrode.

[0033] The stepped structure 40 is disposed above the lower electrode layer 30 , and its area is larger than that of the lower electrode layer 30 , covering the boundary of the lower electrode layer 30 . The stepped structure 40 surrounds the dielectric layer 50 .

[0034] The materials of the step structure 40 and the dielectric layer 50 are thin films of silicon dioxide, silicon nitride, zirconium oxide, hafnium oxide, etc. However, in practical applications or other embodiments, other insulating materials may be selected as required.

[0035] The height of the step structure 40 is 500 angstroms to 2 microns. The thickness of the dielectric layer 50 can be designed according to the actual capacitance requirements.

[0036] An opening area is provided at a position on the step structure 40 corresponding to the lead 31 , and the opening area can realize the connection between the lead 31 and the component.

[0037] The area of ​​the lower electrode layer 30 and the area of ​​the upper electrode layer 60 are both larger than the area of ​​the dielectric layer 50 .

[0038] The upper electrode layer 60 covers the dielectric layer 50 and has an area larger than that of the dielectric layer 50. The bonding area 61 of the upper electrode layer 60 is outside the stepped structure 40. The bonding area 61 is separated from the bonding area of ​​the lower electrode layer 30, that is, the bonding area of ​​the upper electrode layer 60 does not overlap with the lead 31 of the lower electrode layer 30 (i.e., the bonding area of ​​the lower electrode layer).

[0039] The material selected for the upper electrode layer 60 is one or more of gold, titanium, aluminum, copper and silver. After the upper electrode layer 60 is covered, the step structure 40 can be clearly seen under a microscope.

[0040] In the silicon-based capacitor integrated structure of this embodiment, the upper electrode layer 60 , the dielectric layer 50 and the lower electrode layer 30 constitute an effective capacitor region of the silicon-based capacitor integrated structure.

[0041] The method for preparing the above-mentioned silicon-based capacitor integrated structure comprises the following steps:

[0042] A silicon substrate 10 is selected;

[0043] An insulating isolation layer 20 is formed on the surface of the silicon substrate 10. The isolation layer 20 is a silicon dioxide film with a thickness of 0.3 μm.

[0044] Aluminum is selected as the lower electrode layer 30 formed on the isolation layer 20, and the lead 31 is formed on the lower electrode layer 20 by evaporation stripping process. The thickness of the lower electrode layer 30 is 3000 angstroms.

[0045] A layer of silicon dioxide with a thickness of 3000 angstroms is deposited on the lower electrode layer 30, and a capacitor region is etched out on the silicon dioxide by photolithography and etching to expose the lower electrode metal of the lower electrode layer 30, thereby forming a step structure 40;

[0046] Then, a silicon nitride film with a thickness of 500 angstroms is deposited within the stepped structure 40 as a dielectric layer 50;

[0047] Using photolithography and etching methods, a lead 31 of the lower electrode is etched on the lower electrode layer 30;

[0048] Then, a gold upper electrode layer 60 is deposited on the silicon nitride film using photolithography and metal lift-off methods. After the upper electrode layer 60 is deposited, the upper electrode layer 60 is bounded by the step structure 40 to form a bonding area 61 of the upper electrode layer 60 .

[0049] During the packaging process of the silicon-based capacitor integrated structure prepared based on the above preparation method, the lower electrode layer 30 of the capacitor is led out through the lead 31, and the wire bonding can be done in the lead area; the upper electrode layer 60 is distinguished from the capacitor area by a clear step structure 40, and the wire bonding is outside the step structure 40, which can avoid the wire bonding stress being concentrated in the capacitor film area.

[0050] According to the silicon-based capacitor integrated structure in the above embodiment, an isolation layer is formed on the substrate, and then a lower electrode layer is arranged on the isolation layer, and a step structure is arranged on the lower electrode layer, and the step structure is surrounded by a dielectric layer, and the upper electrode layer is covered on the dielectric layer. Based on the above structure, the step structure can separate the wiring area of ​​the dielectric layer and the upper electrode layer, so that the wiring area of ​​the capacitor is located outside the step structure, avoiding the wiring stress concentration in the dielectric layer, thereby avoiding the occurrence of breakdown of the thin film area of ​​the capacitor, and realizing a visual embedded capacitor structure.

[0051] In addition, the area of ​​the lower electrode layer is larger than that of the dielectric layer, and is connected to a lead wire that can be connected to other components. The lead wire portion serves as a bonding area of ​​the lower electrode layer, which is separated from the dielectric layer.

[0052] In addition, the step structure is surrounded by the outside of the dielectric layer, and an opening area is provided at a position corresponding to the lead of the lower electrode layer to achieve the connection between the lead and other components.

[0053] Furthermore, the height of the step structure ranges from 500 angstroms to 2 microns, which allows the bonding area of ​​the top electrode layer to be separated from the dielectric layer.

[0054] In addition, after the upper electrode layer is covered on the dielectric layer, since the area of ​​the upper electrode layer is larger than that of the dielectric layer, the step structure is clearly visible under a microscope.

[0055] In the preparation method of the silicon-based capacitor integrated structure provided by the invention, a substrate is selected; an isolation layer is formed on the silicon substrate; a lower electrode layer is formed on the isolation layer, and a lower electrode and a lead are formed on the lower electrode layer; a step structure is formed on the lower electrode layer, and a dielectric layer is deposited within the encirclement of the step structure; a lead area of ​​the lower electrode is etched on the lower electrode layer; and an upper electrode layer is deposited on the dielectric layer. This preparation method can realize the integration of heat sinks, resistors, embedded capacitors, high-frequency digital displays, gold-tin pads, etc. into a single chip, and has the characteristics of small size, small temperature drift, and easy integration.

[0056] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A silicon-based capacitor integrated structure, characterized in that: include: substrate, an isolation layer formed on the substrate; a lower electrode layer, the lower electrode layer being arranged on the isolation layer; a step structure, the step structure being arranged on the lower electrode layer, the step structure being surrounded by at least one dielectric layer, and the dielectric layer covering the lower electrode layer; an upper electrode layer, the upper electrode layer covering the dielectric layer, the upper electrode layer having an area larger than that of the dielectric layer; The step structure separates the dielectric layer and the bonding area of ​​the upper electrode layer. The bonding area of ​​the upper electrode layer is formed above the step structure, The wiring area of ​​the lower electrode layer is formed on the lead connecting the lower electrode layer and the external electrical components. The bonding area of ​​the upper electrode layer does not overlap with the bonding area of ​​the lower electrode layer.

2. The silicon-based capacitor integrated structure according to claim 1, wherein: The area of ​​the lower electrode layer and the area of ​​the upper electrode layer are both larger than that of the dielectric layer.

3. The silicon-based capacitor integrated structure according to claim 1, wherein: An opening area is formed on the step structure at a position corresponding to the lead.

4. The silicon-based capacitor integrated structure according to claim 1, wherein: The wiring area of ​​the upper electrode layer is separated from the lower electrode layer.

5. The silicon-based capacitor integrated structure according to claim 1, wherein: The step structure and the dielectric layer are made of silicon dioxide, silicon nitride, zirconium oxide, or hafnium oxide.

6. The silicon-based capacitor integrated structure according to claim 5, wherein: The material of the dielectric layer is silicon nitride; The step structure is made of silicon dioxide and has a height of 500 angstroms to 2 microns.

7. The silicon-based capacitor integrated structure according to claim 1, wherein: The substrate is made of silicon, glass or ceramic. The isolation layer is a silicon dioxide film with a thickness of 0.2 microns to 1 micron.

8. The silicon-based capacitor integrated structure according to claim 1, wherein: The lower electrode layer is made of aluminum, copper, gold, silver, polycrystalline silicon or single crystal silicon, and has a thickness of 0.1 micron to 1 micron.

9. The silicon-based capacitor integrated structure according to claim 1, wherein: The upper electrode layer is made of one or more of gold, titanium, aluminum, copper and silver.

10. A method for preparing a silicon-based capacitor integrated structure, for preparing the silicon-based capacitor integrated structure according to any one of claims 1 to 9, characterized in that: The following steps are involved: Select substrate; forming an isolation layer on the substrate; forming a lower electrode layer on the isolation layer, and forming a lower electrode and a lead on the lower electrode layer; forming a step structure on the lower electrode layer, and depositing a dielectric layer within the area surrounded by the step structure; Etching a lead area of ​​the lower electrode on the lower electrode layer; An upper electrode layer is deposited on the dielectric layer.

11. The method for preparing a silicon-based capacitor integrated structure according to claim 10, wherein: forming a lower electrode and a lead on the lower electrode layer by adopting an evaporation stripping process; A step structure is formed by photolithography and etching; Etching the lead area of ​​the lower electrode by photolithography and etching; An upper electrode layer is deposited on the dielectric layer by using photolithography and metal lift-off methods.

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