Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate and a fin protruding from the substrate; forming an isolation layer on the substrate exposed by the fin, the isolation layer covering part of the sidewall of the fin; forming a protective dielectric layer on the top of the isolation layer; after forming the protective dielectric layer, forming a dummy gate structure across the fin, the dummy gate structure covering part of the top and part of the sidewall of the fin. After forming the isolation layer on the substrate exposed by the fin, the present application forms a protective dielectric layer on the top of the isolation layer before forming the dummy gate structure, which can protect the isolation layer when the dummy gate structure is removed later, thereby reducing the probability of the isolation layer being damaged, and further reducing the impact on the height of the effective fin and improving the height uniformity of the effective fin, which is conducive to improving the performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In semiconductor manufacturing, with the development trend of ultra-large scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to the decrease of the feature size, the channel length of MOSFET is also shortened accordingly. However, with the shortening of the device channel length, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is also increasing, making the subthreshold leakage phenomenon, i.e. the so-called short-channel effects (SCE) more likely to occur.

[0003] Therefore, in order to better adapt to the decrease of the feature size, the semiconductor process gradually starts to transition from the planar MOSFET to the three-dimensional transistor with higher efficiency, such as the FinFET. In the FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides, compared with the planar MOSFET, the control ability of the gate structure to the channel is stronger, and the short-channel effects can be well suppressed; and the FinFET has better compatibility with the existing integrated circuit manufacturing than other devices. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, to improve the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present application provide a forming method of a semiconductor structure, comprising: providing a substrate and a fin protruding from the substrate; forming an isolation layer on the substrate exposed by the fin, the isolation layer covering part of the sidewall of the fin; forming a protective dielectric layer on the top of the isolation layer; after forming the protective dielectric layer, forming a dummy gate structure across the fin, the dummy gate structure covering part of the top and part of the sidewall of the fin.

[0006] Correspondingly, embodiments of the present application also provide a semiconductor structure, comprising: a substrate; a fin protruding from the substrate; an isolation layer located on the substrate exposed by the fin, the isolation layer covering part of the sidewall of the fin; a protective dielectric layer located on the top of the isolation layer; a dummy gate structure located on the protective dielectric layer and across the fin, the dummy gate structure covering part of the top and part of the sidewall of the fin.

[0007] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0008] After the isolation layer is formed on the substrate exposed by the fin, the protective medium layer is formed on the top of the isolation layer before the pseudo-gate structure is formed, and when the pseudo-gate structure is removed subsequently, the protective medium layer can play a role in protecting the isolation layer, thereby reducing the probability of damage to the isolation layer, and further facilitating reduction of the influence on the height of the effective fin and improvement of the height uniformity of the effective fin, and accordingly facilitating improvement of the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figures 1-2 is a structure diagram corresponding to each step in a method for forming a semiconductor structure.

[0010] Figures 3-13 is a structure diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0011] The performance of the semiconductor structure needs to be improved at present. The reasons why the performance of the semiconductor structure still needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0012] Figures 1-2 is a structure diagram corresponding to each step in a method for forming a semiconductor structure.

[0013] Reference Figure 1 , a substrate 10 and a fin 11 protruding from the substrate 10 are provided, an isolation layer 15 is formed on the substrate 10 exposed by the fin 11, and the isolation layer 150 covers part of the sidewall of the fin 11.

[0014] Reference Figure 2 After the isolation layer 15 is formed, a pseudo-gate structure 20 is formed across the fin 11, and the pseudo-gate structure 20 covers part of the top and part of the sidewall of the fin 11.

[0015] Subsequent processes further include: forming source-drain doped regions in the fin 11 on both sides of the pseudo-gate structure 20; forming an interlayer dielectric layer covering the source-drain doped regions, the interlayer dielectric layer covering the sidewall of the pseudo-gate structure; after the interlayer dielectric layer is formed, the pseudo-gate structure 20 is removed, and a gate opening is formed in the interlayer dielectric layer; and a metal gate structure is formed in the gate opening.

[0016] When the fins 11 on the substrate 10 have different pattern densities (for example, some fins 11 are provided with other fins 11 on both sides, and some fins 11 are provided with other fins 11 on only one side), in the process of removing the dummy gate structure 20, under the influence of the loading effect, the removal rate of the dummy gate structure 20 in the pattern density area is faster, and when the top of the isolation layer 15 is exposed, the isolation layer 15 is prone to be damaged, thereby affecting the height of the effective fin, and further affecting the performance of the semiconductor structure. The effective fin refers to the part of the fin 11 covered by the device gate structure (for example, the metal gate structure).

[0017] Moreover, under the influence of the loading effect, the amount of damage to the isolation layer 15 is difficult to control, thereby causing the height uniformity of the effective fin to be poor, which in turn affects the performance of the semiconductor structure.

[0018] In addition, when the dummy gate structure 20 includes a gate oxide layer (not shown in the figure) covering the surface of the fin 11, and a dummy gate layer (not shown in the figure) covering the gate oxide layer and spanning the fin 11, the material of the gate oxide layer and the isolation layer 15 is usually the same, so when the gate oxide layer is removed, the isolation layer 15 is also etched, thereby further worsening the damage to the isolation layer 15, and further reducing the height uniformity of the effective fin.

[0019] Especially, when the Certas etching process is used to remove the gate oxide layer, the process temperature of the Certas etching process is relatively low, thereby easily causing the etching rate uniformity of the isolation layer 15 to be poor, and further reducing the height uniformity of the effective fin.

[0020] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, which comprises the following steps: providing a substrate and a fin protruding from the substrate; forming an isolation layer on the substrate exposed by the fin, the isolation layer covering part of the sidewall of the fin; forming a protective medium layer on the top of the isolation layer; after forming the protective medium layer, forming a dummy gate structure spanning the fin, the dummy gate structure covering part of the top and part of the sidewall of the fin.

[0021] The embodiment of the present application forms the isolation layer on the substrate exposed by the fin, and then forms the protective medium layer on the top of the isolation layer before forming the dummy gate structure. When the dummy gate structure is removed subsequently, the protective medium layer can protect the isolation layer, thereby reducing the probability of damage to the isolation layer, and further reducing the influence on the height of the effective fin and improving the height uniformity of the effective fin, which in turn helps to improve the performance of the semiconductor structure.

[0022] In order to make the above objectives, characteristics and advantages of the present application more obvious and comprehensible, specific embodiments of the present application are described in detail below with reference to the drawings.

[0023] Figures 3-13 is a structure diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application.

[0024] Reference Figure 3 A substrate is provided, including a substrate 100 and a fin 110 protruding from the substrate 100.

[0025] The substrate 100 is used to provide a process platform for subsequent processes.

[0026] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0027] In this embodiment, the fin 110 and the substrate 100 are an integral structure. In other embodiments, the fin can also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin 110.

[0028] Therefore, the material of the fin 110 is the same as that of the substrate 100, and the material of the fin 110 is silicon. In other embodiments, the material of the fin can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or other semiconductor materials suitable for forming a fin, and the material of the fin can also be different from that of the substrate.

[0029] In this embodiment, the substrate 100 includes a device unit area (not labeled) for forming a device, and an isolation area (not labeled) for isolating adjacent device unit areas, and a plurality of fins 110 are formed on the substrate 100 in the device unit area. As an example, Figure 3 One device unit area is shown in the figure.

[0030] The fins 110 on the substrate 100 have different pattern densities. For example, in the device unit area, the fins 110 at the edge (i.e., the fins 110 closest to the isolation area) are provided with other fins 110 on only one side, and the remaining fins 110 are provided with other fins 110 on both sides, so the fins 110 in the device unit area also have different pattern densities. In other embodiments, the pattern densities of the fins in different device unit areas can also be different.

[0031] The substrate 100 generally includes a core region for forming core devices, and a peripheral region for forming input / output devices. Among them, the core devices mainly refer to devices used inside the chip, generally using a lower voltage (generally 1.0V, 1.2V, 1.5V and 1.8V), and the input / output devices are devices used when the chip interfaces with the outside, and the working voltage of such devices is generally higher, and depends on the compatible working voltage of the external interface (generally 1.8V, 2.5V, 3.3V and 5V). As an example, the present embodiment only schematically shows the core region.

[0032] In the present embodiment, a hard mask layer 130 is formed on the top of the fin 110, which serves as an etching mask when the fin 110 is formed. In the subsequent planarization process, the surface of the hard mask layer 130 can be used to define the stop position of the planarization process, and the hard mask layer 130 can also play a role in protecting the fin 110.

[0033] Specifically, the material of the hard mask layer 130 is silicon nitride.

[0034] In the present embodiment, a stress buffer layer 120 is further formed between the hard mask layer 130 and the fin 110.

[0035] The stress buffer layer 120 is used to provide a stress buffering effect when the hard mask layer 130 is formed, and to improve the problem of dislocation generated when the hard mask layer 130 is formed.

[0036] In the present embodiment, the material of the stress buffer layer 120 is silicon oxide.

[0037] In combination with reference Figures 4-6 An isolation layer 150 is formed on the substrate 100 exposed by the fin 110, which covers part of the sidewall of the fin 110.

[0038] The isolation layer 150 serves as a shallow trench isolation structure (STI) for isolating adjacent devices.

[0039] In the present embodiment, the material of the isolation layer 150 is silicon oxide. In other embodiments, the material of the isolation layer can also be silicon nitride, silicon oxynitride or other insulating materials.

[0040] Specifically, the step of forming the isolation layer 150 includes:

[0041] As shown in Figure 4 An initial isolation layer 140 is formed on the substrate 100 exposed by the fin 110, and the top surface of the initial isolation layer 140 is flush with the top surface of the hard mask layer 130.

[0042] The initial isolation layer 140 is used to provide a process basis for the subsequent formation of the isolation layer.

[0043] In this embodiment, a layer of isolation material is deposited on the substrate 100 exposed by the fin 110, and the layer of isolation material also covers the hard mask layer 130. The layer of isolation material is planarized (for example, a chemical mechanical polishing process) with the top surface of the hard mask layer 130 as a stop position, so as to form the initial isolation layer 140.

[0044] In this embodiment, the material of the initial isolation layer 140 is silicon oxide.

[0045] As shown in Figure 5 The hard mask layer 130 is removed.

[0046] During the etching back of the initial isolation layer 140, the stress buffer layer 120 is prone to be etched. Therefore, by removing the hard mask layer 130 first, the problem of collapse of the hard mask layer 130 during the etching back of the initial isolation layer 140 is avoided.

[0047] Specifically, the hard mask layer 130 is removed by using a wet etching process, so that the hard mask layer 130 can be completely removed.

[0048] As shown in Figure 6 The initial isolation layer 140 is etched back, so that the top surface of the remaining initial isolation layer 140 is lower than the top surface of the fin 110, and the remaining initial isolation layer 140 serves as the isolation layer 150.

[0049] In this embodiment, the initial isolation layer 140 is etched back by using a Certas etching process. The process temperature of the Certas etching process is relatively low, and the etching rate is relatively slow, so that the etching amount can be accurately controlled.

[0050] In other embodiments, the initial isolation layer 140 can also be etched back by using a SiCoNi etching process. The etching selectivity of the SiCoNi etching process is relatively high.

[0051] It should be noted that a protective dielectric layer will be subsequently formed on the top of the isolation layer 150, and the protective dielectric layer will also cover part of the sidewall of the fin 110. Therefore, in order to make the height of the effective fin meet the process requirements, the thickness of the isolation layer 150 can be appropriately reduced. The effective fin refers to the part of the fin 110 that is covered by the device gate structure (for example, a metal gate structure).

[0052] Referring to Figure 7 A protective dielectric layer 200 is formed on the top of the isolation layer 150.

[0053] Subsequently, a process of forming a dummy gate structure and a process of removing the dummy gate structure are further included. When the dummy gate structure is removed, the protective medium layer 200 can play a role in protecting the isolation layer 150, thereby reducing the probability of the isolation layer 150 being damaged, and further facilitating reduction of the impact on the height of the effective fin and improvement of the height uniformity of the effective fin, and accordingly facilitating improvement of the performance of the semiconductor structure.

[0054] Therefore, the etching resistance of the protective medium layer 200 is greater than that of the isolation layer 150.

[0055] In addition, the protective medium layer 200 located on the isolation layer 150 is subsequently retained, so that the step of removing the protective medium layer 200 is not performed, thereby further reducing the probability of the isolation layer 150 being damaged. Therefore, the material of the protective medium layer 200 is an insulating material, and has good process compatibility.

[0056] To this end, the material of the protective medium layer 200 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon carbon oxynitride, boron nitride, boron carbon nitride, and silicon boron carbon nitride.

[0057] In this embodiment, the deposition process is used to form the protective medium layer 200, thereby improving the process compatibility of forming the protective medium layer 200 and reducing the process difficulty. Therefore, in the step of forming the protective medium layer 200 on the top of the isolation layer 150, the protective medium layer 200 conformally covers the isolation layer 150 and the fin 110. Subsequently, the sidewall of the fin 110 can be exposed by etching the protective medium layer 200.

[0058] In this embodiment, the process of forming the protective medium layer 200 includes an atomic layer deposition process. By using the atomic layer deposition process, the thickness uniformity of the protective medium layer 200 is improved, and the protective medium layer 200 has good step coverage, so that the protective medium layer 200 can well cover the corner of the fin 110 and the isolation layer 150.

[0059] It should be noted that the thickness (not indicated) of the protective medium layer 200 should not be too small or too large. If the thickness of the protective medium layer 200 is too small, the thickness of the protective medium layer 200 can not effectively protect the isolation layer 150, and in the subsequent process of removing the dummy gate structure, the probability of the isolation layer 150 being damaged is still high. As the feature size of the integrated circuit continues to decrease, the distance between adjacent fins 110 becomes smaller. If the thickness of the protective medium layer 200 is too large, the protective medium layer 200 on the sidewall of the adjacent fin 110 can be in contact, thereby causing adverse effects on the subsequent process. Therefore, in this embodiment, the thickness of the protective medium layer 200 is to For example, the thickness of the protective medium layer 200 is or

[0060] In this embodiment, the protective medium layer 200 includes a bottom protective medium layer 210 and a top protective medium layer 220 covering the bottom protective medium layer 210, and the density of the bottom protective medium layer 210 is greater than that of the top protective medium layer 220.

[0061] On the one hand, the density of the bottom protective medium layer 210 is greater, and thus the etching resistance of the bottom protective medium layer 210 is greater than that of the top protective medium layer 220, so that the protective effect of the protective medium layer 200 on the isolation layer 150 is guaranteed.

[0062] On the other hand, the thickness of the bottom protective medium layer 210 is smaller compared with the total thickness of the protective medium layer 200, and thus this is conducive to reducing the influence of the process of forming the bottom protective medium layer 210 on the fin 110, and the density of the bottom protective medium layer 210 is greater than that of the top protective medium layer 220, so that the bottom protective medium layer 210 can protect the fin 110 in the process of forming the top protective medium layer 220, thereby reducing the influence of the process of forming the top protective medium layer 220 on the fin 110 (for example, the bottom protective medium layer 210 is conducive to blocking the reaction gas for forming the top protective medium layer 220 from contacting the fin 110).

[0063] In summary, the embodiment forms the protective medium layer 200 with a stacked structure, thereby guaranteeing the performance of the protective medium layer 200 while reducing the influence on the fin 110, so as to be conducive to further improving the performance of the semiconductor structure.

[0064] In this embodiment, the material of the bottom protective medium layer 210 is silicon rich oxide (SRO), and the material of the top protective medium layer 220 is silicon oxide. The silicon rich oxide refers to a silicon oxide material with a high silicon content, so that the density and etching resistance of the bottom protective medium layer 210 are higher.

[0065] The process compatibility of the silicon rich oxide and the silicon oxide is high, and they have similar lattice constants with silicon, which can improve the stress problem and thus reduce the probability of deformation of the fin 110.

[0066] In addition, compared with the silicon oxide layer, more fins 110 are consumed in forming the silicon rich oxide layer under the same thickness, but the density and etching resistance of the silicon oxide layer are higher, and thus by selecting the silicon rich oxide layer and the silicon oxide layer stacked from bottom to top, the performance of the protective medium layer 200 is guaranteed while the consumption of the fin 110 is reduced.

[0067] In this embodiment, the bottom protection medium layer 210 is formed by using a chemical vapor deposition process. The material of the bottom protection medium layer 210 is silicon-rich silicon oxide, and by using the chemical vapor deposition process, the atomic percentage of silicon in the silicon-rich silicon oxide can be easily controlled. Specifically, during the chemical vapor deposition process, the atomic percentage of silicon in the silicon-rich silicon oxide is adjusted by adjusting the gas flow of the silicon-containing reaction gas.

[0068] In this embodiment, the top protection medium layer 220 is formed by using an atomic layer deposition process to improve the thickness uniformity and step coverage of the top protection medium layer 220.

[0069] It should be noted that the atomic percentage of silicon in the silicon-rich silicon oxide in the bottom protection medium layer 210 should not be too small or too large. If the atomic percentage of silicon is too low, under the condition that the thickness T1 of the bottom protection medium layer 210 is constant, it is difficult to meet the process requirements of the etching resistance and density of the bottom protection medium layer 210; if the atomic percentage of silicon is too high, the insulation performance of the bottom protection medium layer 210 will be poor, which will adversely affect the performance of the device. Therefore, in this embodiment, the atomic percentage of silicon in the silicon-rich silicon oxide is 30% to 60%.

[0070] By using the silicon oxide material, the process compatibility of the protection medium layer 200 is improved, the process difficulty of forming the protection medium layer 200 is reduced, and the stress generated by the protection medium layer 200 on the fin 110 is small, which can reduce the probability of deformation of the fin 110.

[0071] The thickness T1 of the bottom protection medium layer 210 should not be too small or too large. If the thickness T1 of the bottom protection medium layer 210 is too small, in order to ensure the performance of the protection medium layer 200, the thickness T2 of the top protection medium layer 220 needs to be increased, and because the thickness T1 of the bottom protection medium layer 210 is small, the protection effect of the bottom protection medium layer 210 on the fin 110 is poor during the formation of the top protection medium layer 220, which will easily affect the fin 110, and in the process of removing the dummy gate structure, if the top protection medium layer 220 is removed, the bottom protection medium layer 210 is exposed, and the bottom protection medium layer 210 with a small thickness T1 may not be able to protect the isolation layer 150. Therefore, in this embodiment, the thickness T1 of the bottom protection medium layer 210 is 5 nm to 20 nm. to For example, the thickness T1 of the bottom protection medium layer 210 is 5 nm to 20 nm. or

[0072] The thickness T2 of the top protection medium layer 220 should not be too small or too large. If the thickness T2 of the top protection medium layer 220 is too small, the total thickness of the protection medium layer 200 is likely to be too small, thereby reducing the protection effect of the protection medium layer 200 on the isolation layer 150, or in order to make the total thickness of the protection medium layer 200 meet the performance requirements, the thickness T1 of the bottom protection medium layer 210 needs to be increased accordingly, thereby the process of forming the bottom protection medium layer 210 is likely to have an adverse effect on the fin 110; if the thickness T2 of the top protection medium layer 220 is too large, the thickness T1 of the bottom protection medium layer 210 is likely to be too small, and in the process of forming the top protection medium layer 220, the bottom protection medium layer 210 has a poor protection effect on the fin 110, thereby the process of forming the top protection medium layer 220 is likely to have an impact on the fin 110, and in the process of removing the dummy gate structure, if the top protection medium layer 220 is removed, the bottom protection medium layer 210 is exposed, and the bottom protection medium layer 210 with a small thickness T1 may not be able to protect the isolation layer 110. Therefore, in the embodiment, the thickness T2 of the top protection medium layer 220 is to For example, the thickness T2 of the top protection medium layer 220 is or

[0073] In combination with reference to Figure 8 and Figure 9 , after the protection medium layer 200 is formed, the sacrificial layer 160 is formed on the protection medium layer 200 located above the isolation layer 150 (as shown in Figure 8 , and the top of the sacrificial layer 160 is lower than the top of the fin 110.

[0074] The sacrificial layer 160 is used to protect the protection medium layer 200 located above the isolation layer 150, and when the protection medium layer 200 exposed by the sacrificial layer 160 is removed later, the protection medium layer 200 located above the isolation layer 150 can be reserved.

[0075] The materials of the protection medium layer 200 and the sacrificial layer 160 are different, and the protection medium layer 200 and the sacrificial layer 160 have a large etching selectivity, thereby when the protection medium layer 200 exposed by the sacrificial layer 160 is removed later, the sacrificial layer 160 can protect the protection medium layer 200 located above the isolation layer 150. Moreover, the sacrificial layer 160 needs to be removed later, therefore, the sacrificial layer 160 is selected to be made of a material that is easy to be removed, and the process of removing the sacrificial layer 160 has a small damage to the protection medium layer 200 and the fin 110.

[0076] Therefore, the material of the sacrificial layer 160 includes one or more of spin on carbon (SOC), an organic dielectric layer (ODL) material, and a bottom anti-reflective coating (BARC) material. In this embodiment, the material of the sacrificial layer 160 is spin on carbon. Spin on carbon has low cost, simple forming process, and high process compatibility.

[0077] Specifically, the step of forming the sacrificial layer 160 includes: forming a sacrificial material layer 165 covering the protective dielectric layer 200, as shown in FIG. 2B; and Figure 8 Figure 9 As shown in FIG. 2C, a portion of the thickness of the sacrificial material layer 165 is etched back, so that the top of the remaining sacrificial material layer 165 is lower than the top of the fin 110, and the remaining sacrificial material layer 165 serves as the sacrificial layer 160.

[0078] In this embodiment, the material of the sacrificial layer 160 is spin on carbon, and therefore, the sacrificial material layer 165 is formed by a spin coating process.

[0079] In this embodiment, the portion of the thickness of the sacrificial material layer 165 is etched back by a dry etching process (for example, an anisotropic dry etching process). The dry etching process has the characteristic of anisotropic etching, so that the etching can be performed in a direction perpendicular to the surface of the substrate 100, thereby facilitating improvement of the top surface flatness of the sacrificial layer 160. Moreover, the dry etching process has high process stability and controllability, which facilitates accurate control of the etching amount of the sacrificial material layer 165.

[0080] It should be noted that the thickness T3 of the sacrificial layer 160 should not be too small or too large. If the thickness T3 of the sacrificial layer 160 is too small, it is difficult to accurately control the etching stop position in the process of etching back a portion of the thickness of the sacrificial material layer 165, which easily reduces the uniformity of the thickness T3 of the sacrificial layer 160, thereby easily increasing the possibility that the protective dielectric layer 200 on the top of the isolation layer 150 is exposed. Accordingly, when the exposed protective dielectric layer 200 of the sacrificial layer 160 is removed, the protective dielectric layer 200 on the top of the isolation layer 150 is easily damaged, thereby affecting the protection of the isolation layer 150 by the protective dielectric layer 200. If the thickness T3 of the sacrificial layer 160 is too large, after the exposed protective dielectric layer 200 of the sacrificial layer 160 is removed, the height of the fin 110 exposed by the protective dielectric layer 200 is too small, thereby affecting the height of the effective fin and further affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness T3 of the sacrificial layer 160 is 1 nm to 10 nm. For example, the thickness T3 of the sacrificial layer 160 is 3 nm, 5 nm, 7 nm, or 9 nm. ​

[0081] Referring to Figure 10 The protective dielectric layer 200 exposed by the sacrificial layer 160 is removed.

[0082] The protective dielectric layer 200 exposed by the sacrificial layer 160 is removed to expose the fin 110, so as to prepare for forming a device gate structure (for example, a metal gate structure) across the fin 110, that is, for forming a transistor.

[0083] In this embodiment, the wet etching process is used to remove the protective dielectric layer 200 exposed by the sacrificial layer 160. The wet etching process has the characteristic of isotropic etching, so that the protective dielectric layer 200 exposed by the sacrificial layer 160 can be removed completely, thereby reducing the probability of residues of the protective dielectric layer 200 on the sidewall of the fin 110.

[0084] Referring to Figure 11 After the protective dielectric layer 200 exposed by the sacrificial layer 160 is removed, the sacrificial layer 160 is removed.

[0085] The sacrificial layer 160 is removed to expose the fin 110 and the remaining protective dielectric layer 200, so as to prepare for forming a film layer structure.

[0086] In this embodiment, the material of the sacrificial layer 160 is spin-on carbon, and therefore, the ashing process is used to remove the sacrificial layer 160. The ashing process has little damage to the protective dielectric layer 200 and the fin 110.

[0087] It should be noted that the protective dielectric layer 200 is formed by deposition in this embodiment. In other embodiments, a portion of the thickness of the isolation layer can be doped with ions, and the ions are suitable for improving the density of the isolation layer, and the isolation layer doped with the ions serves as the protective dielectric layer. For example, a portion of the thickness of the isolation layer is doped with silicon ions, and the protective dielectric layer is formed of silicon oxide rich in silicon.

[0088] It should be further noted that the protective dielectric layer 200 is formed before the formation of the dummy gate structure in this embodiment, and at this time, the area exposed by the fin 110 is large, which is conducive to the formation of the protective dielectric layer 200.

[0089] Specifically, the subsequently formed dummy gate structure includes a gate oxide layer covering the surface of the fin 110, and a dummy gate layer covering the gate oxide layer and crossing the fin 110. Compared with the scheme of forming the protective dielectric layer on the isolation layer at the bottom of the gate opening after removing the dummy gate layer and forming the gate opening in the interlayer dielectric layer and before removing the gate oxide layer, the present embodiment can avoid the influence of the aspect ratio of the gate opening on the formation process of the protective dielectric layer, thereby facilitating the formation of the protective dielectric layer 200 and improving the formation quality of the protective dielectric layer 200.

[0090] Further, when the dummy gate structure further comprises a gate oxide layer, in the embodiment, the gate oxide layer has not been formed before the protective dielectric layer 200 is formed, and thus, damage to the gate oxide layer caused by a process of forming the protective dielectric layer 200 (for example, a step of removing the protective dielectric layer 200 exposed by the sacrificial layer 160) can be avoided. The gate oxide layer in the core region is usually removed, and thus, the embodiment is beneficial to improving the uniformity of the removal effect of the gate oxide layer in the core region, thereby reducing the influence of the process of removing the gate oxide layer on the fin 110, and further ensuring the performance of the core device formed in the core region. The gate oxide layer in the peripheral region is usually retained, and the embodiment can avoid damage to the gate oxide layer caused by the process of forming the protective dielectric layer 200, thereby ensuring the performance of the input / output device formed in the peripheral region.

[0091] Reference Figure 12 After the protective dielectric layer 200 is formed, a dummy gate structure 300 crossing the fin 110 is formed, and the dummy gate structure 300 covers part of the top and part of the sidewall of the fin 110.

[0092] The dummy gate structure 300 is used to occupy a space position for forming a device gate structure (for example, a metal gate structure).

[0093] In the embodiment, the dummy gate structure 300 comprises a gate oxide layer 310 covering the surface of the fin 110, and a dummy gate layer 320 covering the gate oxide layer 310 and crossing the fin 110.

[0094] In the embodiment, a high-k last metal gate (last) process is used to form the device gate structure, and thus, at least the dummy gate layer 320 in the dummy gate structure 300 will be removed subsequently. In the process of removing the dummy gate layer 320, the gate oxide layer 310 is used as an etching stop layer, thereby reducing the probability of damage to the fin 110.

[0095] In addition, in subsequent processes, the gate oxide layer 310 in the core region is removed, and the gate oxide layer 310 in the peripheral region is retained and used as part of a gate dielectric layer.

[0096] In the embodiment, the material of the gate oxide layer 310 is silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.

[0097] In the embodiment, the material of the dummy gate layer 320 is polysilicon. In other embodiments, the material of the dummy gate layer can also be amorphous silicon.

[0098] In the embodiment, after the pseudo-gate structure 300 is formed, the forming method further comprises: forming source-drain doped regions in the fin 110 on both sides of the pseudo-gate structure 300 (not shown in the figure); and forming an interlayer dielectric layer (not shown in the figure) covering the source-drain doped regions, the interlayer dielectric layer covering the sidewall of the pseudo-gate structure 300.

[0099] Reference Figure 13 , after the interlayer dielectric layer (not shown in the figure) is formed, the forming method further comprises: removing the pseudo-gate structure 300 (as shown in Figure 12 ).

[0100] The pseudo-gate structure 300 is removed, so that a gate opening is formed in the interlayer dielectric layer, and a device gate structure (for example, a metal gate structure) is subsequently formed in the gate opening.

[0101] In the embodiment, the substrate 100 comprises a core region, and thus, in the process of removing the pseudo-gate structure 300, the pseudo-gate layer 320 and the gate oxide layer 310 are removed.

[0102] In the embodiment, in the process of removing the pseudo-gate structure 300, the bottom protection dielectric layer 210 is used as an etching stop layer to remove the top protection dielectric layer 220 (as shown in Figure 12 ).

[0103] In order to completely remove the gate oxide layer 310, the process of removing the gate oxide layer 310 usually comprises a main etching step and an over-etching step, and the top protection dielectric layer 220 is exposed to the etching environment for removing the gate oxide layer 310. In the process of removing the gate oxide layer 310, the top protection dielectric layer 220 is also easily damaged. Therefore, in the embodiment, the bottom protection dielectric layer 210 is used as an etching stop layer to remove the top protection dielectric layer 220 in the process of removing the gate oxide layer 310, so as to improve the height uniformity of the effective fin.

[0104] Specifically, the over-etching process is used to remove the top protection dielectric layer 220. The thickness of the top protection dielectric layer 220 is small, and thus, the top protection dielectric layer 220 is easily removed in the step of the over-etching process.

[0105] In addition, the bottom protection dielectric layer 210 has higher density and etching resistance, and thus, in the process of removing the top protection dielectric layer 220, the top surface of the bottom protection dielectric layer 210 can be used to define the position of the etching stop, and the process of removing the pseudo-gate structure 300 has a small damage amount to the bottom protection dielectric layer 210.

[0106] In the embodiment, the dry etching process is used to remove the pseudo-gate layer 320, or the dry etching and wet etching combined process is used to remove the pseudo-gate layer 320.

[0107] In this embodiment, after the dummy gate layer 320 is removed, the gate oxide layer 310 is removed by using a Certas etching process. The Certas etching process is a chemical gas etching process using ammonia (NH3) and hydrogen fluoride (HF) gas, so as to facilitate removing the gate oxide layer 310 completely while reducing the damage to the fin 110.

[0108] In addition, the process temperature of the Certas etching process is relatively low (usually 100-200 DEG C), and the etching rate is relatively slow, so as to easily control the etching amount of the film layer with small thickness and to have high etching stability.

[0109] In other embodiments, the SiCoNi etching process can also be used to remove the gate oxide layer and the top protective dielectric layer.

[0110] Correspondingly, the application also provides a semiconductor structure. With reference to the structure diagram of an embodiment of the semiconductor structure of the application, Figure 12 , a structure diagram of an embodiment of the semiconductor structure of the application is shown.

[0111] The semiconductor structure comprises a substrate 100, a fin 110 protruding from the substrate 100, an isolation layer 150 on the substrate 100 exposed by the fin 110, the isolation layer 150 covering part of the sidewall of the fin 110, a protective dielectric layer 200 on the top of the isolation layer 150, and a dummy gate structure 300 on the protective dielectric layer 200 and across the fin 110, the dummy gate structure 300 covering part of the top and part of the sidewall of the fin 110.

[0112] In the forming process of the semiconductor structure, the process of removing the dummy gate structure 300 is further included. When the dummy gate structure 300 is removed subsequently, the protective dielectric layer 200 can protect the isolation layer 150, so as to reduce the probability of the damage to the isolation layer 150, thereby facilitating reducing the influence on the height of the effective fin and improving the height uniformity of the effective fin, and correspondingly facilitating improving the performance of the semiconductor structure.

[0113] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0114] In this embodiment, the fin 110 and the substrate 100 are an integral structure. In other embodiments, the fin can also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of accurately controlling the height of the fin.

[0115] Therefore, the material of the fin 110 is the same as that of the substrate 100, and the material of the fin 110 is silicon. In other embodiments, the material of the fin can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other semiconductor materials suitable for forming a fin, and the material of the fin can also be different from the material of the substrate.

[0116] In this embodiment, the substrate 100 includes a device unit area (not labeled) for forming a device, and an isolation area (not labeled) for isolating adjacent device unit areas, and a plurality of fins 110 are formed on the substrate 100 in the device unit area. As an example, Figure 12 One device unit area is shown in the middle.

[0117] The fins 110 on the substrate 100 have different pattern densities. For example, in the device unit area, the edge-most fins 110 (i.e., the fins 110 closest to the isolation area) are provided with other fins 110 on only one side, and the remaining fins 110 are provided with other fins 110 on both sides, so the fins 110 in the device unit area also have different pattern densities. In other embodiments, the fin pattern densities of different device unit areas can also be different.

[0118] The substrate 100 generally includes a core area for forming core devices, and a peripheral area for forming input / output devices. Among them, the core device mainly refers to the device used inside the chip, which generally uses a lower voltage (generally 1.0V, 1.2V, 1.5V and 1.8V), and the input / output device is a device used when the chip interfaces with the outside, and the working voltage of such a device is generally higher, and depends on the compatible working voltage of the external interface (generally 1.8V, 2.5V, 3.3V and 5V). As an example, the core area is only shown in this embodiment.

[0119] The isolation layer 150 serves as a shallow trench isolation structure for isolating adjacent devices.

[0120] In this embodiment, the material of the isolation layer 150 is silicon oxide. In other embodiments, the material of the isolation layer can also be silicon nitride or silicon oxynitride, or other insulating materials.

[0121] The protective dielectric layer 200 can protect the isolation layer 150. Therefore, the etch resistance of the protective dielectric layer 200 is greater than that of the isolation layer 150.

[0122] In addition, the protective dielectric layer 200 located on the isolation layer 150 is reserved in the subsequent process, so as to avoid the step of removing the protective dielectric layer 200, thereby further reducing the probability of damage to the isolation layer 150. Therefore, the material of the protective dielectric layer 200 is an insulating material, and has good process compatibility.

[0123] To this end, the material of the protective medium layer 200 comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon carbon oxynitride, boron nitride, boron carbon nitride, and silicon boron carbon nitride.

[0124] It should be noted that the thickness (not shown) of the protective medium layer 200 should not be too small or too large. If the thickness of the protective medium layer 200 is too small, the thickness of the protective medium layer 200 is not good for the protection effect of the isolation layer 150, and in the subsequent process of removing the dummy gate structure 300, the probability of the isolation layer 150 being damaged is still high. As the feature size of the integrated circuit continues to decrease, the distance between adjacent fin portions 110 is becoming smaller and smaller. If the thickness of the protective medium layer 200 is too large, the protective medium layer 200 on the sidewall of the adjacent fin portion 110 is likely to be in contact, thereby causing adverse effects on the subsequent process. Therefore, in the present embodiment, the thickness of the protective medium layer 200 is to For example, the thickness of the protective medium layer 200 is or

[0125] In the present embodiment, the protective medium layer 200 comprises a bottom protective medium layer 210 and a top protective medium layer 220 covering the bottom protective medium layer 210, and the compactness of the bottom protective medium layer 210 is greater than that of the top protective medium layer 220.

[0126] On the one hand, the compactness of the bottom protective medium layer 210 is greater, and therefore, the etching resistance of the bottom protective medium layer 210 is greater than that of the top protective medium layer 220, so that the protection of the isolation layer 150 by the protective medium layer 200 is guaranteed.

[0127] On the other hand, compared with the total thickness of the protective medium layer 200, the thickness of the bottom protective medium layer 210 is small, and therefore, this is beneficial to reduce the influence of the process of forming the bottom protective medium layer 210 on the fin portion 110. Moreover, the compactness of the bottom protective medium layer 210 is greater than that of the top protective medium layer 220, and in the process of forming the top protective medium layer 220, the bottom protective medium layer 210 can protect the fin portion 110, thereby reducing the influence of the process of forming the top protective medium layer 220 on the fin portion 110 (for example, the bottom protective medium layer 210 is beneficial to block the reaction gas for forming the top protective medium layer 220 from contacting the fin portion 110).

[0128] In summary, the present embodiment forms the protective medium layer 200 with a stacked structure, which guarantees the performance of the protective medium layer 200 while reducing the influence on the fin portion 110, thereby being beneficial to further improve the performance of the semiconductor structure.

[0129] In this embodiment, the bottom protective dielectric layer 210 is made of silicon-rich oxide (SRO), and the top protective dielectric layer 220 is made of silicon oxide. SRO refers to silicon oxide materials with a high silicon content, resulting in higher density and etching resistance of the bottom protective dielectric layer 210.

[0130] Silicon-rich silicon oxide and silicon oxide have high process compatibility and have a similar lattice constant to silicon, which can improve stress problems and reduce the probability of deformation of fin 110.

[0131] Moreover, at the same thickness, forming a silicon-rich silicon oxide layer consumes more fins 110 compared to a silicon oxide layer. However, the silicon oxide layer has higher density and etching resistance. Therefore, by selecting silicon-rich silicon oxide layers and silicon oxide layers stacked sequentially from bottom to top, the consumption of fins 110 can be reduced while ensuring the performance of the protective dielectric layer 200.

[0132] It should be noted that in the bottom protective dielectric layer 210, the atomic percentage content of silicon in the silicon-rich silicon oxide should not be too low or too high. If the atomic percentage content of silicon is too low, the thickness T1 of the bottom protective dielectric layer 210 (e.g., ...) will be affected. Figure 7 (As shown) Under certain conditions, the etching resistance and density of the bottom protective dielectric layer 210 may not meet the process requirements; if the atomic percentage content of silicon is too high, the insulation performance of the bottom protective dielectric layer 210 may deteriorate, which may adversely affect the performance of the device. Therefore, in this embodiment, the atomic percentage content of silicon in the silicon-rich silicon oxide in the bottom protective dielectric layer 210 is 30% to 60%.

[0133] The thickness T1 of the bottom protective dielectric layer 210 should not be too small or too large. If the thickness T1 of the bottom protective dielectric layer 210 is too small, the thickness T2 of the top protective dielectric layer 220 needs to be increased to ensure the performance of the protective dielectric layer 200. Furthermore, because the thickness T1 of the bottom protective dielectric layer 210 is small, the bottom protective dielectric layer 210 will not effectively protect the fin 110 during the formation of the top protective dielectric layer 220, potentially affecting the fin 110. Moreover, if the top protective dielectric layer 220 is removed during the removal of the dummy gate structure 300, exposing the bottom protective dielectric layer 210, the small thickness T1 of the bottom protective dielectric layer 210 may not be able to protect the isolation layer 110. Therefore, in this embodiment, the thickness T1 of the bottom protective dielectric layer 210 is... to For example, the thickness T1 of the bottom protective dielectric layer 210 is or

[0134] The thickness T2 of the top protective dielectric layer 220 (e.g.) Figure 7 (As shown) It should not be too small or too large. If the thickness T2 of the top protective dielectric layer 220 is too small, the total thickness of the protective dielectric layer 200 will be too small, thereby reducing the protective effect of the protective dielectric layer 200 on the isolation layer 110. Alternatively, in order to make the total thickness of the protective dielectric layer 200 meet the performance requirements, the thickness T1 of the bottom protective dielectric layer 210 needs to be increased accordingly, which may cause the process of forming the bottom protective dielectric layer 210 to have an adverse effect on the fin 110. If the thickness T2 of the top protective dielectric layer 220 is too large, the thickness T1 of the bottom protective dielectric layer 210 will be too small. During the process of forming the top protective dielectric layer 220, the protective effect of the bottom protective dielectric layer 210 on the fin 110 will be poor, which may cause the process of forming the top protective dielectric layer 220 to have an effect on the fin 110. Moreover, during the process of removing the pseudo-gate structure 300, if the top protective dielectric layer 220 is removed, and the bottom protective dielectric layer 210 is exposed, the bottom protective dielectric layer 210 with a smaller thickness T1 may not be able to protect the isolation layer 110. Therefore, in this embodiment, the thickness T2 of the top protective dielectric layer 220 is... to For example, the thickness T2 of the top protective dielectric layer 220 is or

[0135] In this embodiment, the protective medium layer 200 also extends to cover part of the sidewall of the fin 110.

[0136] The protective dielectric layer 200 is formed using a deposition process. Therefore, during the formation of the semiconductor structure, after the protective dielectric layer 200 is formed, it conformally covers the fin 110 and the isolation layer 110. Correspondingly, the semiconductor structure formation process also includes forming a sacrificial layer on the protective dielectric layer 200 above the isolation layer 150. The top of the sacrificial layer is lower than the top of the fin 110. The sacrificial layer protects the protective dielectric layer 200 above the isolation layer 150. Removing the protective dielectric layer 200 exposed by the sacrificial layer 160 allows the protective dielectric layer 200 above the isolation layer 150 to be retained. The sacrificial layer is formed by the deposition and back etching of a sacrificial material layer.

[0137] It should be noted that the height (not shown) of the fin 110 covered by the protected medium layer 200 should not be too small or too large. If the height of the fin 110 covered by the protected medium layer 200 is too small, it is difficult to accurately control the etching stop position in the process of etching part of the thickness of the sacrificial layer, which can easily reduce the thickness uniformity of the sacrificial layer, thereby easily increasing the possibility of exposing the protected medium layer 200 on the top of the isolation layer 150, and accordingly, when removing the exposed protected medium layer 200 of the sacrificial layer, the protected medium layer 200 on the top of the isolation layer 150 is easily damaged, thereby affecting the protection of the isolation layer 150 by the protected medium layer 200. If the height of the fin 110 covered by the protected medium layer 200 is too large, the height of the fin 110 exposed by the protected medium layer 200 is correspondingly too small, thereby affecting the height of the effective fin, and further affecting the performance of the semiconductor structure. Therefore, in the embodiment, the height of the fin 110 covered by the protected medium layer 200 is 1 nm to 10 nm. For example, the height of the fin 110 covered by the protected medium layer 200 is 3 nm, 5 nm, 7 nm, or 9 nm.

[0138] The dummy gate structure 300 is used to occupy a spatial position for the formation of a device gate structure (e.g., a metal gate structure).

[0139] In the embodiment, the dummy gate structure 300 includes a gate oxide layer 310 covering the surface of the fin 110, and a dummy gate layer 320 covering the gate oxide layer 310 and spanning the fin 110.

[0140] In the embodiment, the device gate structure is formed by using a post-formed high-k gate medium layer and a post-formed metal gate process, and therefore, at least the dummy gate layer 320 in the dummy gate structure 300 will be removed subsequently. In the process of removing the dummy gate layer 320, the gate oxide layer 310 is used as an etching stop layer, thereby reducing the probability of damaging the fin 110.

[0141] In addition, in subsequent processes, the gate oxide layer 310 in the core region will be removed, and the gate oxide layer 310 in the peripheral region is retained and used as part of the gate medium layer.

[0142] In the embodiment, the material of the gate oxide layer 310 is silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.

[0143] In the embodiment, the material of the dummy gate layer 320 is polysilicon. In other embodiments, the material of the dummy gate layer can also be amorphous silicon.

[0144] The semiconductor structure can be formed by using the forming method described in the foregoing embodiments, or can be formed by using other forming methods. For the specific description of the semiconductor structure in the embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be described herein again.

[0145] Although the present application has been disclosed with reference to various implementations, it is understood that equivalents can be employed and substitutions made herein without departing from the spirit and scope of the application as defined in the following claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provides a substrate and fins protruding from the substrate; An isolation layer is formed on the substrate exposed by the fin, the isolation layer covering a portion of the sidewall of the fin; A protective medium layer is formed on top of the isolation layer, which covers the top of the isolation layer between the fins and also covers the corners of the fins and the isolation layer; After the protective medium layer is formed, a pseudo-gate structure is formed across the fin, the pseudo-gate structure covering part of the top and part of the sidewall of the fin, and the isolation layer is isolated from the pseudo-gate structure by the protective medium layer.

2. The forming method as described in claim 1, characterized in that, In the step of forming a protective medium layer on top of the isolation layer, the protective medium layer conformally covers the isolation layer and the fin; Before forming the pseudo-gate structure spanning the fin, the forming method further includes: forming a sacrificial layer on the protective dielectric layer located above the isolation layer, the top of the sacrificial layer being lower than the top of the fin; removing the protective dielectric layer exposed by the sacrificial layer; and removing the sacrificial layer.

3. The forming method as described in claim 2, characterized in that, The protective medium layer includes a bottom protective medium layer and a top protective medium layer covering the bottom protective medium layer, wherein the density of the bottom protective medium layer is greater than that of the top protective medium layer.

4. The forming method as described in claim 2, characterized in that, The step of forming a sacrificial layer on the protective medium layer located above the isolation layer includes: forming a sacrificial material layer covering the protective medium layer; The sacrificial material layer is etched back to a portion of its thickness, such that the top of the remaining sacrificial material layer is lower than the top of the fin, and the remaining sacrificial material layer serves as the sacrificial layer.

5. The forming method as described in claim 3, characterized in that, The bottom protective dielectric layer is made of silicon-rich silicon oxide, and the top protective dielectric layer is made of silicon oxide.

6. The forming method as described in claim 5, characterized in that, The formation method further includes: removing the pseudo-gate structure, and in the process of removing the pseudo-gate structure, using the bottom protective dielectric layer as an etching stop layer to remove the top protective dielectric layer.

7. The forming method as described in claim 1, characterized in that, The process for forming the protective dielectric layer includes atomic layer deposition.

8. The forming method as described in claim 5, characterized in that, The bottom protective dielectric layer is formed using chemical vapor deposition, and the top protective dielectric layer is formed using atomic layer deposition.

9. The forming method as described in claim 2, characterized in that, The material of the sacrificial layer includes one or more of spin-coated carbon, organic dielectric layer material, and bottom anti-reflective coating material.

10. The forming method as described in claim 2, characterized in that, The thickness of the sacrificial layer is 1 nanometer to 10 nanometers.

11. The forming method as described in claim 2, characterized in that, The protective dielectric layer exposed by the sacrificial layer is removed using a wet etching process.

12. The forming method as described in claim 4, characterized in that, A dry etching process is used to etch back a portion of the thickness of the sacrificial material layer.

13. The forming method as described in claim 1, characterized in that, The pseudo-gate structure includes a gate oxide layer covering the surface of the fin, and a pseudo-gate layer covering the gate oxide layer and spanning the fin.

14. A semiconductor structure, characterized in that, include: Substrate; The fin protrudes from the substrate; An isolation layer is located on the substrate exposed by the fin, and the isolation layer covers a portion of the sidewall of the fin; A protective medium layer is located on top of the isolation layer, the protective medium layer covers the top of the isolation layer between the fins, and also covers the corners of the fins and the isolation layer; A pseudo-gate structure is located on the protective dielectric layer and spans the fin, the pseudo-gate structure covering part of the top and part of the sidewalls of the fin, and the isolation layer is isolated from the pseudo-gate structure by the protective dielectric layer.

15. The semiconductor structure as described in claim 14, characterized in that, The protective medium layer includes a bottom protective medium layer and a top protective medium layer covering the bottom protective medium layer, wherein the density of the bottom protective medium layer is greater than that of the top protective medium layer.

16. The semiconductor structure as claimed in claim 14, characterized in that, The thickness of the protective medium layer is to 17. The semiconductor structure as claimed in claim 15, characterized in that, The bottom protective dielectric layer is made of silicon-rich silicon oxide, and the top protective dielectric layer is made of silicon oxide.

18. The semiconductor structure as claimed in claim 17, characterized in that, The silicon-rich silicon oxide contains 30% to 60% silicon atomic percentage.

19. The semiconductor structure as described in claim 15, characterized in that, The thickness of the bottom protective medium layer is to The thickness of the top protective medium layer is to 20. The semiconductor structure as claimed in claim 14, characterized in that, The pseudo-gate structure includes a gate oxide layer covering the surface of the fin, and a pseudo-gate layer covering the gate oxide layer and spanning the fin.

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