A semiconductor module substrate and design method

Abstract

The present invention provides a semiconductor module substrate and a design method. The semiconductor module substrate includes a power metal cladding group, an auxiliary metal cladding group and a chipset. The power metal cladding group includes a first power metal cladding, a second power metal cladding, a third power metal cladding and a fourth power metal cladding; the auxiliary metal cladding group includes a first auxiliary metal cladding, a second auxiliary metal cladding, a third auxiliary metal cladding, a fourth auxiliary metal cladding and a fifth auxiliary metal cladding; the chipset includes a first chip array, a second chip array, a third chip array and a fourth chip array. After adopting the above technical solution, the rated current of the module can be improved under the premise of ensuring the reliability of the semiconductor module with the corresponding semiconductor module substrate, and the power size, power density, working efficiency and other indicators of the motor controller with the semiconductor module can be increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor module substrate and a design method. Background Art

[0002] As new energy vehicle manufacturers continue to increase their requirements for the power level of motor controllers, the current level requirements for automotive-grade power modules have gradually increased. There has been a method of increasing the number of parallel chips inside the module to increase the rated current of the module. However, the increase in the number of parallel connections makes the steady-state and dynamic current sharing analysis of each chip branch more complicated, and the series heat problem between chips is more serious, resulting in inconsistent junction temperatures of each chip and reduced thermal reliability. At the same time, it is more difficult to suppress the common source stray inductance of the gate-level drive circuit of each chip, which increases the risk of mis-conduction of the bridge arm during commutation transients and reduces electrical reliability.

[0003] Therefore, a new type of semiconductor module substrate and design method is needed to improve the rated current of the module and increase other indicators such as the power size, power density, and working efficiency of the motor controller with the semiconductor module while ensuring the reliability of the semiconductor module with the corresponding semiconductor module substrate. Summary of the invention

[0004] In order to overcome the above technical defects, the purpose of the present invention is to provide a semiconductor module substrate and a design method, which can improve the power level of the motor controller while ensuring other indicators such as power density, working efficiency and reliability of the motor controller having the semiconductor module substrate.

[0005] The invention discloses a semiconductor module substrate, comprising a power metal cladding group, an auxiliary metal cladding group and a chip group laid on the semiconductor module substrate.

[0006] The power metal cladding group includes a first power metal cladding, a second power metal cladding, a third power metal cladding, and a fourth power metal cladding arranged in sequence along the long side direction of the semiconductor module substrate;

[0007] The auxiliary metal coating group includes a first auxiliary metal coating, a second auxiliary metal coating, a third auxiliary metal coating, a fourth auxiliary metal coating, and a fifth auxiliary metal coating, wherein

[0008] The first auxiliary metal coating is arranged between the first power metal coating and the second power metal coating;

[0009] The second auxiliary metal cladding is arranged in the second power metal cladding and is electrically connected to the first auxiliary metal cladding via a bonding wire;

[0010] The third auxiliary metal coating is arranged between the third power metal coating and the fourth power metal coating;

[0011] The fourth auxiliary metal cladding is arranged beside the first auxiliary metal cladding along the short side direction of the semiconductor module substrate;

[0012] The fifth auxiliary metal cladding is arranged beside the fourth auxiliary metal cladding along the long side direction of the semiconductor module substrate and beside the first power metal cladding;

[0013] The chipset includes a first chip array, a second chip array, a third chip array and a fourth chip array.

[0014] The first chip array and the second chip array are arranged in the first power metal cladding layer along the long side direction of the semiconductor module substrate, and are connected to the second power metal cladding layer and the third power metal cladding layer respectively through bonding wires;

[0015] The third chip array and the fourth chip array are arranged in the third power metal cladding layer along the long side direction of the semiconductor module substrate, and are connected to the fourth power metal cladding layer through bonding wires.

[0016] Preferably, the first chip array, the second chip array, the third chip array and the fourth chip array include a plurality of chips of uniform size;

[0017] The spacing between adjacent chips in the first chip array, the second chip array, the third chip array and the fourth chip array is consistent, and is smaller than the distance between the first chip array and the fifth auxiliary metal coating, and smaller than the distance between the third chip array and the fourth chip array and the edge of the third power metal coating.

[0018] Preferably, an upper bridge arm gate-level auxiliary terminal is provided in the second auxiliary metal cladding;

[0019] The third auxiliary metal coating is provided with a lower bridge arm gate-level auxiliary terminal;

[0020] The first auxiliary metal coating, the second auxiliary metal coating, and the third auxiliary metal coating are connected to the gate level circuit of the chipset;

[0021] An upper bridge arm source auxiliary terminal is provided in the second power metal coating, and the upper bridge arm source auxiliary terminal is located next to the upper bridge arm gate level auxiliary terminal;

[0022] The first power metal cladding is provided with a first upper bridge arm drain auxiliary terminal and a second upper bridge arm drain auxiliary terminal at both end edges along the long side direction of the semiconductor module substrate;

[0023] The fourth auxiliary metal cladding layer and the fifth auxiliary metal cladding layer are respectively provided with a first temperature sensor auxiliary terminal and a second temperature sensor auxiliary terminal for connecting to the temperature sensitive resistor;

[0024] A lower bridge arm drain auxiliary terminal is provided at the end edge of the third power metal cladding along the long side direction of the semiconductor module substrate;

[0025] A first lower bridge arm source auxiliary terminal and a second lower bridge arm source auxiliary terminal are provided at the connecting position of the fourth power metal cladding and the end edge of the third auxiliary metal cladding along the long side direction of the semiconductor module substrate, so that the first lower bridge arm source auxiliary terminal and the second lower bridge arm source auxiliary terminal are arranged on both sides of the lower bridge arm gate level auxiliary terminal.

[0026] Preferably, the first power metal cladding layer where the first upper bridge arm drain auxiliary terminal and the second upper bridge arm drain auxiliary terminal are provided is in a first extension shape, and the extension direction is toward the fourth power metal cladding layer and the first power metal cladding layer respectively;

[0027] The third power metal cladding layer where the lower bridge arm drain auxiliary terminal is provided is in a second extension shape, and the extension direction is toward the fourth power metal cladding layer.

[0028] The present invention also discloses a method for designing a semiconductor module substrate to form the semiconductor module substrate as described above, comprising the following steps:

[0029] Based on the packaging form and application scenario power level of the semiconductor module, determine the process route of the semiconductor module, formulate the design boundary of the semiconductor module substrate to generate design files for heating and electromagnetic simulation evaluation;

[0030] Based on the design file, simulate and calculate the current output information of the chip in the semiconductor module substrate at the allowable junction temperature to determine the structural design of the iterative semiconductor module substrate;

[0031] Based on the design file, calculate the spurious parameters of each section of the power module in the semiconductor module substrate;

[0032] Import the self-inductance-mutual inductance matrix into the design file to evaluate the voltage overshoot, dynamic current sharing, and maximum switching speed of the semiconductor module substrate.

[0033] Preferably, based on the packaging form and application scenario power level of the semiconductor module, the process route of the semiconductor module is determined, and the design boundary of the semiconductor module substrate is formulated to generate a design file for heating and electromagnetic simulation evaluation, the steps include:

[0034] Generate expected technical indicators based on the application scenarios of semiconductor modules;

[0035] Generate material and size information of semiconductor module substrate according to expected technical indicators;

[0036] Generate process routes based on expected technical indicators;

[0037] Formulate design boundaries for semiconductor module substrates based on material and dimensional information and process routes;

[0038] Based on the material and size information and the design boundary, a design file including the structural design of the chip, bonding wires and terminals in the semiconductor module substrate is generated.

[0039] Preferably, based on the design file, the step of simulating and calculating the current output information of the chip in the semiconductor module substrate at the allowable junction temperature to determine the structural design of the iterative semiconductor module substrate includes:

[0040] Based on the design file, add the heat dissipation channel of the semiconductor module to define the thermal conductivity and heat capacity of the coating of the semiconductor module substrate;

[0041] Set the simulation heat dissipation configuration according to the heat dissipation conditions of the application scenario of the semiconductor module;

[0042] Based on the simulated heat dissipation configuration, the chip on the semiconductor module substrate is used as the heat source, according to the following formula:

[0043]

[0044] Calculate the steady-state equivalent thermal resistance R between the chip and the coolant th , where P s is the specific loss, T jmax is the specific loss P s Maximum junction temperature under

[0045] According to the standard operating conditions of the semiconductor module, calculate the switching loss P at the standard operating voltage under standard operating conditions sw (I) and conduction loss P con (I) and determine the maximum allowable junction temperature T according to the chip data sheet ja , and according to the following formula:

[0046]

[0047] Calculate the maximum total losses P(I) of the semiconductor module.

[0048] Preferably, the step of calculating the stray parameters of each section of the power module in the semiconductor module substrate based on the design file comprises:

[0049] Based on the design documents, the design requirements for the input power circuit, drive circuit, and power-drive circuit coupling stray inductance;

[0050] According to the design documents, solve the stray inductance and corresponding mutual inductance of each power module section, and generate the self-inductance-mutual inductance matrix to calculate the lumped parameters of stray inductance;

[0051] Determine whether the electromagnetic reliability of the semiconductor module meets the requirements.

[0052] Compared with the prior art, the above technical solution has the following beneficial effects:

[0053] 1. The semiconductor module has a high power density while ensuring high thermal and electrical reliability;

[0054] 2. Reduce the coupling inductance and relative error between the power circuit and the drive circuit;

[0055] 3. This design method integrates the quantitative requirements of process and reliability to avoid invalid iterations of the design. It also accurately calculates the factors affecting bridge arm misconduction and crosstalk by quantitatively analyzing the steady-state and dynamic current-sharing characteristics of the chip, and facilitates the precise location of the fault generation mechanism and rapid iterative design. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A schematic diagram of the structure of a semiconductor module substrate in accordance with a preferred embodiment of the present invention;

[0057] Figure 2 A schematic diagram of a process flow of a method for designing a semiconductor module substrate in accordance with a preferred embodiment of the present invention;

[0058] Figure 3 The figure is a schematic diagram of circuit connections of a chip of a semiconductor module substrate in accordance with a preferred embodiment of the present invention.

[0059] Reference numerals:

[0060] 1-power terminal ultrasonic welding point, 2-upper bridge arm source auxiliary terminal, 3-second power metal coating, 4-upper bridge arm gate level auxiliary terminal, 5-second upper bridge arm drain auxiliary terminal, 6-first temperature sensor auxiliary terminal, 7-fourth auxiliary metal coating, 8-fifth auxiliary metal coating, 9-second temperature sensor auxiliary terminal, 10-lower bridge arm drain auxiliary terminal, 11-first power metal coating, 12-third power metal coating, 13-first upper bridge arm drain auxiliary terminal, 14-fourth power metal coating, 15-first lower bridge arm source auxiliary terminal, 16-lower bridge arm gate level auxiliary terminal, 17-second lower bridge arm source auxiliary terminal, 18-first auxiliary metal coating, 19-second auxiliary metal coating, 20-third auxiliary metal coating. DETAILED DESCRIPTION

[0061] The advantages of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments.

[0062] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0063] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0064] It should be understood that although the terms first, second, third, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0065] In the description of the present invention, it is necessary to understand that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0066] In the description of the present invention, unless otherwise specified and limited, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal connection between two components. It can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances.

[0067] In the following description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings. Therefore, "module" and "component" can be used interchangeably.

[0068] See also Figure 1 The present invention proposes a novel design structure of a semiconductor module substrate. Specifically, it includes a power metal cladding group, an auxiliary metal cladding group and a chip group laid on the semiconductor module substrate. The power metal cladding group includes a first power metal cladding 11, a second power metal cladding 3, a third power metal cladding 12, and a fourth power metal cladding 14 arranged in sequence along the long side direction of the semiconductor module substrate. The long side direction can be understood as a relatively long side of the semiconductor module substrate from top to bottom. The first power metal cladding 11, the second power metal cladding 3, the third power metal cladding 12, and the fourth power metal cladding 14 are insulated and separated.

[0069] The auxiliary metal cladding group includes a first auxiliary metal cladding 18, a second auxiliary metal cladding 19, a third auxiliary metal cladding 20, a fourth auxiliary metal cladding 7, and a fifth auxiliary metal cladding 8, wherein the first auxiliary metal cladding 18 is arranged between the first power metal cladding 11 and the second power metal cladding 3, that is, arranged at the connecting portion of the first power metal cladding 11 and the second power metal cladding 3; the second auxiliary metal cladding 19 is arranged in the second power metal cladding 3, the second auxiliary metal cladding 19 is completely surrounded by the second power metal cladding 3, and is electrically connected to the first auxiliary metal cladding 18 through an electrical connection element, such as a stitching line or a binding line; the third auxiliary metal cladding 20 is arranged between the third power metal cladding 12 and the fourth power metal cladding 14; the fourth auxiliary metal cladding 7 is arranged beside the first auxiliary metal cladding 18 along the short side direction of the semiconductor module substrate; the fifth auxiliary metal cladding 8 is arranged beside the fourth auxiliary metal cladding 7 along the long side direction of the semiconductor module substrate, and is arranged beside the first power metal cladding 11.

[0070] The chipset includes a first chip array, a second chip array, a third chip array and a fourth chip array. The first chip array and the second chip array are arranged in the first power metal coating 11 along the long side direction of the semiconductor module substrate, and are connected to the second power metal coating 3 and the third power metal coating 12 through bonding wires respectively; the third chip array and the fourth chip array are arranged in the third power metal coating 12 along the long side direction of the semiconductor module substrate, and are connected to the fourth power metal coating 14 through bonding wires.

[0071] With the above configuration, the chipset is laid out along the short side direction of the semiconductor module substrate so that the power-drive circuit coupling inductance meets the requirements, and there is a large gap between the combination of the first chip array and the second chip array and the combination of the third chip array and the fourth chip array, thereby solving the problem of series heat dissipation.

[0072] Power terminal ultrasonic welding points 1 are also provided on both sides of the semiconductor module substrate along the long side direction.

[0073] In a preferred embodiment, the first chip array, the second chip array, the third chip array and the fourth chip array include a plurality of chips of the same size, for example, each including 6 chips, and the size is exactly the same. The spacing between adjacent chips in the first chip array, the second chip array, the third chip array and the fourth chip array is consistent, and the spacing is smaller than the distance between the first chip array and the fifth auxiliary metal cladding 8, and smaller than the distance between the third chip array and the fourth chip array and the edge of the third power metal cladding 12 (for example, the insulating edge of the third power metal cladding 12), so as to ensure that the junction temperature of each chip is consistent.

[0074] Preferably or optionally, the second auxiliary metal cladding 19 is provided with an upper bridge arm gate-level auxiliary terminal 4; the third auxiliary metal cladding 20 is provided with a lower bridge arm gate-level auxiliary terminal 16; the first auxiliary metal cladding 18, the second auxiliary metal cladding 19, and the third auxiliary metal cladding 20 are connected to the gate-level circuit of the chipset; the second power metal cladding 3 is provided with an upper bridge arm source auxiliary terminal 2, and the upper bridge arm source auxiliary terminal 2 is located next to the upper bridge arm gate-level auxiliary terminal 4; the first power metal cladding 11 is provided with a first upper bridge arm drain auxiliary terminal 13 and a second upper bridge arm drain auxiliary terminal 5 at both end edges along the long side direction of the semiconductor module substrate; the fourth auxiliary metal cladding 7 and the fifth auxiliary metal cladding 8 are respectively provided with a first temperature sensor auxiliary terminal 6 and a second temperature sensor auxiliary terminal 9 for connecting with the temperature sensitive resistor; the third power metal cladding 12 is provided with a lower bridge arm drain auxiliary terminal 10 at the edge along the long side direction of the semiconductor module substrate; the fourth power metal cladding 14 is provided with a first lower bridge arm source auxiliary terminal 15 and a second lower bridge arm source auxiliary terminal 17 at the connecting position with the third auxiliary metal cladding 20 at the edge along the long side direction of the semiconductor module substrate, so that the first lower bridge arm source auxiliary terminal 15 and the second lower bridge arm source auxiliary terminal 17 are provided on both sides of the lower bridge arm gate level auxiliary terminal 16. Under the above structural design, the absolute value of the coupling inductance between the power circuit and the drive circuit of each chip is relatively small, and the relative error is relatively low, so as to achieve the uniformity of the semiconductor module substrate.

[0075] Further preferably, the first power metal cladding 11 where the first upper bridge arm drain auxiliary terminal 13 and the second upper bridge arm drain auxiliary terminal 5 are provided is in a first extension shape, and the extension direction is toward the fourth power metal cladding 14 and the first power metal cladding 11 respectively; the third power metal cladding 12 where the lower bridge arm drain auxiliary terminal 10 is provided is in a second extension shape, and the extension direction is toward the fourth power metal cladding 14. It can be understood that the lower bridge arm drain auxiliary terminal 10 and the first upper bridge arm drain auxiliary terminal 13 can be bilaterally symmetrical, and are in the same straight line with the first lower bridge arm source auxiliary terminal 15, the lower bridge arm gate-level auxiliary terminal 16, and the second lower bridge arm source auxiliary terminal 17 along the short side direction of the bottom of the semiconductor module.

[0076] Considering that the design of power semiconductor module substrate is restricted by many factors, such as the production process of semiconductor module substrate, chip mounting, bonding wire and other process constraints, as well as the junction temperature distribution of each chip, the distribution of each loop stray parameters and other reliability constraints. Existing power module designs are mostly qualitative analysis, such as verification by referring to the layout of well-known domestic and foreign manufacturers. The reliability mechanism is unclear and the verification cycle is long. To form the above semiconductor module substrate, refer to Figure 2 , the present invention can be designed based on the following design method:

[0077] S100: Based on the packaging form and application scenario power level of the semiconductor module, determine the process route of the semiconductor module, formulate the design boundary of the semiconductor module substrate to generate design files for heating and electromagnetic simulation evaluation;

[0078] The design file may be a CAD file, which forms a preliminary design plan according to the input design requirements.

[0079] S200: Based on the design file, simulate and calculate the current output information of the chip in the semiconductor module substrate at the allowable junction temperature to determine the structural design of the iterative semiconductor module substrate;

[0080] In step S200 , the junction temperature of the semiconductor module and the thermal resistance of the coolant may be calculated, thereby determining whether it is necessary to modify and iterate the structural design of the semiconductor module substrate.

[0081] S300: Calculating spurious parameters of each section of the power module in the semiconductor module substrate based on the design file;

[0082] In order to evaluate the rationality of the electromagnetic design of semiconductor modules with multiple chips in parallel and ensure that the semiconductor modules have excellent current sharing characteristics, high switching speed, short-circuit capability, etc., it is necessary to accurately calculate the stray parameters of each section of the power module in the semiconductor module substrate, especially the stray inductance.

[0083] S400: Import the self-inductance-mutual inductance matrix into the design file to evaluate the voltage overshoot, dynamic current sharing, and maximum switching speed of the semiconductor module substrate.

[0084] In order to ultimately evaluate the voltage overshoot, dynamic current sharing, maximum switching speed and other characteristics of semiconductor modules, actual operating conditions are simulated. The self-inductance-mutual inductance matrix is ​​imported into the circuit simulation software, and combined with the chip model provided by the manufacturer, the switching transient simulation of multi-chip parallel modules is performed to determine whether parameters such as voltage overshoot and current sharing between chips meet the technical requirements.

[0085] In a preferred embodiment, step S100 includes:

[0086] S110: generating expected technical indicators according to application scenarios of semiconductor modules;

[0087] Expected technical indicators include but are not limited to:

[0088] (1) Types of semiconductor modules: single tube, half-bridge module, six-in-one module, etc.

[0089] (2) Chip type: IGBT, FRD, SiC MOSFET, etc.

[0090] (3) Packaging form: glue potting, injection molding, etc.

[0091] (4) Dimensions of semiconductor modules: overall appearance, type, size and position of power terminals and auxiliary terminals, etc.;

[0092] (5) Voltage and current requirements: Voltage requirements include common blocking voltage levels such as 600V, 650V, 750V, 900V, and 1200V. Current requirements generally provide peak and rated requirements.

[0093] (6) Application environment pollution level, altitude, flame retardant requirements, environmentally friendly material requirements, etc.

[0094] The above-mentioned expected technical indicators are important information for determining the selection of relevant materials for semiconductor module substrates and the formulation of packaging process routes, and need to be clearly defined in the early stage of semiconductor module substrate design.

[0095] S120: Generate material and size information of the semiconductor module substrate according to the expected technical indicators;

[0096] Materials and dimensions include but are not limited to:

[0097] (1) Substrate ceramic materials: Al2O3, ZTA, AlN, Si3N4, etc.

[0098] (2) Substrate copper layer-ceramic connection process: DBC, AMB, etc.;

[0099] (3) Substrate size: including overall length, width, and thickness of upper copper layer, middle DBC layer and lower copper layer;

[0100] The above-mentioned substrate material and size are the main influencing factors in defining the substrate design boundary and need to be determined in advance to avoid packaging process problems.

[0101] S130: generating a process route according to the expected technical indicators;

[0102] Process routes include but are not limited to:

[0103] (1) Number of chips: Based on the module current requirements and the current capability of a single chip, a preliminary estimate is made;

[0104] (2) Chip mounting methods: including solder sheet or solder paste reflow soldering, silver sintering and other technologies;

[0105] (3) Chip interconnection methods: including aluminum and copper wire bonding, direct lead frame connection and other technologies;

[0106] (4) Terminal welding method: including reflow soldering, ultrasonic welding and other technologies;

[0107] (5) Overall packaging process: includes chip mounting, chip interconnection, terminal welding, shell installation, glue filling, injection molding and other process sequences and processes.

[0108] The above packaging process route determines the distance information of the chip, terminals, DBC, etc., which needs to be determined in advance to avoid process problems.

[0109] S140: Formulate design boundaries for semiconductor module substrates based on material and dimension information and process routes;

[0110] Design boundaries include but are not limited to:

[0111] (1) Minimum slot spacing and minimum copper layer width of DBC / AMB: This boundary is mainly limited by the substrate ceramic material and the thickness of each layer;

[0112] (2) Minimum spacing between chips: This boundary is mainly limited by the chip mounting method;

[0113] (3) Minimum chip-DBC / AMB groove spacing: This boundary is mainly limited by the chip mounting method;

[0114] (4) Minimum chip-terminal spacing: This boundary is mainly limited by the terminal welding method;

[0115] (5) Number, height, spacing, etc. of bonding wires: This boundary is mainly limited by conditions such as chip interconnection process and module current capability requirements.

[0116] (6) Minimum width of the copper layer of the semiconductor module substrate: This boundary condition is mainly limited by conditions such as the thickness of the substrate material and the module current capability requirements.

[0117] S150: Based on the material and size information and design boundaries, a design file including the structural design of the chip, bonding wires, and terminals in the semiconductor module substrate is formed, which mainly includes the following three processes:

[0118] (1) Terminal and chip layout and positioning;

[0119] (2) Etching trench drawing of copper layer on the upper surface of DBC / AMB;

[0120] (3) Drawing of binding lines.

[0121] After the design is completed, the corresponding CAD model is output for subsequent thermal and electromagnetic simulation analysis.

[0122] In a preferred embodiment, step S200 includes:

[0123] S210: Based on the design file, add a heat dissipation channel of the semiconductor module to define the thermal conductivity and heat capacity of the coating of the semiconductor module substrate;

[0124] Step S210 is to design the material properties of the semiconductor module substrate. The main materials of the coating include but are not limited to:

[0125] (1) Chip body: usually Si or SiC material;

[0126] (2) Chip mounting solder / sintering materials: usually lead-free / leaded solder, silver paste, silver film and other materials;

[0127] (3) Copper layer + ceramic material: Ceramic materials are usually Al2O3, ZTA, AlN, Si3N4, etc.

[0128] (4) Substrate-heat sink thermal conductive material: usually thermal conductive silicone grease, silver sintered material, etc.;

[0129] (5) Radiator body: usually copper.

[0130] S220: Setting a simulation heat dissipation configuration according to a heat dissipation condition of an application scenario of the semiconductor module;

[0131] Heat dissipation configuration includes but is not limited to:

[0132] (1) Ambient temperature T r and coolant temperature T f : Usually defined according to the application scenario of the module;

[0133] (2) Surface heat transfer coefficient between radiator and coolant: It is determined by factors such as coolant composition and radiator structure, and can be provided by fluid finite element simulation or radiator manufacturer.

[0134] S230: Based on the simulated heat dissipation configuration, the chip of the semiconductor module substrate is used as the heat source, according to the following formula:

[0135]

[0136] Calculate the steady-state equivalent thermal resistance R between the chip and the coolant th , where P s is the specific loss, T jmax is the specific loss P s Maximum junction temperature under

[0137] S240: Calculate the switching loss P at the standard operating voltage under standard operating conditions according to the standard operating conditions of the semiconductor module. sw (I) and conduction loss P con (I) and determine the maximum allowable junction temperature T according to the chip data sheet ja , and according to the following formula:

[0138]

[0139] Calculate the maximum total losses P(I) of the semiconductor module.

[0140] Since the relationship between P(I) and the operating current I can be preliminarily obtained from the chip data sheet, the maximum current I can be inversely calculated. max This parameter is compared with the current input in the module design requirement to determine whether the corresponding design meets the requirement. If it meets the requirement, it proceeds to the next step of electromagnetic simulation. If it does not meet the requirement, it returns to step S100 (substrate modeling) to modify the number of chips in parallel, substrate material size, chip layout, etc. for design iteration.

[0141] More preferably, step S300 includes:

[0142] S310: Based on the design documents, input the design requirements of the power circuit, drive circuit, and power-drive circuit coupling stray inductance;

[0143] See also Figure 3 Taking a multi-chip parallel half-bridge module as an example, n chips S are connected in parallel on the upper bridge arm. upp1 —S uppn , n chips S are connected in parallel in the lower bridge arm low1 —S lown .

[0144] For stray inductance, including the upper bridge chip drain stray inductance L d_upp1 —L d_uppn , the upper bridge chip source stray inductance L s_upp1 —L s_uppn , upper bridge chip gate level stray inductance L g_upp1 —L g_uppn , the upper bridge chip auxiliary source stray inductance L st_upp1 —L st_uppn ; Lower bridge chip drain stray inductance L d_low1 —L d_lown , the lower bridge chip source stray inductance L s_low1 —L s_lown , the lower bridge chip gate level stray inductance L g_low1 —L g_lown , the auxiliary source stray inductance L of the lower bridge chip st_low1 —L st_lown .

[0145] In addition to the stray inductance itself, there is also the mutual inductance between the stray inductors, which is uniformly denoted as M a—b For example, the mutual inductance between the drain stray inductance of the first chip in the upper bridge arm and the source stray inductance of the second chip in the lower bridge arm can be recorded as M d_upp1-s_low2 .

[0146] According to the transient characteristics of the parallel modules, the spurious parameters of each chip in the upper and lower bridge arms can be simplified into three main lumped variables:

[0147] (1) Stray inductance of power circuit:

[0148] The total stray inductance of the power circuit is the main factor that determines the module voltage overshoot. At the same time, excessive stray inductance of the power circuit will increase the switching loss of the device. Therefore, the stray inductance of the power circuit should be as small as possible to suppress the module voltage overshoot and switching loss.

[0149] The stray inductance of the power loop of each chip is composed of the chip drain inductance, source inductance and corresponding mutual inductance. The mutual inductance of the drain includes the mutual inductance with the source of its own chip, and the mutual inductance with the source and drain of all other chips in the bridge arm, a total of 4n-1. Similarly, the number of source mutual inductances is also 4n-1. Assuming that the currents of each power loop are equal, the stray inductance of the power loop of the mth chip in the upper bridge arm can be written as the following formula:

[0150]

[0151] According to the stray inductance of the commutation circuit of each chip in the upper and lower bridge arms, the total stray inductance of the power circuit can be calculated, as shown in the following formula:.

[0152]

[0153] In the early stage of module design, the basic requirements of switching loss and voltage overshoot must be input to give the requirements for the total stray inductance of the maximum power loop.

[0154] (2) Driving circuit stray inductance:

[0155] The stray inductance of the drive circuit determines the time it takes for the gate voltage of each chip to rise or fall to the threshold voltage, determines the switching delay of the module, and is one of the determining factors for the dynamic current sharing between the bridge arm chips. The design of the drive circuit mainly needs to ensure that the stray inductance of the drive circuit of each chip is close to ensure excellent current sharing characteristics.

[0156] For the common source connection, the stray inductance of the driving circuit of each chip is mainly determined by the gate-level stray inductance, the common source stray inductance, the auxiliary source stray inductance and the corresponding mutual inductance. Among them, the mutual inductance of the gate level includes the mutual inductance with the source and auxiliary source of its own chip, as well as the mutual inductance between the gate level, common source and auxiliary source of other chips in the same bridge arm, a total of 3n-1. Similarly, the number of mutual inductances of the source and the auxiliary source is 3n-1. Assuming that the current of each driving circuit is the same, the stray inductance of the power circuit of the mth chip in the upper bridge arm can be written as the following formula:

[0157]

[0158] According to the stray inductance of the commutation circuit of each chip in the upper and lower bridge arms, the total stray inductance of the driving circuit of each bridge arm can be calculated. Taking the upper bridge arm as an example, the following formula is used:

[0159]

[0160] In the early stage of module design, the maximum allowable total driving circuit stray inductance and the maximum unbalanced percentage of the stray inductance of each chip driving circuit should be given according to the design requirements such as switching frequency and current sharing characteristics.

[0161] (3) Power-drive circuit coupling stray inductance

[0162] For common source connection, the power loop-drive loop coupling stray inductance is the main influencing parameter of the dynamic current sharing of each chip, one of the limiting factors of the maximum allowable switching speed, and one of the influencing factors of the module short-circuit capacity. Therefore, the power-drive loop coupling stray inductance is an important influencing link of the electromagnetic reliability of multi-chip parallel modules.

[0163] The power-drive circuit coupling stray inductance of each chip is mainly composed of the corresponding mutual inductance of the gate level and auxiliary source, as well as the source stray inductance and the corresponding mutual inductance. The number of mutual inductances of the gate level, auxiliary source and power circuit of each chip is 4n, and the source mutual inductance is 4n-1. Assuming that the current of each power circuit is the same, the power-drive circuit coupling stray inductance of the mth chip of the upper bridge arm can be written as the following formula:

[0164]

[0165] In the early stage of module design, the design requirements such as switching frequency, current sharing characteristics, and expected losses must be input to give the allowable coupling stray inductance range of each chip power-drive circuit and the maximum imbalance percentage.

[0166] Therefore, electromagnetic simulation evaluation needs to provide design requirement inputs for the power loop, drive loop, and power-drive loop coupling stray inductance.

[0167] S320: according to the design file, solving the stray inductance and the corresponding mutual inductance of each power module section, and generating a self-inductance-mutual inductance matrix for calculating the lumped parameters of the stray inductance;

[0168] S330: Determine whether the electromagnetic reliability of the semiconductor module meets the requirements

[0169] According to the above formula and the self-inductance-mutual inductance matrix solved by simulation, the lumped parameter results of stray inductance are obtained, and combined with the design requirements of the power circuit, drive circuit, and power-drive circuit coupled stray inductance, it is judged whether the electromagnetic reliability of the module meets the requirements. If the requirements are met, it will enter the next stage. If not, the substrate design will be traced back for the illegal design interval, and the chip layout, substrate structure, etc. will be modified for design iteration.

[0170] It should be noted that the embodiments of the present invention have better practicability and do not impose any form of limitation on the present invention. Any technician familiar with the field may use the technical content disclosed above to change or modify it into an equivalent effective embodiment. However, any modification or equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A semiconductor module substrate, comprising a power metal cladding group, an auxiliary metal cladding group and a chipset group laid on the semiconductor module substrate, characterized in that: The power metal cladding layer group comprises a first power metal cladding layer, a second power metal cladding layer, a third power metal cladding layer, and a fourth power metal cladding layer arranged in sequence along the long side direction of the semiconductor module substrate; The auxiliary metal coating group includes a first auxiliary metal coating, a second auxiliary metal coating, a third auxiliary metal coating, a fourth auxiliary metal coating, and a fifth auxiliary metal coating, wherein The first auxiliary metal coating is arranged between the first power metal coating and the second power metal coating; The second auxiliary metal cladding is arranged in the second power metal cladding and is electrically connected to the first auxiliary metal cladding via a bonding wire; The third auxiliary metal coating is arranged between the third power metal coating and the fourth power metal coating; The fourth auxiliary metal cladding is arranged beside the first auxiliary metal cladding along the short side direction of the semiconductor module substrate; The fifth auxiliary metal cladding is arranged beside the fourth auxiliary metal cladding along the long side direction of the semiconductor module substrate and beside the first power metal cladding; The chipset includes a first chip array, a second chip array, a third chip array and a fourth chip array, The first chip array and the second chip array are arranged in the first power metal cladding layer along the long side direction of the semiconductor module substrate, and are connected to the second power metal cladding layer and the third power metal cladding layer respectively through bonding wires; The third chip array and the fourth chip array are arranged in the third power metal cladding layer along the long side direction of the semiconductor module substrate and connected to the fourth power metal cladding layer through bonding wires, and The first power metal cladding layer provided with the first upper bridge arm drain auxiliary terminal and the second upper bridge arm drain auxiliary terminal is in a first extension shape, and the extension direction is toward the fourth power metal cladding layer and the first power metal cladding layer respectively; The third power metal cladding layer where the lower bridge arm drain auxiliary terminal is provided is in a second extension shape, and the extension direction is toward the fourth power metal cladding layer.

2. The semiconductor module substrate according to claim 1, characterized in that The first chip array, the second chip array, the third chip array and the fourth chip array include several chips of uniform size; the spacing between adjacent chips in the first chip array, the second chip array, the third chip array and the fourth chip array is uniform, and the spacing is smaller than the distance between the first chip array and the fifth auxiliary metal coating, and smaller than the distance between the third chip array and the fourth chip array and the edge of the third power metal coating.

3. The semiconductor module substrate according to claim 1, characterized in that The second auxiliary metal coating is provided with an upper bridge arm gate-level auxiliary terminal; The third auxiliary metal coating is provided with a lower bridge arm gate-level auxiliary terminal; The first auxiliary metal coating, the second auxiliary metal coating, and the third auxiliary metal coating are connected to the gate-level circuit of the chipset; an upper bridge arm source auxiliary terminal is provided in the second power metal coating, and the upper bridge arm source auxiliary terminal is located next to the upper bridge arm gate-level auxiliary terminal; The first power metal cladding is provided with a first upper bridge arm drain auxiliary terminal and a second upper bridge arm drain auxiliary terminal at both end edges along the long side direction of the semiconductor module substrate; The fourth auxiliary metal cladding layer and the fifth auxiliary metal cladding layer are respectively provided with a first temperature sensor auxiliary terminal and a second temperature sensor auxiliary terminal for connecting to the temperature sensitive resistor; A lower bridge arm drain auxiliary terminal is provided at the end edge of the third power metal cladding along the long side direction of the semiconductor module substrate; A first lower bridge arm source auxiliary terminal and a second lower bridge arm source auxiliary terminal are provided at the connecting position of the fourth power metal cladding and the end edge of the third auxiliary metal cladding along the long side direction of the semiconductor module substrate, so that the first lower bridge arm source auxiliary terminal and the second lower bridge arm source auxiliary terminal are arranged on both sides of the lower bridge arm gate level auxiliary terminal.

4. A method for designing a semiconductor module substrate to form a semiconductor module substrate as claimed in any one of claims 1 to 3, characterized in that: The following steps are involved: Based on the packaging form and application scenario power level of the semiconductor module, determine the process route of the semiconductor module, formulate the design boundary of the semiconductor module substrate to generate design files for heating and electromagnetic simulation evaluation; Based on the design file, simulating and calculating the current output of the chip in the semiconductor module substrate at an allowable junction temperature to determine the structural design of the iterative semiconductor module substrate; Based on the design file, calculating the spurious parameters of each section of the power module in the semiconductor module substrate; Import the self-inductance-mutual inductance matrix into the design file to evaluate the voltage overshoot, dynamic current sharing, and maximum switching speed of the semiconductor module substrate.

5. The design method according to claim 4, characterized in that: Based on the packaging form and application scenario power level of the semiconductor module, the process route of the semiconductor module is determined, and the design boundary of the semiconductor module substrate is formulated to generate the design file for heating and electromagnetic simulation evaluation. The steps include: Generate expected technical indicators based on the application scenarios of semiconductor modules; generating material and size information of a semiconductor module substrate according to the desired technical specifications; Generate a process route according to the expected technical indicators; Formulate design boundaries for semiconductor module substrates based on material and dimensional information and process routes; Based on the material and size information and the design boundary, a design file including the structural design of the chip, bonding wires and terminals in the semiconductor module substrate is generated.

6. The design method according to claim 4, characterized in that: The steps of simulating and calculating the current output information of the chip in the semiconductor module substrate at the allowable junction temperature based on the design file to determine the structural design of the iterative semiconductor module substrate include: Based on the design file, add the heat dissipation channel of the semiconductor module to define the thermal conductivity and heat capacity of the coating of the semiconductor module substrate; Set the simulation heat dissipation configuration according to the heat dissipation conditions of the application scenario of the semiconductor module; Based on the simulated heat dissipation configuration, the chip on the semiconductor module substrate is used as the heat source, according to the following formula: Calculate the steady-state equivalent thermal resistance R between the chip and the coolant th , where P s is the specific loss, T jmax is the specific loss P s Maximum junction temperature under According to the standard operating conditions of the semiconductor module, calculate the switching loss P at the standard operating voltage under standard operating conditions sw (I) and conduction loss P con (I) and determine the maximum allowable junction temperature T according to the chip data sheet ja , and according to the following formula: Calculate the maximum total losses P(I) of the semiconductor module.

7. The design method according to claim 4, characterized in that: Based on the design file, the step of calculating the stray parameters of each section of the power module in the semiconductor module substrate includes: Based on the design documents, the design requirements for the input power circuit, drive circuit, and power-drive circuit coupling stray inductance; According to the design documents, solve the stray inductance and corresponding mutual inductance of each power module section, and generate the self-inductance-mutual inductance matrix to calculate the lumped parameters of stray inductance; Determine whether the electromagnetic reliability of the semiconductor module meets the requirements.

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