A memory and an electronic device

Abstract

Embodiments of the present application disclose a memory and an electronic device; wherein, the memory includes a first metal layer, a storage block, a peripheral part, and a last metal layer cover plate; a first electromagnetic shielding structure is formed on the first metal layer; the storage block is disposed on the first metal layer, and the first electromagnetic shielding structure is disposed around the storage block; the peripheral part surrounds the edge of the first metal layer, a second electromagnetic shielding structure is formed on the peripheral part, and a plurality of vias are formed in the second electromagnetic shielding structure; the last metal layer cover plate covers the peripheral part, and a third electromagnetic shielding structure is formed on the last metal layer cover plate; the first electromagnetic shielding structure, the second electromagnetic shielding structure, and the third electromagnetic shielding structure can enclose an electromagnetic shielding space, and the storage block is received in the electromagnetic shielding space. Embodiments of the present application provide a solution for preventing electromagnetic and other magnetic interferences for the memory, which can effectively shield the electromagnetic influence in the external environment and has a better electromagnetic shielding effect.

Description

Technical Field

[0001] This application belongs to the technical field of electronic products, and particularly relates to a memory and an electronic device. Background Art

[0002] The microcontroller unit (MCU) has developed to below 28nm. Due to its high integration density, it is difficult to use the previous electronic storage mode for data storage. In recent years, a new storage solution, namely the magnetic random access memory (MRAM), has been proposed in the industry. It has the characteristics of high integration density, low power consumption, and fast read / write speed.

[0003] Since the development of microprocessors, the front-end floating gate / electron trapping and other modes have been unable to adapt to the 22nm and below processes due to integration density limitations. There are currently two modes for 22nm and below: the magnetic random access memory (MRAM) and the resistive random access memory (ReRAM). Both of these modes characterize the storage state by high and low resistance values, and both have the possibility of further integration. They also have low energy consumption and fast response speed, meeting the current requirements for higher computing power and storage space of the microcontroller unit (MCU). In particular, the magnetic random access memory (MRAM) can achieve a storage level of GB (gigabit).

[0004] However, it has been found that the magnetic random access memory (MRAM) has high requirements for the application environment magnetic field during application, but its own anti-magnetic ability is very limited. In related technologies, the current anti-magnetic shielding packaging methods all generate large structural redundancies and have poor anti-magnetic effects. Summary of the Invention

[0005] This application aims to provide a memory and an electronic device, at least solving the problem that the anti-electromagnetic interference ability of the storage block in the existing memory is low and it is easily interfered by the electromagnetic field in the surrounding environment.

[0006] To solve the above technical problems, this application is implemented as follows:

[0007] In a first aspect, an embodiment of this application provides a memory, which includes:

[0008] A first metal layer, on which a first electromagnetic shielding structure is formed;

[0009] A storage block, which is arranged on the first metal layer, and the first electromagnetic shielding structure is arranged around the storage block;

[0010] An outer peripheral part, which is arranged around the edge of the first metal layer, a second electromagnetic shielding structure is formed on the outer peripheral part, and a plurality of vias are formed in the second electromagnetic shielding structure; and

[0011] A last metal layer cover plate, which is covered on the outer peripheral part, and a third electromagnetic shielding structure is formed on the last metal layer cover plate;

[0012] The first electromagnetic shielding structure, the second electromagnetic shielding structure and the third electromagnetic shielding structure can enclose to form an electromagnetic shielding space, and the storage block is received in the electromagnetic shielding space.

[0013] In a second aspect, an embodiment of the present application provides an electronic device, and the electronic device includes the memory as described above.

[0014] In the embodiment of the present application, a scheme for preventing electromagnetic interference is provided for the memory. By adjusting the metal wiring layer structure of the latter stage of the memory, the entire storage block can be comprehensively wrapped (for example, six-sided wrapping) without increasing the existing manufacturing process. In this way, the closing effect is good, and the influence of the electric and magnetic fields in the environment can be effectively blocked, improving the electromagnetic protection ability of the existing memory itself. Compared with the prior art, it has a better electromagnetic protection effect. Moreover, this scheme takes the entire storage block as a unit for overall isolation, and the manufacturing difficulty is relatively low.

[0015] Additional aspects and advantages of the present application will be given in part in the following description, will become apparent in part from the following description, or will be understood through the practice of the present application. Description of the Drawings

[0016] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0017] Figure 1 is one of the schematic structural diagrams of the memory provided by the embodiment of the present application;

[0018] Figure 2 is a schematic cross-sectional view of the electromagnetic shielding structure outside the storage block of the memory provided by the embodiment of the present application;

[0019] Figure 3 is one of the schematic diagrams of the electromagnetic protection principle of the memory provided by the embodiment of the present application;

[0020] Figure 4 is another schematic diagram of the electromagnetic protection principle of the memory provided by the embodiment of the present application;

[0021] Figure 5It is the third schematic structural diagram of the memory provided by the embodiments of the present application;

[0022] Figure 6 It is the fourth schematic structural diagram of the memory provided by the embodiments of the present application;

[0023] Figure 7 It is Figure 6 the schematic structural diagram of a single MRAM microcell shown in;

[0024] Figure 8 It is the schematic structure of the magnetic tunnel junction device of the memory provided by the embodiments of the present application.

[0025] Reference numerals:

[0026] 1 - First metal layer, 2 - Peripheral part, 3 - Via hole, 4 - Final metal layer cover plate, 5 - First electromagnetic shielding layer, 6 - Second electromagnetic shielding layer, 7 - Isolation layer, 8 - MRAM microcell, 801 - Magnetic tunnel junction device, 8011 - Fixed magnetic layer, 8012 - Free magnetic layer, 8013 - Insulating layer, 9 - Transistor array layer, 10 - Drain terminal, 11 - Source terminal, 12 - Gate terminal, 13 - Lead, 14 - Spacer layer, 15 - Spacer ring. Detailed implementation manners

[0027] Hereinafter, embodiments of the present application will be described in detail. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0028] The terms "first" and "second" in the description and claims of the present application may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "plurality" is two or more. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally means an "or" relationship between the associated objects before and after.

[0029] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0030] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected" and "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0031] The following will be combined with Figures 1 to 8 to describe the specific structure of the memory provided according to the embodiments of the present application.

[0032] The memory provided according to the embodiments of the present application, referring to Figure 1 and Figure 2 , includes a first metal layer 1, a memory block, a peripheral part 2, and a last metal layer cover plate 4. Among them, a first electromagnetic shielding structure is formed on the first metal layer 1; the memory block is disposed on the first metal layer 1, and the first electromagnetic shielding structure surrounds the memory block; the peripheral part 2 is disposed around the edge of the first metal layer 1, a second electromagnetic shielding structure is formed on the peripheral part 2, and a plurality of vias 3 are formed in the second electromagnetic shielding structure; the last metal layer cover plate 4 is covered on the peripheral part 2, and a third electromagnetic shielding structure is formed on the last metal layer cover plate 4; wherein, the first electromagnetic shielding structure, the second electromagnetic shielding structure, and the third electromagnetic shielding structure can enclose an electromagnetic shielding space, and the memory block is received in the electromagnetic shielding space.

[0033] The first metal layer 1 can be used to support the memory block and the peripheral part 2.

[0034] Referring to Figure 1, the peripheral part 2 itself can enclose to form an accommodation space, and the last metal layer cover plate 4 is covered on the top of the peripheral part 2, which can be used to enclose the accommodation space. The peripheral part 2 and the last metal layer cover plate 4 cooperate to cover the entire first metal layer 1 in a mode of integrally enclosing to form a protective cover.

[0035] Among them, the first electromagnetic shielding structure is formed on the first metal layer 1, the second electromagnetic shielding structure is formed on the peripheral part 2, and the third electromagnetic shielding structure is formed on the last metal layer cover plate 4. In this way, the first electromagnetic shielding structure, the second electromagnetic shielding structure and the third electromagnetic shielding structure can conduct comprehensive (such as six-sided) electromagnetic shielding protection for it from the top surface, bottom surface and the entire side part (such as four side surfaces) of the storage block, so as to effectively block the influence of external electromagnetic interference, and thus can effectively protect the internal storage block from electromagnetic interference.

[0036] That is to say, the first metal layer 1 serves as the bottom plate and can conduct electromagnetic shielding protection for the bottom surface of the storage block through the first electromagnetic shielding structure formed thereon. The peripheral part 2 serves as the side part and can conduct electromagnetic shielding protection for the four sides (side parts) of the storage block through the second electromagnetic shielding structure formed thereon. The last metal layer cover plate 4 serves as the top plate and can conduct electromagnetic shielding protection for the top surface of the storage block through the third electromagnetic shielding structure formed thereon. In this way, comprehensive protection for the storage block can be formed, so that each surface of the storage block can be effectively protected.

[0037] In the embodiment of the present application, a good electromagnetic interference prevention scheme is provided for the memory. Refer to Figure 1 , by adjusting the metal wiring layer structure in the latter stage of the memory, the entire storage block can be comprehensively wrapped (for example, truly achieve six-sided wrapping) without increasing the existing manufacturing process, forming a mode of an electromagnetic shielding protection cover, so as to control the influence of electromagnetic interference in the external environment on the internal storage block.

[0038] The electromagnetic interference prevention scheme provided by the embodiment of the present application has the characteristics of good closing effect. The influence of the electromagnetic field in the environment can be well blocked without affecting the internal storage block arranged therein, which improves the problem of poor anti-magnetic ability of the existing memory itself. Compared with the prior art, the scheme of the present application has better electromagnetic interference prevention effect, which helps to greatly improve the performance of the memory and expand the application range of the memory.

[0039] In addition, the scheme of the present application takes the entire storage block as a unit for overall isolation, and its manufacturing difficulty is relatively low. At the same time, it improves the edge area of the storage block. Therefore, it has almost no influence on the size of the chip.

[0040] See Figure 3 When the storage block is entirely housed within the electromagnetic shielding space enclosed by the first electromagnetic shielding structure, the second electromagnetic shielding structure, and the third electromagnetic shielding structure, the storage block can be unaffected by the electric and magnetic fields in the external environment. That is, the first electromagnetic shielding structure, the second electromagnetic shielding structure, and the third electromagnetic shielding structure are equivalent to forming an electromagnetic shielding wall to protect the internal storage block.

[0041] Among them, the structures of the first electromagnetic shielding structure, the second electromagnetic shielding structure, and the third electromagnetic shielding structure are, for example, the same, and they can be connected to each other to enclose the electromagnetic shielding space to protect the internal storage block.

[0042] In some embodiments of the present application, the first electromagnetic shielding structure, the second electromagnetic shielding structure, and the third electromagnetic shielding structure are the same, and each includes: a first electromagnetic shielding layer 5 or a second electromagnetic shielding layer 6; one of the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6 is an electromagnetic field shielding layer, and the other of the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6 is a static magnetic field shielding layer.

[0043] For example, the first electromagnetic shielding structure, the second electromagnetic shielding structure, and the third electromagnetic shielding structure are all single-layer structures and each includes the first electromagnetic shielding layer 5, and, for example, the first electromagnetic shielding layer 5 is an electromagnetic field shielding layer. See Figure 3 , in this design, a mode of an electromagnetic field shielding cover is formed outside the storage block, which can effectively block the electromagnetic interference of the external electromagnetic field on the internal storage block, thereby being able to perform electromagnetic protection on the internal storage block.

[0044] Again, for example, the first electromagnetic shielding structure, the second electromagnetic shielding structure, and the third electromagnetic shielding structure are all single-layer structures and each includes the second electromagnetic shielding layer 6, and the second electromagnetic shielding layer 6 is, for example, a static magnetic field shielding layer. This design is for the possible external static magnetic field, and a static magnetic shielding is set outside the storage area as a magnetic isolation method. The static magnetic field shielding layer will also shield the magnetic field, that is, a magnetic field shielding is formed within its protected area. See Figure 4 . In this design, a mode of a static magnetic field shielding cover is formed outside the storage block, which can effectively block the influence of the external static magnetic field on the internal storage area, thereby being able to perform static magnetic protection on the internal storage block.

[0045] In some embodiments of the present application, see Figure 2, the first electromagnetic shielding structure, the second electromagnetic shielding structure, and the third electromagnetic shielding structure are all multi-layer structures and have the same structure, which includes: a first electromagnetic shielding layer 5, a second electromagnetic shielding layer 6, and an isolation layer 7. The first electromagnetic shielding layer 5, the second electromagnetic shielding layer 6, and the isolation layer 7 are stacked, and the isolation layer 7 is sandwiched between the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6. One of the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6 is an electromagnetic field shielding layer, and the other of the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6 is a static magnetic field shielding layer.

[0046] See Figure 2 , under this structural design, a good electromagnetic shielding structure can be formed outside the storage block, and this electromagnetic shielding structure has the ability to prevent electromagnetic waves and static magnetic fields at the same time. The electromagnetic shielding effect is better.

[0047] See Figure 2 , when the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6 are applied simultaneously, the materials of the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6 are different, which involves combining two different materials.

[0048] In order to prevent the two materials from diffusing into each other after combination and affecting the electromagnetic protection effect, a diffusion prevention layer, that is, the isolation layer 7, is designed in the solution of this application between the two different materials.

[0049] See Figure 2 In the solution shown, the electromagnetic field shielding layer is located in the inner layer, which can play the role of shielding electric field interference; the static magnetic field shielding layer is located in the outer layer, which can play the role of shielding static magnetic field interference; and the isolation layer 7 is located between the two, that is, the middle layer, which can play the role of preventing the materials of the electromagnetic field shielding layer and the static magnetic field shielding layer from diffusing into each other.

[0050] It should be noted that the solution provided in the embodiments of this application is not limited to Figure 2 the embodiment shown in, that is to say, the positions of the electromagnetic field shielding layer and the static magnetic field shielding layer can be interchanged.

[0051] For example, the electromagnetic field shielding layer is located in the outer layer, the static magnetic field shielding layer is located in the inner layer, and the isolation layer 7 is located in the middle layer. Under this structure, a double magnetic shielding structure can also be formed, and it can also play the role of preventing electromagnetic waves and static magnetic fields at the same time.

[0052] In some embodiments of this application, one of the materials of the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6 is a metal material, and the other of the materials of the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6 is a soft magnetic material.

[0053] Among them, the metal material includes metallic copper, which can play a role in shielding electromagnetic waves. It can be used as the material for manufacturing the electromagnetic field shielding layer. Refer to Figure 3 , and the metal material isolates the interior of the space from being affected by the external electric field.

[0054] Among them, the soft magnetic material includes zinc manganese alloy or chromium zirconium alloy. The soft magnetic material can shield static magnetic fields and form a magnetic field shielding within its protected area to provide a static magnetic protection effect for the internal storage block. It can be used as the material for manufacturing the static magnetic shielding layer.

[0055] Refer to Figure 4 , and the soft magnetic material will twist the magnetic field direction to shield the internal environment from the magnetic field, so that the internally installed storage block can resist the influence of external magnetic fields.

[0056] Among them, the isolation layer 7 can be made of a relatively dense material, for example. It can effectively block the mutual diffusion between metals.

[0057] In some embodiments of the present application, the material of the isolation layer 7 is thallium or thallium nitride.

[0058] Once the metal material (such as copper) and the soft magnetic material (zinc manganese alloy or chromium zirconium alloy) diffuse into each other, the corresponding anti-electromagnetic field and static magnetic field capabilities will be significantly weakened. Therefore, in order to prevent the mutual diffusion of the metal material and the soft magnetic material, the isolation layer 7 is also designed to be added between these two materials, and the isolation layer 7 can be made of thallium or thallium nitride.

[0059] In a specific embodiment of the present application, refer to Figure 2 , the first electromagnetic shielding structure, the second electromagnetic shielding structure and the third electromagnetic shielding structure are all multi-layer structures and have the same structure. They include: a first electromagnetic shielding layer 5, a second electromagnetic shielding layer 6 and an isolation layer 7. The first electromagnetic shielding layer 5, the second electromagnetic shielding layer 6 and the isolation layer 7 are stacked, and the isolation layer 7 is sandwiched between the first electromagnetic shielding layer 5 and the second electromagnetic shielding layer 6. Among them, the first electromagnetic shielding layer 5 is located on the inner layer, and the second electromagnetic shielding layer 6 is located on the outer layer; the first electromagnetic shielding layer 5 is made of metallic copper material to shield electromagnetic waves and resist external electric field interference; the second electromagnetic shielding layer 6 is made of zinc manganese alloy material or chromium zirconium alloy material to shield the interference of static magnetic fields; the isolation layer 7 is made of thallium material or thallium nitride material to block the mutual diffusion between metals.

[0060] In this way, the first electromagnetic shielding structure, the second electromagnetic shielding structure and the third electromagnetic shielding structure can provide effective dual magnetic protection for the internal storage block, that is, they can simultaneously achieve the effects of preventing electromagnetic waves and static magnetic fields.

[0061] For the memory according to the embodiment of the present application, refer to Figures 5 to 7 , the storage block includes a plurality of MRAM micro-units 8, and the plurality of MRAM micro-units 8 are arranged in a matrix form on the first metal layer 1. Moreover, an etching area is formed on the first metal layer 1, and the etching area is distributed outside the storage block and between the MRAM micro-units 8, and the first magnetic shielding structure is arranged in the etching area in a filling manner, for example.

[0062] Refer to Figure 5 and Figure 6 , a plurality of MRAM micro-units 8 are arranged on the first metal layer 1. At the same time, the first electromagnetic shielding structure is also arranged on the first metal layer 1.

[0063] Among them, the stacking of each layer in the first electromagnetic shielding structure can be realized by physical vapor deposition. Similarly, the stacking of each layer in the second electromagnetic shielding structure and the third electromagnetic shielding structure can also be realized by physical vapor deposition. Physical vapor deposition is well known to those skilled in the art, and will not be specifically described herein.

[0064] Among them, the first metal layer 1 is an island structure, and the metal layer in the first electromagnetic shielding structure can be used for interconnection.

[0065] In some embodiments of the present application, refer to Figure 7 , each of the MRAM micro-units 8 includes a magnetic tunnel junction device 801.

[0066] Actually, for the memory according to the embodiment of the present application, refer to Figure 1 , it further includes a transistor array layer 9, and the first metal layer 1 is arranged on the transistor array layer 9.

[0067] The transistor array layer 9 includes a plurality of transistors. Each of the transistors includes a drain terminal 10, a source terminal 11, and a gate terminal 12, and leads 13 (for example, drain leads, source leads, gate leads) are respectively led out from the drain terminal 10, the source terminal 11, and the gate terminal 12, and the leads 13 can extend out of the electromagnetic shielding space through vias 3 formed on the second electromagnetic shielding structure. And the magnetic tunnel junction device 801 is electrically coupled to the drain terminal 10.

[0068] In this way, by driving a current through a transistor (such as a MOSFET) under the first metal layer 1, the storage state of the magnetic tunnel junction device 801 can be controlled.

[0069] In addition, refer to Figure 5, a spacer ring 15 is provided on the outer periphery of the drain terminal 10, the source terminal 11, and the gate terminal 12.

[0070] In some embodiments of the present application, refer to Figure 8 , the magnetic tunnel junction device 801 includes a fixed magnetic layer 8011, a free magnetic layer 8012, and an insulating layer 8013. The fixed magnetic layer 8011, the free magnetic layer 8012, and the insulating layer 8013 are stacked, and the insulating layer 8013 is sandwiched between the fixed magnetic layer 8011 and the free magnetic layer 8012.

[0071] Among them, when a first current is applied to the free magnetic layer 8012, it has the same magnetism as the fixed magnetic layer 8011; when a second current is applied to the free magnetic layer 8012, it has the opposite magnetism to the fixed magnetic layer 8011.

[0072] That is to say, the change of the current is driven by the lower transistor (such as MOSFET) to change the magnetic pole of the free magnetic layer 8012, so as to change the storage state.

[0073] Specifically, 0 or 1 stored is defined by the direction of the magnetic pole of the free magnetic layer 8012. Different magnetic pole directions will affect the path resistance value (low resistance in the same direction, high resistance in the opposite direction). The free magnetic layer 8012 can achieve the flipping of the magnetic pole through different current control drives, thereby controlling the stored content.

[0074] For example, the directions of the first current and the second current are different.

[0075] For another example, the current values of the first current and the second current are different. Those skilled in the art can flexibly select according to specific needs, and the present application does not limit this.

[0076] In addition, the drain terminal 10, the source terminal 11, and the gate terminal 12 respectively represent three terminals, and the required read / write / erase block can be located through the corresponding lead addressing method, and the periphery corresponds to an addressing and parsing circuit.

[0077] In some embodiments of the present application, refer to Figure 1 , a spacer layer 14 is provided between the transistor array layer 9 and the first metal layer 1.

[0078] In addition, the present application embodiment also provides a manufacturing method of the memory, which will be described below.

[0079] After the first metal layer 1 is fabricated, the periphery of the storage block, i.e., the portions around each MRAM microcell 8, is etched out separately first. Then, soft magnetic materials, spacer materials, and metal materials are filled into the etched area by physical vapor deposition (PVD) to form the first electromagnetic shielding structure on the first metal layer 1. After that, it is polished flat by, for example, chemical mechanical polishing (CMP).

[0080] Through the above process, the first electromagnetic shielding structure is fabricated on the first metal layer 1.

[0081] There is an isolation ring around each MRAM microcell 8, and its specific width can be adjusted according to the integration degree of the MRAM microcells, for example, it is 2 μm.

[0082] As the density of the MRAM memory increases, the corresponding interval size can be adjusted. Currently, the MRAM memory can already be integrated into the 14nm platform, and the structure provided by the embodiments of the present application can also be adjusted to the acceptable range of the 14nm platform accordingly, only by adjusting the interval size.

[0083] A protection ring, i.e., the peripheral part 2, is additionally provided on the periphery of the storage block. And the second electromagnetic shielding structure is fabricated on the peripheral part 2, and a plurality of vias 3 are formed in the second electromagnetic shielding structure.

[0084] Among them, the via 3 is formed, for example, by etching through the multi-layer metal layers of the second electromagnetic shielding structure and the isolation layer 7 between the multi-layer metal layers.

[0085] As described above, a plurality of leads 13 are led out from each MRAM microcell in the storage block. These vias 3 designed on the second electromagnetic shielding structure can lead the leads out of the storage block, that is, the vias 3 can avoid the leads of the storage block.

[0086] It should be noted that the area on the peripheral part 2 other than the vias 3 is filled with the second electromagnetic shielding structure to constitute electromagnetic protection for the four sides around the storage block.

[0087] In some embodiments of the present application, the second electromagnetic shielding structure can be disposed in the peripheral part 2 in a filling manner; among them, the stacked arrangement of the soft magnetic material layer, spacer layer, and metal material layer of the second electromagnetic shielding structure can be realized by physical vapor deposition (PVD), and then it is polished flat by, for example, chemical mechanical polishing (CMP).

[0088] After the last metal layer cover plate 4 is manufactured, for example, a certain area is etched thereon, and then the third electromagnetic shielding structure is disposed in the last metal layer cover plate 4, for example, by filling.

[0089] For example, the lamination of the soft magnetic material layer, the spacer layer, and the metal material layer of the third electromagnetic shielding structure is realized by physical vapor deposition (PVD), and then it is polished by, for example, chemical mechanical polishing (CMP).

[0090] The beneficial effects of the solution of the present application are as follows:

[0091] The solution provided by the embodiment of the present application takes the MRAM storage block as a unit for overall isolation, which is equivalent to setting a protective cover for the MRAM storage block to achieve efficient dual magnetic shielding of electromagnetic and static magnetism, and the protective cover achieves full coverage (for example, six-sided coverage). The solution of the embodiment of the present application is different from the existing electromagnetic shielding by encapsulating a single unit in the storage block.

[0092] The isolation effect of the existing electromagnetic shielding of a single storage unit is not good. It is not six-sided covered, and some isolation layers even directly contact the free magnetic layer in the MRAM micro-unit, greatly weakening the isolation effect (magnetic pole isolation requires a certain isolation space). At the same time, the sidewall isolation structure of a single storage unit will damage the size of the unit, greatly affecting the possibility of further high-density integration. The biggest problem with encapsulation shielding is the high difficulty of encapsulation customization, and it is difficult to achieve six-sided full enclosure; moreover, for applications such as microprocessors with MRAM as storage, it is impossible to distinguish the computing part and the storage part, so the overall product iteration and integration are poor.

[0093] Compared with some previous cases, the biggest feature of the solution of the present application is to abandon the concept of a single storage unit and adopt a mode of overall protection for the entire storage block, with good sealing effect and high integration. This solution can be integrated with a process below 14nm.

[0094] The existing MRAM storage block structure is generally concentrated before the fourth metal layer, that is, the front end, while the solution of the present application can be extended for multiple combinations in the future and can continue, and its longitudinal structure is also suitable. Since the last metal layer is far apart, there is almost no influence of parasitic capacitance and no influence on the reaction speed, which is one of the reasons for choosing the last metal.

[0095] In addition, the present application has no limitation on the size of a single storage unit, and even has good adaptability to possible multi-layer structures.

[0096] The embodiment of the present application also provides an electronic device, and the electronic device includes the memory as described above.

[0097] The electronic devices provided by the embodiments of the present application are, for example, smart phones, tablet computers, laptop computers, etc. The specific types of the electronic devices are not limited in the present application.

[0098] Other components and operations of the electronic devices according to the embodiments of the present application are known to those of ordinary skill in the art and will not be described in detail here.

[0099] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0100] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A memory, characterized in that, Comprising: A first metal layer (1) on which a first electromagnetic shielding structure is formed; A storage block disposed on the first metal layer (1), and the first electromagnetic shielding structure is disposed around the storage block; A peripheral portion (2) surrounding the edge of the first metal layer (1), a second electromagnetic shielding structure is formed on the peripheral portion (2), and a plurality of vias (3) are formed in the second electromagnetic shielding structure; and A last metal layer cover plate (4) covering the peripheral portion (2), and a third electromagnetic shielding structure is formed on the last metal layer cover plate (4); The first electromagnetic shielding structure, the second electromagnetic shielding structure and the third electromagnetic shielding structure enclose an electromagnetic shielding space, and the storage block is received in the electromagnetic shielding space; The memory further includes a transistor array layer (9), and the first metal layer (1) is disposed on the transistor array layer (9); The transistor array layer (9) includes a plurality of transistors, each transistor includes a drain terminal (10), a source terminal (11) and a gate terminal (12), and leads (13) are respectively led out from the drain terminal (10), the source terminal (11) and the gate terminal (12), and the leads (13) extend out of the electromagnetic shielding space through the vias (3) formed in the second electromagnetic shielding structure.

2. The memory according to claim 1, characterized in that, The first electromagnetic shielding structure, the second electromagnetic shielding structure and the third electromagnetic shielding structure are the same, and each of them includes: a first electromagnetic shielding layer (5) or a second electromagnetic shielding layer (6); One of the first electromagnetic shielding layer (5) and the second electromagnetic shielding layer (6) is an electromagnetic field shielding layer, and the other of the first electromagnetic shielding layer (5) and the second electromagnetic shielding layer (6) is a static magnetic field shielding layer.

3. The memory according to claim 1, characterized in that, The first electromagnetic shielding structure, the second electromagnetic shielding structure and the third electromagnetic shielding structure are all multi-layer structures and have the same structure, and they include: a first electromagnetic shielding layer (5), a second electromagnetic shielding layer (6) and an isolation layer (7), the first electromagnetic shielding layer (5), the second electromagnetic shielding layer (6) and the isolation layer (7) are stacked, and the isolation layer (7) is sandwiched between the first electromagnetic shielding layer (5) and the second electromagnetic shielding layer (6); One of the first electromagnetic shielding layer (5) and the second electromagnetic shielding layer (6) is an electromagnetic field shielding layer, and the other of the first electromagnetic shielding layer (5) and the second electromagnetic shielding layer (6) is a static magnetic field shielding layer.

4. The memory according to claim 2 or 3, characterized in that, One of the first electromagnetic shielding layer (5) and the second electromagnetic shielding layer (6) is made of a metal material, and the other of the first electromagnetic shielding layer (5) and the second electromagnetic shielding layer (6) is made of a soft magnetic material.

5. The memory according to claim 3, characterized in that, The material of the isolation layer (7) is thallium or thallium nitride.

6. The memory according to claim 1, characterized in that, The storage block includes a plurality of MRAM micro-units (8), and the plurality of MRAM micro-units (8) are arranged in a matrix form on the first metal layer (1); Etching regions are formed on the first metal layer (1), and the etching regions are distributed outside the storage block and between the MRAM micro-units (8), and the first electromagnetic shielding structure is disposed in the etching regions.

7. The memory according to claim 6, characterized in that, Each of the MRAM micro-units (8) includes a magnetic tunnel junction device (801); The magnetic tunnel junction device (801) is electrically coupled to the drain terminal (10).

8. The memory according to claim 7, characterized in that, The magnetic tunnel junction device (801) includes a fixed magnetic layer (8011), a free magnetic layer (8012) and an insulating layer (8013), and the fixed magnetic layer (8011), the free magnetic layer (8012) and the insulating layer (8013) are stacked, and the insulating layer (8013) is sandwiched between the fixed magnetic layer (8011) and the free magnetic layer (8012).

9. The memory according to claim 7, characterized in that, A spacer layer (14) is disposed between the transistor array layer (9) and the first metal layer (1).

10. An electronic device, characterized in that, Comprising a memory according to any one of claims 1-9.

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