A semiconductor device, a memory, and a storage system

Abstract

The application discloses a semiconductor device, a memory and a storage system, the semiconductor device comprising a substrate, a stack layer on the substrate and a virtual channel structure, the stack layer comprising a stepped region, the virtual channel structure comprising a plurality of and penetrating the stack layer along a first direction perpendicular to the substrate. Wherein, each virtual channel structure comprises a center structure and a plurality of outward protruding branch structures, in at least part of the virtual channel structure, the plurality of outward protruding branch structures are uniformly spaced around the center structure and connected with the center structure, and the plurality of outward protruding branch structures protrude outward relative to the center structure along a second direction perpendicular to the first direction and away from the center structure. The shape of the virtual channel structure makes the upper and lower parts consistent in shape when etching the virtual channel hole, that is, the shape retention is good, and the support performance is better. In addition, since the size of the virtual channel structure in the application is large, the aspect ratio can be reduced, and therefore the etching difficulty of the channel hole can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to electronic devices, and more particularly, to a semiconductor device, a memory, and a storage system. BACKGROUND

[0002] NAND memory device is a non-volatile storage product with low power consumption, light weight and good performance, which has been widely used in electronic products. The planar structure of NAND device has reached the limit of actual expansion. In order to further improve the storage capacity and reduce the storage cost per bit, 3D NAND memory is proposed. In the structure of 3D NAND memory, the way of vertically stacking multiple layers of data storage units is adopted to realize the stacked memory structure.

[0003] The preparation process of NAND includes forming a stack layer alternately stacked by insulating layers and sacrificial layers, and then removing the sacrificial layers to form a gate layer. When the sacrificial layers are removed, the stack layer is easy to collapse, so a dummy channel structure penetrating through the stack layer is used to support the stack layer to prevent the insulating layer from collapsing.

[0004] In the prior art, a circular dummy channel structure is used. With the increase of the thickness of the stack layer, the etching difficulty of the dummy channel hole (DCH) gradually increases (the top size is large and the bottom size is small), and a large enough top size is needed to ensure that it can be etched to the bottom. However, a larger top size also has problems. Even if the bottom is opened, the shape of the bottom of the DCH will change due to the loading effect, and this poor shape retention has a negative impact on the support effect of the DCH near the bottom. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a semiconductor device, a memory, and a storage system, which aims to reduce the etching difficulty of DCH and improve the shape retention of the dummy channel column to further improve the support performance.

[0006] In one aspect, the embodiments of the present application provide a semiconductor device, comprising:

[0007] a substrate;

[0008] a stack layer located on the substrate, the stack layer comprising a staircase region; and

[0009] a dummy channel structure penetrating through the staircase region along a first direction, the first direction being a direction perpendicular to the substrate;

[0010] wherein the dummy channel structure comprises a center structure extending along the first direction and a plurality of outer protruding branch structures, and the dummy channel structure comprises a plurality of

[0011] In at least some of the virtual channel structures, the plurality of outward protruding branch structures are evenly spaced around and connected to the central structure, and the plurality of outward protruding branch structures protrude in a second direction relative to the central structure, the second direction being perpendicular to the first direction and away from the central structure.

[0012] Further, in each of the virtual channel structures, the plurality of outward protruding branch structures are evenly spaced around the central structure

[0013] Further, each of the outward protruding branch structures has an equal length protruding in the second direction.

[0014] Further, the virtual channel structure includes three outward protruding branch structures, and the virtual channel structure has a Y shape in a cross section perpendicular to the first direction, and an included angle between two adjacent outward protruding branch structures is equal to 120 degrees.

[0015] Further, the outward protruding branch structure has a rectangular shape in a cross section perpendicular to the first direction, and the central structure has a triangular shape in a cross section perpendicular to the first direction, and one side of the rectangular shape is connected to one side of the triangular shape.

[0016] Further, some of the virtual channel structures include two outward protruding branch structures, and the virtual channel structure has a V shape in a cross section perpendicular to the first direction, and an included angle between two adjacent outward protruding branch structures is equal to 120 degrees.

[0017] Further, the virtual channel structure includes a plurality of first virtual channel structures having three outward protruding branch structures and a plurality of second virtual channel structures having two outward protruding branch structures, the first virtual channel structure has a Y shape in a cross section perpendicular to the first direction, and the second virtual channel structure has a V shape in a cross section perpendicular to the first direction.

[0018] Further, an included angle between two adjacent outward protruding branch structures in each of the first virtual channel structures is equal to 120 degrees, and an included angle between two adjacent outward protruding branch structures in each of the second virtual channel structures is equal to 120 degrees.

[0019] Further, the semiconductor device further includes:

[0020] a plurality of gate line slits extending through the stack layer in the first direction, the plurality of gate line slits extending in a third direction, the third direction being a direction parallel to the substrate;

[0021] wherein the virtual channel structure is located between two adjacent gate line slits.

[0022] Further, the plurality of first dummy channel structures are arranged into one or more rows along the third direction, and the plurality of second dummy channel structures are arranged into one row along the third direction; two adjacent gate line slits include a first gate line slit and a second gate line slit, and the second gate line slit is adjacent to the plurality of second dummy channel structures.

[0023] Further, the plurality of first dummy channel structures and the plurality of second dummy channel structures are staggered along the third direction.

[0024] Further, the Y-shaped opening of the first dummy channel structure is opposite to the first gate line slit, and the V-shaped opening of the second dummy channel structure is opposite to the first gate line slit.

[0025] Further, the plurality of dummy channel structures are uniformly spaced.

[0026] Further, the stack layer includes insulating layers and gate layers which are alternately stacked, and the semiconductor device further includes:

[0027] a plurality of word line contacts extending along the first direction and contacting each of the gate layers at the bottom, the plurality of word line contacts being located in the staircase region.

[0028] wherein the plurality of dummy channel structures are arranged around and spaced apart from the word line contacts.

[0029] Further, the stack layer further includes a storage region, the staircase region is located at the periphery of the storage region, and the stack layer has a stepped structure in the staircase region.

[0030] In another aspect, an embodiment of the present application provides a memory, comprising:

[0031] the semiconductor device provided by any of the above embodiments;

[0032] a peripheral circuit, the peripheral circuit being electrically connected to the semiconductor device.

[0033] In still another aspect, an embodiment of the present application provides a memory system, comprising:

[0034] the memory provided by any of the above embodiments;

[0035] a controller, the controller being electrically connected to the memory and configured to control the memory to store data.

[0036] The beneficial effects of the embodiments of the present application are: to provide a semiconductor device, a memory and a storage system, the semiconductor device comprising a substrate, a stack layer and a virtual channel structure on the substrate, the stack layer comprising a stepped region, the virtual channel structure comprising a plurality of and penetrating the stack layer along a first direction perpendicular to the substrate. Wherein, each of the virtual channel structures comprises a center structure extending along the first direction and a plurality of outward protruding branch structures. In at least part of the virtual channel structures, the plurality of outward protruding branch structures are uniformly spaced around and connected to the center structure, and the plurality of outward protruding branch structures protrude outward relative to the center structure along a second direction perpendicular to the first direction and away from the center structure. Therefore, the plurality of outward protruding branch structures protrude outward relative to the center structure, and there is a certain spacing between the plurality of outward protruding branch structures, and such a shape makes the upper and lower shapes consistent during etching to form a virtual channel hole, that is, the shape retention is good, and the support performance is better. In addition, since the size of the virtual channel structure in the present application is large, the aspect ratio can be reduced, and therefore the etching difficulty of the channel hole can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0037] The technical solutions and other beneficial effects of the present application will become apparent from the following detailed description of the specific embodiments of the present application, combined with the accompanying drawings.

[0038] Figure 1 is a top view structural schematic diagram of a semiconductor device;

[0039] Figure 2 is a scanning electron microscope diagram of the top and bottom of a virtual channel column;

[0040] Figure 3 is a top view structural schematic diagram of a semiconductor device provided by the first embodiment of the present application;

[0041] Figure 4 is a sectional view structural schematic diagram of the semiconductor device provided by the first embodiment of the present application at A-A1;

[0042] Figure 5 is a scanning electron microscope diagram of a semiconductor device provided by the first embodiment of the present application;

[0043] Figure 6 is a top view structural schematic diagram of a semiconductor device provided by the second embodiment of the present application;

[0044] Figure 7 is a top view structural schematic diagram of a semiconductor device provided by the third embodiment of the present application;

[0045] Figure 8 is a structural schematic diagram of a memory provided by the fourth embodiment of the present application;

[0046] Figure 9 is a structural schematic diagram of a storage system provided by the fifth embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0048] It should be understood that although the terms first, second, etc. can be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present application.

[0049] It should be understood that when a component is referred to as being "on" or "connected to" another component, it can be directly on or connected to the other component, or intervening components can also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0050] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively close to a substrate and the top side is relatively far from the substrate. A layer can extend over an entire underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes that are between and at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, where it can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more electrically conductive layers and contact layers (where contacts, interconnect lines, and one or more dielectric layers are formed).

[0051] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate. Directions are represented herein in Cartesian coordinates, with "X" representing a direction parallel to the substrate; with "Z" representing a direction perpendicular to the substrate; with "Y" representing a direction parallel to the substrate and perpendicular to X; and "vertical" refers to a direction perpendicular to the substrate (Z).

[0052] It should be noted that the diagrams provided in the embodiments of the present application only schematically illustrate the basic concepts of the present application, and although only the components related to the present application are shown in the diagrams, the diagrams are not drawn according to the number, shape and size of the components in actual implementation, and the shape, number and ratio of each component in actual implementation can be arbitrarily changed, and the component layout pattern can also be more complex.

[0053] In the preparation process of 3D NAND, a stack layer formed by alternately stacking interlayer insulating layers and interlayer sacrificial layers is generally formed first, and then the interlayer sacrificial layers are removed to form gaps, and then the gate layers are filled in the gaps. The inventors found that, in this process, in order to avoid the collapse of the stack structure after the formation of the gap, it is usually necessary to form a virtual channel hole penetrating through the stack layer, and fill an insulating support material in the virtual channel hole to form a support column, so as to realize the support effect of the stack structure in the process of replacing the sacrificial layer with the gate layer.

[0054] Please refer to Figure 1 , Figure 1 is a schematic diagram of a top view of a semiconductor device. The semiconductor device 100 includes a substrate and a stack layer located on the substrate, the stack layer including alternately stacked insulating layers and gate layers, the stack layer including a staircase region. The semiconductor device 100 also includes virtual channel columns 101 and gate line gaps 102 penetrating through the stack layer along a first direction perpendicular to the substrate in the staircase region, and word line contacts 103 connecting the gate layers of each layer in the stack layer and the staircase region, the bottom. The top view of the virtual channel column 101 can be circular or square, and the top view of the word line contact 103 can be circular or square. The word line contacts 103 are located in the blank area between the virtual channel columns 101, and the virtual channel columns 101 and the word line contacts 103 are located between two adjacent gate line gaps 102.

[0055] However, as the number of stack layers continues to increase, the aspect ratio of the virtual channel hole continues to increase, and the etching difficulty of the virtual channel hole gradually increases. Through a large number of experiments and in-depth research by the inventors, it is found that the virtual channel hole has poor shape retention, and the shape retention of the virtual channel hole is related to the shape of the virtual channel hole.

[0056] Please refer to Figure 2 , Figure 2 is a scanning electron microscope image of the top and bottom of a virtual channel column. The left image is a scanning electron microscope image of the top of the virtual channel column, and the right image is a scanning electron microscope image of the bottom of the virtual channel column. From Figure 1 it can be seen that the top of the virtual channel column is circular, while the shape of the bottom has changed, and the size of the top is significantly larger than the size of the bottom. This poor shape retention makes the support effect of the virtual channel column near the bottom poor. Since the size of the bottom is smaller than the size of the top, it is necessary to Figure 1The increase of the top size on the basis of the structure to ensure that it can be etched to the bottom, which will squeeze the process window of the subsequent process, such as the process window of the word line contact. Similarly, for the square virtual channel column also has similar problems with the circular virtual channel column, such as poor shape retention, poor support performance.

[0057] Please refer to Figure 3 and Figure 4 , Figure 3 is a schematic diagram of the top structure of the semiconductor device provided by the first embodiment of the present application, Figure 4 is a schematic diagram of the cross-sectional structure of the semiconductor device provided by the first embodiment of the present application at A-A1. The semiconductor device 200 includes a substrate 20, a stack layer 21 located on the substrate 20, a plurality of virtual channel structures 22, and a plurality of word line contacts 23. Figure 4 The stack layer 21 includes insulating layers 211 and gate layers 212 stacked alternately, the bottommost gate layer 212 can be used as a bottom selection gate, the topmost gate layer 212 can be used as a top selection gate, and the intermediate gate layers 212 can be used as control gates. The stack layer 21 includes a storage area 201 and a step area 202 located on the periphery of the storage area 201, and the stack layer 21 has a stepped structure in the step area 202. The plurality of virtual channel structures 22 penetrate the stack layer 21 in the step area 202 along a first direction (Z) perpendicular to the substrate 20. The semiconductor device 200 further includes a dielectric layer 24 covering the stack layer 21 of the step area 202.

[0058] The plurality of word line contacts 23 extend along the first direction (Z) and are in contact with each layer of the gate layers 212 at the bottom, and the plurality of word line contacts 23 are located in the step area 202 Figure 4 , not shown in the figure). Among them, the plurality of virtual channel structures 22 are arranged around and spaced apart from the word line contacts 23, which can also be said that the word line contacts 23 are located in the blank area between the plurality of virtual channel structures 22, and the depth of the word line contacts 23 is different from that of the virtual channel structures 22. When the shape retention of the virtual channel structure 22 is poor, it is possible to etch to the position of the virtual channel structure 22 when forming the word line contact 23, so that the etching of the word line contact 23 is difficult to stop at a certain layer, which may cause the word line contact 23 to penetrate through two gate layers 212, which may cause the two gate layers 212 to be conductive through the word line contact 23. The plurality of virtual channel structures 22 are uniformly and evenly distributed, which can improve the support effect of the overall structure, and at the same time, the process window of the word line contact 23 is left between the virtual channel structures 22, so that the yield of the word line contact 23 can be increased, and the formed word line contact 23 is uniformly and evenly distributed.

[0059] In the embodiment, each of the virtual channel structures 22 comprises a central structure 221 extending along the first direction (Z) and a plurality of outward protruding branch structures 222 uniformly spaced around and connected to the central structure 221, the plurality of outward protruding branch structures 222 protruding outward relative to the central structure 221 along a second direction perpendicular to the first direction (Z) and away from the central structure 221. In at least some of the virtual channel structures 22, the plurality of outward protruding branch structures 222 are uniformly spaced around the central structure 221, that is, the spacing or angle between the plurality of outward protruding branch structures 222 are equal. In each of the virtual channel structures 22, the plurality of outward protruding branch structures 222 are uniformly spaced around the central structure 221. Each of the outward protruding branch structures 222 has an equal length protruding outward along the second direction.

[0060] The semiconductor device 200 further comprises a plurality of gate line slits 25 extending through the stack layer 21 along the first direction (Z), the plurality of gate line slits 25 extending along a third direction (X) which is parallel to the substrate 20. The virtual channel structures 22 and the word line contacts 23 are located between two adjacent gate line slits 25. The gate line slits 25 can also be virtual trenches located only in the stepped region 202, and the material of the gate line slits 25 can be silicon dioxide.

[0061] By contrast Figure 1 and Figure 3 , the cross-sectional area (XY section) of the virtual channel structure 22 can be greater than 3 times the cross-sectional area (XY section) of the virtual channel pillar 101, so the aspect ratio of the virtual channel structure 22 in the embodiment is less than Figure 1 the aspect ratio of the virtual channel pillar 101 in the embodiment, so the difficulty of etching the virtual channel hole can be reduced. Moreover, when etching to form the virtual channel hole, some waste will be produced, such as gas molecules containing C, F, S and O in the mask layer and molecules or molecular chains containing Si and O in the stack layer 21. The cross-sectional area of the virtual channel hole in the embodiment is increased, so it is easier to discharge these waste. In addition, Figure 1 The virtual channel pillar 101 and the gate line slit 102 can be etched simultaneously in the embodiment, and since the cross-sectional area of the virtual channel pillar 101 is small, the etching rate of the virtual channel pillar 101 is small, so the load stress generated by the gate line slit 102 is large. In the embodiment, the cross-sectional area of the virtual channel structure 22 is large, so the etching rate of the virtual channel structure 22 is increased, which can reduce the load stress generated by the gate line slit 25.

[0062] In the embodiment, the plurality of outward protruding branch structures 222 protrude outward relative to the central structure 221, and there is a certain spacing between the plurality of outward protruding branch structures 222. Such a shape makes the upper and lower shapes consistent during etching of the virtual channel hole, that is, the shape retention is good, and the support performance is better.

[0063] Further, each of the virtual channel structures 22 includes three outward protruding branch structures 222, and the virtual channel structure 22 is in a Y shape in a cross section (XY) perpendicular to the first direction (Z), and the included angle between two adjacent outward protruding branch structures 222 is equal to 120 degrees.

[0064] In a variant, the virtual channel structure 22 includes two outward protruding branch structures 222, and the virtual channel structure 22 is in a V shape in a cross section perpendicular to the longitudinal direction, and the included angle between two adjacent outward protruding branch structures 222 is equal to 120 degrees.

[0065] Please refer to Figure 5 , Figure 5 is a scanning electron microscope image of the semiconductor device provided by the first embodiment of the application. The left image is a scanning electron microscope image of the top of the semiconductor device 200, and the right image is a scanning electron microscope image of the bottom of the semiconductor device 200. From Figure 5 It can be seen that the size (cross-sectional area) of the virtual channel structure 22 at the top is slightly larger than the size (cross-sectional area) at the bottom, but the shape of the virtual channel structure 22 at the top and the bottom is still in a Y shape, and the shape does not change. Therefore, the shape retention of the virtual channel structure 22 in the embodiment is good, which means that the support effect at the bottom of the virtual channel structure 22 is improved, and the influence on the word line contact 23 during formation of the word line contact 23 can be reduced.

[0066] Unlike the prior art, because the shape retention of the Y-shaped virtual channel structure 22 is good, the size of the top of the virtual channel structure 22 is not much different from the size of the bottom, so it is not necessary to increase the size of the top to ensure that the virtual channel hole can be etched to the bottom. That is, the virtual channel structure 22 does not need to squeeze the space of the word line contact 23, which is equivalent to increasing the process window of the word line contact 23.

[0067] In the embodiment, the virtual channel structures 22 are arranged in multiple rows along the third direction (X), and there are three outer protruding branch structures 222 between any two adjacent virtual channel structures 22, which results in more blank areas between the two adjacent gate line slits 25, and thus the density of the virtual channel structures 22 is reduced, and the supporting effect is poor. For example, one outer protruding branch structure 222 in each virtual channel structure 22 in the second row of virtual channel structures 22 extends to the lower gate line slit 25, which results in a large number of blank areas between the second row of virtual channel structures 22 and the lower gate line slit 25.

[0068] Please refer to Figure 6 , Figure 6 is a schematic diagram of a top view of a semiconductor device provided by the second embodiment of the present application. The semiconductor device 300 includes multiple gate line slits 31 extending along the third direction (X), virtual channel structures and word line contacts 32 between any two adjacent gate line slits 31. In the embodiment, the virtual channel structures include multiple first virtual channel structures 33 having one center structure 331 and three outer protruding branch structures 332, and multiple second virtual channel structures 34 having one center structure 331 and two outer protruding branch structures 332, the first virtual channel structures 33 are Y-shaped in a cross section (XY) perpendicular to the first direction, and the second virtual channel structures 34 are V-shaped in the cross section (XY) perpendicular to the first direction. The included angle between any two adjacent outer protruding branch structures 332 in the first virtual channel structure 33 is equal to 120 degrees, and the included angle between the two outer protruding branch structures 332 in the second virtual channel structure 34 is equal to 120 degrees. Specifically, the outer protruding branch structure 332 is a rectangle in the cross section (XY) perpendicular to the first direction, and the center structure 331 is a triangle in the cross section (XY) perpendicular to the first direction, one side of the rectangle is connected to the triangle, which means that the first virtual channel structure 33 is composed of three rectangles and one triangle in the cross section (XY) direction, and the second virtual channel structure 34 is composed of two rectangles and one triangle in the cross section (XY) direction. More specifically, the width of the rectangle is connected to the triangle, for example, the length of the rectangle is 225 nm, and the width of the rectangle is 150 nm.

[0069] In a variant, the XY cross section of the center structure 331 can also be a circle, and the XY cross section of the outer protruding branch structure 332 can also be a semicircle or a semi-ellipse.

[0070] In the embodiment, the plurality of first dummy channel structures 33 are arranged in a row along the third direction (X), the plurality of second dummy channel structures 34 are arranged in a row along the third direction (X), and the plurality of first dummy channel structures 33 and the plurality of second dummy channel structures 34 are staggered along the third direction (X). Taking the middle two adjacent gate line slits 31 as an example, the adjacent two gate line slits 31 include a first gate line slit 311 and a second gate line slit 312, the first gate line slit 311 is adjacent to the plurality of first dummy channel structures 33, and the second gate line slit 312 is adjacent to the plurality of second dummy channel structures 34. It should be noted that in the above two adjacent gate line slits 31, the first gate line slit 311 is the second gate line slit, and in the below two gate line slits 31, the second gate line slit 312 is the first gate line slit. The Y-shaped opening of the first dummy channel structure 33 is directly opposite the first gate line slit 311, and the V-shaped opening of the second dummy channel structure 34 is directly opposite the first gate line slit 311. Since the second dummy channel structure 34 is V-shaped and the opening is directly opposite the first gate line slit 311, the Y-shaped opening of the first dummy channel structure 33 is also directly opposite the first gate line slit 311, so that the blank area between the first gate line slit 311 and the second gate line slit 312 is small, thereby increasing the density of the dummy channel structure and improving the support performance of the dummy channel structure.

[0071] Please refer to Figure 7 , Figure 7 is a schematic diagram of the top view structure of a semiconductor device provided by the third embodiment of the present application. For brief description, the same reference numerals are used for the same structures in the third embodiment as in the second embodiment. Figure 7 Only two adjacent gate line slits are shown, and the semiconductor device 400 is different from the semiconductor device 300 in the second embodiment in that when the space between the first gate line slit 311 and the second gate line slit 312 is larger, the plurality of first dummy channel structures 33 are arranged in multiple rows along the third direction (X), and the plurality of second dummy channel structures 34 are arranged in a row along the third direction (X). The first gate line slit 311 is adjacent to a row of first dummy channel structures 33, and the second gate line slit 312 is adjacent to the plurality of second dummy channel structures 34. The density of the dummy channel structure in the semiconductor device 400 provided by the embodiment is also improved compared with the density of the dummy channel structure 22 in the first embodiment, and thus the support effect is better.

[0072] The semiconductor device provided by the embodiment of the present application is characterized in that the virtual channel structure adopts a center structure and a plurality of outward protruding branch structures surrounding the center structure, each outward protruding branch structure protrudes outward along a second direction perpendicular to the first direction and away from the center structure, and the plurality of outward protruding branch structures are arranged at intervals. Such a shape makes the virtual channel structure have good shape retention, thus having good supporting performance, and can reduce the aspect ratio of the virtual channel structure, thereby reducing the etching difficulty of the virtual channel hole. In addition, in the preparation process of the 3D NAND, when the interlayer sacrificial layer in the stacked layer is replaced by the gate layer, the virtual channel structure with good shape retention can serve as a support column after the interlayer sacrificial layer is removed to prevent the stacked layer from collapsing. The virtual channel structure can also play a supporting role during the entire preparation process, and because of the good shape retention, it will not affect other structures.

[0073] Please refer to Figure 8 , Figure 8 is a structural schematic diagram of a memory provided by the fourth embodiment of the present application. The memory 500 can be a three-dimensional memory, such as a 3D NAND, 3D NOR memory.

[0074] The memory 500 includes a semiconductor device 501 and a peripheral circuit 502. The semiconductor device 501 can be any of the semiconductor devices in the above embodiments, and the peripheral circuit 502 can be a COMS (Complementary Metal Oxide Semiconductor). The peripheral circuit 502 is electrically connected to the semiconductor device 501 to transmit signals with the semiconductor device 501. The peripheral circuit 502 can be used for logic operation and control and detection of the switching state of each memory cell in the above semiconductor device 501 through metal wiring to realize data storage and reading.

[0075] The semiconductor device 501 includes a substrate, a stacked layer on the substrate, and a virtual channel structure. The stacked layer includes a stepped region, and the virtual channel structure penetrates the stepped region along a first direction perpendicular to the substrate.

[0076] The virtual channel structure includes a center structure and a plurality of outward protruding branch structures extending along the first direction. In at least part of the virtual channel structure, the plurality of outward protruding branch structures are uniformly spaced around and connected to the center structure, and the plurality of outward protruding branch structures protrude outward relative to the center structure along a second direction perpendicular to the first direction and away from the center structure.

[0077] Please refer to Figure 9 , Figure 9is a structural schematic diagram of a storage system provided by a fifth embodiment of the present application. The storage system 600 comprises a memory 601 and a controller 602, the memory 601 can be the memory in any of the above embodiments, the memory 601 can comprise any of the semiconductor devices in the above embodiments, the controller 602 is electrically connected with the memory 601, for controlling the memory 601 to store data, and the memory 601 can perform the operation of storing data based on the control of the controller 602.

[0078] In some embodiments, the storage system can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of RS-MMC and micro- MMC, a secure digital card in the form of SD, mini-SD and micro-SD, a storage device in the form of a personal computer memory card international association (PCMCIA) card type, a storage device in the form of a peripheral component interconnect (PCI) type, a storage device in the form of a high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0079] The semiconductor device in the memory 601 comprises a substrate, a stack layer located on the substrate, the stack layer comprising a stepped region, and a virtual channel structure penetrating through the stepped region along a first direction, the first direction being a direction perpendicular to the substrate.

[0080] The virtual channel structure comprises a center structure and a plurality of outward protruding branch structures extending along the first direction, the plurality of outward protruding branch structures are uniformly spaced around and connected with the center structure in at least part of the virtual channel structure, and the plurality of outward protruding branch structures protrude outward relative to the center structure along a second direction, the second direction being a direction perpendicular to the first direction and away from the center structure.

[0081] The above descriptions of the embodiments are only used to help understand the technical solutions and the core ideas of the present application; those skilled in the art should understand that they can still modify the technical solutions recorded in the above embodiments, or make equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized by, Comprise: a substrate; a stack layer on the substrate, the stack layer comprising a staircase region; and a dummy channel structure penetrating the staircase region along a first direction, the first direction being a direction perpendicular to the substrate; wherein the dummy channel structure comprises a center structure extending along the first direction and a plurality of outward protruding branch structures, the dummy channel structure comprising a plurality of; in at least part of the dummy channel structure, the plurality of outward protruding branch structures are uniformly spaced around and connected to the center structure, the plurality of outward protruding branch structures protruding outward relative to the center structure along a second direction, the second direction being a direction perpendicular to the first direction and away from the center structure; part of the dummy channel structure comprises only 3 outward protruding branch structures, the dummy channel structure being Y-shaped in a cross section perpendicular to the first direction.

2. The semiconductor device according to claim 1, wherein in each of the dummy channel structure, the plurality of outward protruding branch structures are uniformly spaced around the center structure.

3. The semiconductor device of claim 1, wherein a length of each of the outward protruding branch structures protruding outward along the second direction is equal.

4. The semiconductor device of claim 2, wherein an included angle between two adjacent outward protruding branch structures is equal to 120 degrees.

5. The semiconductor device of claim 4, wherein, the outward protruding branch structure is rectangular in a cross section perpendicular to the first direction, the center structure is triangular in a cross section perpendicular to the first direction, one side of the rectangle being connected to one side of the triangle.

6. The semiconductor device of claim 1, wherein part of the dummy channel structure comprises 2 outward protruding branch structures, the dummy channel structure being V-shaped in a cross section perpendicular to the first direction, an included angle between two adjacent outward protruding branch structures being equal to 120 degrees.

7. The semiconductor device of claim 1, wherein the dummy channel structure comprises a plurality of first dummy channel structures with 3 outward protruding branch structures and a plurality of second dummy channel structures with 2 outward protruding branch structures, the first dummy channel structure being Y-shaped in a cross section perpendicular to the first direction, the second dummy channel structure being V-shaped in a cross section perpendicular to the first direction.

8. The semiconductor device of claim 7, wherein, an included angle between two adjacent outward protruding branch structures in each of the first dummy channel structure is equal to 120 degrees, an included angle between two adjacent outward protruding branch structures in each of the second dummy channel structure is equal to 120 degrees.

9. The semiconductor device of claim 7, wherein, the semiconductor device further comprises: a plurality of gate line slits penetrating the stack layer along the first direction, the plurality of gate line slits extending along a third direction, the third direction being a direction parallel to the substrate; wherein the dummy channel structure is located between two adjacent gate line slits.

10. The semiconductor device of claim 9, wherein, the plurality of first dummy channel structures are arranged into one or more rows along the third direction, the plurality of second dummy channel structures are arranged into one row along the third direction; two adjacent gate line slits comprise a first gate line slit and a second gate line slit, the second gate line slit being adjacent to the plurality of second dummy channel structures.

11. The semiconductor device of claim 10, wherein, the plurality of first dummy channel structures and the plurality of second dummy channel structures are staggered along the third direction.

12. The semiconductor device of claim 10, wherein, an opening of the Y-shape of the first dummy channel structure is directly opposite to the first gate line slit; an opening of the V-shape of the second dummy channel structure is directly opposite to the first gate line slit.

13. The semiconductor device of claim 1, wherein The plurality of dummy channel structures are uniformly distributed.

14. The semiconductor device of claim 13, wherein, The stack layer comprises insulating layers and gate layers which are alternately stacked, and the semiconductor device further comprises: A plurality of word line contacts extending along the first direction and contacting the gate layers of each layer, the plurality of word line contacts being located in the staircase region; The plurality of dummy channel structures are arranged around and spaced apart from the word line contacts.

15. The semiconductor device of claim 1, wherein, The stack layer further comprises a storage region, the staircase region being located at the periphery of the storage region, and the stack layer has a stepped structure in the staircase region.

16. A memory, comprising: Comprise: The semiconductor device of any one of claims 1-15; A peripheral circuit electrically connected to the semiconductor device.

17. A storage system, characterized by Comprise: The memory of claim 16; A controller electrically connected to the memory and configured to control the memory to store data.

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