A power management circuit

Abstract

The present application discloses a power management circuit, including an input MOS tube, a reverse blocking MOS tube, an anti-reverse connection MOS tube, a first resistor, a second resistor, and a third resistor; the drain of the input MOS tube is used to connect to the input power supply; the source of the reverse blocking MOS tube is connected in series to the source of the input MOS tube, and the drain is the output end of the power management circuit for outputting a power supply signal; the drain of the anti-reverse connection MOS tube is interconnected with the gate of the input MOS tube and the gate of the reverse blocking MOS tube, and is used to receive a first control signal through a third resistor; the source of the anti-reverse connection MOS tube is interconnected with the source of the input MOS tube and the source of the reverse blocking MOS tube; the gate of the anti-reverse connection MOS tube is grounded through a first resistor, and is connected to the source of the anti-reverse connection MOS tube through a second resistor. The present application can automatically cut off the power transmission path in time, realize the anti-reverse connection protection of the external input power supply, and improve the safety and stability of the product.

Description

Technical Field

[0001] The present application relates to the technical field of power supply protection, and in particular to a power supply management circuit. Background Art

[0002] Notebook computers, also known as portable computers, have become a common device in people's daily life and office due to their compact size and portability.

[0003] In addition to using an external power supply based on an adapter to power its motherboard, a laptop can also store the power of the external power supply in its lithium battery module so that the motherboard can be powered based on battery energy storage when there is no external power supply. Currently, the commonly used power management solutions for laptops generally take into account the problem of preventing battery voltage backflow, but do not provide a reverse connection protection function for external power supplies. In this way, once the front-end power supply is reversed, it will cause irreversible damage to the front-end chip and battery.

[0004] In view of this, providing a solution to the above-mentioned technical problems has become an urgent concern for those skilled in the art. Summary of the invention

[0005] The purpose of the present application is to provide a power management circuit to effectively protect an external power supply from reverse connection and prevent related power devices from being damaged by negative pressure.

[0006] In order to solve the above technical problems, on the one hand, the present application discloses a power management circuit, including an input MOS tube, a reverse blocking MOS tube, an anti-reverse connection MOS tube, a first resistor, a second resistor, and a third resistor;

[0007] The drain of the input MOS tube is used to be connected to the input power supply; the source of the reverse blocking MOS tube is connected in series to the source of the input MOS tube, and the drain is the output end of the power management circuit for outputting a power supply signal;

[0008] The drain of the anti-reverse connection MOS tube is connected to the gate of the input MOS tube and the gate of the reverse blocking MOS tube, and is used to receive a first control signal through the third resistor; the source of the anti-reverse connection MOS tube is connected to the source of the input MOS tube and the source of the reverse blocking MOS tube; the gate of the anti-reverse connection MOS tube is grounded through the first resistor, and is connected to the source of the anti-reverse connection MOS tube through the second resistor.

[0009] Optionally, a fourth resistor is further included; the source and source connection points of the anti-reverse connection MOS tube, the input MOS tube, and the reverse blocking MOS tube receive the second control signal through the fourth resistor.

[0010] Optionally, a fifth resistor is also included; one end of the fifth resistor is connected to the gate of the input MOS tube, and the other end is connected to the gate of the reverse blocking MOS tube, the drain of the anti-reverse connection MOS tube and the common point of the third resistor.

[0011] Optionally, it also includes a first capacitor; one end of the first capacitor is connected to the drain of the input MOS tube, and the other end is connected to the gate of the reverse blocking MOS tube, the drain of the anti-reverse connection MOS tube and the common point of the third resistor.

[0012] Optionally, a second capacitor is also included; one end of the second capacitor is connected to the parallel connection point of the source of the anti-reverse connection MOS tube, the input MOS tube and the reverse blocking MOS tube, and the other end is connected to the gate of the reverse blocking MOS tube, the drain of the anti-reverse connection MOS tube and the common connection point of the third resistor.

[0013] Optionally, the first control signal and the second control signal are both output signals of a battery management chip in a subsequent circuit.

[0014] Optionally, the anti-reverse connection MOS tube, the input MOS tube and the reverse blocking MOS tube are all NMOS tubes.

[0015] Optionally, the conduction threshold voltage of the anti-reverse connection MOS tube is lower than the conduction threshold voltage of the distributor input MOS tube and the reverse blocking MOS tube.

[0016] The power management circuit provided in the present application includes an input MOS tube, a reverse blocking MOS tube, an anti-reverse connection MOS tube, a first resistor, a second resistor, and a third resistor; the drain of the input MOS tube is used to be connected to an input power supply; the source of the reverse blocking MOS tube is connected in series to the source of the input MOS tube, and the drain is the output end of the power management circuit for outputting a power supply signal; the drain of the anti-reverse connection MOS tube is interconnected with the gate of the input MOS tube and the gate of the reverse blocking MOS tube, and is used to receive a first control signal through the third resistor; the source of the anti-reverse connection MOS tube is interconnected with the source of the input MOS tube and the source of the reverse blocking MOS tube; the gate of the anti-reverse connection MOS tube is grounded through the first resistor, and is connected to the source of the anti-reverse connection MOS tube through the second resistor.

[0017] The beneficial effects of the power management circuit provided in the present application are as follows: based on the setting of the relevant switch tube, the present application can effectively shut down the power transmission path when the input power is reversed, protect the subsequent circuit and battery from damage by negative pressure, effectively realize the anti-reverse connection protection of the external input power, and improve the safety and stability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings required for use in the description of the prior art and the embodiments of the present application are briefly introduced below. Of course, the drawings described below in relation to the embodiments of the present application are only part of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without creative work, and the obtained other drawings also belong to the protection scope of the present application.

[0019] Figure 1 A circuit structure diagram of a power management circuit disclosed in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the structure of a power management circuit disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The core of the present application is to provide a power management circuit to effectively protect an external power supply from reverse connection and prevent related power devices from being damaged by negative pressure.

[0022] In order to describe the technical solutions in the embodiments of the present application more clearly and completely, the technical solutions in the embodiments of the present application will be introduced below in conjunction with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0023] At present, laptop computers have become a common device for people's daily life and office due to their small size and portability. In addition to using an external power supply based on an adapter to power its mainboard, laptop computers can also store the electrical energy of the external power supply in their lithium battery modules, so that the mainboard can be powered based on battery energy storage when there is no external power supply. The power management solutions commonly used in laptops currently generally take into account the problem of preventing battery voltage backflow, but do not provide a reverse connection protection function for external power supplies. In this way, once the front-end power supply is reversed, it will cause irreversible damage to the front-stage chip and battery. In view of this, the present application provides a power management circuit that can effectively solve the above problems.

[0024] See also Figure 1 As shown, the embodiment of the present application discloses a power management circuit, including an input MOS tube Q1, a reverse blocking MOS tube Q2, an anti-reverse connection MOS tube Q3, a first resistor R1, a second resistor R2, and a third resistor R3;

[0025] The drain of the input MOS tube Q1 is used to connect to the input power supply; the source of the reverse blocking MOS tube Q2 is connected in series to the source of the input MOS tube Q1, and the drain is the output end of the power management circuit for outputting the power supply signal;

[0026] The drain of the anti-reverse connection MOS tube Q3 is connected to the gate of the input MOS tube Q1 and the gate of the reverse blocking MOS tube Q2, and is used to receive the first control signal through the third resistor R3; the source of the anti-reverse connection MOS tube Q3 is connected to the source of the input MOS tube Q1 and the source of the reverse blocking MOS tube Q2; the gate of the anti-reverse connection MOS tube Q3 is grounded through the first resistor R1, and is connected to the source of the anti-reverse connection MOS tube Q3 through the second resistor R2.

[0027] Specifically, the external power supply of a laptop computer is generally direct current converted from AC power through an adapter. Therefore, the input MOS tube Q1 connected to the adapter in the power management circuit is generally called an adapter input MOS tube, that is, AdapterInput MOSFET.

[0028] Among them, MOS tube is MOSFET (Metal Oxide Semiconductor Field Effect Transistor). MOS tube has three terminals: gate, drain and source. The gate is the control terminal. By controlling the gate-source voltage difference, the conduction state between the drain and source of the MOS tube can be changed.

[0029] In the present application, the input MOS tube Q1 is connected in series with the reverse blocking MOS tube (Reverse Blocking MOSFET) Q2, and the drain of the input MOS tube Q1 serves as the input end DCIN of the power management circuit, which is used to be connected to the output end of the computer adapter to access the power supply; the drain of the reverse blocking MOS tube Q2 serves as the output end VOUT of the power management circuit, which is used to output the power supply signal to the subsequent circuit, the motherboard of the laptop computer, and also includes the battery of the laptop computer.

[0030] When the DCIN terminal is connected to an external power supply, the gate voltage of the input MOS tube Q1 is controlled by the corresponding first control signal, so that the gate-source voltage difference of the input MOS tube Q1 reaches its conduction threshold voltage, and the input MOS tube Q1 will be turned on; similarly, the reverse blocking MOS tube Q2 will also be turned on, and the VOUT terminal of the power management circuit will supply power to the subsequent circuit.

[0031] In order to prevent the negative pressure generated when the external power supply is reversely connected from damaging the circuit, the present application also provides an anti-reverse connection MOS tube Q3. Figure 2 , Figure 2 This is a schematic diagram of the structure of the power management circuit disclosed in the embodiment of the present application.

[0032] Specifically, the function of the reverse connection protection MOS tube Q3 is as follows: when the external power supply is positively connected, the reverse connection protection MOS tube Q3 is not turned on; when the external power supply is reversely connected, the reverse connection protection MOS tube Q3 is turned on, and the gate-source voltage difference between the input MOS tube Q1 and the reverse blocking MOS tube Q2 is changed, so that the gate-source power difference of the two MOS tubes cannot meet the conduction threshold voltage, thereby turning off the input MOS tube Q1 and the reverse blocking MOS tube Q2 to prevent negative pressure from damaging the subsequent circuit and the battery.

[0033] In order to achieve the above effect, the source of the anti-reverse MOS tube Q3 is connected in parallel with the source of the input MOS tube Q1 and the source of the reverse blocking MOS tube Q2. At the same time, the drain of the anti-reverse MOS tube Q3 is connected in parallel with the gate of the input MOS tube Q1 and the gate of the reverse blocking MOS tube Q2. In this way, once the anti-reverse MOS tube Q3 is turned on, the gate and source of the input MOS tube Q1 will be turned on, and the gate-source voltage difference will be close to zero, so that the input MOS tube Q1 will be turned off. The reverse blocking MOS tube Q2 is similar.

[0034] In addition, the first resistor R1 and the second resistor R2 form a resistor voltage-dividing structure, one end of the resistor voltage-dividing structure is grounded, and the other end is connected to the parallel connection point of the source of the anti-reverse MOS tube Q3, the input MOS tube Q1 and the reverse blocking MOS tube Q2; and the common end of the two resistors, that is, the voltage-dividing point, is connected to the gate of the anti-reverse MOS tube Q3. In this way, when the external power supply is positively connected and the circuit normally outputs a high level, the parallel connection point of the source of the anti-reverse MOS tube Q3, the input MOS tube Q1 and the reverse blocking MOS tube Q2 is also a high level, and the gate-source voltage difference of the anti-reverse MOS tube Q3 cannot meet its conduction threshold voltage, so the anti-reverse MOS tube Q3 is turned off.

[0035] When the external power supply is reversely connected, the source parallel connection point of the anti-reverse connection MOS tube Q3, the input MOS tube Q1 and the reverse blocking MOS tube Q2 is at a low level, and the gate-source voltage difference of the anti-reverse connection MOS tube Q3 meets its conduction threshold voltage. At this time, the anti-reverse connection MOS tube Q3 is turned on, and then the input MOS tube Q1 and the reverse blocking MOS tube Q2 are turned off due to the gate-source short circuit, thereby playing the role of anti-reverse connection protection.

[0036] It can be seen that the power management circuit provided in the present application, based on the setting of the relevant switch tube, can effectively shut down the power transmission path when the input power is reversed, protect the subsequent circuit and battery from damage by negative pressure, effectively realize the anti-reverse connection protection of the external input power, and improve the safety and stability of the product.

[0037] As a specific embodiment, the power management circuit provided in the embodiment of the present application further includes a fourth resistor R4 based on the above content; the source parallel connection point of the anti-reverse MOS tube Q3, the input MOS tube Q1, and the reverse blocking MOS tube Q2 receives the second control signal through the fourth resistor R4.

[0038] Specifically, since the MOS tube can be turned on only after the gate-source power difference reaches the turn-on threshold voltage, in order to accurately control the gate-source voltage difference of the input MOS tube Q1 and the reverse blocking MOS tube Q2, in addition to controlling the gate voltages of the two MOS tubes based on the first control signal, this embodiment also controls the source voltages of the two MOS tubes based on the second control signal.

[0039] As a specific embodiment, the power management circuit provided in the embodiment of the present application further includes a fifth resistor R5 based on the above content; one end of the fifth resistor R5 is connected to the gate of the input MOS tube Q1, and the other end is connected to the gate of the reverse blocking MOS tube Q2, the drain of the anti-reverse connection MOS tube Q3 and the common point of the third resistor R3.

[0040] As a specific embodiment, the power management circuit provided in the embodiment of the present application further includes a first capacitor C1 based on the above content; one end of the first capacitor C1 is connected to the drain of the input MOS tube Q1, and the other end is connected to the gate of the reverse blocking MOS tube Q2, the drain of the anti-reverse connection MOS tube Q3 and the common point of the third resistor R3.

[0041] Specifically, in order to further stabilize the drain voltage of the input MOS tube Q1 , a first capacitor C1 is further provided in this embodiment.

[0042] As a specific embodiment, the power management circuit provided in the embodiment of the present application further includes a second capacitor C2 on the basis of the above content; one end of the second capacitor C2 is connected to the parallel connection point of the source of the anti-reverse connection MOS tube Q3, the input MOS tube Q1 and the reverse blocking MOS tube Q2, and the other end is connected to the gate of the reverse blocking MOS tube Q2, the drain of the anti-reverse connection MOS tube Q3 and the common connection point of the third resistor R3.

[0043] Specifically, in order to further stabilize the source voltage of the input MOS transistor Q1 and the reverse blocking MOS transistor Q2, a second capacitor C2 is further provided in this embodiment.

[0044] As a specific embodiment, the power management circuit provided in the embodiment of the present application is based on the above content, and the first control signal and the second control signal are both output signals of a battery management chip in a subsequent circuit.

[0045] Specifically, the battery management chip is an integrated chip used to manage the charging and discharging of the battery, and the first control signal and the second control signal can both be provided by the battery management chip.

[0046] As a specific embodiment, the power management circuit provided in the embodiment of the present application is based on the above content, and the anti-reverse connection MOS tube Q3, the input MOS tube Q1 and the reverse blocking MOS tube Q2 are all NMOS tubes.

[0047] Specifically, Figure 1 As shown, the anti-reverse connection MOS tube Q3, input MOS tube Q1 and reverse blocking MOS tube Q2 in the present application are all NMOS tubes. For NMOS tubes, they will be turned on only when the gate-source voltage difference is greater than a certain positive value, and this positive value is the turn-on threshold voltage.

[0048] As a specific embodiment, the power management circuit provided in the embodiment of the present application is based on the above content, and the turn-on threshold voltage of the anti-reverse connection MOS tube Q3 is lower than the turn-on threshold voltage of the distributor input MOS tube Q1 and the reverse blocking MOS tube Q2.

[0049] Specifically, in order to enable the anti-reverse connection MOS tube Q3 to be turned on quickly when the external power supply is reversely connected to avoid untimely shutdown, this embodiment can specifically select a MOS tube with a lower turn-on threshold voltage as the anti-reverse connection MOS tube Q3.

[0050] In this application, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0051] It should also be noted that, in this application document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. In addition, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0052] The technical solution provided by the present application is described in detail above. The principle and implementation method of the present application are described in detail using specific examples herein, and the description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A power management circuit, characterized in that: It includes an input MOS tube, a reverse blocking MOS tube, an anti-reverse connection MOS tube, a first resistor, a second resistor, and a third resistor; The drain of the input MOS tube is used to be connected to the input power supply; the source of the reverse blocking MOS tube is connected in series to the source of the input MOS tube, and the drain is the output end of the power management circuit for outputting a power supply signal; The drain of the anti-reverse connection MOS tube is connected to the gate of the input MOS tube and the gate of the reverse blocking MOS tube, and is used to receive a first control signal through the third resistor; the source of the anti-reverse connection MOS tube is connected to the source of the input MOS tube and the source of the reverse blocking MOS tube; the gate of the anti-reverse connection MOS tube is grounded through the first resistor, and is connected to the source of the anti-reverse connection MOS tube through the second resistor.

2. The circuit according to claim 1, characterized in that It also includes a fourth resistor; the source and contact point of the anti-reverse connection MOS tube, the input MOS tube, and the reverse blocking MOS tube receive the second control signal through the fourth resistor.

3. The circuit according to claim 2, characterized in that It also includes a fifth resistor; one end of the fifth resistor is connected to the gate of the input MOS tube, and the other end is connected to the gate of the reverse blocking MOS tube, the drain of the anti-reverse connection MOS tube and the common point of the third resistor.

4. The circuit according to claim 3, characterized in that It also includes a first capacitor; one end of the first capacitor is connected to the drain of the input MOS tube, and the other end is connected to the gate of the reverse blocking MOS tube, the drain of the anti-reverse connection MOS tube and the common point of the third resistor.

5. The circuit according to claim 4, characterized in that It also includes a second capacitor; one end of the second capacitor is connected to the parallel connection point of the source of the anti-reverse connection MOS tube, the input MOS tube and the reverse blocking MOS tube, and the other end is connected to the gate of the reverse blocking MOS tube, the drain of the anti-reverse connection MOS tube and the common connection point of the third resistor.

6. The circuit according to claim 5, characterized in that The first control signal and the second control signal are both output signals of a battery management chip in a subsequent circuit.

7. The circuit according to any one of claims 1 to 6, characterized in that: The anti-reverse connection MOS tube, the input MOS tube and the reverse blocking MOS tube are all NMOS tubes.

8. The circuit according to claim 7, characterized in that The conduction threshold voltage of the anti-reverse connection MOS tube is lower than the conduction threshold voltages of the input MOS tube and the reverse blocking MOS tube.

Images