IGBT electro-thermal stress equalization device

Abstract

The application discloses an IGBT electric-thermal stress balancing device, which comprises a primary side control circuit, an isolation transformer, a secondary side digital drive circuit and a detection circuit. The primary side control circuit is used for generating a control signal according to a pulse width modulation signal issued by an upper computer and fault information of the IGBT, and transmitting the control signal to the secondary side digital drive circuit through the isolation transformer. The secondary side digital drive circuit is used for driving the IGBT according to the control signal, receiving the fault information of the IGBT, and transmitting the fault information to the primary side control circuit through the isolation transformer. The detection circuit is used for collecting the fault information of the IGBT and transmitting the fault information to the secondary side digital drive circuit. The device has faster response, better adaptability and higher stability, and can realize reliable operation of the IGBT in a whole life cycle and flexible margin configuration.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronic devices, in particular to an IGBT electric and thermal stress balancing device. BACKGROUND

[0002] Adopting medium-voltage IGBTs in series to replace high-voltage IGBTs can effectively reduce device switching loss, reduce cost, shorten delivery period, and play an important role in important fields such as metallurgical rolling, rail transit, and new energy utilization. At present, most researches focus on solving the voltage balance of each device when the IGBTs are in series. According to the stage of voltage imbalance, the voltage imbalance when the series devices are off is called static voltage imbalance, and the voltage imbalance when the device switching transient occurs is called dynamic voltage imbalance. Generally, the former is caused by the difference in leakage current when the device is off. Dynamic voltage imbalance is mainly caused by inconsistent driving circuits or IGBT parameter dispersion, and devices that turn on slowly and turn off quickly will bear higher electric stress. In addition to voltage balance, thermal stress balance of series IGBTs also deeply affects the safe operation and reliable operation of the system. Severe thermal stress imbalance can cause device over-temperature failure and open-circuit failure. At the next turn-on instant, the device with open-circuit failure will appear serious overvoltage, causing secondary damage to the device and packaging insulation, and even further damaging the driving circuit. Even if the thermal stress imbalance does not cause device over-temperature, long-term imbalance operation will lead to different aging degrees of devices and serious parameter dispersion, further increasing voltage and loss imbalance, and also seriously affecting the reliability of the system.

[0003] For voltage balance and thermal stress balance, the existing technical solutions have technical defects such as inability to avoid tail phase voltage imbalance again, overvoltage failure risk still exists, poor stability, slow response, etc. Therefore, it has become a technical problem to be solved by those skilled in the art to provide an electric and thermal stress balancing scheme with fast response, good adaptability, and high stability. SUMMARY

[0004] The purpose of the present application is to provide an IGBT electric and thermal stress balancing device with faster response, better adaptability, and higher stability, which can realize reliable operation of IGBTs throughout their life cycle and flexible margin configuration.

[0005] To solve the above technical problems, the present application provides an IGBT electric and thermal stress balancing device, which comprises:

[0006] The primary side control circuit, the isolation transformer, the secondary side digital driving circuit, and the detection circuit;

[0007] The primary side control circuit is configured to generate a control signal according to the received pulse width modulation signal and the fault information of the IGBT, and transmit the control signal to the secondary side digital drive circuit through the isolation transformer.

[0008] The secondary side digital drive circuit is configured to drive the IGBT according to the control signal, receive the fault information of the IGBT, and transmit the fault information to the primary side control circuit through the isolation transformer.

[0009] The detection circuit is configured to collect the fault information of the IGBT and transmit the fault information to the secondary side digital drive circuit.

[0010] Optionally, the primary side control circuit is one-way, the isolation transformer, the secondary side digital drive circuit and the detection circuit are n-way, n is the number of the IGBTs in the series components, and the isolation transformer, the secondary side digital drive circuit and the detection circuit correspond to the IGBTs one by one.

[0011] Optionally, the primary side control circuit comprises:

[0012] a primary side digital chip, a first modulation circuit and a first demodulation circuit.

[0013] The primary side digital chip is configured to generate a trigger pulse width modulation signal according to the pulse width modulation signal and a fault pulse width modulation signal.

[0014] The first modulation circuit is configured to convert the trigger pulse width signal into a trigger edge modulation signal, and output the trigger edge modulation signal to the secondary side digital drive circuit through the isolation transformer.

[0015] The first demodulation circuit is configured to receive a fault edge modulation signal output by the secondary side digital drive circuit through the isolation transformer, and convert the fault edge modulation into the fault pulse width modulation signal.

[0016] Optionally, the secondary side digital drive circuit is specifically configured to classify the fault information, transmit first type fault information to the primary side control circuit through the isolation transformer, and drive the IGBT according to second type fault information and the control signal.

[0017] Optionally, the secondary side digital drive circuit comprises:

[0018] a second modulation circuit, a second demodulation circuit, a secondary side digital chip and a hierarchical drive circuit.

[0019] The second demodulation circuit is configured to convert the edge modulation signal output by the primary side control circuit through the isolation transformer into the trigger pulse width signal.

[0020] The secondary side digital chip is configured to output a driving signal to the hierarchical driving circuit according to the trigger pulse width information, and generate the fault pulse width modulation signal.

[0021] The second modulation circuit is configured to convert the fault pulse width modulation signal into the fault edge modulation signal, and transmit the fault edge modulation signal to the primary side control circuit through the isolation transformer.

[0022] The hierarchical driving circuit is configured to perform hierarchical soft turn-off or closed-loop triggering on the IGBT according to the driving signal.

[0023] Optionally, the hierarchical driving circuit comprises:

[0024] a first driving switch, a second driving switch, a third driving switch, a first resistor, a second resistor, and a third resistor.

[0025] The drain of the first driving switch is connected to a high level, the source of the first driving switch is connected to a first end of the first resistor, and the gate of the first driving switch is connected to the secondary side digital chip; the source of the second driving switch is connected to a low level, the drain of the second driving switch is connected to a first end of the second resistor, and the gate of the second driving switch is connected to the secondary side digital chip; the source of the third driving switch is connected to a first end of the third resistor, the drain of the third driving switch is connected to a zero level, and the gate of the third driving switch is connected to the secondary side digital chip; a second end of the first resistor, a second end of the second resistor, and a second end of the third resistor are connected together and connected to the gate of the IGBT as an output end of the hierarchical driving circuit.

[0026] Optionally, the detection circuit comprises:

[0027] a voltage detection circuit, an overcurrent detection circuit, a junction temperature detection circuit, and a clamping detection circuit.

[0028] The voltage detection circuit is configured to detect a voltage state of the IGBT.

[0029] The overcurrent detection circuit is configured to detect a current state of the IGBT.

[0030] The junction temperature detection circuit is configured to detect a junction temperature state of the IGBT.

[0031] The clamping detection circuit is configured to detect a clamping state of the IGBT.

[0032] Optionally, the clamping detection circuit comprises:

[0033] a first clamping diode, a second clamping diode, a third clamping diode, a bidirectional clamping diode, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a second capacitor, and a comparison circuit;

[0034] an anode of the first clamping diode is connected with a cathode of the second clamping diode in series through the first capacitor and the second capacitor, a cathode of the first clamping diode is connected with a collector of the IGBT, an anode of the second clamping diode is connected with an emitter of the IGBT; the fourth resistor and the fifth resistor are connected in series, and the fourth resistor and the fifth resistor are connected between the first end and the second end of the detection circuit; one end of the sixth resistor is connected with one end of the fourth resistor and the fifth resistor and one end of the first capacitor and the second capacitor, and the other end of the sixth resistor is connected with one end of the bidirectional clamping diode; the other end of the bidirectional clamping diode is connected with one end of the seventh resistor, and the other end of the seventh resistor is connected with a gate of the IGBT as the third end of the detection circuit; a cathode of the third clamping diode is connected with an anode of the first clamping diode, an anode of the third clamping diode is connected with one end of the eighth resistor, and the other end of the eighth resistor is connected with a cathode of the second clamping diode; an input end of the comparison circuit is connected with the seventh resistor in parallel, and an output end of the comparison circuit is connected with the auxiliary digital chip.

[0035] Optionally, the comparison circuit comprises:

[0036] a first operational amplifier, a second operational amplifier, a third operational amplifier, a comparator, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor;

[0037] The positive input end of the first operational amplifier is used as the positive input end of the comparison circuit, the negative input end of the first operational amplifier is connected with the output end of the first operational amplifier, the output end of the first operational amplifier is further connected with one end of the ninth resistor, the other end of the ninth resistor is connected with the positive input end of the third operational amplifier, the negative input end of the second operational amplifier is connected with the output end of the second operational amplifier, the output end of the second operational amplifier is further connected with one end of the tenth resistor, the other end of the tenth resistor is connected with the negative input end of the third operational amplifier, the positive input end of the third operational amplifier is further connected with one end of the eleventh resistor, the other end of the eleventh resistor is connected with a high level, the negative input end of the third operational amplifier is further connected with one end of the twelfth resistor, the other end of the twelfth resistor is connected with the output end of the third operational amplifier, the output end of the third operational amplifier is further connected with the positive input end of the comparator, the negative input end of the comparator is connected with the reference voltage, the output end of the comparator is used as the output end of the comparison circuit and is connected with the secondary-side digital chip.

[0038] Optionally, the primary-side control circuit is further configured to transmit the fault information to an upper computer.

[0039] The IGBT electric-thermal stress equalization device provided in the application comprises a primary-side control circuit, an isolation transformer, a secondary-side digital driving circuit and a detection circuit. The primary-side control circuit is configured to generate a control signal according to a received pulse width modulation signal and fault information of the IGBT, and transmit the control signal to the secondary-side digital driving circuit through the isolation transformer. The secondary-side digital driving circuit is configured to drive the IGBT according to the control signal, receive the fault information of the IGBT, and transmit the fault information to the primary-side control circuit through the isolation transformer. The detection circuit is configured to collect the fault information of the IGBT and transmit the fault information to the secondary-side digital driving circuit. It can be seen that the IGBT electric-thermal stress equalization device provided in the application adopts a magnetic isolation mode to transmit signals, has the characteristics of low transmission delay and high isolation voltage resistance, and makes the fault feedback and the electric-thermal stress equalization action response faster. In addition, the IGBT is driven by the secondary-side digital driving circuit, which has better flexibility and adaptability, and can realize reliable operation of the IGBT in the whole life cycle and flexible margin configuration. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the prior art and the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creating any inventive effort.

[0041] Figure 1 A schematic diagram of an IGBT electric-thermal stress balancing device provided by an embodiment of the present application;

[0042] Figure 2 A schematic diagram of another IGBT electric-thermal stress balancing device provided by an embodiment of the present application;

[0043] Figure 3 A schematic diagram of a primary-side control circuit provided by an embodiment of the present application;

[0044] Figure 4 A schematic diagram of a secondary-side digital drive circuit provided by an embodiment of the present application;

[0045] Figure 5 A schematic diagram of a hierarchical drive circuit provided by an embodiment of the present application;

[0046] Figure 6 A schematic diagram of a clamping detection circuit provided by an embodiment of the present application;

[0047] Figure 7 A schematic diagram of a comparison circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0048] The core of the present application is to provide an IGBT electric-thermal stress balancing device, which is faster in response, better in adaptability, higher in stability, and capable of realizing reliable operation of IGBT in the whole life cycle and flexible margin configuration.

[0049] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in detail with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0050] Reference is made to Figure 1 , Figure 1 A schematic diagram of an IGBT electric-thermal stress balancing device provided by an embodiment of the present application, as shown in Figure 1 , the device mainly comprises a primary-side control circuit 10, an isolation transformer T, a secondary-side digital drive circuit 20, and a detection circuit 30.

[0051] In one specific implementation, the primary-side control circuit 10 is 1-channel, while the isolation transformer T, the secondary-side digital drive circuit 20, and the detection circuit 30 are all n-channel, where n is the number of IGBTs in the series assembly, and the isolation transformer T, the secondary-side digital drive circuit 20, and the detection circuit 30 correspond one-to-one with the IGBTs.

[0052] Specifically, refer to Figure 2 As shown, in this embodiment, the IGBT electrothermal stress equalization device mainly consists of one primary-side control circuit 10, n isolation transformers T, n secondary-side digital drive circuits 20, and n detection circuits 30. The primary-side control circuit 10 generates an independent control signal for each IGBT and transmits the control signal to the corresponding secondary-side digital drive circuit 20 through each isolation transformer T, thereby driving the corresponding IGBT. Each detection circuit 30 collects the fault signal of its corresponding IGBT. The series assembly consists of n IGBTs, with the collectors and emitters of each IGBT connected end-to-end.

[0053] The primary-side control circuit 10 is located on the primary side of the isolation transformer T. A pulse-width modulation (PWM) signal, sent from the host computer to control the switching timing and conduction duration of each IGBT in the series assembly, is input to the primary-side control circuit 10. Additionally, the primary-side control circuit 10 receives IGBT fault signals transmitted from the secondary-side digital drive circuit 20 via the isolation transformer T. Based on the PWM signal from the host computer and the IGBT fault signals, the primary-side control circuit 10 generates control signals for the IGBTs and transmits these control signals to the secondary-side digital drive circuit 20 via the isolation transformer T.

[0054] The secondary-side digital drive circuit 20 is located on the secondary side of the isolation transformer T. On one hand, the secondary-side digital drive circuit 20 drives the IGBT according to the control signals transmitted by the primary-side control circuit 10. On the other hand, it receives fault information from the IGBT and transmits the fault information to the primary-side control circuit 10 through the isolation transformer T.

[0055] The detection circuit 30 is used to collect fault information of IGBT and transmit the fault information to the secondary digital drive circuit 20.

[0056] refer to Figure 3 As shown, in one specific embodiment, the primary-side control circuit 10 includes:

[0057] Primary-side digital chip, first modulation circuit, and first demodulation circuit;

[0058] The primary-side digital chip is used to generate a trigger pulse width modulation signal based on the pulse width modulation signal and the fault pulse width modulation signal.

[0059] The first modulation circuit is configured to convert the trigger pulse width signal into a trigger edge modulation signal and output the trigger edge modulation signal to the secondary digital drive circuit 20 through the isolation transformer T.

[0060] The first demodulation circuit is configured to receive the fault edge modulation signal output by the secondary digital drive circuit 20 through the isolation transformer T and convert the fault edge modulation into a fault pulse width modulation signal.

[0061] Reference Figure 4 In a specific embodiment, the secondary digital drive circuit 20 includes:

[0062] The second modulation circuit, the second demodulation circuit, the secondary digital chip, and the hierarchical drive circuit;

[0063] The second demodulation circuit is configured to convert the edge modulation signal output by the primary control circuit 10 through the isolation transformer T into a trigger pulse width signal.

[0064] The secondary digital chip is configured to output a drive signal to the hierarchical drive circuit according to the trigger pulse width information to generate a fault pulse width modulation signal.

[0065] The second modulation circuit is configured to convert the fault pulse width modulation signal into a fault edge modulation signal and transmit the fault edge modulation signal to the primary control circuit 10 through the isolation transformer T.

[0066] The hierarchical drive circuit is configured to perform hierarchical soft turn-off or closed-loop triggering on the IGBT according to the drive signal.

[0067] Specifically, in order to reduce the loss and volume of the isolation transformer T, the primary control circuit 10 in the embodiment is provided with a first modulation circuit and a first demodulation circuit. The primary control circuit 10 converts the trigger pulse width modulation signal generated by the primary digital chip into a trigger edge modulation signal through the first modulation circuit, i.e., the conversion of the pulse signal into the edge signal is performed by the first modulation circuit. The converted trigger edge modulation signal is then transmitted to the secondary digital drive circuit 20 by the isolation transformer T. In addition, the primary control circuit 10 converts the fault edge modulation signal transmitted by the secondary digital drive circuit 20 into a fault pulse width modulation signal through the first demodulation circuit, i.e., the conversion of the edge signal into the pulse signal is performed by the first demodulation circuit. The converted fault pulse width modulation signal is transmitted to the primary digital chip.

[0068] The secondary side digital drive circuit 20 is provided with a second modulation circuit and a second demodulation circuit. The secondary side digital drive circuit 20 converts the trigger edge modulation signal transmitted by the primary side digital chip through the isolation transformer T into a trigger pulse width signal through the second demodulation circuit, and then inputs the converted trigger pulse width signal into the secondary side digital chip. The secondary side digital drive circuit 20 converts the fault pulse width modulation signal generated by the secondary side digital chip into a fault edge modulation signal through the second modulation circuit. The converted fault edge modulation signal is transmitted to the primary side control circuit 10 through the isolation transformer T.

[0069] By signal modulation, the pulse signal is converted into an edge signal, which on the one hand reduces the magnetic core volume and loss of the isolation transformer T, and on the other hand realizes the multiplexing of the two signals, greatly reducing the number of magnetic cores.

[0070] As shown in Figure 3 , for the embodiment corresponding to the primary side control circuit 10 being 1-way, the isolation transformer T, the secondary side digital drive circuit 20 and the detection circuit 30 being n-way, the first modulation circuit and the first demodulation circuit being n-way.

[0071] In a specific embodiment, the secondary side digital drive circuit 20 is specifically configured to classify the fault information, transmit the first type of fault information to the primary side control circuit 10 through the isolation transformer T, and drive the IGBT according to the second fault information and the control signal.

[0072] Specifically, after receiving various types of fault information, the secondary side digital drive circuit 20 first classifies the fault information. For the fault information that will not affect other IGBTs in the series component, i.e. the second type of fault information, the digital drive circuit performs local processing. For the fault information that will affect other IGBTs in the series component, i.e. the first type of fault information, the digital drive circuit transmits it to the primary side control circuit 10 through the isolation transformer T, so that the primary side control circuit 10 performs unified processing.

[0073] The first type of fault information includes under-voltage, short circuit, over-voltage, clamping state and other information occurring in the IGBT turn-on process. The second type of fault information includes over-voltage and clamping state in the IGBT turn-off process.

[0074] Further, referring to Figure 5 , on the basis of the above embodiment, the hierarchical drive circuit can include:

[0075] a first drive switch M1, a second drive switch M2, a third drive switch M3, a first resistor R1, a second resistor R2 and a third resistor R3;

[0076] The drain of the first driving switch M1 is connected to a high level, the source of the first driving switch M1 is connected to the first end of the first resistor R1, and the gate of the first driving switch M1 is connected to the secondary-side digital chip; the source of the second driving switch M2 is connected to a low level, the drain of the second driving switch M2 is connected to the first end of the second resistor R2, and the gate of the second driving switch M2 is connected to the secondary-side digital chip; the source of the third driving switch M3 is connected to the first end of the third resistor R3, the drain of the third driving switch M3 is connected to a zero level, and the gate of the third driving switch M3 is connected to the secondary-side digital chip; the second end of the first resistor R1, the second end of the second resistor R2, and the second end of the third resistor R3 are connected together and serve as an output end of the hierarchical driving circuit and are connected to the gate of the IGBT.

[0077] Therefore, when the hierarchical soft turn-off is performed, the secondary-side digital chip closes the second driving switch M2 in the hierarchical driving circuit, opens the third driving switch M3, connects the gate of the IGBT to the emitter through the third resistor R3, reduces the turn-off speed, and waits for the electrical stress to be rebalanced. The closed-loop multiple triggering is in the turn-off tail phase, and when the overvoltage occurs again, the secondary-side digital chip closes the second driving switch M2 and the third driving switch M3 in the hierarchical driving circuit, opens the first driving switch M1 for a short time, and makes the overvoltage IGBT re-enter the active region to balance the remaining carrier concentration difference of the series devices, thereby achieving the electrical stress balancing.

[0078] Further, in a specific embodiment, the detection circuit 30 can include:

[0079] a voltage detection circuit, an overcurrent detection circuit, a junction temperature detection circuit, and a clamping detection circuit;

[0080] the voltage detection circuit is configured to detect a voltage state of the IGBT;

[0081] the overcurrent detection circuit is configured to detect a current state of the IGBT;

[0082] the junction temperature detection circuit is configured to detect a junction temperature state of the IGBT;

[0083] the clamping detection circuit is configured to detect a clamping state of the IGBT.

[0084] Further, referring to FIG. 1, Figure 6 as shown, the clamping detection circuit can include:

[0085] a first clamping diode D1, a second clamping diode D2, a third clamping diode D3, a bidirectional clamping diode D4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, and a comparison circuit;

[0086] Anode of the first clamping diode D1 is connected with cathode of the second clamping diode D2 in sequence through the first capacitor C1 and the second capacitor C2, the cathode of the first clamping diode D1 is the first end of the detection circuit 30, and is connected with the collector of the IGBT, the anode of the second clamping diode D2 is the second end of the detection circuit 30, and is connected with the emitter of the IGBT; the fourth resistor R4 and the fifth resistor R5 are connected in series, and are connected between the first end and the second end of the detection circuit 30; one end of the sixth resistor R6 is connected with one end of the fourth resistor R4 and the fifth resistor R5, and one end of the first capacitor C1 and the second capacitor C2, and the other end of the sixth resistor R6 is connected with one end of the bidirectional clamping diode D4; the other end of the bidirectional clamping diode D4 is connected with one end of the seventh resistor R7, and the other end of the seventh resistor R7 is the third end of the detection circuit 30, and is connected with the gate of the IGBT; the cathode of the third clamping diode D3 is connected with the anode of the first clamping diode D1, the anode of the third clamping diode D3 is connected with one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected with the cathode of the second clamping diode D2; the input end of the comparison circuit is connected with the seventh resistor R7 in parallel, and the output end of the comparison circuit is connected with the secondary digital chip.

[0087] Specifically, the first clamping diode D1, the first capacitor C1, the second capacitor C2 and the second clamping diode D2 are connected in series and connected between the positive pole and the negative pole of the clamping detection circuit 30, i.e. between the first end and the second end. The fourth resistor R4 and the fifth resistor R5 are connected in series and also connected between the positive pole and the negative pole of the clamping detection circuit 30, and one end of the fourth resistor R4 is connected with one end of the first capacitor C1 to form a dynamic and static voltage division structure, and the connection point is connected with the sixth resistor R6, the bidirectional clamping diode D4 and the seventh resistor R7 and then output from the G end, i.e. the third end. The seventh resistor R7 is connected with the comparison circuit to obtain the clamping working time information. In addition, the first capacitor C1 and the second capacitor C2 are connected with the third clamping diode D3 and the eighth resistor R8 in parallel.

[0088] When the voltage between the positive and negative poles of the clamping detection circuit 30 is constant, the ratio of the fourth resistor R4 and the fifth resistor R5 is controlled to ensure that the potential between the two does not break the bidirectional clamping diode D4; when the voltage between the positive and negative poles gradually rises and exceeds the voltage of the first clamping diode D1, the first capacitor C1 and the second capacitor C2 begin to charge, the instantaneous midpoint potential of the two rises, breaks the bidirectional clamping diode D4, and injects current into the G terminal, realizing active clamping of the IGBT. At this time, if the voltage across the seventh resistor R7 exceeds the reference voltage, the comparator outputs a high level, which continues until the active clamping effect is not obvious. If, in the tail phase, the voltage between the positive and negative poles again appears serious imbalance, and the charging voltage of the first capacitor C1 and the second capacitor C2 is too high, then the third clamping diode D3 and the second clamping diode D2 will be broken, and a clamping current will flow between the positive and negative poles, limiting the further deterioration of the overvoltage.

[0089] wherein the reference Figure 7 As shown in the figure, the comparison circuit can include:

[0090] The first operational amplifier A1, the second operational amplifier A2, the third operational amplifier A3, the comparator A4, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, and the twelfth resistor R12;

[0091] The positive input terminal of the first operational amplifier A1 serves as the positive input terminal of the comparison circuit, the negative input terminal of the first operational amplifier A1 is connected to the output terminal of the first operational amplifier A1, the output terminal of the first operational amplifier A1 is also connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the positive input terminal of the third operational amplifier A3, the negative input terminal of the second operational amplifier A2 is connected to the output terminal of the second operational amplifier A2, the output terminal of the second operational amplifier A2 is also connected to one end of the tenth resistor R10, the other end of the tenth resistor R10 is connected to the negative input terminal of the third operational amplifier A3, the positive input terminal of the third operational amplifier A3 is also connected to one end of the eleventh resistor R11, the other end of the eleventh resistor R11 is connected to a high level, the negative input terminal of the third operational amplifier A3 is also connected to one end of the twelfth resistor R12, the other end of the twelfth resistor R12 is connected to the output terminal of the third operational amplifier A3, the output terminal of the third operational amplifier A3 is also connected to the positive input terminal of the comparator A4, the negative input terminal of the comparator A4 is connected to a reference voltage, and the output terminal of the comparator A4 serves as the output terminal of the comparison circuit and is connected to the secondary-side digital chip.

[0092] Specifically, the first operational amplifier A1 and the second operational amplifier A2 realize differential extraction of the voltage drop of the seventh resistor R7, the third operational amplifier A3 restores the differential signal to a voltage drop signal, and the comparator A4 outputs clamping state information, including the triggering time and the duration, by comparing the voltage drop of the seventh resistor R7 with the reference voltage value.

[0093] The circuit structure of the voltage detection circuit, the overcurrent detection circuit and the junction temperature detection circuit is not described herein, and can be referred to the corresponding circuit.

[0094] Further, the primary side control circuit 10 gives a synchronous soft turn-off instruction for short circuit, under-voltage and other serious fault information after receiving the second type of fault information of all IGBTs, to ensure the synchronous turn-off of all devices. For the state information of over-voltage and over-voltage clamping, it is first verified whether an open circuit fault occurs. If it occurs, the device is turned off synchronously. If it does not occur, the backup tube is switched on, and the overheat stress balance is realized by advancing the turn-on trigger. For the state information of turn-off over-voltage and clamping time being too long, the backup tube is switched off, and the overheat stress balance is realized by delaying the turn-off trigger. After the above control actions are completed, the primary side control circuit 10 can further return the major fault information to the upper computer.

[0095] In summary, the IGBT overheat stress balancing device provided by the present application uses a magnetic isolation method to transmit signals, has the characteristics of low transmission delay and high isolation voltage, and makes the fault feedback and overheat stress balancing action response faster. In addition, the IGBT is driven by the secondary side digital drive circuit, which has better flexibility and adaptability, and can realize reliable operation of the IGBT throughout its life cycle and flexible margin configuration.

[0096] Because the situation is complex, it is impossible to enumerate and describe it one by one. Those skilled in the art should be aware that under the basic principles of the embodiments provided by the present application, there can be many examples in combination with actual situations, and without sufficient creative labor, they should all be within the scope of the present application.

[0097] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be mutually referred to.

[0098] The IGBT overheat stress balancing device provided by the present application is described in detail above. The principles and implementation methods of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that those skilled in the art can make some improvements and modifications to the present application without departing from the principles of the present application. These improvements and modifications also fall within the protection scope of the claims of the present application.

[0099] It also needs to be explained that in the present specification, the relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Claims

1. An IGBT electro-thermal stress equalization device, characterized by, The application relates to a control circuit for an IGBT (Insulated Gate Bipolar Transistor) in a series connection, and belongs to the technical field of power electronic. The application comprises: a primary side control circuit, an isolation transformer, a secondary side digital drive circuit and a detection circuit; The primary side control circuit is used for generating a control signal according to a received pulse width modulation signal and fault information of the IGBT, and transmitting the control signal to the secondary side digital drive circuit through the isolation transformer; The secondary side digital drive circuit is used for driving the IGBT according to the control signal, receiving the fault information of the IGBT and transmitting the fault information to the primary side control circuit through the isolation transformer; The detection circuit is used for collecting the fault information of the IGBT and transmitting the fault information to the secondary side digital drive circuit; 2. The IGBT electro-thermal stress equalization device of claim 1, wherein, The secondary side digital drive circuit is specifically used for classifying the fault information, transmitting first-class fault information to the primary side control circuit through the isolation transformer and driving the IGBT according to second-class fault information and the control signal; the first-class fault information refers to fault information that will affect other IGBTs in a series connection component; and the second-class fault information refers to fault information that will not affect other IGBTs in the series connection component.

3. The IGBT electro-thermal stress equalization device of claim 1, wherein, The primary side control circuit is 1-way, the isolation transformer, the secondary side digital drive circuit and the detection circuit are n-way, n is the number of the IGBTs in the series connection component, and the isolation transformer, the secondary side digital drive circuit and the detection circuit correspond to the IGBTs one by one. The primary side control circuit comprises: a primary side digital chip, a first modulation circuit and a first demodulation circuit; The primary side digital chip is used for generating a trigger pulse width modulation signal according to the pulse width modulation signal and a fault pulse width modulation signal; The first modulation circuit is used for converting the trigger pulse width signal into a trigger edge modulation signal and outputting the trigger edge modulation signal to the secondary side digital drive circuit through the isolation transformer; 4. The IGBT electro-thermal stress equalization device of claim 3, wherein, The first demodulation circuit is used for receiving a fault edge modulation signal output by the secondary side digital drive circuit through the isolation transformer and converting the fault edge modulation into the fault pulse width modulation signal. The secondary side digital drive circuit comprises: a second modulation circuit, a second demodulation circuit, a secondary side digital chip and a hierarchical drive circuit; The second demodulation circuit is used for converting an edge modulation signal output by the primary side control circuit through the isolation transformer into the trigger pulse width signal; The secondary side digital chip is used for outputting a drive signal to the hierarchical drive circuit according to the trigger pulse width information, generating the fault pulse width modulation signal; The second modulation circuit is used for converting the fault pulse width modulation signal into the fault edge modulation signal and transmitting the fault edge modulation signal to the primary side control circuit through the isolation transformer; 5. The IGBT electro-thermal stress equalization device of claim 4, wherein, The hierarchical drive circuit is used for hierarchically soft shutting off or closed-loop triggering the IGBT according to the drive signal. The hierarchical drive circuit comprises: a first drive switch, a second drive switch, a third drive switch, a first resistor, a second resistor and a third resistor; The drain of the first driving switch is connected to a high level, the source of the first driving switch is connected to the first end of the first resistor, and the gate of the first driving switch is connected to the secondary-side digital chip; the source of the second driving switch is connected to a low level, the drain of the second driving switch is connected to the first end of the second resistor, and the gate of the second driving switch is connected to the secondary-side digital chip; the source of the third driving switch is connected to the first end of the third resistor, the drain of the third driving switch is connected to a zero level, and the gate of the third driving switch is connected to the secondary-side digital chip; the second end of the first resistor, the second end of the second resistor, and the second end of the third resistor are connected together and connected to the gate of the IGBT as an output end of the hierarchical driving circuit.

6. The IGBT electro-thermal stress equalization device of claim 1, wherein, The detection circuit comprises: a voltage detection circuit, an overcurrent detection circuit, a junction temperature detection circuit, and a clamping detection circuit; the voltage detection circuit is configured to detect a voltage state of the IGBT; the overcurrent detection circuit is configured to detect a current state of the IGBT; the junction temperature detection circuit is configured to detect a junction temperature state of the IGBT; the clamping detection circuit is configured to detect a clamping state of the IGBT.

7. The IGBT electro-thermal stress equalization device of claim 6, wherein, The clamping detection circuit comprises: a first clamping diode, a second clamping diode, a third clamping diode, a bidirectional clamping diode, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a second capacitor, and a comparison circuit; the anode of the first clamping diode is connected in series with the first capacitor, the second capacitor, and the cathode of the second clamping diode in sequence, the cathode of the first clamping diode is connected to the collector of the IGBT as a first end of the detection circuit, the anode of the second clamping diode is connected to the emitter of the IGBT as a second end of the detection circuit; the fourth resistor and the fifth resistor are connected in series, and the fourth resistor and the fifth resistor are connected between the first end and the second end of the detection circuit; one end of the sixth resistor is connected to the end of the fourth resistor and the fifth resistor, and the end of the first capacitor and the second capacitor, and the other end of the sixth resistor is connected to one end of the bidirectional clamping diode; the other end of the bidirectional clamping diode is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the gate of the IGBT as a third end of the detection circuit; the cathode of the third clamping diode is connected to the anode of the first clamping diode, the anode of the third clamping diode is connected to one end of the eighth resistor, and the other end of the eighth resistor is connected to the cathode of the second clamping diode; the input end of the comparison circuit is connected in parallel with the seventh resistor, and the output end of the comparison circuit is connected to the secondary-side digital chip.

8. The IGBT electro-thermal stress equalization device of claim 7, wherein, The comparison circuit comprises: a first operational amplifier, a second operational amplifier, a third operational amplifier, a comparator, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor; The positive input end of the first operational amplifier is used as the positive input end of the comparison circuit, the negative input end of the first operational amplifier is connected with the output end of the first operational amplifier, the output end of the first operational amplifier is further connected with one end of the ninth resistor, the other end of the ninth resistor is connected with the positive input end of the third operational amplifier, the negative input end of the second operational amplifier is connected with the output end of the second operational amplifier, the output end of the second operational amplifier is further connected with one end of the tenth resistor, the other end of the tenth resistor is connected with the negative input end of the third operational amplifier, the positive input end of the third operational amplifier is further connected with one end of the eleventh resistor, the other end of the eleventh resistor is connected with a high level, the negative input end of the third operational amplifier is further connected with one end of the twelfth resistor, the other end of the twelfth resistor is connected with the output end of the third operational amplifier, the output end of the third operational amplifier is further connected with the positive input end of the comparator, the negative input end of the comparator is connected with a reference voltage, the output end of the comparator is used as the output end of the comparison circuit and is connected with the secondary-side digital chip.

9. The IGBT electro-thermal stress equalization device of claim 1, wherein, The primary-side control circuit is further configured to transmit the fault information to a host computer.

Images