Multi-input floating-point adder

Abstract

Methods, systems, and apparatus include apparatus for adding three or more floating-point numbers. In one aspect, the method includes receiving, for each of three or more operands, a bit group comprising a floating-point representation of the operand. For each additional operand, the mantissa bits of the operand are shifted so that the operand's bits align with the bits of the given operand. A sticky bit is determined for each additional operand. A total sticky bit value is determined based on each sticky bit. Whenever all sticky bits have a zero value, or at least two sticky bits are non-zero and do not match, the total sticky bit value is zero. Whenever all non-zero sticky bits match or only one non-zero sticky bit exists, the total sticky bit value matches the value of each non-zero sticky bit.

Description

Background Art

[0001] Floating-point format is often used in computers to represent numbers. A two-input adder is commonly used to perform addition and subtraction (using the two's complement of one of the numbers) on floating-point numbers. To perform this operation on more than two floating-point numbers, multiple adders can be used to add two floating-point numbers at a time, or a single adder can perform multiple additions. For example, to add three floating-point numbers, the adder can add two of the numbers together and then add the third number to the sum of the two numbers.

[0002] Floating-point addition can involve multiple steps, including shifting to align the numbers' exponents, performing the addition, normalizing the sum, and rounding the sum as appropriate. Therefore, performing more than one addition operation to add more than two floating-point numbers results in multiple iterations of these steps. If multiple adders are used to compute the sum in parallel, the additional adders take up more of the limited space on the chip, including the adders. Summary of the Invention

[0003] This specification describes techniques related to multi-input adders that add three or more floating-point numbers.

[0004] Generally, one innovative aspect of the subject matter described herein can be embodied in a method comprising: for each of three or more operands to be added by the multi-input hardware adder, receiving a bit group comprising a floating-point representation of the operand; identifying a given operand to be aligned with each other operand; for each other operand, generating a shifted bit group of the operand by shifting the mantissa bits of the operand by zero or more bit positions so that the bits of the operand are aligned with the bits of the given operand; and determining a value of a sticky bit for each other operand based on the shifting, wherein the sticky bit of the operand is: The method of claim 1, wherein the sticky bit value of the three or more operands is determined based on the sticky bit value of each operand, wherein the sticky bit value of each operand is zero when (i) all of the sticky bits of all of the other operands are zero or (ii) at least two of the other operands have non-zero and non-matching sticky bits, and the sticky bit value of each operand is matched when all non-zero sticky bits match or there is only one non-zero sticky bit. The method of claim 1, wherein the sticky bit value of each operand is zero when all of the sticky bits of the other operands are zero or (ii) at least two of the other operands have non-zero and non-matching sticky bits, and the sticky bit value of each operand is matched when all of the non-zero sticky bits match or there is only one non-zero sticky bit. The method of claim 1, wherein the sticky bit value of each operand is zero when all of the non-zero sticky bits of the other operands are zero or (iii) at least two of the other operands have non-zero and non-matching sticky bits, and the sticky bit value of each operand is matched when all of the non-zero sticky bits match or there is only one non-zero sticky bit. The method of claim 1, wherein the sticky bit value of each operand is zero when all of the non-zero sticky bits of the other operands are zero or (iv) at least two of the other operands have non-zero and non-matching sticky bits, and the sticky bit value of each operand is matched when all of the non-zero sticky bits match or there is only one non-zero sticky bit.

[0005] These and other embodiments can each optionally include one or more of the following features. In some aspects, determining the sum of the three or more operands comprises: determining a summed set of bits representing the sum of the bit groups representing the given operand and each shifted bit group; normalizing the mantissa of the summed set of bits by shifting the mantissa of the summed set of bits until the hidden bit is one whenever a hidden bit of the mantissa of the summed set of bits is zero; and determining whether to round a floating-point value represented by the summed set of bits based on the mantissa of the summed set of bits and the total sticky bit value.

[0006] In some aspects, determining whether to round the floating-point value represented by the summed set of bits comprises determining a number of bit positions by which the mantissa of the summed set of bits is shifted to normalize the mantissa of the summed set of bits; and determining, based on the floating-point value represented by the summed set of bits and the total sticky bit value, to round the floating-point value represented by the summed set of bits whenever the number of bit positions exceeds a number of precision bits of the multi-input adder excluding the sticky bit.

[0007] Some aspects can include preventing the total sticky bit value from being included in the mantissa of the summed set of bits during normalization by assigning bits of the mantissa representing the total sticky bit value to zero whenever the total sticky bit value is non-zero and the total sticky bit value is shifted into the mantissa during normalization. In some aspects, shifting the mantissa bits of the operand by zero or more bit positions includes shifting the mantissa bits based on a difference between an exponent of the operand and an exponent of the given operand.

[0008] In some aspects, identifying a given operand to be aligned with each other operand includes identifying the operand having the largest exponent value. In some aspects, the multi-input adder is a four-input adder having four floating-point inputs and determining a sum of four floating-point values ​​received at the four floating-point inputs.

[0009] In general, another innovative aspect of the subject matter described herein can be embodied in a multi-input hardware adder comprising three or more inputs and adder circuitry configured to receive three or more floating-point operands. The adder circuitry is configured to perform operations including, for each of the three or more operands to be added by the multi-input hardware adder, receiving a bit group comprising a floating-point representation of the operand. The adder circuitry is configured to identify a given operand to be aligned with each other operand; and for each other operand, generate a shifted bit group of the operand by shifting the mantissa bits of the operand by zero or more bit positions such that the bits of the operand are aligned with the bits of the given operand. The adder circuitry is configured to determine a sticky bit value for each other operand based on the shifting. The total sticky bit value is zero whenever (i) all of the sticky bits of all of the other operands are zero or (ii) at least two of the other operands have non-zero and mismatching sticky bits. Whenever all non-zero sticky bits match or there is only one non-zero sticky bit, the total sticky bit value matches the value of each non-zero sticky bit. The adder circuit can determine the sum of the three or more operands using (i) the group of bits representing the given operand, (ii) the shifted group of bits of each other operand, and (iii) the total sticky bit value.

[0010] These and other embodiments can each optionally include one or more of the following features. In some aspects, determining the sum of the three or more operands can include determining a summed set of bits representing the sum of the bit groups representing the given operand and each shifted bit group. Whenever a hidden bit of the mantissa of the summed set of bits is zero, normalizing the mantissa of the summed set of bits by shifting the mantissa of the summed set of bits until the hidden bit is one. Based on the mantissa of the summed set of bits and the total sticky bit value, the adder circuit determines whether to round the floating-point value represented by the summed set of bits.

[0011] In some aspects, determining whether to round the floating-point value represented by the sum of the set of bits may include: determining a number of bit positions by which the mantissa of the sum of the set of bits is shifted to normalize the mantissa of the sum of the set of bits; and determining, based on the floating-point value represented by the sum of the set of bits and the total sticky bit value, to round the floating-point value represented by the sum of the set of bits whenever the number of bit positions exceeds the number of precision bits of the multi-input adder excluding the sticky bit.

[0012] In some aspects, the operations may include, whenever the total sticky bit value is non-zero and the total sticky bit value is shifted to the mantissa during normalization, preventing the total sticky bit value from being included in the mantissa of the summed set of bits during normalization by assigning bits of the mantissa representing the total sticky bit value to zero.

[0013] In some aspects, the operation can include shifting each bit group right by a specified number of bit positions before determining the sum. In some aspects, shifting the mantissa bits of the operand zero or more bit positions includes shifting the mantissa bits based on a difference between an exponent of the operand and an exponent of the given operand.

[0014] In some aspects, identifying a given operand to be aligned with each other operand includes identifying the operand having the largest exponent value. In some aspects, the multi-input adder is a four-input adder having four floating-point inputs and determining a sum of four floating-point values ​​received at the four floating-point inputs.

[0015] In general, another innovative aspect of the subject matter described in this specification can be embodied in a multi-input hardware adder comprising three or more inputs configured to receive three or more floating-point operands. Each input is configured to receive a bit group comprising a floating-point representation of the operand. The multi-input hardware adder can include an exponent subtraction and swap component configured to identify a given operand to be aligned with each other operand. The multi-input hardware adder can include one or more shifters configured to, for each other operand, generate a shifted bit group of the operand by shifting the mantissa bits of the operand by zero or more bit positions so that the bits of the operand are aligned with the bits of the given operand, and to determine the value of a sticky bit for each other operand based on the shifting. The sticky bit of the operand has a non-zero value when a non-zero value is shifted beyond the least significant position of the mantissa bits of the operand and any precision bit positions to generate the shifted bit group of the operand. The multi-input hardware adder may include a sticky bit calculator configured to determine a total sticky bit value based on the value of each sticky bit. The total sticky bit value is zero whenever (i) all of the sticky bits of all of the other operands are zero or (ii) at least two of the other operands have non-zero and non-matching sticky bits. The total sticky bit value matches the value of each non-zero sticky bit whenever all non-zero sticky bits match or there is only one non-zero sticky bit. The multi-input hardware adder may include an adder circuit configured to use (i) the bit group representing the given operand, (ii) the shifted bit group of each other operand, and (iii) the total sticky bit value to determine the sum of the three or more operands.

[0016] These and other embodiments can each optionally include one or more of the following features. In some aspects, the one or more shifters set the sticky bit of the operand to a value of 1 whenever a non-zero value is shifted into the sticky bit.

[0017] In some aspects, the adder circuit is further configured to determine a summed set of bits representing the sum of the bit groups, the bit groups representing the given operand and each shifted bit group. Whenever a hidden bit of the mantissa of the summed set of bits is zero, normalize the mantissa of the summed set of bits by shifting the mantissa of the summed set of bits until the hidden bit is 1. The adder circuit may determine whether to round a floating-point value represented by the summed set of bits based on the mantissa of the summed set of bits and the total sticky bit value.

[0018] In some aspects, determining whether to round the floating-point value represented by the summed set of bits comprises determining a number of bit positions by which the mantissa of the summed set of bits is shifted to normalize the mantissa of the summed set of bits, and determining, based on the floating-point value represented by the summed set of bits and the total sticky bit value, to round the floating-point value represented by the summed set of bits whenever the number of bit positions exceeds a number of precision bits of the multi-input adder excluding the sticky bit.

[0019] In some aspects, the operations can include, whenever the total sticky bit value is non-zero and the total sticky bit value is shifted into the mantissa during normalization, preventing the total sticky bit value from being included in the mantissa of the summed set of bits during normalization by assigning bits of the mantissa representing the total sticky bit value to zero. In some aspects, shifting the mantissa bits of the operand by zero or more bit positions can include shifting the mantissa bits based on a difference between an exponent of the operand and an exponent of the given operand.

[0020] In general, another innovative aspect of the subject matter described in this specification can be embodied in a method comprising the steps of: for each of three or more operands to be added by the multi-input hardware adder, receiving a bit group comprising a floating-point representation of the operand; identifying a given operand to be aligned with each other operand; for each other operand, generating a shifted bit group of the operand by shifting the mantissa bits of the operand by zero or more bit positions so that the bits of the operand are aligned with the bits of the given operand; and determining a value of a sticky bit for each other operand based on the shifting, wherein the sticky bit of the operand is: The method of claim 1, wherein the method comprises the steps of: shifting the bit group representing the given operand, shifting the bit group representing the given operand, shifting the bit group representing the given operand, and shifting the bit group representing the given operand, wherein the shifting bit group has a non-zero value when the bit group is shifted except for any precision bit position to generate the shifted bit group of the operand; determining a total sticky bit value based on the value of each sticky bit, wherein: the total sticky bit value is zero whenever (i) all the sticky bits of all the other operands are zero or (ii) at least two of the other operands have non-zero and non-matching sticky bits; and the total sticky bit value matches the value of each non-zero sticky bit whenever all non-zero sticky bits match or there is only one non-zero sticky bit; and determining the sum of the three or more operands using (i) the bit group representing the given operand, (ii) the shifted bit group of each other operand, and (iii) the total sticky bit value. Other embodiments of this aspect and other aspects include corresponding systems and devices configured to perform the actions of the method. Other embodiments of this aspect and other aspects include corresponding systems and devices configured to perform the actions of the method.

[0021] These and other embodiments can each optionally include one or more of the following features. In some aspects, determining the sum of the three or more operands comprises: determining a summed set of bits representing the sum of the bit groups representing the given operand and each shifted bit group; normalizing the mantissa of the summed set of bits by shifting the mantissa of the summed set of bits until the hidden bit is one whenever a hidden bit of the mantissa of the summed set of bits is zero; and determining whether to round a floating-point value represented by the summed set of bits based on the mantissa of the summed set of bits and the total sticky bit value.

[0022] In some aspects, determining whether to round the floating-point value represented by the summed set of bits comprises determining a number of bit positions by which the mantissa of the summed set of bits is shifted to normalize the mantissa of the summed set of bits; and determining, based on the floating-point value represented by the summed set of bits and the total sticky bit value, to round the floating-point value represented by the summed set of bits whenever the number of bit positions exceeds a number of precision bits of the multi-input adder excluding the sticky bit.

[0023] Some aspects can include preventing the total sticky bit value from being included in the mantissa of the summed set of bits during normalization by assigning bits of the mantissa representing the total sticky bit value to zero whenever the total sticky bit value is non-zero and the total sticky bit value is shifted into the mantissa during normalization. In some aspects, shifting the mantissa bits of the operand by zero or more bit positions includes shifting the mantissa bits based on a difference between an exponent of the operand and an exponent of the given operand.

[0024] In some aspects, identifying a given operand to be aligned with each other operand includes identifying the operand having the largest exponent value. In some aspects, the multi-input adder is a four-input adder having four floating-point inputs and determining a sum of four floating-point values ​​received at the four floating-point inputs.

[0025] In general, another innovative aspect of the subject matter described herein can be included in a multi-input hardware adder comprising three or more inputs and adder circuitry configured to receive three or more floating-point operands. The adder circuitry is configured to perform operations including, for each of the three or more operands to be added by the multi-input hardware adder, receiving a bit group comprising a floating-point representation of the operand. The adder circuitry is configured to identify a given operand to be aligned with each of the other operands; and for each of the other operands, generating a shifted bit group of the operand by shifting the mantissa bits of the operand by zero or more bit positions such that the bits of the operand align with the bits of the given operand. The adder circuitry is configured to determine a sticky bit value for each of the other operands based on the shifting. The total sticky bit value is zero whenever (i) all of the sticky bits of all of the other operands are zero or (ii) at least two of the other operands have non-zero and mismatching sticky bits. Whenever all non-zero sticky bits match or there is only one non-zero sticky bit, the total sticky bit value matches the value of each non-zero sticky bit. The adder circuit can determine the sum of the three or more operands using (i) the group of bits representing the given operand, (ii) the shifted group of bits of each other operand, and (iii) the total sticky bit value.

[0026] These and other embodiments can each optionally include one or more of the following features. In some aspects, determining the sum of the three or more operands can include determining a summed set of bits representing the sum of the bit groups representing the given operand and each shifted bit group. Whenever a hidden bit of the mantissa of the summed set of bits is zero, normalizing the mantissa of the summed set of bits by shifting the mantissa of the summed set of bits until the hidden bit is one. Based on the mantissa of the summed set of bits and the total sticky bit value, the adder circuit determines whether to round the floating-point value represented by the summed set of bits.

[0027] In some aspects, determining whether to round the floating-point value represented by the sum of the set of bits may include: determining a number of bit positions by which the mantissa of the sum of the set of bits is shifted to normalize the mantissa of the sum of the set of bits; and determining, based on the floating-point value represented by the sum of the set of bits and the total sticky bit value, to round the floating-point value represented by the sum of the set of bits whenever the number of bit positions exceeds the number of precision bits of the multi-input adder excluding the sticky bit.

[0028] In some aspects, the operations may include, whenever the total sticky bit value is non-zero and the total sticky bit value is shifted to the mantissa during normalization, preventing the total sticky bit value from being included in the mantissa of the summed set of bits during normalization by assigning bits of the mantissa representing the total sticky bit value to zero.

[0029] In some aspects, the operation can include shifting each bit group right by a specified number of bit positions before determining the sum. In some aspects, shifting the mantissa bits of the operand zero or more bit positions includes shifting the mantissa bits based on a difference between an exponent of the operand and an exponent of the given operand.

[0030] In some aspects, identifying a given operand to be aligned with each other operand includes identifying the operand having the largest exponent value. In some aspects, the multi-input adder is a four-input adder having four floating-point inputs and determining a sum of four floating-point values ​​received at the four floating-point inputs.

[0031] In general, another innovative aspect of the subject matter described in this specification can be embodied in a multi-input hardware adder comprising three or more inputs configured to receive three or more floating-point operands. Each input is configured to receive a bit group comprising a floating-point representation of the operand. The multi-input hardware adder can include an exponent subtraction and swap component configured to identify a given operand to be aligned with each other operand. The multi-input hardware adder can include one or more shifters configured to, for each other operand, generate a shifted bit group of the operand by shifting the mantissa bits of the operand by zero or more bit positions so that the bits of the operand are aligned with the bits of the given operand, and to determine the value of a sticky bit for each other operand based on the shifting. The sticky bit of the operand has a non-zero value when a non-zero value is shifted beyond the least significant position of the mantissa bits of the operand and any precision bit positions to generate the shifted bit group of the operand. The multi-input hardware adder may include a sticky bit calculator configured to determine a total sticky bit value based on the value of each sticky bit. The total sticky bit value is zero whenever (i) all of the sticky bits of all of the other operands are zero or (ii) at least two of the other operands have non-zero and non-matching sticky bits. The total sticky bit value matches the value of each non-zero sticky bit whenever all non-zero sticky bits match or there is only one non-zero sticky bit. The multi-input hardware adder may include an adder circuit configured to use (i) the bit group representing the given operand, (ii) the shifted bit group of each other operand, and (iii) the total sticky bit value to determine the sum of the three or more operands.

[0032] These and other embodiments can each optionally include one or more of the following features. In some aspects, the one or more shifters set the sticky bit of the operand to a value of 1 whenever a non-zero value is shifted into the sticky bit.

[0033] In some aspects, the adder circuit is further configured to determine a summed set of bits representing the sum of the bit groups, the bit groups representing the given operand and each shifted bit group. Whenever a hidden bit of the mantissa of the summed set of bits is zero, normalize the mantissa of the summed set of bits by shifting the mantissa of the summed set of bits until the hidden bit is 1. The adder circuit may determine whether to round a floating-point value represented by the summed set of bits based on the mantissa of the summed set of bits and the total sticky bit value.

[0034] In some aspects, determining whether to round the floating-point value represented by the summed set of bits comprises determining a number of bit positions by which the mantissa of the summed set of bits is shifted to normalize the mantissa of the summed set of bits, and determining, based on the floating-point value represented by the summed set of bits and the total sticky bit value, to round the floating-point value represented by the summed set of bits whenever the number of bit positions exceeds a number of precision bits excluding sticky bits of the multi-input adder.

[0035] In some aspects, the operations can include preventing the total sticky bit value from being included in the mantissa of the summed set of bits during normalization by assigning bits of the mantissa representing the total sticky bit value to zero whenever the total sticky bit value is non-zero and the total sticky bit value is shifted into the mantissa during normalization. In some aspects, shifting the mantissa bits of the operand by zero or more bit positions can include shifting the mantissa bits based on a difference between an exponent of the operand and an exponent of the given operand.

[0036] The subject matter described in this specification can be implemented in specific embodiments to achieve one or more of the following advantages. The multi-input adders described herein can add three or more operands using less power than performing multiple additions using a dual-input adder because some steps, such as normalization and rounding, are performed once by the multi-input adder instead of multiple times (e.g., instead of once for each of the multiple addition operations of each dual-input adder). This can also result in faster and more efficient additions because fewer normalization and rounding steps need to be performed to determine the sum of more than two operands, which is particularly beneficial in integrated circuits that perform many complex mathematical operations, such as machine learning accelerator circuits. The multi-input adders also consume less space on a chip than multiple dual-input adders performing addition operations in parallel, freeing up space for other components or reducing the size of the chip.

[0037] The total sticky bit value used to determine whether and how to round the sum can be calculated based on the sticky bit values ​​of the operands in a manner that ensures that errors due to rounding are within acceptable limits and that there is no bias away from zero. That is, by calculating the total sticky bit as described herein, any bias tends to round towards zero rather than towards a positive or negative number. Biasing towards zero in this manner can minimize the impact on the convergence of a machine learning model, such as a neural network. Thus, the described techniques determine the total sticky bit value in a manner that is optimized for training a machine learning model, such as when the multi-input adder is on a dedicated machine learning accelerator chip that performs the training of the machine learning model.

[0038] Various features and advantages of the foregoing subject matter will be described below with reference to the accompanying drawings. Other features and advantages will be apparent from the subject matter described herein and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a block diagram of an exemplary multi-input hardware adder.

[0040] Figure 2 is a flow chart illustrating an exemplary process for adding three or more operands.

[0041] Figure 3 Illustrated illustrates an example of adding four operands using a four-input adder.

[0042] Like reference numerals and designations in the various drawings represent like elements. DETAILED DESCRIPTION

[0043] Generally, systems and techniques described herein relate to a multi-input hardware adder that calculates the sum of three or more floating-point inputs. For example, a four-input adder can calculate the sum of four floating-point numbers. Floating-point numbers are represented by a group of bits, including a sign bit representing whether a number is positive or negative, an exponent bit representing the floating-point exponent value, and a mantissa position (also referred to as a significant digit) representing the floating-point number's significant digit. For example, the floating-point number of IEEE 754 single-precision format includes 1 sign bit, 8 exponent bits, and 24 mantissa bits (23 explicit storage bits and 1 recessive hidden bit). In order to draw the value of a floating-point number, the mantissa is multiplied by the base (for example, base 2) of the power raised to the exponent.

[0044] In order to determine the sum of three or more floating-point operands (operand), a multi-input adder can identify the operand that each other operand will align with. This operand can be the operand with the maximum exponent value. In order to set up alignment, that is, in order to align other operands with a given operand, the multi-input adder can shift the mantissa bits of each other operand based on the difference between the exponent value of the identified operand and the exponent value of the other operands, so that the mantissa bits of all operands are aligned. If a given operand has an exponent greater than the exponent of the other operands, the position in the mantissa of the other operands is shifted right by several positions, wherein the most significant bit is set to zero (logical shift), and the number of positions to be shifted corresponds to the difference in the exponent. After the shift, the exponent of the other operand is set to the same value as the exponent of the given operand, and the value of the mantissa of the other operand is reduced by right shift. In other words, when aligned, each operand has the same exponent value. If right shift occurs, then the other operand is no longer normalized in the sense of the IEEE floating-point format. The alignment process of the other operands may result in some loss of precision because some non-zero bits, i.e., less significant bits, of the lower end of the mantissa of the original other operands may be shifted out of the mantissa, or even out of additional precision bits, and the information they represent may be lost. Among other aspects, as disclosed herein, the sticky bit and determination of the overall sticky bit are intended to avoid or mitigate such loss in precision and the significant biasing or reduction in precision of the summation result by the effective change (-) of the value of the non-normalized representation of the other operands at the immediate stage of the addition, as described above. While higher precision of the summation result can be achieved, for example, by increasing the number of internal precision bits of the summing operands, for the case of adding three or more floating-point numbers, the disclosed techniques related to the sticky bit and the overall sticky bit achieve rounding of the summation result within acceptable limits and without deviating from zero using a single sticky bit of each operand. Thus, the disclosed techniques require less hardware resources than conventional techniques for increasing precision in multi-input floating-point addition.

[0045] When the mantissa bits of the shift operands, some mantissa bits can be shifted outside the available bits for representing the floating-point operands. The multi-input adder can include some extra bits for precision and rounding. For example, the multi-input adder can include three additional bits for precision and a sticky bit for internal calculations and rounding. The sticky bit can be in the least significant bit (LSB) position, and the three precision bits can be between the sticky bit and the mantissa bits. In this example, if the operand is shifted to the right by more than three bit positions during alignment, one or more least significant mantissa bits will be shifted from the available bits to the sticky bit position or through the sticky bit position. The sticky bit indicates what may be contained in the less significant bits that are not retained after alignment. If the value 1 is shifted to the sticky bit position of the operand, the sticky bit remains at 1 despite further shifting.

[0046] The number of precision bits can be selected based on the target error bound for the multi-input adder, as the number of precision bits affects the number of potential lost bits due to shifting during alignment. For example, using three precision bits and one sticky bit, the error of a 4-input adder relative to an adder with an infinite number of precision bits is shown in the following Relationship 1. In Relationship 1, parameter M is the mantissa bits of each operand (including hidden bits), and parameter E is the number of exponent bits of each operand. Parameter z is the output of the 4-input adder, parameter z_ref is the output of the adder with an infinite number of precision bits, parameter z_ref.exp is the exponent of the output of the adder, and parameter a.exp-d.exp is the exponent of the four input operands. Using ".exp" in this relationship means the actual exponent of the floating-point number rather than the stored exponent. The actual exponent of the floating-point number can be derived by subtracting the bias from the stored exponent. This relationship is valid if neither parameter z nor parameter z_ref is infinite or not a number (NaN). If either argument z or argument z_ref is infinite or NaN, then the absolute value of argument z minus argument z_ref is infinite or NaN.

[0047]

[0048] The sign of the sticky bit of an operand may be based on whether the sign of the operand is the same as the sign of the operand with the largest exponent value. For example, during mantissa addition, if the mantissa of the operand with a different sign from the operand with the largest exponent value is considered a negative value, the sign of the sticky bit will be positive if the signs are the same and negative if the signs are different.

[0049] After aligning the mantissa bits, the multi-input adder can add the mantissas of the operands. As part of the addition, the multi-input adder can also add additional precision bits. If necessary, the multi-input adder can then normalize the sum. For example, if the value of the most significant bit (MSB) is 0, the multi-input adder can shift the mantissa of the sum until the value of the MSB is 1. The multi-input adder can also determine whether to round the mantissa based on the overall sticky bit value. For multi-input adders that add more than two operands, the calculation of the total sticky bit needs to be carefully handled to minimize its impact on accuracy and error deviation.

[0050] When large-scale mantissa cancellation occurs, the value of the sticky bit may have a large impact on accuracy and error deviation. The exponent difference between the operands may be large, resulting in a non-zero sticky bit. Therefore, the calculation of the overall sticky bit needs to be handled carefully. Large-scale mantissa cancellation occurs when the mantissa values ​​of the operands being added are close but have opposite signs, which results in more than one leading zero appearing in the sum of the mantissas before normalization. Large-scale mantissa cancellation can occur through a two-input adder. However, when it occurs through a two-input adder, the sticky bit is always zero. This is because large-scale mantissa cancellation only occurs when the exponent difference is less than or equal to 1. When large-scale mantissa cancellation occurs through a multi-input adder, the exponent difference between some operands and the operand with the largest exponent may be large, resulting in a non-zero sticky bit. Therefore, the calculation of the overall sticky bit needs to be handled with caution.

[0051] In some embodiments, the multi-input adder determines a total sticky bit value so that whenever all sticky bits of all other operands (except the operand with the maximum exponent value identified) are zero, the total sticky bit value is zero. Whenever at least two of the other operands have non-zero and mismatched sticky bits, the total sticky bit value is also zero. For example, if one operand has a sticky bit with a value of -1, and another operand has a sticky bit with a value of +1, the total sticky bit value will be zero. If all non-zero sticky bits match, for example, all have a value of +1, the total sticky bit value can be the same as the non-zero sticky bit +1 in this example. When determining the total sticky bit in this way, it can be ensured that the error in the summation result of the multi-input adder can be within certain limits and without a bias that deviates from zero. In particular, in order to achieve this effect, it is not necessary to maintain a large number of additional precision bits for each operand of the multi-input adder. This results in the advantage that, compared with traditional multi-input adder implementations, the disclosed technology can be implemented with fewer hardware resources.

[0052] Figure 1is a block diagram of an exemplary multi-input hardware adder 100. In this example, the multi-input adder 100 is a four-input adder in the form of a hardware circuit that includes several components for determining the sum of four floating-point operands. However, as described below, the multi-input adder 100 can be configured to determine the sum of three floating-point operands, five floating-point operands, or another suitable number of floating-point operands.

[0053] Multi-input adder 100 can determine the sum of floating-point numbers with a given format. The format can be defined by the number of digits used to represent the various parts of the floating-point number. As mentioned above, the IEEE 754 single-precision format floating-point number includes 1 sign bit, 8 exponent bits, and 24 mantissa bits (23 explicit storage bits and 1 recessive hidden bit). Multi-input adder 100 can be configured to determine the sum of these 32-bit single-precision format floating-point numbers. In another example, multi-input adder 100 can be configured to determine a 24-bit number including 1 sign bit, 8 exponent bits, and 16 mantissa bits (15 explicit storage bits and 1 recessive hidden bit), or the sum of other floating-point format numbers. In order to configure the multi-input adder for a specific format, adder 150 (described in more detail below) can be configured to add the mantissa with a specific number of bits, and be configured to include an additional bit for internal calculation and rounding, including a sticky bit.

[0054] The multi-input adder 100 includes an exponent subtraction and swap component 110 that receives four floating-point operands (a, b, c, and d) as inputs and assigns them to intermediate operands (x, y, m, and n) based on the exponent values ​​of the input operands. The exponent subtraction and swap component 110 may assign the input operand with the largest exponent value to operand x and the other input operands to intermediate operands y, m, and n. If all operands have the same exponent value, the exponent subtraction and swap component 110 may assign input operand a to intermediate operand x, input operand b to intermediate operand y, input operand c to intermediate operand m, and input operand d to intermediate operand n.

[0055] Exponent subtraction and exchange component 110 can comprise one or more exchange units, one or more subtractors and / or one or more absolute value calculators.For example, exponent subtraction and exchange component 110 can comprise three exchange units, four 8-bit subtractors (based on the quantity of exponent bit) and two absolute value calculators.The quantity of each in these assemblies and the configuration of these assemblies can be configured to change with the number of the exponent bit of the input operand that it adds based on the number of the input of multi-input adder 100 and / or multi-input adder 100.For example, if input operand has 4 exponent bits, then subtractor can be 4 subtractors.

[0056] The exponent subtract and swap component 110 identifies the input operand with the largest exponent value and calculates the difference between the exponent value of that operand and the exponent value of each other input operand. In hardware, a subtractor can determine the difference between the exponent value of input operand a and the exponent value of input operand b. The subtractor can also determine the difference between the exponent value of operand c and the exponent value of operand d.

[0057] The swap unit can then assign the input operands to the intermediate operands using the following relations 2 and 3:

[0058] (p,m)=(a,b)if ae-be≥0; else(p,m)=(b,a) (2)

[0059] (r,n)=(c,d)if ce-de≥0; else(r,n)=(d,c) (3)

[0060] Parameters with ".e" after the operand name refer to the exponential value of the operand. For example, parameter ae is the exponential value of input operand a. After this initial swap, two of the input operands are assigned to their intermediate operands m and n.

[0061] The subtractor can then determine the difference between pe and re after the previous swap. The swap unit can then assign the input operands to the intermediate operands x and y using the following relation 4:

[0062] (x,y)=(p,r)if pe-re≥0; else(x,y)=(r,p) (4)

[0063] The exponent subtraction and swap component 110 can then determine the number of bit positions to shift the mantissas of the intermediate operands y, m, and n based on the difference between the exponent values ​​of these operands and the intermediate operand x. For example, the exponent subtraction and swap component 110 can use the following relations 5, 6, and 7 to determine the number of bit positions to shift the mantissas of each intermediate operand:

[0064] y_shift=|pe-re| (5)

[0065] m_shift=|ae-be|if pe-re≥0; else m_shift=(xe-me) (6)

[0066] n_shift=xe-ne if pe-re≥0; else n_shift=|ce-de| (7)

[0067] Parameters with "_shift" after the operand name refer to the number of bits to shift that operand, for example, m_shift is the number of bits to shift operand m. Using the above logic, the exponential subtract and swap component 110 assigns the input operands a, b, c, and d to x, y, m, and n such that xe is greater than or equal to ye, me, and ne. The exponential subtract and swap component 110 also determines the number of bits to shift the mantissas of operands y, m, and n such that the shift of operand y is equal to the difference between xe and ye, the shift of operand m is equal to the difference between xe and me, and the shift of operand n is equal to the difference between xe and ne.

[0068] Based on the sign of each operand relative to the sign of the intermediate operand x, the exponent subtract and swap component 110 may also determine whether any of the intermediate operands y, m, or n is to be inverted. If the intermediate operand is to be inverted, the exponent subtract and swap component 110 may set the value of the inversion operation "_op" parameter (e.g., stored as a bit) of the operand to 1. The exponent subtract and swap component 110 may use relations 8, 9, and 10 to determine whether to invert the intermediate operands y, m, or n:

[0069] y op =xs XOR ys (8)

[0070] m op =xs XOR ms (9)

[0071] n op =xs XOR ns (10)

[0072] The exponent subtraction and swap component 110 outputs intermediate operands to pipeline registers 125. The exponent subtraction and swap component 110 also outputs inversion operation parameters to pipeline registers 125. Pipeline registers 125 and 165 are used to divide the datapath of the multi-input adder 110 into stages. In this example, the datapath includes a first alignment stage before pipeline register 125, a second addition stage between pipeline register 125 and pipeline register 165, and a third normalization and rounding stage after pipeline registers 125 and 165. Other components can obtain data required for their operations from pipeline registers 125 and 165.

[0073] The pipeline registers 125 can store the sign, exponent, and mantissa of each intermediate operand. For example, for operand x, the pipeline registers 125 can store x.sign (sign value), x.exponent (exponent value), and x.mantissa (mantissa value). For other operands, the pipeline registers 125 can store the shifted mantissa (e.g., y_shifted_f for operand y). The shifted mantissa of a shifted operand can include extra precision bits and a sticky bit for the operand. The pipeline registers 125 can also store the values ​​of the reverse operation "_op" parameters (e.g., y_op, m_op, and n_op).

[0074] The pipeline register 125 may also store the value of the result_is_special parameter. Special cases may exist where one or more of the input operands is a NaN, one or more of the input operands is an infinity, or all of the input operands are zero or denormals (floating point numbers with a zero exponent and a non-zero mantissa). In either case, the value of result_is_special may be 1 to indicate that the result of the addition is one of the special cases.

[0075] Despite Figure 1 Not shown, the multi-input hardware adder 100 may include additional components or logic for handling special cases. For example, if at least one of the input operands is NaN or at least two of the input operands are infinities with opposite signs, the multi-input adder 100 may output a final result (z) as NaN. In another example, if all input operands are zero or denormalized numbers, the multi-input hardware adder 100 may output a final result (z) as zero. In another example, if at least one of the input operands is infinity and all infinite operands have the same sign, the multi-input hardware adder may output a final result (z) as positive or negative infinity. The multi-input hardware adder 100 may treat denormalized numbers as appropriately signed zeros and flush the denormalized results to zero.

[0076] The exponent subtraction and swap component 110 also adds the mantissa bits ( Figure 1 121, 122, and 123. For operands that do not have a maximum exponent value, the multi-input adder 100 may include a right shifter for each operand. Thus, the multi-input adder 100 may include n-1 right shifters, where n is the number of input operands to the multi-input adder 100. In this example, a 6-input adder would have 5 right shifters. In other examples, fewer right shifters may be used, and each right shifter may shift more than one operand in each addition operation.

[0077] Right shifter 121 can be based on y_shift for operand y shift mantissa yf.For example, if y_shift is five (meaning that the difference between the exponential value of x is greater than the exponential value of y by five), then right shifter 121 can be with the mantissa yf of operand y to the right shift 5 position.Similarly, right shifter 122 can be based on m_shift with the mantissa mf shift of operand m, and right shifter 123 can be based on n_shift with the mantissa nf shift of operand n.If the shift of operand is zero, then the mantissa of operand is not shifted, for example, is shifted zero position.After operand is shifted, if suitable, then the exponential value of each operand x, y, m and n is identical.That is, due to the shift of mantissa, the exponential value of y, m and n is now equal to the exponential value of operand x. Each right shifter 121, 122, and 123 may output a shifted version of its mantissa that has been shifted by zero or more bit positions. For example, right shifter 121 may output a shifted version of the mantissa of operand y (y_shifted_f); right shifter 122 may output a shifted version of the mantissa of operand m (m_shifted_f); and right shifter 123 may output a shifted version of the mantissa of operand n (n_shifted_f).

[0078] In some embodiments, the multi-input adder 100 includes additional bits for precision and rounding of the mantissa. For example, the multi-input adder 100 can include one or more precision bits to the right of the mantissa and a sticky bit to the right of the one or more precision bits. When the mantissa of the operand is shifted right, the LSB of the mantissa is moved to the precision bit position and, if the shift is sufficient, to the sticky bit position, potentially shifting out of an available bit of the mantissa. In this way, if the mantissa of the operand is shifted to fewer positions than the number of precision bits, the value of the bit shifted into the precision bit position can remain unchanged.

[0079] For example, the multi-input adder 100 can use 28 bits to store a 24-bit mantissa. In this example, the 24 mantissa bits can be the 24 MSBs. The next three bits can be the precision bits, and the LSB can be the sticky bit. If the mantissa of the operand is shifted right by three positions, the LSB of the mantissa will be stored in the third precision bit position. However, if the mantissa of the operand is shifted right by five positions, the LSB will be shifted outside the available bit positions.

[0080] The sticky bit of an operand is used to indicate what may have been shifted from an available bit position. If a value of 1 is shifted into a sticky bit position, the sticky bit value is set to 1. Even if a zero is later shifted into the sticky bit position, for example, after a lower significant bit with a value of 1 is shifted into the sticky bit position, if the value of the higher significant bit is zero and the higher significant bit is shifted into the sticky bit position, the sticky bit value may remain at a value of 1 after being set to that value.

[0081] The sign of the sticky bit of an operand may be based on whether the sign of the operand is the same as the sign of the operand with the largest exponent value. If the signs are the same, the sign of the sticky bit is positive. If the signs are different, the sign of the sticky bit is -1.

[0082] In some embodiments, the sticky bit of an operand may have a value of zero if all of the mantissa bits of the operand are shifted out of the available bit positions. For example, a right shifter that shifts the mantissa bits may set the sticky bit to zero if all of the mantissa bits are shifted out of the available bit positions.

[0083] The multi-input adder 110 further includes inversion components 131, 132, and 133. If the value of the inversion operation parameter of the operand is set to 1, the inversion components 131, 132, and 133 can perform an inversion operation on the shifted mantissa bits. For example, if the value of the inversion operation parameter of the operand is set to 1, each inversion component 131-133 can perform a two's complement inversion on the mantissa bits of the operand. In this way, adding the mantissa of another operand to the inverted mantissa results in a subtraction operation between the two mantissas.

[0084] The multi-input adder 110 also includes a sticky bit calculator 134. The sticky bit calculator 134 can calculate the total sticky bit value of the sum (e.g., the summed set of bits representing the sum of the mantissas). The sticky bit calculator 134 can calculate the total sticky bit value such that whenever all sticky bits of operands y, m, and n are zero, the total sticky bit value is zero. Whenever at least two of the other operands have non-zero and non-matching sticky bits, the total sticky bit value is also zero. If all non-zero sticky bits match, for example, all non-zero sticky bits have a value of +1, the total sticky bit value can be the same as the non-zero sticky bit +1 in this example.

[0085] For example, if the sticky bit of operand y is +1, the sticky bit of m is +1, and the sticky bit of n is 0, because all non-zero sticky bits are +1, the total sticky bit value is +1. In another example, if the sticky bit of operand y is -1, the sticky bit of m is 0, and the sticky bit of n is 0, because the only non-zero sticky bit has a value of -1, the total sticky bit value is -1. In another example, if the sticky bit of operand y is -1, the sticky bit of m is -1, and the sticky bit of n is -1, because all sticky bits have a value of -1, the total sticky bit value is -1. In another example, if the sticky bit of operand y is +1, the sticky bit of m is -1, and the sticky bit of n is -1, because the values ​​of all non-zero sticky bits of operands y, m, and n do not match, the total sticky bit value is 0. In yet another example, if the sticky bit of operand y is 0, the sticky bit of m is 0, and the sticky bit of n is 0, the total sticky bit value is 0 because all sticky bits have a value of zero.

[0086] In some embodiments, sticky bit calculator 134 may assign the total sticky bits to one of the operands (y, m, or n) and clear the sticky bits for the other operands before inversion components 131, 132, and 133 perform an inversion operation on the shifted mantissa bits. If the total sticky bits are +1, sticky bit calculator 134 sets the sticky bit of the operand with the same sign as operand x to 1 and sets the sticky bits of the other two operands to 0. If the total sticky bits are -1, sticky bit calculator 134 sets the sticky bit of the operand with the opposite sign of operand x to 1 and sets the sticky bits of the other two operands to 0.

[0087] The multi-input adder 100 also includes a four-input mantissa adder 150 that adds the mantissas, precision bits, and sticky bits of operands x, y, m, and n. For example, the four-input adder 150 can add the original mantissa of operand x to the shifted versions of the mantissas of operands y, m, and n (as well as their precision bits and sticky bits). Because the mantissa of operand x is not shifted, the precision bits and sticky bits of operand x are zero. For different numbers of inputs, the multi-input adder 100 can include an adder that calculates the sum of the mantissas of that number.

[0088] Adder 150 can output a summed set of bits representing the sum of the four mantissas and their precision and sticky bits. For example, if two overflow bits are included, the summed set of bits can include 31 bits, which include the two overflow bits, 24 mantissa bits, three precision bits, a two's complement inversion bit, and the final sticky bit. If the two overflow bits are not included, the summed set of bits can include an additional 29 bits. Of course, other formats are also possible based on the format of the input operands, the desired precision, etc.

[0089] The multi-input adder 100 further includes an inversion component 155 that can invert the sum of the mantissas if the sign of the sum of the mantissas is negative. For example, if the sum of the mantissas is less than zero, the inversion component 155 can invert the sum of the mantissas using a two's complement inversion.

[0090] In some embodiments, the multi-input adder shifts the radix of the sum of bits to the right by one or more bit positions (e.g., two bit positions for a 2-bit overflow) by remapping the sum of bits output by the adder. This can prevent the need for a right shift in the event of an overflow. For example, if each input operand includes 24 mantissa bits, and the multi-input adder 100 can use 29 bits to store the mantissa. These 29 bits can include 24 mantissa bits, 3 precision bits, 1 two's complement inverted bit (in the MSB), and 1 sticky bit position (LSB). The output of the inversion component 155 can include the sum of the two overflow bits, 24 mantissa bits, three precision bits, and the sticky bit. The multi-input adder can treat the MSB of the overflow bit as a hidden bit of the mantissa, the next 23 bits as the remaining bits of the mantissa, the next 5 bits as additional precision bits, and the LSB as the sticky bit. The number of right shifts to the radix affects the exponent value of the sum. For example, if the base of the sum is right shifted two bit positions, the number 2 may be added to the exponent value of the sum as described below.

[0091] The multi-input adder 100 also includes a leading zero detector 160. The leading zero detector 160 can determine whether there are any leading zeros in the mantissa of the sum set of bits. If so, the sum represented by the sum set of bits can be normalized so that the MSB in the MSB of the mantissa has a value of one. The leading zero detector 160 can determine the number of leading zeros in the mantissa and provide the sum set of bits and the number of leading zeros to the left shifter 170.

[0092] The left shifter 170 may shift the sum of bits to the left until the MSB of the mantissa has a value of one. The left shifter 170 may shift the sum of bits to the left based on the number of leading zeros. For example, if the mantissa has two leading zeros, the left shifter 170 may shift each bit in the sum of two bit positions to the left.

[0093] Left shifter 170 can also prevent the value of sticky bit from being shifted into the mantissa.If the sticky bit in the sum of the bits is shifted into the mantissa, the value of the sticky bit can be set to zero.If all extra precision bits are shifted into the mantissa, the sticky bit will also be set to zero.Left shifter can use the number of leading zeros (the number of positions to which the sum of its representation bits is shifted) to determine whether the sticky bit is shifted into the mantissa.If there is no extra bit for overflow, and use three precision bits, then if the sum of the bits is shifted to the left by three or more positions, the value of the sticky bit will be moved into the mantissa.In this case, if the sticky bit has a non-zero value, then the value that the sticky bit is shifted into the mantissa can be replaced by a zero value.

[0094] The multi-input adder 100 also includes a rounder 175. The rounder 175 can round the mantissa based on the value of the LSB of the mantissa and all bits to the left, where the all bits to the left can include sticky bits, extra precision bits, and bits of the mantissa region that have been right-shifted out of the region when normalizing for mantissa overflow. In some embodiments, the rounder 175 uses round to the nearest or half-to-even rounding techniques. Other rounding techniques can also be used.

[0095] Using a round-to-nearest, half-to-even rounding technique, if the value of the bit truncated from the mantissa (e.g., the value of the precision bit after the shift and the value of the sticky bit immediately following the precision bit) is greater than half the value of the LSB of the mantissa, the value of the mantissa will be rounded up. If the value of the truncated bit is less than half the value of the LSB of the mantissa, the value of the mantissa will be rounded down. If the value of the truncated bit is half the value of the LSB of the mantissa, the value of the mantissa will be rounded down if the LSB of the mantissa is zero, or rounded up if the LSB of the mantissa is one. If no special cases occur (e.g., where z is a NaN, infinity, or zero), the rounded mantissa bits can be output as the mantissa (zf) of the sum of the four input operands.

[0096] The multi-input adder also includes an exponent updater 180 that determines an exponent value for the sum. The exponent value may be equal to the sum of the exponent (xe) of operand z, any rounding overflow (e.g., if rounding causes the mantissa to overflow to the most significant bit), and the number of bits by which the radix of the sum was right-shifted (if any), minus the number of bits by which the summed set of bits was left-shifted by left shifter 170 (e.g., the same number of leading zeros determined by leading zero detector 160). Exponent updater 180 may output the exponent (ze) of the sum of the four input operands.

[0097] Multi-input adder 100 also includes an XOR gate 185 that performs an exclusive disjunction between the sign bit of operand x (1 if negative) and a bit indicating whether the sum of the adder outputs is negative (also 1 if negative). If the two bits have the same value, the output of XOR gate 185 is zero. That is, if the signs are the same (i.e., both positive or both negative), the sign of the sum (zs) is positive. If the bits have different values, the output of the XOR gate is 1. That is, if the signs are different, the sign of the sum (zs) is negative.

[0098] Figure 2 is a flow chart illustrating an exemplary process 200 for adding three or more operands. The operations of process 200 may be performed by, for example Figure 1 The multi-input adder 100 is implemented by a multi-input hardware adder. Figure 3 To describe Figure 2 , Figure 3 An example of adding four operands using a four-input adder is shown.

[0099] The multi-input adder has three or more floating-point inputs. Each input is configured to receive a floating-point operand to be added to two or more other operands. The multi-input adder is configured to determine the sum of floating-point operands in a specific format, such as a floating-point operand with a sign bit, a specific number of exponent bits, and a specific number of mantissa bits. As described above, due to the alignment step, the multi-input adder can use extra bits for precision and tracking of the sticky bit of the mantissa.

[0100] For each of three or more operands to be added by the multi-input adder, the multi-input adder receives a set of bits comprising a floating point representation of the operand 210. For example, the set of bits for the operand may include a sign bit representing the sign of the operand, exponent bits representing the exponent value of the operand, and mantissa bits representing the significand of the floating point number.

[0101] In a multiple-input adder, operands may include hidden bits, additional bits for precision, and sticky bits. Figure 3In the example of FIG. 301 , each operand 321-324 includes a sign bit 311, three exponent bits 312, one hidden bit 313, five mantissa bits 314, two precision bits 315, and one sticky bit 316. For example, a multi-input adder may receive a 9-bit input operand in a 13-bit format (e.g., one sign bit 311, three exponent bits 312, and five mantissa bits 314), which is one sign bit 311, three exponent bits 312, six mantissa bits 313 and 314 including the hidden bit 313, two precision bits 315, and one sticky bit 316. As described above, the multi-input adder may include additional bits for internal calculations and rounding. In this example, the multi-input adder includes two precision bits 315 and one sticky bit 316 for each operand. Other numbers of precision bits may also be used based on the target precision of the multi-input adder.

[0102] The multi-input adder identifies a given operand with which each other operand is to be aligned (220). For example, the multi-input adder may identify the operand with the largest exponent value as the given operand with which each other operand is to be aligned. In this example, operand 322 has the largest exponent value (binary 110 or decimal 6).

[0103] For each other operand, the multi-input adder generates a shifted group of bits for the operand (230). The multi-input adder can generate the shifted group of bits by shifting the bits of the operand by one or more bit positions so that the bits of the operand are aligned with the bits of the given operand. For example, the multi-input adder can determine, for each operand, the difference between the exponent value of the given operand and the exponent value of the other operands. If the difference is zero, the other operands may not be shifted, for example, by zero bit positions.

[0104] The multi-input adder can then right-shift the mantissa bits of the other operand (i.e., from the most significant side of the mantissa to the least significant side of the mantissa, in Figure 3 The number of positions shifted right is equal to the difference between the exponent value of the given operand and the exponent value of the other operand (from left to right in the input adder). For example, if the decimal value of the exponent of the given operand is 5 and the decimal value of the exponent of the other operand is 3, the multi-input adder may shift the mantissa bits of the other operand to the right by 2 bit positions.

[0105] As shown in reference numeral 302, the mantissa of each other operand 321, 323 and 324 has been shifted. Because the exponent value of operand 321 is binary 011 or decimal 3, the mantissa of operand 321 is shifted to the right by three positions. Since the difference between the exponent values ​​of operand 322 and operand 321 is 3 (6-3), the mantissa of operand 321 is shifted to the right by three positions. Due to the shift, the precision bit 314 of operand 321 has 1 and 0. Based on the difference between the exponent value of operand 322 and the exponent values ​​of each operand 323 and 324, the other two operands 323 and 324 are also shifted to the right. As described below, the shift also includes the precision bit immediately after the least significant mantissa. Similarly, as will be discussed below, the value of the sticky bit immediately after the least significant precision bit is also affected by the right shift operation.

[0106] In this example, the other operands 321, 323, and 324 also include an inversion operation bit 317. If the sign of the operand is different from the sign of the operand 322 having the largest exponent value, the inversion operation bit 317 of the operand is set to 1. If the inversion operation bit 317 is set to 1, the multi-input adder performs a two's complement inversion on the mantissa bits of the operand. In this way, adding the mantissa of the other operand to the inverted mantissa results in a subtraction operation between the two mantissas.

[0107] Based on the shift, the multi-input adder determines the value of the sticky bit of each other operand (240). When a non-zero value is shifted from the bit group representing the operand to generate the shifted bit group of the operand, the sticky bit of the operand has a non-zero value. In addition, a sign value is associated with the sticky bit. Hereinafter, we simply refer to it as the sign of the sticky bit. The sticky bit value of the operand also has a sign that matches the sign of the operand.

[0108] As shown at reference numeral 302, because the LSB of the original mantissa of operand 321 is shifted three bit positions into sticky bit 316, the value of sticky bit 316 of operand 321 is 1. If the mantissa bits of the operand were shifted four bit positions instead of three bit positions, the value of sticky bit 316 of the operand would still be 1, even though zero would be shifted into that bit position. This is because once the sticky bit of an operand is set to a non-zero value during alignment, the sticky bit remains at that value.

[0109] Based on the value of each sticky bit, the multi-input adder determines a total sticky bit value (250). As described above, whenever (i) all sticky bits of all other operands are zero; or (ii) at least two of the other operands have non-zero and mismatched sticky bits (e.g., the sign bits of the operands with non-zero sticky bits do not match), the total sticky bit value is zero. Whenever all non-zero sticky bits match or there is only one non-zero sticky bit, the total sticky bit value matches the value of each non-zero sticky bit. In this example, since there are two non-zero sticky bits (the sticky bits of operands 321 and 324), and they both match by having a value of 1, the total sticky bit value of the sum is 1.

[0110] As described above, the multi-input adder can assign the total sticky bit value to one of the other operands 321, 323, or 324 and clear the sticky bit value of each of the other operands, for example, by assigning a zero value to each of the other sticky bit values. In the example of step 303, the multi-input adder assigns the total sticky bit value to operand 321 and clears the sticky bit value of operand 324, as shown by reference numeral 303.

[0111] The multi-input adder uses (i) the bit group representing a given operand; (ii) the shifted bit group of each other operand; and (iii) the total sticky bit value to determine the sum of three or more operands. As described above, the multi-input adder can first add the mantissa bits of the operand with the largest exponent value to the shifted mantissa bits of the other operands. The sum can be represented as a sum set of bits 304, where the sum process also includes bits 315 and 316 after the least significant end of the mantissa of each operand in addition to the mantissa bits 314.

[0112] Before adding the operands, the multi-input adder may add an overflow bit to each operand 321-324. For example, as shown at 303, each operand 321-324 includes a two's complement bit 320, two overflow bits 318 having a value of zero, a hidden bit 313, five mantissa bits 314, two precision bits 315, and a sticky bit 316. The multi-input adder may add groups of bits of the operands 321-324, as shown at 303, to determine a summed bit set 304. The summed bit set 304 represents an unsigned sum of the operands 321-324. The summed bit set 304 includes two overflow bits 318, a hidden bit 313, five mantissa bits 314, two precision bits 315, and a sticky bit 316 representing a total sticky bit value.

[0113] As described above, the multi-input adder can shift the base of the sum to the right (e.g., two bit positions) before normalization. This shift may not be an actual shift of the value of the sum set of bits. Instead, the shift can be a remapping of the bit positions. For example, the multi-input adder can generate a remapped sum set of bits 304, 304 including one hidden bit 313 (having the value of the MSB of the overflow bit 318), five mantissa bits 314 (including the LSB of the overflow bit 318, the hidden bit 313 of the sum set of bits 304, and the first three MSBs of the mantissa 314 of the sum set of bits 304), four additional bits 319 (including the two LSBs of the mantissa 314 of the sum set of bits 304 and the precision bit 315 of the sum set of bits 304), and a sticky bit 316. The multi-input adder can also add the number of shifted bit positions (e.g., two in this example) to the exponent value of the sum based on this shift.

[0114] The multi-input adder can then normalize the sum of the bits representing the sum. The normalization of the bit sequence 305 to the sequence 306 can include shifting the mantissa bits of the sum of the bits to the left if the mantissa bits include any leading zeros. For example, for each leading zero in the mantissa, the multi-input adder can shift the mantissa bits and the precision bits to the left by one position so that the most significant bit of the mantissa has a value of 1. In the sequence 306, this is the leftmost bit shown.

[0115] In this example, the summed set of bits 305 includes a leading zero in the MSB. Therefore, the multi-input adder can shift the summed set of bits 305 left by one position, thereby generating the summed set of bits 306. At this point, the MSB of the summed set of bits is a hidden bit 313 having a value of 1. The summed set of bits 306 includes the hidden bit 313, five mantissa bits 314, three additional bits 319, and a sticky bit 316. The multi-input adder can also update the exponent of the sum based on the shift. For example, the multi-input adder can subtract from the exponent of the sum the number of bit positions by which the summed set of bits 305 was shifted left to obtain the normalized summed set of bits 306. In this example, the multi-input adder can subtract the value 1 from the exponent value of the sum.

[0116] The sum can then be rounded based on the precision bits and the total sticky bit value. As described above, the sum can be rounded using a round-to-nearest, half-to-even rounding technique. Using the round-to-nearest, half-to-even rounding technique, if the value of the bit truncated from the mantissa (e.g., the value of the precision bit after the shift and the total sticky bit value after the precision bit) is greater than half the value of the LSB of the mantissa, the value of the mantissa will be rounded up. If the value of the truncated bit is less than half the value of the LSB of the mantissa, the value of the mantissa will be rounded down. If the value of the truncated bit is half the value of the LSB of the mantissa, the value of the mantissa will be rounded down if the LSB of the mantissa is zero, or rounded up if the LSB of the mantissa is one. If no special cases occur (e.g., where z is a NaN, infinity, or zero), the rounded mantissa bits can be output as the mantissa (zf) of the sum of the four input operands.

[0117] In this example, the LSB of the mantissa is zero, each of the additional precision bits 319 has a value of zero, and the sticky bit has a value of 1. The value of the truncated bit is 0.0625, which is less than half of 1 (the value of the LSB of the mantissa). Therefore, the LSB of the mantissa of the summed set of bits is not rounded, as shown by reference numeral 307, which shows the mantissa 314 of the sum of the four operands 321-324. The hidden bit 313 can be discarded and the multi-input adder can output a 5-bit mantissa 314.

[0118] Furthermore, the multi-input adder can determine a sign 331 of the sum and an exponent value 332 of the sum. As described above, the sign 331 of the sum can be the output of an XOR operation of the sign of the operand with the largest exponent value and the sign of the output of the sum mantissa adder 150. In this example, because all four operands are positive, the sign 331 of the sum is positive. The exponent value 332 of the sum is based on the exponent value of the operand 322 with the largest exponent value, the number of bit positions that the radix was right-shifted to generate the sum set of bits 305 (if performed) during remapping, and the number of bit positions that the sum set of bits 305 was left-shifted to generate the sum set of bits 306 during normalization. For example, the exponent value 332 can be the sum of the exponent value of the operand 322 and the number of bit positions by which the radix was right-shifted, minus the number of bit positions by which the sum was left-shifted during normalization. In this example, the exponent value 332 would be 7 (e.g., 6+2-1).

[0119] The bit group 308 representing the sum can be generated using a sign bit 331, exponent bits 332 representing the determined exponent value, and mantissa bits 314 representing the mantissa of the sum. For example, a multi-input adder can output the bit group to corresponding memory locations of one or more bytes of memory to calculate the sum.

[0120] The term "data processing apparatus" includes all types of apparatus, devices, and machines for processing data, including, for example, a programmable processor, a computer, a system on a chip, or a combination of the foregoing. The apparatus may include special-purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0121] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input data and generating output. The processes and logic flows can also be, and means can also be, implemented to be performed by special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0122] Processors suitable for executing computer programs include, by way of example, general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, a processor will receive instructions and data from a read-only memory or a random access memory, or both. The essential elements of a computer are a processor for performing actions in accordance with instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include, or be operatively coupled to receive data from, transfer data to, or both, one or more mass storage devices for storing data, such as magnetic, magneto-optical, or optical disks. Typically, a computer also includes, or is operatively coupled to receive data from, or transfer data to, one or more mass storage devices for storing data, such as magnetic, magneto-optical, or optical disks.

[0123] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope of what is claimed, but rather as descriptions of specific features of specific embodiments of specific inventions. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable subcombination. Furthermore, although features may be described above as working in certain combinations, and even initially claimed as such, in some cases one or more features in the claimed combination may be removed from the combination, and the claimed combination may be intended to be a subcombination or a variation of a subcombination.

[0124] Similarly, although operations are described in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequence, or that all of the illustrated operations be performed to obtain the desired results. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated into a single software product or packaged into multiple software products.

[0125] Thus, certain embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. Furthermore, the processes illustrated in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing may be advantageous.

Claims

1. A method performed by a multi-input hardware adder having three or more floating-point inputs, characterized in that The method comprises: for each of three or more operands to be added by the multi-input hardware adder, receiving a bit group comprising a floating-point representation of the operand; identifying a given operand to be aligned with each other operand; for each other operand, generating a shifted group of bits of the operand by shifting the mantissa bits of the operand by zero or more bit positions so that the bits of the operand are aligned with the bits of the given operand; Based on the shift, the value of the sticky bit of each other operand is determined, where the sticky bit of the operand is: has a non-zero value when a non-zero value is shifted out of a least significant position of the mantissa bits and any precision bit positions of the operand to generate the shifted group of bits of the operand; A total sticky bit value is determined based on the value of each sticky bit, where: said total sticky bit value is zero whenever (i) all said sticky bits of all said other operands are zero or (ii) at least two of said other operands have non-zero and non-matching sticky bits; and Whenever all non-zero sticky bits match or there is only one non-zero sticky bit, the total sticky bit value matches the value of each non-zero sticky bit; and A sum of the three or more operands is determined using (i) the set of bits representing the given operand, (ii) the shifted set of bits of each other operand, and (iii) the total sticky bit value.

2. The method according to claim 1, wherein The determining the sum of the three or more operands includes: determining a summed set of bits representing a sum of the bit groups representing the given operand and each shifted bit group; normalizing the mantissa of the sum of the bits by shifting the mantissa of the sum of the bits until the hidden bit is 1 whenever the hidden bit of the mantissa of the sum of the bits is zero; and Based on the mantissa of the summed set of bits and the total sticky bit value, it is determined whether to round a floating point value represented by the summed set of bits.

3. The method according to claim 2, wherein Determining whether to round the floating point value represented by the summed set of bits comprises: determining a number of bit positions by which the mantissa of the summed set of bits is shifted to normalize the mantissa of the summed set of bits; and Whenever the number of bit positions exceeds the number of precision bits of the multi-input hardware adder excluding the sticky bit, determine to round the floating-point value represented by the summed set of bits based on the floating-point value represented by the summed set of bits and the total sticky bit value.

4. The method according to claim 2, wherein The method also includes preventing the total sticky bit value from being included in the mantissa of the summed set of bits during normalization by assigning bits of the mantissa representing the total sticky bit value to zero whenever the total sticky bit value is non-zero and the total sticky bit value is shifted to the mantissa during normalization.

5. The method according to claim 1, wherein Shifting the mantissa bits of the operand by zero or more bit positions includes shifting the mantissa bits based on a difference between an exponent of the operand and an exponent of the given operand.

6. The method according to claim 1, characterized in that Identifying a given operand to be aligned with each other operand includes identifying the operand having the largest exponent value.

7. The method according to claim 1, characterized in that The multi-input hardware adder is a four-input adder having four floating-point inputs and determining a sum of four floating-point values ​​received at the four floating-point inputs.

8. A multi-input hardware adder, characterized in that: The multi-input hardware adder comprises: three or more inputs configured to receive three or more floating-point operands; and An adder circuit configured to perform the following operations, including: for each of three or more operands to be added by the multi-input hardware adder, receiving a bit group comprising a floating-point representation of the operand; identifying a given operand to be aligned with each other operand; for each other operand, generating a shifted group of bits of the operand by shifting the mantissa bits of the operand by zero or more bit positions so that the bits of the operand are aligned with the bits of the given operand; Based on the shift, the value of the sticky bit of each other operand is determined, where the sticky bit of the operand is: has a non-zero value when a non-zero value is shifted out of a least significant position of the mantissa bits and any precision bit positions of the operand to generate the shifted group of bits of the operand; A total sticky bit value is determined based on the value of each sticky bit, where: said total sticky bit value is zero whenever (i) all said sticky bits of all said other operands are zero or (ii) at least two of said other operands have non-zero and non-matching sticky bits; and Whenever all non-zero sticky bits match or there is only one non-zero sticky bit, the total sticky bit value matches the value of each non-zero sticky bit; and A sum of the three or more operands is determined using (i) the set of bits representing the given operand, (ii) the shifted set of bits of each other operand, and (iii) the total sticky bit value.

9. The multi-input hardware adder according to claim 8, wherein: The determining the sum of the three or more operands includes: determining a summed set of bits representing a sum of the bit groups representing the given operand and each shifted bit group; normalizing the mantissa of the sum of the bits by shifting the mantissa of the sum of the bits until the hidden bit is 1 whenever the hidden bit of the mantissa of the sum of the bits is zero; and Based on the mantissa of the summed set of bits and the total sticky bit value, it is determined whether to round a floating point value represented by the summed set of bits.

10. The multi-input hardware adder according to claim 9, wherein: Determining whether to round the floating point value represented by the summed set of bits comprises: determining a number of bit positions by which the mantissa of the summed set of bits is shifted to normalize the mantissa of the summed set of bits; and Whenever the number of bit positions exceeds the number of precision bits of the multi-input hardware adder excluding the sticky bit, determine to round the floating-point value represented by the summed set of bits based on the floating-point value represented by the summed set of bits and the total sticky bit value.

11. The multi-input hardware adder according to claim 9, wherein: The operations include preventing the total sticky bit value from being included in the mantissa of the summed set of bits during normalization by assigning bits of the mantissa representing the total sticky bit value to zero whenever the total sticky bit value is non-zero and the total sticky bit value is shifted to the mantissa during normalization.

12. The multi-input hardware adder according to claim 8, wherein: Shifting the mantissa bits of the operand by zero or more bit positions includes shifting the mantissa bits based on a difference between an exponent of the operand and an exponent of the given operand.

13. The multi-input hardware adder according to claim 8, wherein: Identifying a given operand to be aligned with each other operand includes identifying the operand having the largest exponent value.

14. The multi-input hardware adder according to claim 8, wherein: The multi-input hardware adder is a four-input adder having four floating-point inputs and determining a sum of four floating-point values ​​received at the four floating-point inputs.

15. A multi-input hardware adder, characterized in that: The multi-input hardware adder comprises: three or more inputs configured to receive three or more floating-point operands, each input configured to receive a bit group comprising a floating-point representation of the operand; an exponent subtraction and swap component configured to identify a given operand to be aligned with each other operand; One or more shifters configured to: for each other operand, generating a shifted group of bits of the operand by shifting the mantissa bits of the operand by zero or more bit positions so that the bits of the operand are aligned with the bits of the given operand; Based on the shift, the value of the sticky bit of each other operand is determined, where the sticky bit of the operand is: has a non-zero value when a non-zero value is shifted out of a least significant position of the mantissa bits and any precision bit positions of the operand to generate the shifted group of bits of the operand; a sticky bit calculator configured to determine a total sticky bit value based on the value of each sticky bit, wherein: said total sticky bit value is zero whenever (i) all said sticky bits of all said other operands are zero or (ii) at least two of said other operands have non-zero and non-matching sticky bits; and Whenever all non-zero sticky bits match or there is only one non-zero sticky bit, the total sticky bit value matches the value of each non-zero sticky bit; and Adder circuitry is configured to determine a sum of the three or more operands using (i) the group of bits representing the given operand, (ii) the shifted group of bits of each other operand, and (iii) the total sticky bit value.

16. The multi-input hardware adder according to claim 15, wherein: The one or more shifters set the sticky bit of an operand to a value of 1 whenever a non-zero value is shifted into the sticky bit.

17. The multi-input hardware adder according to claim 15, wherein: The adder circuit is further configured to: determining a summed set of bits representing a sum of the bit groups representing the given operand and each shifted bit group; normalizing the mantissa of the sum of the bits by shifting the mantissa of the sum of the bits until the hidden bit is 1 whenever the hidden bit of the mantissa of the sum of the bits is zero; as well as Based on the mantissa of the summed set of bits and the total sticky bit value, it is determined whether to round a floating point value represented by the summed set of bits.

18. The multi-input hardware adder according to claim 17, wherein: Determining whether to round the floating point value represented by the summed set of bits comprises: determining a number of bit positions by which the mantissa of the summed set of bits is shifted to normalize the mantissa of the summed set of bits; and Whenever the number of bit positions exceeds the number of precision bits of the multi-input hardware adder excluding the sticky bit, determine to round the floating-point value represented by the summed set of bits based on the floating-point value represented by the summed set of bits and the total sticky bit value.

19. The multi-input hardware adder according to claim 15, wherein: The operations include preventing the total sticky bit value from being included in the mantissa of the summed set of bits during normalization by assigning bits of the mantissa representing the total sticky bit value to zero whenever the total sticky bit value is non-zero and the total sticky bit value is shifted to the mantissa during normalization.

20. The multi-input hardware adder according to claim 15, wherein: Shifting the mantissa bits of the operand by zero or more bit positions includes shifting the mantissa bits based on a difference between an exponent of the operand and an exponent of the given operand.

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